sys/dev/buslogic/btreg.h

   1 /*-
   2  * Generic register and struct definitions for the BusLogic
   3  * MultiMaster SCSI host adapters.  Product specific probe and
   4  * attach routines can be found in:
   5  * sys/dev/buslogic/bt_isa.c    BT-54X, BT-445 cards
   6  * sys/dev/buslogic/bt_mca.c    BT-64X, SDC3211B, SDC3211F
   7  * sys/dev/buslogic/bt_pci.c    BT-946, BT-948, BT-956, BT-958 cards
   8  *
   9  * Copyright (c) 1998, 1999 Justin T. Gibbs.
  10  * All rights reserved.
  11  *
  12  * Redistribution and use in source and binary forms, with or without
  13  * modification, are permitted provided that the following conditions
  14  * are met:
  15  * 1. Redistributions of source code must retain the above copyright
  16  *    notice, this list of conditions, and the following disclaimer,
  17  *    without modification, immediately at the beginning of the file.
  18  * 2. The name of the author may not be used to endorse or promote products
  19  *    derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  25  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  31  * SUCH DAMAGE.
  32  *
  33  * $FreeBSD$
  34  */
  35
  36 #ifndef _BTREG_H_
  37 #define _BTREG_H_
  38
  39 #include <sys/queue.h>
  40
  41 #define BT_MAXTRANSFER_SIZE      0xffffffff     /* limited by 32bit counter */
  42 #define BT_NSEG         32      /* The number of dma segments supported.
  43                                  * BT_NSEG can be maxed out at 8192 entries,
  44                                  * but the kernel will never need to transfer
  45                                  * such a large request.  To reduce the
  46                                  * driver's memory consumption, we reduce the
  47                                  * max to 32.  16 would work if all transfers
  48                                  * are paged alined since the kernel will only
  49                                  * generate at most a 64k transfer, but to
  50                                  * handle non-page aligned transfers, you need
  51                                  * 17, so we round to the next power of two
  52                                  * to make allocating SG space easy and
  53                                  * efficient.
  54                                  */
  55
  56 #define ALL_TARGETS (~0)
  57
  58 /*
  59  * Control Register pp. 1-8, 1-9 (Write Only)
  60  */
  61 #define CONTROL_REG             0x00
  62 #define         HARD_RESET      0x80    /* Hard Reset - return to POST state */
  63 #define         SOFT_RESET      0x40    /* Soft Reset - Clears Adapter state */
  64 #define         RESET_INTR      0x20    /* Reset/Ack Interrupt */
  65 #define         RESET_SBUS      0x10    /* Drive SCSI bus reset signal */
  66
  67 /*
  68  * Status Register pp. 1-9, 1-10 (Read Only)
  69  */
  70 #define STATUS_REG                      0x00
  71 #define         DIAG_ACTIVE             0x80    /* Performing Internal Diags */
  72 #define         DIAG_FAIL               0x40    /* Internal Diags failed */
  73 #define         INIT_REQUIRED           0x20    /* MBOXes need initialization */
  74 #define         HA_READY                0x10    /* HA ready for new commands */
  75 #define         CMD_REG_BUSY            0x08    /* HA busy with last cmd byte */
  76 #define         DATAIN_REG_READY        0x04    /* Data-in Byte available */
  77 #define         STATUS_REG_RSVD         0x02
  78 #define         CMD_INVALID             0x01    /* Invalid Command detected */
  79
  80 /*
  81  * Command/Parameter Register pp. 1-10, 1-11 (Write Only)
  82  */
  83 #define COMMAND_REG                     0x01
  84
  85 /*
  86  * Data in Register p. 1-11 (Read Only)
  87  */
  88 #define DATAIN_REG                      0x01
  89
  90 /*
  91  * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only)
  92  */
  93 #define INTSTAT_REG                     0x02
  94 #define         INTR_PENDING            0x80    /* There is a pending INTR */
  95 #define         INTSTAT_REG_RSVD        0x70
  96 #define         SCSI_BUS_RESET          0x08    /* Bus Reset detected */
  97 #define         CMD_COMPLETE            0x04
  98 #define         OMB_READY               0x02    /* Outgoin Mailbox Ready */
  99 #define         IMB_LOADED              0x01    /* Incoming Mailbox loaded */
 100
 101 /*
 102  * Definitions for the "undocumented" geometry register
 103  */
 104 typedef enum {
 105         GEOM_NODISK,
 106         GEOM_64x32,
 107         GEOM_128x32,
 108         GEOM_255x32
 109 } disk_geom_t;
 110
 111 #define GEOMETRY_REG                    0x03
 112 #define         DISK0_GEOMETRY          0x03
 113 #define         DISK1_GEOMETRY          0x0c
 114 #define         EXTENDED_TRANSLATION    0x80
 115 #define         GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY)
 116 #define         GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2)
 117
 118 #define BT_NREGS        (4)
 119 /*
 120  * Opcodes for Adapter commands.
 121  * pp 1-18 -> 1-20
 122  */
 123 typedef enum {
 124         BOP_TEST_CMDC_INTR      = 0x00,
 125         BOP_INITIALIZE_24BMBOX  = 0x01,
 126         BOP_START_MBOX          = 0x02,
 127         BOP_EXECUTE_BIOS_CMD    = 0x03,
 128         BOP_INQUIRE_BOARD_ID    = 0x04,
 129         BOP_ENABLE_OMBR_INT     = 0x05,
 130         BOP_SET_SEL_TIMOUT      = 0x06,
 131         BOP_SET_TIME_ON_BUS     = 0x07,
 132         BOP_SET_TIME_OFF_BUS    = 0x08,
 133         BOP_SET_BUS_TRANS_RATE  = 0x09,
 134         BOP_INQUIRE_INST_LDEVS  = 0x0A,
 135         BOP_INQUIRE_CONFIG      = 0x0B,
 136         BOP_ENABLE_TARGET_MODE  = 0x0C,
 137         BOP_INQUIRE_SETUP_INFO  = 0x0D,
 138         BOP_WRITE_LRAM          = 0x1A,
 139         BOP_READ_LRAM           = 0x1B,
 140         BOP_WRITE_CHIP_FIFO     = 0x1C,
 141         BOP_READ_CHIP_FIFO      = 0x1C,
 142         BOP_ECHO_DATA_BYTE      = 0x1F,
 143         BOP_ADAPTER_DIAGNOSTICS = 0x20,
 144         BOP_SET_ADAPTER_OPTIONS = 0x21,
 145         BOP_INQUIRE_INST_HDEVS  = 0x23,
 146         BOP_INQUIRE_TARG_DEVS   = 0x24,
 147         BOP_DISABLE_HAC_INTR    = 0x25,
 148         BOP_INITIALIZE_32BMBOX  = 0x81,
 149         BOP_EXECUTE_SCSI_CMD    = 0x83,
 150         BOP_INQUIRE_FW_VER_3DIG = 0x84,
 151         BOP_INQUIRE_FW_VER_4DIG = 0x85,
 152         BOP_INQUIRE_PCI_INFO    = 0x86,
 153         BOP_INQUIRE_MODEL       = 0x8B,
 154         BOP_TARG_SYNC_INFO      = 0x8C,
 155         BOP_INQUIRE_ESETUP_INFO = 0x8D,
 156         BOP_ENABLE_STRICT_RR    = 0x8F,
 157         BOP_STORE_LRAM          = 0x90,
 158         BOP_FETCH_LRAM          = 0x91,
 159         BOP_SAVE_TO_EEPROM      = 0x92,
 160         BOP_UPLOAD_AUTO_SCSI    = 0x94,
 161         BOP_MODIFY_IO_ADDR      = 0x95,
 162         BOP_SET_CCB_FORMAT      = 0x96,
 163         BOP_FLASH_ROM_DOWNLOAD  = 0x97,
 164         BOP_FLASH_WRITE_ENABLE  = 0x98,
 165         BOP_WRITE_INQ_BUFFER    = 0x9A,
 166         BOP_READ_INQ_BUFFER     = 0x9B,
 167         BOP_FLASH_UP_DOWNLOAD   = 0xA7,
 168         BOP_READ_SCAM_DATA      = 0xA8,
 169         BOP_WRITE_SCAM_DATA     = 0xA9
 170 } bt_op_t;
 171
 172 /************** Definitions of Multi-byte commands and responses ************/
 173
 174 typedef struct {
 175         u_int8_t num_mboxes;
 176         u_int8_t base_addr[3];
 177 } init_24b_mbox_params_t;
 178
 179 typedef struct {
 180         u_int8_t board_type;
 181 #define         BOARD_TYPE_NON_MCA      0x41
 182 #define         BOARD_TYPE_MCA          0x42
 183         u_int8_t cust_features;
 184 #define         FEATURES_STANDARD       0x41
 185         u_int8_t firmware_rev_major;
 186         u_int8_t firmware_rev_minor;
 187 } board_id_data_t;
 188
 189 typedef struct {
 190         u_int8_t enable;
 191 } enable_ombr_intr_params_t;
 192
 193 typedef struct {
 194         u_int8_t enable;
 195         u_int8_t reserved;
 196         u_int8_t timeout[2];    /* timeout in milliseconds */
 197 } set_selto_parmas_t;
 198
 199 typedef struct {
 200         u_int8_t time;          /* time in milliseconds (2-15) */
 201 } set_timeon_bus_params_t;
 202
 203 typedef struct {
 204         u_int8_t time;          /* time in milliseconds (2-15) */
 205 } set_timeoff_bus_params_t;
 206
 207 typedef struct {
 208         u_int8_t rate;
 209 } set_bus_trasfer_rate_params_t;
 210
 211 typedef struct {
 212         u_int8_t targets[8];
 213 } installed_ldevs_data_t;
 214
 215 typedef struct {
 216         u_int8_t dma_chan;
 217 #define         DMA_CHAN_5      0x20
 218 #define         DMA_CHAN_6      0x40
 219 #define         DMA_CHAN_7      0x80
 220         u_int8_t irq;
 221 #define         IRQ_9           0x01
 222 #define         IRQ_10          0x02
 223 #define         IRQ_11          0x04
 224 #define         IRQ_12          0x08
 225 #define         IRQ_14          0x20
 226 #define         IRQ_15          0x40
 227         u_int8_t scsi_id;
 228 } config_data_t;
 229
 230 typedef struct {
 231         u_int8_t enable;
 232 } target_mode_params_t;
 233
 234 typedef struct {
 235         u_int8_t offset : 4,
 236                  period : 3,
 237                  sync   : 1;
 238 } targ_syncinfo_t;
 239
 240 typedef struct {
 241         u_int8_t        initiate_sync   : 1,
 242                         parity_enable   : 1,
 243                                         : 6;
 244
 245         u_int8_t        bus_transfer_rate;
 246         u_int8_t        time_on_bus;
 247         u_int8_t        time_off_bus;
 248         u_int8_t        num_mboxes;
 249         u_int8_t        mbox_base_addr[3];
 250         targ_syncinfo_t low_syncinfo[8];        /* For fast and ultra, use 8C */
 251         u_int8_t        low_discinfo;
 252         u_int8_t        customer_sig;
 253         u_int8_t        letter_d;
 254         u_int8_t        ha_type;
 255         u_int8_t        low_wide_allowed;
 256         u_int8_t        low_wide_active;
 257         targ_syncinfo_t high_syncinfo[8];
 258         u_int8_t        high_discinfo;
 259         u_int8_t        high_wide_allowed;
 260         u_int8_t        high_wide_active;
 261 } setup_data_t;
 262
 263 typedef struct {
 264         u_int8_t phys_addr[3];
 265 } write_adapter_lram_params_t;
 266
 267 typedef struct {
 268         u_int8_t phys_addr[3];
 269 } read_adapter_lram_params_t;
 270
 271 typedef struct {
 272         u_int8_t phys_addr[3];
 273 } write_chip_fifo_params_t;
 274
 275 typedef struct {
 276         u_int8_t phys_addr[3];
 277 } read_chip_fifo_params_t;
 278
 279 typedef struct {
 280         u_int8_t length;                /* Excludes this member */
 281         u_int8_t low_disc_disable;
 282         u_int8_t low_busy_retry_disable;
 283         u_int8_t high_disc_disable;
 284         u_int8_t high_busy_retry_disable;
 285 } set_adapter_options_params_t;
 286
 287 typedef struct {
 288         u_int8_t targets[8];
 289 } installed_hdevs_data_t;
 290
 291 typedef struct {
 292         u_int8_t low_devs;
 293         u_int8_t high_devs;
 294 } target_devs_data_t;
 295
 296 typedef struct {
 297         u_int8_t enable;
 298 } enable_hac_interrupt_params_t;
 299
 300 typedef struct {
 301         u_int8_t num_boxes;
 302         u_int8_t base_addr[4];
 303 } init_32b_mbox_params_t;
 304
 305 typedef u_int8_t fw_ver_3dig_data_t;
 306
 307 typedef u_int8_t fw_ver_4dig_data_t;
 308
 309 typedef struct  {
 310         u_int8_t offset;
 311         u_int8_t response_len;
 312 } fetch_lram_params_t;
 313
 314 #define AUTO_SCSI_BYTE_OFFSET   64
 315 typedef struct {
 316         u_int8_t        factory_sig[2];
 317         u_int8_t        auto_scsi_data_size;    /* 2 -> 64 bytes */
 318         u_int8_t        model_num[6];
 319         u_int8_t        adapter_ioport;
 320         u_int8_t        floppy_enabled   :1,
 321                         floppy_secondary :1,
 322                         level_trigger    :1,
 323                                          :2,
 324                         system_ram_area  :3;
 325         u_int8_t        dma_channel      :7,
 326                         dma_autoconf     :1;
 327         u_int8_t        irq_channel      :7,
 328                         irq_autoconf     :1;
 329         u_int8_t        dma_trans_rate;
 330         u_int8_t        scsi_id;
 331         u_int8_t        low_termination  :1,
 332                         scsi_parity      :1,
 333                         high_termination :1,
 334                         req_ack_filter   :1,
 335                         fast_sync        :1,
 336                         bus_reset        :1,
 337                                          :1,
 338                         active_negation  :1;
 339         u_int8_t        bus_on_delay;
 340         u_int8_t        bus_off_delay;
 341         u_int8_t        bios_enabled     :1,
 342                         int19h_redirect  :1,
 343                         extended_trans   :1,
 344                         removable_drives :1,
 345                                          :1,
 346                         morethan2disks   :1,
 347                         interrupt_mode   :1,
 348                         floptical_support:1;
 349         u_int8_t        low_device_enabled;
 350         u_int8_t        high_device_enabled;
 351         u_int8_t        low_wide_permitted;
 352         u_int8_t        high_wide_permitted;
 353         u_int8_t        low_fast_permitted;
 354         u_int8_t        high_fast_permitted;
 355         u_int8_t        low_sync_permitted;
 356         u_int8_t        high_sync_permitted;
 357         u_int8_t        low_disc_permitted;
 358         u_int8_t        high_disc_permitted;
 359         u_int8_t        low_send_start_unit;
 360         u_int8_t        high_send_start_unit;
 361         u_int8_t        low_ignore_in_bios_scan;
 362         u_int8_t        high_ignore_in_bios_scan;
 363         u_int8_t        pci_int_pin      :2,
 364                         host_ioport      :2,
 365                         round_robin      :1,
 366                         vesa_bus_over_33 :1,
 367                         vesa_burst_write :1,
 368                         vesa_burst_read  :1;
 369         u_int8_t        low_ultra_permitted;
 370         u_int8_t        high_ultra_permitted;
 371         u_int8_t        reserved[5];
 372         u_int8_t        auto_scsi_max_lun;
 373         u_int8_t                         :1,
 374                         scam_dominant    :1,
 375                         scam_enabled     :1,
 376                         scam_level2      :1,
 377                                          :4;
 378         u_int8_t        int13_extensions :1,
 379                                          :1,
 380                         cdrom_boot       :1,
 381                                          :2,
 382                         multi_boot       :1,
 383                                          :2;
 384         u_int8_t        boot_target_id   :4,
 385                         boot_channel     :4;
 386         u_int8_t        force_dev_scan   :1,
 387                                          :7;
 388         u_int8_t        low_tagged_lun_independance;
 389         u_int8_t        high_tagged_lun_independance;
 390         u_int8_t        low_renegotiate_after_cc;
 391         u_int8_t        high_renegotiate_after_cc;
 392         u_int8_t        reserverd2[10];
 393         u_int8_t        manufacturing_diagnotic[2];
 394         u_int8_t        checksum[2];
 395 } auto_scsi_data_t;
 396
 397 struct bt_isa_port {
 398         u_int16_t addr;
 399         u_int8_t  probed;
 400         u_int8_t  bio;
 401 };
 402
 403 extern struct bt_isa_port bt_isa_ports[];
 404
 405 #define BT_NUM_ISAPORTS 6
 406
 407 typedef enum {
 408         BIO_330         = 0,
 409         BIO_334         = 1,
 410         BIO_230         = 2,
 411         BIO_234         = 3,
 412         BIO_130         = 4,
 413         BIO_134         = 5,
 414         BIO_DISABLED    = 6,
 415         BIO_DISABLED2   = 7
 416 } isa_compat_io_t;
 417
 418 typedef struct {
 419         u_int8_t io_port;
 420         u_int8_t irq_num;
 421         u_int8_t low_byte_term  :1,
 422                  high_byte_term :1,
 423                                 :2,
 424                  jp1_status     :1,
 425                  jp2_status     :1,
 426                  jp3_status     :1,
 427                                 :1;
 428         u_int8_t reserved;
 429 } pci_info_data_t;
 430
 431 typedef struct {
 432         u_int8_t ascii_model[5];        /* Fifth byte is always 0 */
 433 } ha_model_data_t;
 434
 435 typedef struct {
 436         u_int8_t sync_rate[16];         /* Sync in 10ns units */
 437 } target_sync_info_data_t;
 438
 439 typedef struct {
 440         u_int8_t  bus_type;
 441         u_int8_t  bios_addr;
 442         u_int16_t max_sg;
 443         u_int8_t  num_mboxes;
 444         u_int8_t  mbox_base[4];
 445         u_int8_t                        :2,
 446                   sync_neg10MB          :1,
 447                   floppy_disable        :1,
 448                   floppy_secondary_port :1,
 449                   burst_mode_enabled    :1,
 450                   level_trigger_ints    :1,
 451                                         :1;
 452         u_int8_t  fw_ver_bytes_2_to_4[3];
 453         u_int8_t  wide_bus              :1,
 454                   diff_bus              :1,
 455                   scam_capable          :1,
 456                   ultra_scsi            :1,
 457                   auto_term             :1,
 458                                         :3;
 459 } esetup_info_data_t;
 460
 461 typedef struct {
 462         u_int32_t len;
 463         u_int32_t addr;
 464 } bt_sg_t;
 465
 466 /********************** Mail Box definitions *******************************/
 467
 468 typedef enum {
 469         BMBO_FREE               = 0x0,  /* MBO intry is free */
 470         BMBO_START              = 0x1,  /* MBO activate entry */
 471         BMBO_ABORT              = 0x2   /* MBO abort entry */
 472 } bt_mbo_action_code_t;
 473
 474 typedef struct bt_mbox_out {
 475         u_int32_t ccb_addr;
 476         u_int8_t  reserved[3];
 477         u_int8_t  action_code;
 478 } bt_mbox_out_t;
 479
 480 typedef enum {
 481         BMBI_FREE               = 0x0,  /* MBI entry is free */
 482         BMBI_OK                 = 0x1,  /* completed without error */
 483         BMBI_ABORT              = 0x2,  /* aborted ccb */
 484         BMBI_NOT_FOUND          = 0x3,  /* Tried to abort invalid CCB */
 485         BMBI_ERROR              = 0x4   /* Completed with error */
 486 } bt_mbi_comp_code_t;
 487
 488 typedef struct bt_mbox_in {
 489         u_int32_t ccb_addr;
 490         u_int8_t  btstat;
 491         u_int8_t  sdstat;
 492         u_int8_t  reserved;
 493         u_int8_t  comp_code;
 494 } bt_mbox_in_t;
 495
 496 /***************** Compiled Probe Information *******************************/
 497 struct bt_probe_info {
 498         int     drq;
 499         int     irq;
 500 };
 501
 502 /****************** Hardware CCB definition *********************************/
 503 typedef enum {
 504         INITIATOR_CCB           = 0x00,
 505         INITIATOR_SG_CCB        = 0x02,
 506         INITIATOR_CCB_WRESID    = 0x03,
 507         INITIATOR_SG_CCB_WRESID = 0x04,
 508         INITIATOR_BUS_DEV_RESET = 0x81
 509 } bt_ccb_opcode_t;
 510
 511 typedef enum {
 512         BTSTAT_NOERROR                  = 0x00,
 513         BTSTAT_LINKED_CMD_COMPLETE      = 0x0A,
 514         BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B,
 515         BTSTAT_DATAUNDERUN_ERROR        = 0x0C,
 516         BTSTAT_SELTIMEOUT               = 0x11,
 517         BTSTAT_DATARUN_ERROR            = 0x12,
 518         BTSTAT_UNEXPECTED_BUSFREE       = 0x13,
 519         BTSTAT_INVALID_PHASE            = 0x14,
 520         BTSTAT_INVALID_ACTION_CODE      = 0x15,
 521         BTSTAT_INVALID_OPCODE           = 0x16,
 522         BTSTAT_LINKED_CCB_LUN_MISMATCH  = 0x17,
 523         BTSTAT_INVALID_CCB_OR_SG_PARAM  = 0x1A,
 524         BTSTAT_AUTOSENSE_FAILED         = 0x1B,
 525         BTSTAT_TAGGED_MSG_REJECTED      = 0x1C,
 526         BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D,
 527         BTSTAT_HARDWARE_FAILURE         = 0x20,
 528         BTSTAT_TARGET_IGNORED_ATN       = 0x21,
 529         BTSTAT_HA_SCSI_BUS_RESET        = 0x22,
 530         BTSTAT_OTHER_SCSI_BUS_RESET     = 0x23,
 531         BTSTAT_INVALID_RECONNECT        = 0x24,
 532         BTSTAT_HA_BDR                   = 0x25,
 533         BTSTAT_ABORT_QUEUE_GENERATED    = 0x26,
 534         BTSTAT_HA_SOFTWARE_ERROR        = 0x27,
 535         BTSTAT_HA_WATCHDOG_ERROR        = 0x28,
 536         BTSTAT_SCSI_PERROR_DETECTED     = 0x30
 537 } btstat_t;
 538
 539 struct bt_hccb {
 540         u_int8_t  opcode;
 541         u_int8_t                        :3,
 542                   datain                :1,
 543                   dataout               :1,
 544                   wide_tag_enable       :1,     /* Wide Lun CCB format */
 545                   wide_tag_type         :2;     /* Wide Lun CCB format */
 546         u_int8_t  cmd_len;
 547         u_int8_t  sense_len;
 548         int32_t   data_len;                     /* residuals can be negative */
 549         u_int32_t data_addr;
 550         u_int8_t  reserved[2];
 551         u_int8_t  btstat;
 552         u_int8_t  sdstat;
 553         u_int8_t  target_id;
 554         u_int8_t  target_lun    :5,
 555                   tag_enable    :1,
 556                   tag_type      :2;
 557         u_int8_t  scsi_cdb[12];
 558         u_int8_t  reserved2[6];
 559         u_int32_t sense_addr;
 560 };
 561
 562 typedef enum {
 563         BCCB_FREE               = 0x0,
 564         BCCB_ACTIVE             = 0x1,
 565         BCCB_DEVICE_RESET       = 0x2,
 566         BCCB_RELEASE_SIMQ       = 0x4
 567 } bccb_flags_t;
 568
 569 struct bt_ccb {
 570         struct  bt_hccb          hccb;
 571         SLIST_ENTRY(bt_ccb)      links;
 572         u_int32_t                flags;
 573         union ccb               *ccb;
 574         bus_dmamap_t             dmamap;
 575         struct callout           timer;
 576         bt_sg_t                 *sg_list;
 577         u_int32_t                sg_list_phys;
 578 };
 579
 580 struct sg_map_node {
 581         bus_dmamap_t             sg_dmamap;
 582         bus_addr_t               sg_physaddr;
 583         bt_sg_t*                 sg_vaddr;
 584         SLIST_ENTRY(sg_map_node) links;
 585 };
 586
 587 struct bt_softc {
 588         device_t                dev;
 589         struct resource         *port;
 590         struct resource         *irq;
 591         struct resource         *drq;
 592         void                    *ih;
 593         struct mtx               lock;
 594         struct  cam_sim         *sim;
 595         struct  cam_path        *path;
 596         bt_mbox_out_t           *cur_outbox;
 597         bt_mbox_in_t            *cur_inbox;
 598         bt_mbox_out_t           *last_outbox;
 599         bt_mbox_in_t            *last_inbox;
 600         struct  bt_ccb          *bt_ccb_array;
 601         SLIST_HEAD(,bt_ccb)      free_bt_ccbs;
 602         LIST_HEAD(,ccb_hdr)      pending_ccbs;
 603         u_int                    active_ccbs;
 604         u_int32_t                bt_ccb_physbase;
 605         bt_mbox_in_t            *in_boxes;
 606         bt_mbox_out_t           *out_boxes;
 607         struct scsi_sense_data  *sense_buffers;
 608         u_int32_t                sense_buffers_physbase;
 609         struct  bt_ccb          *recovery_bccb;
 610         u_int                    num_boxes;
 611         bus_dma_tag_t            parent_dmat;   /*
 612                                                  * All dmat's derive from
 613                                                  * the dmat defined by our
 614                                                  * bus.
 615                                                  */
 616         bus_dma_tag_t            buffer_dmat;   /* dmat for buffer I/O */
 617         bus_dma_tag_t            mailbox_dmat;  /* dmat for our mailboxes */
 618         bus_dmamap_t             mailbox_dmamap;
 619         bus_dma_tag_t            ccb_dmat;      /* dmat for our ccb array */
 620         bus_dmamap_t             ccb_dmamap;
 621         bus_dma_tag_t            sg_dmat;       /* dmat for our sg segments */
 622         bus_dma_tag_t            sense_dmat;    /* dmat for our sense buffers */
 623         bus_dmamap_t             sense_dmamap;
 624         SLIST_HEAD(, sg_map_node) sg_maps;
 625         bus_addr_t               mailbox_physbase;
 626         bus_addr_t               mailbox_addrlimit;
 627         u_int                    num_ccbs;      /* Number of CCBs malloc'd */
 628         u_int                    max_ccbs;      /* Maximum allocatable CCBs */
 629         u_int                    max_sg;
 630         u_int                    scsi_id;
 631         u_int32_t                extended_trans    :1,
 632                                  wide_bus          :1,
 633                                  diff_bus          :1,
 634                                  ultra_scsi        :1,
 635                                  extended_lun      :1,
 636                                  strict_rr         :1,
 637                                  tag_capable       :1,
 638                                  wide_lun_ccb      :1,
 639                                  resource_shortage :1,
 640                                  level_trigger_ints:1,
 641                                                    :22;
 642         u_int16_t                tags_permitted;
 643         u_int16_t                disc_permitted;
 644         u_int16_t                sync_permitted;
 645         u_int16_t                fast_permitted;
 646         u_int16_t                ultra_permitted;
 647         u_int16_t                wide_permitted;
 648         u_int8_t                 init_level;
 649         volatile u_int8_t        command_cmp;
 650         volatile u_int8_t        latched_status;
 651         u_int32_t                bios_addr;
 652         char                     firmware_ver[6];
 653         char                     model[5];
 654 };
 655
 656 #define BT_TEMP_UNIT 0xFF               /* Unit for probes */
 657 void                    bt_init_softc(device_t dev,
 658                                       struct resource *port,
 659                                       struct resource *irq,
 660                                       struct resource *drq);
 661 void                    bt_free_softc(device_t dev);
 662 int                     bt_port_probe(device_t dev,
 663                                       struct bt_probe_info *info);
 664 int                     bt_probe(device_t dev);
 665 int                     bt_fetch_adapter_info(device_t dev);
 666 int                     bt_init(device_t dev);
 667 int                     bt_attach(device_t dev);
 668 void                    bt_intr(void *arg);
 669 int                     bt_check_probed_iop(u_int ioport);
 670 void                    bt_mark_probed_bio(isa_compat_io_t port);
 671 void                    bt_mark_probed_iop(u_int ioport);
 672 void                    bt_find_probe_range(int ioport,
 673                                             int *port_index,
 674                                             int *max_port_index);
 675
 676 int                     bt_iop_from_bio(isa_compat_io_t bio_index);
 677
 678 #define DEFAULT_CMD_TIMEOUT 100000      /* 10 sec */
 679 int                     bt_cmd(struct bt_softc *bt, bt_op_t opcode,
 680                                u_int8_t *params, u_int param_len,
 681                                u_int8_t *reply_data, u_int reply_len,
 682                                u_int cmd_timeout);
 683
 684 #define bt_name(bt)     device_get_nameunit(bt->dev)
 685
 686 #define bt_inb(bt, reg)                         \
 687         bus_read_1((bt)->port, reg)
 688
 689 #define bt_outb(bt, reg, value)                 \
 690         bus_write_1((bt)->port, reg, value)
 691
 692 #endif  /* _BT_H_ */