sys/dev/bwi/bwiphy.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-3-Clause
   3  *
   4  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
   5  *
   6  * This code is derived from software contributed to The DragonFly Project
   7  * by Sepherosa Ziehau <sepherosa@gmail.com>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  *
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in
  17  *    the documentation and/or other materials provided with the
  18  *    distribution.
  19  * 3. Neither the name of The DragonFly Project nor the names of its
  20  *    contributors may be used to endorse or promote products derived
  21  *    from this software without specific, prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  26  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
  27  * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  28  * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
  29  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  30  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  31  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  33  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  34  * SUCH DAMAGE.
  35  *
  36  * $DragonFly: src/sys/dev/netif/bwi/bwiphy.c,v 1.5 2008/01/15 09:01:13 sephe Exp $
  37  */
  38
  39 #include <sys/cdefs.h>
  40 __FBSDID("$FreeBSD$");
  41
  42 #include "opt_inet.h"
  43 #include "opt_wlan.h"
  44
  45 #include <sys/param.h>
  46 #include <sys/endian.h>
  47 #include <sys/kernel.h>
  48 #include <sys/bus.h>
  49 #include <sys/malloc.h>
  50 #include <sys/proc.h>
  51 #include <sys/rman.h>
  52 #include <sys/socket.h>
  53 #include <sys/sockio.h>
  54 #include <sys/sysctl.h>
  55 #include <sys/systm.h>
  56
  57 #include <net/if.h>
  58 #include <net/if_var.h>
  59 #include <net/if_dl.h>
  60 #include <net/if_media.h>
  61 #include <net/if_types.h>
  62 #include <net/if_arp.h>
  63 #include <net/ethernet.h>
  64 #include <net/if_llc.h>
  65
  66 #include <net80211/ieee80211_var.h>
  67 #include <net80211/ieee80211_radiotap.h>
  68 #include <net80211/ieee80211_amrr.h>
  69
  70 #include <machine/bus.h>
  71
  72 #include <dev/bwi/bitops.h>
  73 #include <dev/bwi/if_bwireg.h>
  74 #include <dev/bwi/if_bwivar.h>
  75 #include <dev/bwi/bwimac.h>
  76 #include <dev/bwi/bwirf.h>
  77 #include <dev/bwi/bwiphy.h>
  78
  79 static void     bwi_phy_init_11a(struct bwi_mac *);
  80 static void     bwi_phy_init_11g(struct bwi_mac *);
  81 static void     bwi_phy_init_11b_rev2(struct bwi_mac *);
  82 static void     bwi_phy_init_11b_rev4(struct bwi_mac *);
  83 static void     bwi_phy_init_11b_rev5(struct bwi_mac *);
  84 static void     bwi_phy_init_11b_rev6(struct bwi_mac *);
  85
  86 static void     bwi_phy_config_11g(struct bwi_mac *);
  87 static void     bwi_phy_config_agc(struct bwi_mac *);
  88
  89 static void     bwi_tbl_write_2(struct bwi_mac *mac, uint16_t, uint16_t);
  90 static void     bwi_tbl_write_4(struct bwi_mac *mac, uint16_t, uint32_t);
  91 #define SUP_BPHY(num)   { .rev = num, .init = bwi_phy_init_11b_rev##num }
  92
  93 static const struct {
  94         uint8_t rev;
  95         void    (*init)(struct bwi_mac *);
  96 } bwi_sup_bphy[] = {
  97         SUP_BPHY(2),
  98         SUP_BPHY(4),
  99         SUP_BPHY(5),
 100         SUP_BPHY(6)
 101 };
 102
 103 #undef SUP_BPHY
 104
 105 #define BWI_PHYTBL_WRSSI        0x1000
 106 #define BWI_PHYTBL_NOISE_SCALE  0x1400
 107 #define BWI_PHYTBL_NOISE        0x1800
 108 #define BWI_PHYTBL_ROTOR        0x2000
 109 #define BWI_PHYTBL_DELAY        0x2400
 110 #define BWI_PHYTBL_RSSI         0x4000
 111 #define BWI_PHYTBL_SIGMA_SQ     0x5000
 112 #define BWI_PHYTBL_WRSSI_REV1   0x5400
 113 #define BWI_PHYTBL_FREQ         0x5800
 114
 115 static const uint16_t   bwi_phy_freq_11g_rev1[] =
 116         { BWI_PHY_FREQ_11G_REV1 };
 117 static const uint16_t   bwi_phy_noise_11g_rev1[] =
 118         { BWI_PHY_NOISE_11G_REV1 };
 119 static const uint16_t   bwi_phy_noise_11g[] =
 120         { BWI_PHY_NOISE_11G };
 121 static const uint32_t   bwi_phy_rotor_11g_rev1[] =
 122         { BWI_PHY_ROTOR_11G_REV1 };
 123 static const uint16_t   bwi_phy_noise_scale_11g_rev2[] =
 124         { BWI_PHY_NOISE_SCALE_11G_REV2 };
 125 static const uint16_t   bwi_phy_noise_scale_11g_rev7[] =
 126         { BWI_PHY_NOISE_SCALE_11G_REV7 };
 127 static const uint16_t   bwi_phy_noise_scale_11g[] =
 128         { BWI_PHY_NOISE_SCALE_11G };
 129 static const uint16_t   bwi_phy_sigma_sq_11g_rev2[] =
 130         { BWI_PHY_SIGMA_SQ_11G_REV2 };
 131 static const uint16_t   bwi_phy_sigma_sq_11g_rev7[] =
 132         { BWI_PHY_SIGMA_SQ_11G_REV7 };
 133 static const uint32_t   bwi_phy_delay_11g_rev1[] =
 134         { BWI_PHY_DELAY_11G_REV1 };
 135
 136 void
 137 bwi_phy_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
 138 {
 139         struct bwi_softc *sc = mac->mac_sc;
 140
 141         CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
 142         CSR_WRITE_2(sc, BWI_PHY_DATA, data);
 143 }
 144
 145 uint16_t
 146 bwi_phy_read(struct bwi_mac *mac, uint16_t ctrl)
 147 {
 148         struct bwi_softc *sc = mac->mac_sc;
 149
 150         CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl);
 151         return CSR_READ_2(sc, BWI_PHY_DATA);
 152 }
 153
 154 int
 155 bwi_phy_attach(struct bwi_mac *mac)
 156 {
 157         struct bwi_softc *sc = mac->mac_sc;
 158         struct bwi_phy *phy = &mac->mac_phy;
 159         uint8_t phyrev, phytype, phyver;
 160         uint16_t val;
 161         int i;
 162
 163         /* Get PHY type/revision/version */
 164         val = CSR_READ_2(sc, BWI_PHYINFO);
 165         phyrev = __SHIFTOUT(val, BWI_PHYINFO_REV_MASK);
 166         phytype = __SHIFTOUT(val, BWI_PHYINFO_TYPE_MASK);
 167         phyver = __SHIFTOUT(val, BWI_PHYINFO_VER_MASK);
 168         device_printf(sc->sc_dev, "PHY: type %d, rev %d, ver %d\n",
 169                       phytype, phyrev, phyver);
 170
 171         /*
 172          * Verify whether the revision of the PHY type is supported
 173          * Convert PHY type to ieee80211_phymode
 174          */
 175         switch (phytype) {
 176         case BWI_PHYINFO_TYPE_11A:
 177                 if (phyrev >= 4) {
 178                         device_printf(sc->sc_dev, "unsupported 11A PHY, "
 179                                       "rev %u\n", phyrev);
 180                         return ENXIO;
 181                 }
 182                 phy->phy_init = bwi_phy_init_11a;
 183                 phy->phy_mode = IEEE80211_MODE_11A;
 184                 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11A;
 185                 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11A;
 186                 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11A;
 187                 break;
 188         case BWI_PHYINFO_TYPE_11B:
 189                 for (i = 0; i < nitems(bwi_sup_bphy); ++i) {
 190                         if (phyrev == bwi_sup_bphy[i].rev) {
 191                                 phy->phy_init = bwi_sup_bphy[i].init;
 192                                 break;
 193                         }
 194                 }
 195                 if (i == nitems(bwi_sup_bphy)) {
 196                         device_printf(sc->sc_dev, "unsupported 11B PHY, "
 197                                       "rev %u\n", phyrev);
 198                         return ENXIO;
 199                 }
 200                 phy->phy_mode = IEEE80211_MODE_11B;
 201                 break;
 202         case BWI_PHYINFO_TYPE_11G:
 203                 if (phyrev > 8) {
 204                         device_printf(sc->sc_dev, "unsupported 11G PHY, "
 205                                       "rev %u\n", phyrev);
 206                         return ENXIO;
 207                 }
 208                 phy->phy_init = bwi_phy_init_11g;
 209                 phy->phy_mode = IEEE80211_MODE_11G;
 210                 phy->phy_tbl_ctrl = BWI_PHYR_TBL_CTRL_11G;
 211                 phy->phy_tbl_data_lo = BWI_PHYR_TBL_DATA_LO_11G;
 212                 phy->phy_tbl_data_hi = BWI_PHYR_TBL_DATA_HI_11G;
 213                 break;
 214         default:
 215                 device_printf(sc->sc_dev, "unsupported PHY type %d\n",
 216                               phytype);
 217                 return ENXIO;
 218         }
 219         phy->phy_rev = phyrev;
 220         phy->phy_version = phyver;
 221         return 0;
 222 }
 223
 224 void
 225 bwi_phy_set_bbp_atten(struct bwi_mac *mac, uint16_t bbp_atten)
 226 {
 227         struct bwi_phy *phy = &mac->mac_phy;
 228         uint16_t mask = __BITS(3, 0);
 229
 230         if (phy->phy_version == 0) {
 231                 CSR_FILT_SETBITS_2(mac->mac_sc, BWI_BBP_ATTEN, ~mask,
 232                                    __SHIFTIN(bbp_atten, mask));
 233         } else {
 234                 if (phy->phy_version > 1)
 235                         mask <<= 2;
 236                 else
 237                         mask <<= 3;
 238                 PHY_FILT_SETBITS(mac, BWI_PHYR_BBP_ATTEN, ~mask,
 239                                  __SHIFTIN(bbp_atten, mask));
 240         }
 241 }
 242
 243 int
 244 bwi_phy_calibrate(struct bwi_mac *mac)
 245 {
 246         struct bwi_phy *phy = &mac->mac_phy;
 247
 248         /* Dummy read */
 249         CSR_READ_4(mac->mac_sc, BWI_MAC_STATUS);
 250
 251         /* Don't re-init */
 252         if (phy->phy_flags & BWI_PHY_F_CALIBRATED)
 253                 return 0;
 254
 255         if (phy->phy_mode == IEEE80211_MODE_11G && phy->phy_rev == 1) {
 256                 bwi_mac_reset(mac, 0);
 257                 bwi_phy_init_11g(mac);
 258                 bwi_mac_reset(mac, 1);
 259         }
 260
 261         phy->phy_flags |= BWI_PHY_F_CALIBRATED;
 262         return 0;
 263 }
 264
 265 static void
 266 bwi_tbl_write_2(struct bwi_mac *mac, uint16_t ofs, uint16_t data)
 267 {
 268         struct bwi_phy *phy = &mac->mac_phy;
 269
 270         KASSERT(phy->phy_tbl_ctrl != 0 && phy->phy_tbl_data_lo != 0,
 271            ("phy_tbl_ctrl %d phy_tbl_data_lo %d",
 272              phy->phy_tbl_ctrl, phy->phy_tbl_data_lo));
 273         PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
 274         PHY_WRITE(mac, phy->phy_tbl_data_lo, data);
 275 }
 276
 277 static void
 278 bwi_tbl_write_4(struct bwi_mac *mac, uint16_t ofs, uint32_t data)
 279 {
 280         struct bwi_phy *phy = &mac->mac_phy;
 281
 282         KASSERT(phy->phy_tbl_data_lo != 0 && phy->phy_tbl_data_hi != 0 &&
 283                  phy->phy_tbl_ctrl != 0,
 284             ("phy_tbl_data_lo %d phy_tbl_data_hi %d phy_tbl_ctrl %d",
 285               phy->phy_tbl_data_lo, phy->phy_tbl_data_hi, phy->phy_tbl_ctrl));
 286
 287         PHY_WRITE(mac, phy->phy_tbl_ctrl, ofs);
 288         PHY_WRITE(mac, phy->phy_tbl_data_hi, data >> 16);
 289         PHY_WRITE(mac, phy->phy_tbl_data_lo, data & 0xffff);
 290 }
 291
 292 void
 293 bwi_nrssi_write(struct bwi_mac *mac, uint16_t ofs, int16_t data)
 294 {
 295         PHY_WRITE(mac, BWI_PHYR_NRSSI_CTRL, ofs);
 296         PHY_WRITE(mac, BWI_PHYR_NRSSI_DATA, (uint16_t)data);
 297 }
 298
 299 int16_t
 300 bwi_nrssi_read(struct bwi_mac *mac, uint16_t ofs)
 301 {
 302         PHY_WRITE(mac, BWI_PHYR_NRSSI_CTRL, ofs);
 303         return (int16_t)PHY_READ(mac, BWI_PHYR_NRSSI_DATA);
 304 }
 305
 306 static void
 307 bwi_phy_init_11a(struct bwi_mac *mac)
 308 {
 309         /* TODO:11A */
 310 }
 311
 312 static void
 313 bwi_phy_init_11g(struct bwi_mac *mac)
 314 {
 315         struct bwi_softc *sc = mac->mac_sc;
 316         struct bwi_phy *phy = &mac->mac_phy;
 317         struct bwi_rf *rf = &mac->mac_rf;
 318         const struct bwi_tpctl *tpctl = &mac->mac_tpctl;
 319
 320         if (phy->phy_rev == 1)
 321                 bwi_phy_init_11b_rev5(mac);
 322         else
 323                 bwi_phy_init_11b_rev6(mac);
 324
 325         if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED))
 326                 bwi_phy_config_11g(mac);
 327
 328         if (phy->phy_rev >= 2) {
 329                 PHY_WRITE(mac, 0x814, 0);
 330                 PHY_WRITE(mac, 0x815, 0);
 331
 332                 if (phy->phy_rev == 2) {
 333                         PHY_WRITE(mac, 0x811, 0);
 334                         PHY_WRITE(mac, 0x15, 0xc0);
 335                 } else if (phy->phy_rev > 5) {
 336                         PHY_WRITE(mac, 0x811, 0x400);
 337                         PHY_WRITE(mac, 0x15, 0xc0);
 338                 }
 339         }
 340
 341         if (phy->phy_rev >= 2 || (phy->phy_flags & BWI_PHY_F_LINKED)) {
 342                 uint16_t val;
 343
 344                 val = PHY_READ(mac, 0x400) & 0xff;
 345                 if (val == 3 || val == 5) {
 346                         PHY_WRITE(mac, 0x4c2, 0x1816);
 347                         PHY_WRITE(mac, 0x4c3, 0x8006);
 348                         if (val == 5) {
 349                                 PHY_FILT_SETBITS(mac, 0x4cc,
 350                                                  0xff, 0x1f00);
 351                         }
 352                 }
 353         }
 354
 355         if ((phy->phy_rev <= 2 && (phy->phy_flags & BWI_PHY_F_LINKED)) ||
 356             phy->phy_rev >= 2)
 357                 PHY_WRITE(mac, 0x47e, 0x78);
 358
 359         if (rf->rf_rev == 8) {
 360                 PHY_SETBITS(mac, 0x801, 0x80);
 361                 PHY_SETBITS(mac, 0x43e, 0x4);
 362         }
 363
 364         if (phy->phy_rev >= 2 && (phy->phy_flags & BWI_PHY_F_LINKED))
 365                 bwi_rf_get_gains(mac);
 366
 367         if (rf->rf_rev != 8)
 368                 bwi_rf_init(mac);
 369
 370         if (tpctl->tp_ctrl2 == 0xffff) {
 371                 bwi_rf_lo_update(mac);
 372         } else {
 373                 if (rf->rf_type == BWI_RF_T_BCM2050 && rf->rf_rev == 8) {
 374                         RF_WRITE(mac, 0x52,
 375                                  (tpctl->tp_ctrl1 << 4) | tpctl->tp_ctrl2);
 376                 } else {
 377                         RF_FILT_SETBITS(mac, 0x52, 0xfff0, tpctl->tp_ctrl2);
 378                 }
 379
 380                 if (phy->phy_rev >= 6) {
 381                         PHY_FILT_SETBITS(mac, 0x36, 0xfff,
 382                                          tpctl->tp_ctrl2 << 12);
 383                 }
 384
 385                 if (sc->sc_card_flags & BWI_CARD_F_PA_GPIO9)
 386                         PHY_WRITE(mac, 0x2e, 0x8075);
 387                 else
 388                         PHY_WRITE(mac, 0x2e, 0x807f);
 389
 390                 if (phy->phy_rev < 2)
 391                         PHY_WRITE(mac, 0x2f, 0x101);
 392                 else
 393                         PHY_WRITE(mac, 0x2f, 0x202);
 394         }
 395
 396         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 397                 bwi_rf_lo_adjust(mac, tpctl);
 398                 PHY_WRITE(mac, 0x80f, 0x8078);
 399         }
 400
 401         if ((sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
 402                 bwi_rf_init_hw_nrssi_table(mac, 0xffff /* XXX */);
 403                 bwi_rf_set_nrssi_thr(mac);
 404         } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 405                 if (rf->rf_nrssi[0] == BWI_INVALID_NRSSI) {
 406                         KASSERT(rf->rf_nrssi[1] == BWI_INVALID_NRSSI,
 407                             ("rf_nrssi[1] %d", rf->rf_nrssi[1]));
 408                         bwi_rf_calc_nrssi_slope(mac);
 409                 } else {
 410                         KASSERT(rf->rf_nrssi[1] != BWI_INVALID_NRSSI,
 411                             ("rf_nrssi[1] %d", rf->rf_nrssi[1]));
 412                         bwi_rf_set_nrssi_thr(mac);
 413                 }
 414         }
 415
 416         if (rf->rf_rev == 8)
 417                 PHY_WRITE(mac, 0x805, 0x3230);
 418
 419         bwi_mac_init_tpctl_11bg(mac);
 420
 421         if (sc->sc_bbp_id == BWI_BBPID_BCM4306 && sc->sc_bbp_pkg == 2) {
 422                 PHY_CLRBITS(mac, 0x429, 0x4000);
 423                 PHY_CLRBITS(mac, 0x4c3, 0x8000);
 424         }
 425 }
 426
 427 static void
 428 bwi_phy_init_11b_rev2(struct bwi_mac *mac)
 429 {
 430         /* TODO:11B */
 431         device_printf(mac->mac_sc->sc_dev,
 432                   "%s is not implemented yet\n", __func__);
 433 }
 434
 435 static void
 436 bwi_phy_init_11b_rev4(struct bwi_mac *mac)
 437 {
 438         struct bwi_softc *sc = mac->mac_sc;
 439         struct bwi_rf *rf = &mac->mac_rf;
 440         uint16_t val, ofs;
 441         u_int chan;
 442
 443         CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
 444
 445         PHY_WRITE(mac, 0x20, 0x301c);
 446         PHY_WRITE(mac, 0x26, 0);
 447         PHY_WRITE(mac, 0x30, 0xc6);
 448         PHY_WRITE(mac, 0x88, 0x3e00);
 449
 450         for (ofs = 0, val = 0x3c3d; ofs < 30; ++ofs, val -= 0x202)
 451                 PHY_WRITE(mac, 0x89 + ofs, val);
 452
 453         CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
 454
 455         chan = rf->rf_curchan;
 456         if (chan == IEEE80211_CHAN_ANY)
 457                 chan = 6;       /* Force to channel 6 */
 458         bwi_rf_set_chan(mac, chan, 0);
 459
 460         if (rf->rf_type != BWI_RF_T_BCM2050) {
 461                 RF_WRITE(mac, 0x75, 0x80);
 462                 RF_WRITE(mac, 0x79, 0x81);
 463         }
 464
 465         RF_WRITE(mac, 0x50, 0x20);
 466         RF_WRITE(mac, 0x50, 0x23);
 467
 468         if (rf->rf_type == BWI_RF_T_BCM2050) {
 469                 RF_WRITE(mac, 0x50, 0x20);
 470                 RF_WRITE(mac, 0x5a, 0x70);
 471                 RF_WRITE(mac, 0x5b, 0x7b);
 472                 RF_WRITE(mac, 0x5c, 0xb0);
 473                 RF_WRITE(mac, 0x7a, 0xf);
 474                 PHY_WRITE(mac, 0x38, 0x677);
 475                 bwi_rf_init_bcm2050(mac);
 476         }
 477
 478         PHY_WRITE(mac, 0x14, 0x80);
 479         PHY_WRITE(mac, 0x32, 0xca);
 480         if (rf->rf_type == BWI_RF_T_BCM2050)
 481                 PHY_WRITE(mac, 0x32, 0xe0);
 482         PHY_WRITE(mac, 0x35, 0x7c2);
 483
 484         bwi_rf_lo_update(mac);
 485
 486         PHY_WRITE(mac, 0x26, 0xcc00);
 487         if (rf->rf_type == BWI_RF_T_BCM2050)
 488                 PHY_WRITE(mac, 0x26, 0xce00);
 489
 490         CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100);
 491
 492         PHY_WRITE(mac, 0x2a, 0x88a3);
 493         if (rf->rf_type == BWI_RF_T_BCM2050)
 494                 PHY_WRITE(mac, 0x2a, 0x88c2);
 495
 496         bwi_mac_set_tpctl_11bg(mac, NULL);
 497         if (sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
 498                 bwi_rf_calc_nrssi_slope(mac);
 499                 bwi_rf_set_nrssi_thr(mac);
 500         }
 501         bwi_mac_init_tpctl_11bg(mac);
 502 }
 503
 504 static void
 505 bwi_phy_init_11b_rev5(struct bwi_mac *mac)
 506 {
 507         struct bwi_softc *sc = mac->mac_sc;
 508         struct bwi_rf *rf = &mac->mac_rf;
 509         struct bwi_phy *phy = &mac->mac_phy;
 510         u_int orig_chan;
 511
 512         if (phy->phy_version == 1)
 513                 RF_SETBITS(mac, 0x7a, 0x50);
 514
 515         if (sc->sc_pci_subvid != PCI_VENDOR_BROADCOM &&
 516             sc->sc_pci_subdid != BWI_PCI_SUBDEVICE_BU4306) {
 517                 uint16_t ofs, val;
 518
 519                 val = 0x2120;
 520                 for (ofs = 0xa8; ofs < 0xc7; ++ofs) {
 521                         PHY_WRITE(mac, ofs, val);
 522                         val += 0x202;
 523                 }
 524         }
 525
 526         PHY_FILT_SETBITS(mac, 0x35, 0xf0ff, 0x700);
 527
 528         if (rf->rf_type == BWI_RF_T_BCM2050)
 529                 PHY_WRITE(mac, 0x38, 0x667);
 530
 531         if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
 532                 if (rf->rf_type == BWI_RF_T_BCM2050) {
 533                         RF_SETBITS(mac, 0x7a, 0x20);
 534                         RF_SETBITS(mac, 0x51, 0x4);
 535                 }
 536
 537                 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0);
 538
 539                 PHY_SETBITS(mac, 0x802, 0x100);
 540                 PHY_SETBITS(mac, 0x42b, 0x2000);
 541                 PHY_WRITE(mac, 0x1c, 0x186a);
 542
 543                 PHY_FILT_SETBITS(mac, 0x13, 0xff, 0x1900);
 544                 PHY_FILT_SETBITS(mac, 0x35, 0xffc0, 0x64);
 545                 PHY_FILT_SETBITS(mac, 0x5d, 0xff80, 0xa);
 546         }
 547
 548         /* TODO: bad_frame_preempt? */
 549
 550         if (phy->phy_version == 1) {
 551                 PHY_WRITE(mac, 0x26, 0xce00);
 552                 PHY_WRITE(mac, 0x21, 0x3763);
 553                 PHY_WRITE(mac, 0x22, 0x1bc3);
 554                 PHY_WRITE(mac, 0x23, 0x6f9);
 555                 PHY_WRITE(mac, 0x24, 0x37e);
 556         } else {
 557                 PHY_WRITE(mac, 0x26, 0xcc00);
 558         }
 559         PHY_WRITE(mac, 0x30, 0xc6);
 560
 561         CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT);
 562
 563         if (phy->phy_version == 1)
 564                 PHY_WRITE(mac, 0x20, 0x3e1c);
 565         else
 566                 PHY_WRITE(mac, 0x20, 0x301c);
 567
 568         if (phy->phy_version == 0)
 569                 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1);
 570
 571         /* Force to channel 7 */
 572         orig_chan = rf->rf_curchan;
 573         bwi_rf_set_chan(mac, 7, 0);
 574
 575         if (rf->rf_type != BWI_RF_T_BCM2050) {
 576                 RF_WRITE(mac, 0x75, 0x80);
 577                 RF_WRITE(mac, 0x79, 0x81);
 578         }
 579
 580         RF_WRITE(mac, 0x50, 0x20);
 581         RF_WRITE(mac, 0x50, 0x23);
 582
 583         if (rf->rf_type == BWI_RF_T_BCM2050) {
 584                 RF_WRITE(mac, 0x50, 0x20);
 585                 RF_WRITE(mac, 0x5a, 0x70);
 586         }
 587
 588         RF_WRITE(mac, 0x5b, 0x7b);
 589         RF_WRITE(mac, 0x5c, 0xb0);
 590         RF_SETBITS(mac, 0x7a, 0x7);
 591
 592         bwi_rf_set_chan(mac, orig_chan, 0);
 593
 594         PHY_WRITE(mac, 0x14, 0x80);
 595         PHY_WRITE(mac, 0x32, 0xca);
 596         PHY_WRITE(mac, 0x2a, 0x88a3);
 597
 598         bwi_mac_set_tpctl_11bg(mac, NULL);
 599
 600         if (rf->rf_type == BWI_RF_T_BCM2050)
 601                 RF_WRITE(mac, 0x5d, 0xd);
 602
 603         CSR_FILT_SETBITS_2(sc, BWI_PHY_MAGIC_REG1, 0xffc0, 0x4);
 604 }
 605
 606 static void
 607 bwi_phy_init_11b_rev6(struct bwi_mac *mac)
 608 {
 609         struct bwi_softc *sc = mac->mac_sc;
 610         struct bwi_rf *rf = &mac->mac_rf;
 611         struct bwi_phy *phy = &mac->mac_phy;
 612         uint16_t val, ofs;
 613         u_int orig_chan;
 614
 615         PHY_WRITE(mac, 0x3e, 0x817a);
 616         RF_SETBITS(mac, 0x7a, 0x58);
 617
 618         if (rf->rf_rev == 4 || rf->rf_rev == 5) {
 619                 RF_WRITE(mac, 0x51, 0x37);
 620                 RF_WRITE(mac, 0x52, 0x70);
 621                 RF_WRITE(mac, 0x53, 0xb3);
 622                 RF_WRITE(mac, 0x54, 0x9b);
 623                 RF_WRITE(mac, 0x5a, 0x88);
 624                 RF_WRITE(mac, 0x5b, 0x88);
 625                 RF_WRITE(mac, 0x5d, 0x88);
 626                 RF_WRITE(mac, 0x5e, 0x88);
 627                 RF_WRITE(mac, 0x7d, 0x88);
 628                 HFLAGS_SETBITS(mac, BWI_HFLAG_MAGIC1);
 629         } else if (rf->rf_rev == 8) {
 630                 RF_WRITE(mac, 0x51, 0);
 631                 RF_WRITE(mac, 0x52, 0x40);
 632                 RF_WRITE(mac, 0x53, 0xb7);
 633                 RF_WRITE(mac, 0x54, 0x98);
 634                 RF_WRITE(mac, 0x5a, 0x88);
 635                 RF_WRITE(mac, 0x5b, 0x6b);
 636                 RF_WRITE(mac, 0x5c, 0xf);
 637                 if (sc->sc_card_flags & BWI_CARD_F_ALT_IQ) {
 638                         RF_WRITE(mac, 0x5d, 0xfa);
 639                         RF_WRITE(mac, 0x5e, 0xd8);
 640                 } else {
 641                         RF_WRITE(mac, 0x5d, 0xf5);
 642                         RF_WRITE(mac, 0x5e, 0xb8);
 643                 }
 644                 RF_WRITE(mac, 0x73, 0x3);
 645                 RF_WRITE(mac, 0x7d, 0xa8);
 646                 RF_WRITE(mac, 0x7c, 0x1);
 647                 RF_WRITE(mac, 0x7e, 0x8);
 648         }
 649
 650         val = 0x1e1f;
 651         for (ofs = 0x88; ofs < 0x98; ++ofs) {
 652                 PHY_WRITE(mac, ofs, val);
 653                 val -= 0x202;
 654         }
 655
 656         val = 0x3e3f;
 657         for (ofs = 0x98; ofs < 0xa8; ++ofs) {
 658                 PHY_WRITE(mac, ofs, val);
 659                 val -= 0x202;
 660         }
 661
 662         val = 0x2120;
 663         for (ofs = 0xa8; ofs < 0xc8; ++ofs) {
 664                 PHY_WRITE(mac, ofs, (val & 0x3f3f));
 665                 val += 0x202;
 666
 667                 /* XXX: delay 10 us to avoid PCI parity errors with BCM4318 */
 668                 DELAY(10);
 669         }
 670
 671         if (phy->phy_mode == IEEE80211_MODE_11G) {
 672                 RF_SETBITS(mac, 0x7a, 0x20);
 673                 RF_SETBITS(mac, 0x51, 0x4);
 674                 PHY_SETBITS(mac, 0x802, 0x100);
 675                 PHY_SETBITS(mac, 0x42b, 0x2000);
 676                 PHY_WRITE(mac, 0x5b, 0);
 677                 PHY_WRITE(mac, 0x5c, 0);
 678         }
 679
 680         /* Force to channel 7 */
 681         orig_chan = rf->rf_curchan;
 682         if (orig_chan >= 8)
 683                 bwi_rf_set_chan(mac, 1, 0);
 684         else
 685                 bwi_rf_set_chan(mac, 13, 0);
 686
 687         RF_WRITE(mac, 0x50, 0x20);
 688         RF_WRITE(mac, 0x50, 0x23);
 689
 690         DELAY(40);
 691
 692         if (rf->rf_rev < 6 || rf->rf_rev == 8) {
 693                 RF_SETBITS(mac, 0x7c, 0x2);
 694                 RF_WRITE(mac, 0x50, 0x20);
 695         }
 696         if (rf->rf_rev <= 2) {
 697                 RF_WRITE(mac, 0x7c, 0x20);
 698                 RF_WRITE(mac, 0x5a, 0x70);
 699                 RF_WRITE(mac, 0x5b, 0x7b);
 700                 RF_WRITE(mac, 0x5c, 0xb0);
 701         }
 702
 703         RF_FILT_SETBITS(mac, 0x7a, 0xf8, 0x7);
 704
 705         bwi_rf_set_chan(mac, orig_chan, 0);
 706
 707         PHY_WRITE(mac, 0x14, 0x200);
 708         if (rf->rf_rev >= 6)
 709                 PHY_WRITE(mac, 0x2a, 0x88c2);
 710         else
 711                 PHY_WRITE(mac, 0x2a, 0x8ac0);
 712         PHY_WRITE(mac, 0x38, 0x668);
 713
 714         bwi_mac_set_tpctl_11bg(mac, NULL);
 715
 716         if (rf->rf_rev <= 5) {
 717                 PHY_FILT_SETBITS(mac, 0x5d, 0xff80, 0x3);
 718                 if (rf->rf_rev <= 2)
 719                         RF_WRITE(mac, 0x5d, 0xd);
 720         }
 721
 722         if (phy->phy_version == 4) {
 723                 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2);
 724                 PHY_CLRBITS(mac, 0x61, 0xf000);
 725         } else {
 726                 PHY_FILT_SETBITS(mac, 0x2, 0xffc0, 0x4);
 727         }
 728
 729         if (phy->phy_mode == IEEE80211_MODE_11B) {
 730                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC2);
 731                 PHY_WRITE(mac, 0x16, 0x410);
 732                 PHY_WRITE(mac, 0x17, 0x820);
 733                 PHY_WRITE(mac, 0x62, 0x7);
 734
 735                 bwi_rf_init_bcm2050(mac);
 736                 bwi_rf_lo_update(mac);
 737                 if (sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
 738                         bwi_rf_calc_nrssi_slope(mac);
 739                         bwi_rf_set_nrssi_thr(mac);
 740                 }
 741                 bwi_mac_init_tpctl_11bg(mac);
 742         } else {
 743                 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0);
 744         }
 745 }
 746
 747 static void
 748 bwi_phy_config_11g(struct bwi_mac *mac)
 749 {
 750         struct bwi_softc *sc = mac->mac_sc;
 751         struct bwi_phy *phy = &mac->mac_phy;
 752         const uint16_t *tbl;
 753         uint16_t wrd_ofs1, wrd_ofs2;
 754         int i, n;
 755
 756         if (phy->phy_rev == 1) {
 757                 PHY_WRITE(mac, 0x406, 0x4f19);
 758                 PHY_FILT_SETBITS(mac, 0x429, 0xfc3f, 0x340);
 759                 PHY_WRITE(mac, 0x42c, 0x5a);
 760                 PHY_WRITE(mac, 0x427, 0x1a);
 761
 762                 /* Fill frequency table */
 763                 for (i = 0; i < nitems(bwi_phy_freq_11g_rev1); ++i) {
 764                         bwi_tbl_write_2(mac, BWI_PHYTBL_FREQ + i,
 765                                         bwi_phy_freq_11g_rev1[i]);
 766                 }
 767
 768                 /* Fill noise table */
 769                 for (i = 0; i < nitems(bwi_phy_noise_11g_rev1); ++i) {
 770                         bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE + i,
 771                                         bwi_phy_noise_11g_rev1[i]);
 772                 }
 773
 774                 /* Fill rotor table */
 775                 for (i = 0; i < nitems(bwi_phy_rotor_11g_rev1); ++i) {
 776                         /* NB: data length is 4 bytes */
 777                         bwi_tbl_write_4(mac, BWI_PHYTBL_ROTOR + i,
 778                                         bwi_phy_rotor_11g_rev1[i]);
 779                 }
 780         } else {
 781                 bwi_nrssi_write(mac, 0xba98, (int16_t)0x7654); /* XXX */
 782
 783                 if (phy->phy_rev == 2) {
 784                         PHY_WRITE(mac, 0x4c0, 0x1861);
 785                         PHY_WRITE(mac, 0x4c1, 0x271);
 786                 } else if (phy->phy_rev > 2) {
 787                         PHY_WRITE(mac, 0x4c0, 0x98);
 788                         PHY_WRITE(mac, 0x4c1, 0x70);
 789                         PHY_WRITE(mac, 0x4c9, 0x80);
 790                 }
 791                 PHY_SETBITS(mac, 0x42b, 0x800);
 792
 793                 /* Fill RSSI table */
 794                 for (i = 0; i < 64; ++i)
 795                         bwi_tbl_write_2(mac, BWI_PHYTBL_RSSI + i, i);
 796
 797                 /* Fill noise table */
 798                 for (i = 0; i < nitems(bwi_phy_noise_11g); ++i) {
 799                         bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE + i,
 800                                         bwi_phy_noise_11g[i]);
 801                 }
 802         }
 803
 804         /*
 805          * Fill noise scale table
 806          */
 807         if (phy->phy_rev <= 2) {
 808                 tbl = bwi_phy_noise_scale_11g_rev2;
 809                 n = nitems(bwi_phy_noise_scale_11g_rev2);
 810         } else if (phy->phy_rev >= 7 && (PHY_READ(mac, 0x449) & 0x200)) {
 811                 tbl = bwi_phy_noise_scale_11g_rev7;
 812                 n = nitems(bwi_phy_noise_scale_11g_rev7);
 813         } else {
 814                 tbl = bwi_phy_noise_scale_11g;
 815                 n = nitems(bwi_phy_noise_scale_11g);
 816         }
 817         for (i = 0; i < n; ++i)
 818                 bwi_tbl_write_2(mac, BWI_PHYTBL_NOISE_SCALE + i, tbl[i]);
 819
 820         /*
 821          * Fill sigma square table
 822          */
 823         if (phy->phy_rev == 2) {
 824                 tbl = bwi_phy_sigma_sq_11g_rev2;
 825                 n = nitems(bwi_phy_sigma_sq_11g_rev2);
 826         } else if (phy->phy_rev > 2 && phy->phy_rev <= 8) {
 827                 tbl = bwi_phy_sigma_sq_11g_rev7;
 828                 n = nitems(bwi_phy_sigma_sq_11g_rev7);
 829         } else {
 830                 tbl = NULL;
 831                 n = 0;
 832         }
 833         for (i = 0; i < n; ++i)
 834                 bwi_tbl_write_2(mac, BWI_PHYTBL_SIGMA_SQ + i, tbl[i]);
 835
 836         if (phy->phy_rev == 1) {
 837                 /* Fill delay table */
 838                 for (i = 0; i < nitems(bwi_phy_delay_11g_rev1); ++i) {
 839                         bwi_tbl_write_4(mac, BWI_PHYTBL_DELAY + i,
 840                                         bwi_phy_delay_11g_rev1[i]);
 841                 }
 842
 843                 /* Fill WRSSI (Wide-Band RSSI) table */
 844                 for (i = 4; i < 20; ++i)
 845                         bwi_tbl_write_2(mac, BWI_PHYTBL_WRSSI_REV1 + i, 0x20);
 846
 847                 bwi_phy_config_agc(mac);
 848
 849                 wrd_ofs1 = 0x5001;
 850                 wrd_ofs2 = 0x5002;
 851         } else {
 852                 /* Fill WRSSI (Wide-Band RSSI) table */
 853                 for (i = 0; i < 0x20; ++i)
 854                         bwi_tbl_write_2(mac, BWI_PHYTBL_WRSSI + i, 0x820);
 855
 856                 bwi_phy_config_agc(mac);
 857
 858                 PHY_READ(mac, 0x400);   /* Dummy read */
 859                 PHY_WRITE(mac, 0x403, 0x1000);
 860                 bwi_tbl_write_2(mac, 0x3c02, 0xf);
 861                 bwi_tbl_write_2(mac, 0x3c03, 0x14);
 862
 863                 wrd_ofs1 = 0x401;
 864                 wrd_ofs2 = 0x402;
 865         }
 866
 867         if (!(BWI_IS_BRCM_BU4306(sc) && sc->sc_pci_revid == 0x17)) {
 868                 bwi_tbl_write_2(mac, wrd_ofs1, 0x2);
 869                 bwi_tbl_write_2(mac, wrd_ofs2, 0x1);
 870         }
 871
 872         /* phy->phy_flags & BWI_PHY_F_LINKED ? */
 873         if (sc->sc_card_flags & BWI_CARD_F_PA_GPIO9)
 874                 PHY_WRITE(mac, 0x46e, 0x3cf);
 875 }
 876
 877 /*
 878  * Configure Automatic Gain Controller
 879  */
 880 static void
 881 bwi_phy_config_agc(struct bwi_mac *mac)
 882 {
 883         struct bwi_phy *phy = &mac->mac_phy;
 884         uint16_t ofs;
 885
 886         ofs = phy->phy_rev == 1 ? 0x4c00 : 0;
 887
 888         bwi_tbl_write_2(mac, ofs, 0xfe);
 889         bwi_tbl_write_2(mac, ofs + 1, 0xd);
 890         bwi_tbl_write_2(mac, ofs + 2, 0x13);
 891         bwi_tbl_write_2(mac, ofs + 3, 0x19);
 892
 893         if (phy->phy_rev == 1) {
 894                 bwi_tbl_write_2(mac, 0x1800, 0x2710);
 895                 bwi_tbl_write_2(mac, 0x1801, 0x9b83);
 896                 bwi_tbl_write_2(mac, 0x1802, 0x9b83);
 897                 bwi_tbl_write_2(mac, 0x1803, 0xf8d);
 898                 PHY_WRITE(mac, 0x455, 0x4);
 899         }
 900
 901         PHY_FILT_SETBITS(mac, 0x4a5, 0xff, 0x5700);
 902         PHY_FILT_SETBITS(mac, 0x41a, 0xff80, 0xf);
 903         PHY_FILT_SETBITS(mac, 0x41a, 0xc07f, 0x2b80);
 904         PHY_FILT_SETBITS(mac, 0x48c, 0xf0ff, 0x300);
 905
 906         RF_SETBITS(mac, 0x7a, 0x8);
 907
 908         PHY_FILT_SETBITS(mac, 0x4a0, 0xfff0, 0x8);
 909         PHY_FILT_SETBITS(mac, 0x4a1, 0xf0ff, 0x600);
 910         PHY_FILT_SETBITS(mac, 0x4a2, 0xf0ff, 0x700);
 911         PHY_FILT_SETBITS(mac, 0x4a0, 0xf0ff, 0x100);
 912
 913         if (phy->phy_rev == 1)
 914                 PHY_FILT_SETBITS(mac, 0x4a2, 0xfff0, 0x7);
 915
 916         PHY_FILT_SETBITS(mac, 0x488, 0xff00, 0x1c);
 917         PHY_FILT_SETBITS(mac, 0x488, 0xc0ff, 0x200);
 918         PHY_FILT_SETBITS(mac, 0x496, 0xff00, 0x1c);
 919         PHY_FILT_SETBITS(mac, 0x489, 0xff00, 0x20);
 920         PHY_FILT_SETBITS(mac, 0x489, 0xc0ff, 0x200);
 921         PHY_FILT_SETBITS(mac, 0x482, 0xff00, 0x2e);
 922         PHY_FILT_SETBITS(mac, 0x496, 0xff, 0x1a00);
 923         PHY_FILT_SETBITS(mac, 0x481, 0xff00, 0x28);
 924         PHY_FILT_SETBITS(mac, 0x481, 0xff, 0x2c00);
 925
 926         if (phy->phy_rev == 1) {
 927                 PHY_WRITE(mac, 0x430, 0x92b);
 928                 PHY_FILT_SETBITS(mac, 0x41b, 0xffe1, 0x2);
 929         } else {
 930                 PHY_CLRBITS(mac, 0x41b, 0x1e);
 931                 PHY_WRITE(mac, 0x41f, 0x287a);
 932                 PHY_FILT_SETBITS(mac, 0x420, 0xfff0, 0x4);
 933
 934                 if (phy->phy_rev >= 6) {
 935                         PHY_WRITE(mac, 0x422, 0x287a);
 936                         PHY_FILT_SETBITS(mac, 0x420, 0xfff, 0x3000);
 937                 }
 938         }
 939
 940         PHY_FILT_SETBITS(mac, 0x4a8, 0x8080, 0x7874);
 941         PHY_WRITE(mac, 0x48e, 0x1c00);
 942
 943         if (phy->phy_rev == 1) {
 944                 PHY_FILT_SETBITS(mac, 0x4ab, 0xf0ff, 0x600);
 945                 PHY_WRITE(mac, 0x48b, 0x5e);
 946                 PHY_FILT_SETBITS(mac, 0x48c, 0xff00, 0x1e);
 947                 PHY_WRITE(mac, 0x48d, 0x2);
 948         }
 949
 950         bwi_tbl_write_2(mac, ofs + 0x800, 0);
 951         bwi_tbl_write_2(mac, ofs + 0x801, 7);
 952         bwi_tbl_write_2(mac, ofs + 0x802, 16);
 953         bwi_tbl_write_2(mac, ofs + 0x803, 28);
 954
 955         if (phy->phy_rev >= 6) {
 956                 PHY_CLRBITS(mac, 0x426, 0x3);
 957                 PHY_CLRBITS(mac, 0x426, 0x1000);
 958         }
 959 }
 960
 961 void
 962 bwi_set_gains(struct bwi_mac *mac, const struct bwi_gains *gains)
 963 {
 964         struct bwi_phy *phy = &mac->mac_phy;
 965         uint16_t tbl_gain_ofs1, tbl_gain_ofs2, tbl_gain;
 966         int i;
 967
 968         if (phy->phy_rev <= 1) {
 969                 tbl_gain_ofs1 = 0x5000;
 970                 tbl_gain_ofs2 = tbl_gain_ofs1 + 16;
 971         } else {
 972                 tbl_gain_ofs1 = 0x400;
 973                 tbl_gain_ofs2 = tbl_gain_ofs1 + 8;
 974         }
 975
 976         for (i = 0; i < 4; ++i) {
 977                 if (gains != NULL) {
 978                         tbl_gain = gains->tbl_gain1;
 979                 } else {
 980                         /* Bit swap */
 981                         tbl_gain = (i & 0x1) << 1;
 982                         tbl_gain |= (i & 0x2) >> 1;
 983                 }
 984                 bwi_tbl_write_2(mac, tbl_gain_ofs1 + i, tbl_gain);
 985         }
 986
 987         for (i = 0; i < 16; ++i) {
 988                 if (gains != NULL)
 989                         tbl_gain = gains->tbl_gain2;
 990                 else
 991                         tbl_gain = i;
 992                 bwi_tbl_write_2(mac, tbl_gain_ofs2 + i, tbl_gain);
 993         }
 994
 995         if (gains == NULL || (gains != NULL && gains->phy_gain != -1)) {
 996                 uint16_t phy_gain1, phy_gain2;
 997
 998                 if (gains != NULL) {
 999                         phy_gain1 =
1000                         ((uint16_t)gains->phy_gain << 14) |
1001                         ((uint16_t)gains->phy_gain << 6);
1002                         phy_gain2 = phy_gain1;
1003                 } else {
1004                         phy_gain1 = 0x4040;
1005                         phy_gain2 = 0x4000;
1006                 }
1007                 PHY_FILT_SETBITS(mac, 0x4a0, 0xbfbf, phy_gain1);
1008                 PHY_FILT_SETBITS(mac, 0x4a1, 0xbfbf, phy_gain1);
1009                 PHY_FILT_SETBITS(mac, 0x4a2, 0xbfbf, phy_gain2);
1010         }
1011         bwi_mac_dummy_xmit(mac);
1012 }
1013
1014 void
1015 bwi_phy_clear_state(struct bwi_phy *phy)
1016 {
1017         phy->phy_flags &= ~BWI_CLEAR_PHY_FLAGS;
1018 }