2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/bwirf.c,v 1.9 2008/08/21 12:19:33 swildner Exp $
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/endian.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/systm.h>
57 #include <net/if_var.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_arp.h>
62 #include <net/ethernet.h>
63 #include <net/if_llc.h>
65 #include <net80211/ieee80211_var.h>
66 #include <net80211/ieee80211_radiotap.h>
67 #include <net80211/ieee80211_amrr.h>
69 #include <machine/bus.h>
71 #include <dev/bwi/bitops.h>
72 #include <dev/bwi/if_bwireg.h>
73 #include <dev/bwi/if_bwivar.h>
74 #include <dev/bwi/bwimac.h>
75 #include <dev/bwi/bwirf.h>
76 #include <dev/bwi/bwiphy.h>
78 #define RF_LO_WRITE(mac, lo) bwi_rf_lo_write((mac), (lo))
80 #define BWI_RF_2GHZ_CHAN(chan) \
81 (ieee80211_ieee2mhz((chan), IEEE80211_CHAN_2GHZ) - 2400)
83 #define BWI_DEFAULT_IDLE_TSSI 52
106 #define SAVE_RF_REG(mac, regs, n) (regs)->rf_##n = RF_READ((mac), 0x##n)
107 #define RESTORE_RF_REG(mac, regs, n) RF_WRITE((mac), 0x##n, (regs)->rf_##n)
109 #define SAVE_PHY_REG(mac, regs, n) (regs)->phy_##n = PHY_READ((mac), 0x##n)
110 #define RESTORE_PHY_REG(mac, regs, n) PHY_WRITE((mac), 0x##n, (regs)->phy_##n)
112 static int bwi_rf_calc_txpower(int8_t *, uint8_t, const int16_t[]);
113 static void bwi_rf_work_around(struct bwi_mac *, u_int);
114 static int bwi_rf_gain_max_reached(struct bwi_mac *, int);
115 static uint16_t bwi_rf_calibval(struct bwi_mac *);
116 static uint16_t bwi_rf_get_tp_ctrl2(struct bwi_mac *);
118 static void bwi_rf_lo_update_11b(struct bwi_mac *);
119 static uint16_t bwi_rf_lo_measure_11b(struct bwi_mac *);
121 static void bwi_rf_lo_update_11g(struct bwi_mac *);
122 static uint32_t bwi_rf_lo_devi_measure(struct bwi_mac *, uint16_t);
123 static void bwi_rf_lo_measure_11g(struct bwi_mac *,
124 const struct bwi_rf_lo *, struct bwi_rf_lo *, uint8_t);
125 static uint8_t _bwi_rf_lo_update_11g(struct bwi_mac *, uint16_t);
126 static void bwi_rf_lo_write(struct bwi_mac *, const struct bwi_rf_lo *);
128 static void bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *);
129 static void bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *);
130 static void bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *);
131 static void bwi_rf_set_nrssi_thr_11b(struct bwi_mac *);
132 static void bwi_rf_set_nrssi_thr_11g(struct bwi_mac *);
134 static void bwi_rf_init_sw_nrssi_table(struct bwi_mac *);
136 static int bwi_rf_calc_rssi_bcm2050(struct bwi_mac *,
137 const struct bwi_rxbuf_hdr *);
138 static int bwi_rf_calc_rssi_bcm2053(struct bwi_mac *,
139 const struct bwi_rxbuf_hdr *);
140 static int bwi_rf_calc_rssi_bcm2060(struct bwi_mac *,
141 const struct bwi_rxbuf_hdr *);
142 static int bwi_rf_calc_noise_bcm2050(struct bwi_mac *);
143 static int bwi_rf_calc_noise_bcm2053(struct bwi_mac *);
144 static int bwi_rf_calc_noise_bcm2060(struct bwi_mac *);
146 static void bwi_rf_on_11a(struct bwi_mac *);
147 static void bwi_rf_on_11bg(struct bwi_mac *);
149 static void bwi_rf_off_11a(struct bwi_mac *);
150 static void bwi_rf_off_11bg(struct bwi_mac *);
151 static void bwi_rf_off_11g_rev5(struct bwi_mac *);
153 static const int8_t bwi_txpower_map_11b[BWI_TSSI_MAX] =
154 { BWI_TXPOWER_MAP_11B };
155 static const int8_t bwi_txpower_map_11g[BWI_TSSI_MAX] =
156 { BWI_TXPOWER_MAP_11G };
158 static __inline int16_t
159 bwi_nrssi_11g(struct bwi_mac *mac)
163 #define NRSSI_11G_MASK __BITS(13, 8)
165 val = (int16_t)__SHIFTOUT(PHY_READ(mac, 0x47f), NRSSI_11G_MASK);
170 #undef NRSSI_11G_MASK
173 static __inline struct bwi_rf_lo *
174 bwi_get_rf_lo(struct bwi_mac *mac, uint16_t rf_atten, uint16_t bbp_atten)
178 n = rf_atten + (14 * (bbp_atten / 2));
179 KASSERT(n < BWI_RFLO_MAX, ("n %d", n));
181 return &mac->mac_rf.rf_lo[n];
185 bwi_rf_lo_isused(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
187 struct bwi_rf *rf = &mac->mac_rf;
190 idx = lo - rf->rf_lo;
191 KASSERT(idx >= 0 && idx < BWI_RFLO_MAX, ("idx %d", idx));
193 return isset(rf->rf_lo_used, idx);
197 bwi_rf_write(struct bwi_mac *mac, uint16_t ctrl, uint16_t data)
199 struct bwi_softc *sc = mac->mac_sc;
201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data);
206 bwi_rf_read(struct bwi_mac *mac, uint16_t ctrl)
208 struct bwi_rf *rf = &mac->mac_rf;
209 struct bwi_softc *sc = mac->mac_sc;
211 ctrl |= rf->rf_ctrl_rd;
212 if (rf->rf_ctrl_adj) {
216 else if (ctrl < 0x80)
220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl);
221 return CSR_READ_2(sc, BWI_RF_DATA_LO);
225 bwi_rf_attach(struct bwi_mac *mac)
227 struct bwi_softc *sc = mac->mac_sc;
228 struct bwi_phy *phy = &mac->mac_phy;
229 struct bwi_rf *rf = &mac->mac_rf;
234 * Get RF manufacture/type/revision
236 if (sc->sc_bbp_id == BWI_BBPID_BCM4317) {
240 manu = BWI_RF_MANUFACT_BCM;
241 type = BWI_RF_T_BCM2050;
242 if (sc->sc_bbp_rev == 0)
244 else if (sc->sc_bbp_rev == 1)
251 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
252 val = CSR_READ_2(sc, BWI_RF_DATA_HI);
255 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO);
256 val |= CSR_READ_2(sc, BWI_RF_DATA_LO);
258 manu = __SHIFTOUT(val, BWI_RFINFO_MANUFACT_MASK);
259 type = __SHIFTOUT(val, BWI_RFINFO_TYPE_MASK);
260 rev = __SHIFTOUT(val, BWI_RFINFO_REV_MASK);
262 device_printf(sc->sc_dev, "RF: manu 0x%03x, type 0x%04x, rev %u\n",
266 * Verify whether the RF is supported
270 switch (phy->phy_mode) {
271 case IEEE80211_MODE_11A:
272 if (manu != BWI_RF_MANUFACT_BCM ||
273 type != BWI_RF_T_BCM2060 ||
275 device_printf(sc->sc_dev, "only BCM2060 rev 1 RF "
276 "is supported for 11A PHY\n");
279 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11A;
280 rf->rf_on = bwi_rf_on_11a;
281 rf->rf_off = bwi_rf_off_11a;
282 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2060;
283 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2060;
285 case IEEE80211_MODE_11B:
286 if (type == BWI_RF_T_BCM2050) {
287 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
288 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
289 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2050;
290 } else if (type == BWI_RF_T_BCM2053) {
292 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2053;
293 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2053;
295 device_printf(sc->sc_dev, "only BCM2050/BCM2053 RF "
296 "is supported for 11B PHY\n");
299 rf->rf_on = bwi_rf_on_11bg;
300 rf->rf_off = bwi_rf_off_11bg;
301 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11b;
302 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11b;
303 if (phy->phy_rev == 6)
304 rf->rf_lo_update = bwi_rf_lo_update_11g;
306 rf->rf_lo_update = bwi_rf_lo_update_11b;
308 case IEEE80211_MODE_11G:
309 if (type != BWI_RF_T_BCM2050) {
310 device_printf(sc->sc_dev, "only BCM2050 RF "
311 "is supported for 11G PHY\n");
314 rf->rf_ctrl_rd = BWI_RF_CTRL_RD_11BG;
315 rf->rf_on = bwi_rf_on_11bg;
316 if (mac->mac_rev >= 5)
317 rf->rf_off = bwi_rf_off_11g_rev5;
319 rf->rf_off = bwi_rf_off_11bg;
320 rf->rf_calc_nrssi_slope = bwi_rf_calc_nrssi_slope_11g;
321 rf->rf_set_nrssi_thr = bwi_rf_set_nrssi_thr_11g;
322 rf->rf_calc_rssi = bwi_rf_calc_rssi_bcm2050;
323 rf->rf_calc_noise = bwi_rf_calc_noise_bcm2050;
324 rf->rf_lo_update = bwi_rf_lo_update_11g;
327 device_printf(sc->sc_dev, "unsupported PHY mode\n");
334 rf->rf_curchan = IEEE80211_CHAN_ANY;
335 rf->rf_ant_mode = BWI_ANT_MODE_AUTO;
340 bwi_rf_set_chan(struct bwi_mac *mac, u_int chan, int work_around)
342 struct bwi_softc *sc = mac->mac_sc;
344 if (chan == IEEE80211_CHAN_ANY)
347 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_CHAN, chan);
352 bwi_rf_work_around(mac, chan);
354 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
357 if (sc->sc_locale == BWI_SPROM_LOCALE_JAPAN)
358 HFLAGS_CLRBITS(mac, BWI_HFLAG_NOT_JAPAN);
360 HFLAGS_SETBITS(mac, BWI_HFLAG_NOT_JAPAN);
361 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, (1 << 11)); /* XXX */
363 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0x840); /* XXX */
365 DELAY(8000); /* DELAY(2000); */
367 mac->mac_rf.rf_curchan = chan;
371 bwi_rf_get_gains(struct bwi_mac *mac)
373 #define SAVE_PHY_MAX 15
374 #define SAVE_RF_MAX 3
376 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
377 { 0x52, 0x43, 0x7a };
378 static const uint16_t save_phy_regs[SAVE_PHY_MAX] = {
379 0x0429, 0x0001, 0x0811, 0x0812,
380 0x0814, 0x0815, 0x005a, 0x0059,
381 0x0058, 0x000a, 0x0003, 0x080f,
382 0x0810, 0x002b, 0x0015
385 struct bwi_softc *sc = mac->mac_sc;
386 struct bwi_phy *phy = &mac->mac_phy;
387 struct bwi_rf *rf = &mac->mac_rf;
388 uint16_t save_phy[SAVE_PHY_MAX];
389 uint16_t save_rf[SAVE_RF_MAX];
391 int i, j, loop1_max, loop1, loop2;
394 * Save PHY/RF registers for later restoration
396 for (i = 0; i < SAVE_PHY_MAX; ++i)
397 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
398 PHY_READ(mac, 0x2d); /* dummy read */
400 for (i = 0; i < SAVE_RF_MAX; ++i)
401 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
403 PHY_CLRBITS(mac, 0x429, 0xc000);
404 PHY_SETBITS(mac, 0x1, 0x8000);
406 PHY_SETBITS(mac, 0x811, 0x2);
407 PHY_CLRBITS(mac, 0x812, 0x2);
408 PHY_SETBITS(mac, 0x811, 0x1);
409 PHY_CLRBITS(mac, 0x812, 0x1);
411 PHY_SETBITS(mac, 0x814, 0x1);
412 PHY_CLRBITS(mac, 0x815, 0x1);
413 PHY_SETBITS(mac, 0x814, 0x2);
414 PHY_CLRBITS(mac, 0x815, 0x2);
416 PHY_SETBITS(mac, 0x811, 0xc);
417 PHY_SETBITS(mac, 0x812, 0xc);
418 PHY_SETBITS(mac, 0x811, 0x30);
419 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
421 PHY_WRITE(mac, 0x5a, 0x780);
422 PHY_WRITE(mac, 0x59, 0xc810);
423 PHY_WRITE(mac, 0x58, 0xd);
424 PHY_SETBITS(mac, 0xa, 0x2000);
426 PHY_SETBITS(mac, 0x814, 0x4);
427 PHY_CLRBITS(mac, 0x815, 0x4);
429 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
431 if (rf->rf_rev == 8) {
433 RF_WRITE(mac, 0x43, loop1_max);
436 RF_WRITE(mac, 0x52, 0x0);
437 RF_FILT_SETBITS(mac, 0x43, 0xfff0, loop1_max);
440 bwi_phy_set_bbp_atten(mac, 11);
442 if (phy->phy_rev >= 3)
443 PHY_WRITE(mac, 0x80f, 0xc020);
445 PHY_WRITE(mac, 0x80f, 0x8020);
446 PHY_WRITE(mac, 0x810, 0);
448 PHY_FILT_SETBITS(mac, 0x2b, 0xffc0, 0x1);
449 PHY_FILT_SETBITS(mac, 0x2b, 0xc0ff, 0x800);
450 PHY_SETBITS(mac, 0x811, 0x100);
451 PHY_CLRBITS(mac, 0x812, 0x3000);
453 if ((sc->sc_card_flags & BWI_CARD_F_EXT_LNA) &&
455 PHY_SETBITS(mac, 0x811, 0x800);
456 PHY_SETBITS(mac, 0x812, 0x8000);
458 RF_CLRBITS(mac, 0x7a, 0xff08);
461 * Find out 'loop1/loop2', which will be used to calculate
462 * max loopback gain later
465 for (i = 0; i < loop1_max; ++i) {
466 for (j = 0; j < 16; ++j) {
467 RF_WRITE(mac, 0x43, i);
469 if (bwi_rf_gain_max_reached(mac, j))
478 * Find out 'trsw', which will be used to calculate
479 * TRSW(TX/RX switch) RX gain later
482 PHY_SETBITS(mac, 0x812, 0x30);
484 for (i = loop2 - 8; i < 16; ++i) {
486 if (bwi_rf_gain_max_reached(mac, i))
494 * Restore saved PHY/RF registers
496 /* First 4 saved PHY registers need special processing */
497 for (i = 4; i < SAVE_PHY_MAX; ++i)
498 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
500 bwi_phy_set_bbp_atten(mac, mac->mac_tpctl.bbp_atten);
502 for (i = 0; i < SAVE_RF_MAX; ++i)
503 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
505 PHY_WRITE(mac, save_phy_regs[2], save_phy[2] | 0x3);
507 PHY_WRITE(mac, save_phy_regs[2], save_phy[2]);
508 PHY_WRITE(mac, save_phy_regs[3], save_phy[3]);
509 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
510 PHY_WRITE(mac, save_phy_regs[1], save_phy[1]);
515 rf->rf_lo_gain = (loop2 * 6) - (loop1 * 4) - 11;
516 rf->rf_rx_gain = trsw * 2;
517 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_INIT,
518 "lo gain: %u, rx gain: %u\n",
519 rf->rf_lo_gain, rf->rf_rx_gain);
526 bwi_rf_init(struct bwi_mac *mac)
528 struct bwi_rf *rf = &mac->mac_rf;
530 if (rf->rf_type == BWI_RF_T_BCM2060) {
533 if (rf->rf_flags & BWI_RF_F_INITED)
534 RF_WRITE(mac, 0x78, rf->rf_calib);
536 bwi_rf_init_bcm2050(mac);
541 bwi_rf_off_11a(struct bwi_mac *mac)
543 RF_WRITE(mac, 0x4, 0xff);
544 RF_WRITE(mac, 0x5, 0xfb);
546 PHY_SETBITS(mac, 0x10, 0x8);
547 PHY_SETBITS(mac, 0x11, 0x8);
549 PHY_WRITE(mac, 0x15, 0xaa00);
553 bwi_rf_off_11bg(struct bwi_mac *mac)
555 PHY_WRITE(mac, 0x15, 0xaa00);
559 bwi_rf_off_11g_rev5(struct bwi_mac *mac)
561 PHY_SETBITS(mac, 0x811, 0x8c);
562 PHY_CLRBITS(mac, 0x812, 0x8c);
566 bwi_rf_work_around(struct bwi_mac *mac, u_int chan)
568 struct bwi_softc *sc = mac->mac_sc;
569 struct bwi_rf *rf = &mac->mac_rf;
571 if (chan == IEEE80211_CHAN_ANY) {
572 device_printf(sc->sc_dev, "%s invalid channel!!\n", __func__);
576 if (rf->rf_type != BWI_RF_T_BCM2050 || rf->rf_rev >= 6)
580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4));
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1));
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan));
587 static __inline struct bwi_rf_lo *
588 bwi_rf_lo_find(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
590 uint16_t rf_atten, bbp_atten;
598 if (tpctl->tp_ctrl1 == 3)
601 bbp_atten = tpctl->bbp_atten;
602 rf_atten = tpctl->rf_atten;
608 if (remap_rf_atten) {
610 static const uint16_t map[MAP_MAX] =
611 { 11, 10, 11, 12, 13, 12, 13, 12, 13, 12 };
614 KASSERT(rf_atten < MAP_MAX, ("rf_atten %d", rf_atten));
615 rf_atten = map[rf_atten];
617 if (rf_atten >= MAP_MAX) {
618 rf_atten = 0; /* XXX */
620 rf_atten = map[rf_atten];
626 return bwi_get_rf_lo(mac, rf_atten, bbp_atten);
630 bwi_rf_lo_adjust(struct bwi_mac *mac, const struct bwi_tpctl *tpctl)
632 const struct bwi_rf_lo *lo;
634 lo = bwi_rf_lo_find(mac, tpctl);
635 RF_LO_WRITE(mac, lo);
639 bwi_rf_lo_write(struct bwi_mac *mac, const struct bwi_rf_lo *lo)
643 val = (uint8_t)lo->ctrl_lo;
644 val |= ((uint8_t)lo->ctrl_hi) << 8;
646 PHY_WRITE(mac, BWI_PHYR_RF_LO, val);
650 bwi_rf_gain_max_reached(struct bwi_mac *mac, int idx)
652 PHY_FILT_SETBITS(mac, 0x812, 0xf0ff, idx << 8);
653 PHY_FILT_SETBITS(mac, 0x15, 0xfff, 0xa000);
654 PHY_SETBITS(mac, 0x15, 0xf000);
658 return (PHY_READ(mac, 0x2d) >= 0xdfc);
661 /* XXX use bitmap array */
662 static __inline uint16_t
663 bitswap4(uint16_t val)
667 ret = (val & 0x8) >> 3;
668 ret |= (val & 0x4) >> 1;
669 ret |= (val & 0x2) << 1;
670 ret |= (val & 0x1) << 3;
674 static __inline uint16_t
675 bwi_phy812_value(struct bwi_mac *mac, uint16_t lpd)
677 struct bwi_softc *sc = mac->mac_sc;
678 struct bwi_phy *phy = &mac->mac_phy;
679 struct bwi_rf *rf = &mac->mac_rf;
680 uint16_t lo_gain, ext_lna, loop;
682 if ((phy->phy_flags & BWI_PHY_F_LINKED) == 0)
685 lo_gain = rf->rf_lo_gain;
691 if (lo_gain >= 0x46) {
694 } else if (lo_gain >= 0x3a) {
697 } else if (lo_gain >= 0x2e) {
705 for (loop = 0; loop < 16; ++loop) {
706 lo_gain -= (6 * loop);
711 if (phy->phy_rev >= 7 && (sc->sc_card_flags & BWI_CARD_F_EXT_LNA)) {
714 ext_lna |= (loop << 8);
719 return (0x8092 | ext_lna);
721 return (0x2092 | ext_lna);
723 return (0x2093 | ext_lna);
725 panic("unsupported lpd\n");
728 ext_lna |= (loop << 8);
734 return (0x92 | ext_lna);
736 return (0x93 | ext_lna);
738 panic("unsupported lpd\n");
742 panic("never reached\n");
747 bwi_rf_init_bcm2050(struct bwi_mac *mac)
749 #define SAVE_RF_MAX 3
750 #define SAVE_PHY_COMM_MAX 4
751 #define SAVE_PHY_11G_MAX 6
753 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
754 { 0x0043, 0x0051, 0x0052 };
755 static const uint16_t save_phy_regs_comm[SAVE_PHY_COMM_MAX] =
756 { 0x0015, 0x005a, 0x0059, 0x0058 };
757 static const uint16_t save_phy_regs_11g[SAVE_PHY_11G_MAX] =
758 { 0x0811, 0x0812, 0x0814, 0x0815, 0x0429, 0x0802 };
760 uint16_t save_rf[SAVE_RF_MAX];
761 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
762 uint16_t save_phy_11g[SAVE_PHY_11G_MAX];
763 uint16_t phyr_35, phyr_30 = 0, rfr_78, phyr_80f = 0, phyr_810 = 0;
764 uint16_t bphy_ctrl = 0, bbp_atten, rf_chan_ex;
767 uint32_t test_lim, test;
768 struct bwi_softc *sc = mac->mac_sc;
769 struct bwi_phy *phy = &mac->mac_phy;
770 struct bwi_rf *rf = &mac->mac_rf;
774 * Save registers for later restoring
776 for (i = 0; i < SAVE_RF_MAX; ++i)
777 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
778 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
779 save_phy_comm[i] = PHY_READ(mac, save_phy_regs_comm[i]);
781 if (phy->phy_mode == IEEE80211_MODE_11B) {
782 phyr_30 = PHY_READ(mac, 0x30);
783 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
785 PHY_WRITE(mac, 0x30, 0xff);
786 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f);
787 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
788 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
790 PHY_READ(mac, save_phy_regs_11g[i]);
793 PHY_SETBITS(mac, 0x814, 0x3);
794 PHY_CLRBITS(mac, 0x815, 0x3);
795 PHY_CLRBITS(mac, 0x429, 0x8000);
796 PHY_CLRBITS(mac, 0x802, 0x3);
798 phyr_80f = PHY_READ(mac, 0x80f);
799 phyr_810 = PHY_READ(mac, 0x810);
801 if (phy->phy_rev >= 3)
802 PHY_WRITE(mac, 0x80f, 0xc020);
804 PHY_WRITE(mac, 0x80f, 0x8020);
805 PHY_WRITE(mac, 0x810, 0);
807 phy812_val = bwi_phy812_value(mac, 0x011);
808 PHY_WRITE(mac, 0x812, phy812_val);
809 if (phy->phy_rev < 7 ||
810 (sc->sc_card_flags & BWI_CARD_F_EXT_LNA) == 0)
811 PHY_WRITE(mac, 0x811, 0x1b3);
813 PHY_WRITE(mac, 0x811, 0x9b3);
815 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
817 phyr_35 = PHY_READ(mac, 0x35);
818 PHY_CLRBITS(mac, 0x35, 0x80);
820 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
821 rf_chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
823 if (phy->phy_version == 0) {
824 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
826 if (phy->phy_version >= 2)
827 PHY_FILT_SETBITS(mac, 0x3, 0xffbf, 0x40);
828 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
831 calib = bwi_rf_calibval(mac);
833 if (phy->phy_mode == IEEE80211_MODE_11B)
834 RF_WRITE(mac, 0x78, 0x26);
836 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
837 phy812_val = bwi_phy812_value(mac, 0x011);
838 PHY_WRITE(mac, 0x812, phy812_val);
841 PHY_WRITE(mac, 0x15, 0xbfaf);
842 PHY_WRITE(mac, 0x2b, 0x1403);
844 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
845 phy812_val = bwi_phy812_value(mac, 0x001);
846 PHY_WRITE(mac, 0x812, phy812_val);
849 PHY_WRITE(mac, 0x15, 0xbfa0);
851 RF_SETBITS(mac, 0x51, 0x4);
852 if (rf->rf_rev == 8) {
853 RF_WRITE(mac, 0x43, 0x1f);
855 RF_WRITE(mac, 0x52, 0);
856 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
860 PHY_WRITE(mac, 0x58, 0);
861 for (i = 0; i < 16; ++i) {
862 PHY_WRITE(mac, 0x5a, 0x480);
863 PHY_WRITE(mac, 0x59, 0xc810);
865 PHY_WRITE(mac, 0x58, 0xd);
866 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
867 phy812_val = bwi_phy812_value(mac, 0x101);
868 PHY_WRITE(mac, 0x812, phy812_val);
870 PHY_WRITE(mac, 0x15, 0xafb0);
873 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
874 phy812_val = bwi_phy812_value(mac, 0x101);
875 PHY_WRITE(mac, 0x812, phy812_val);
877 PHY_WRITE(mac, 0x15, 0xefb0);
880 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
881 phy812_val = bwi_phy812_value(mac, 0x100);
882 PHY_WRITE(mac, 0x812, phy812_val);
884 PHY_WRITE(mac, 0x15, 0xfff0);
887 test_lim += PHY_READ(mac, 0x2d);
889 PHY_WRITE(mac, 0x58, 0);
890 if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
891 phy812_val = bwi_phy812_value(mac, 0x101);
892 PHY_WRITE(mac, 0x812, phy812_val);
894 PHY_WRITE(mac, 0x15, 0xafb0);
902 PHY_WRITE(mac, 0x58, 0);
903 for (i = 0; i < 16; ++i) {
906 rfr_78 = (bitswap4(i) << 1) | 0x20;
907 RF_WRITE(mac, 0x78, rfr_78);
910 /* NB: This block is slight different than the above one */
911 for (j = 0; j < 16; ++j) {
912 PHY_WRITE(mac, 0x5a, 0xd80);
913 PHY_WRITE(mac, 0x59, 0xc810);
915 PHY_WRITE(mac, 0x58, 0xd);
916 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
918 phy812_val = bwi_phy812_value(mac, 0x101);
919 PHY_WRITE(mac, 0x812, phy812_val);
921 PHY_WRITE(mac, 0x15, 0xafb0);
924 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
926 phy812_val = bwi_phy812_value(mac, 0x101);
927 PHY_WRITE(mac, 0x812, phy812_val);
929 PHY_WRITE(mac, 0x15, 0xefb0);
932 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
934 phy812_val = bwi_phy812_value(mac, 0x100);
935 PHY_WRITE(mac, 0x812, phy812_val);
937 PHY_WRITE(mac, 0x15, 0xfff0);
940 test += PHY_READ(mac, 0x2d);
942 PHY_WRITE(mac, 0x58, 0);
943 if ((phy->phy_flags & BWI_PHY_F_LINKED) ||
945 phy812_val = bwi_phy812_value(mac, 0x101);
946 PHY_WRITE(mac, 0x812, phy812_val);
948 PHY_WRITE(mac, 0x15, 0xafb0);
958 rf->rf_calib = rfr_78;
960 rf->rf_calib = calib;
961 if (rf->rf_calib != 0xffff) {
962 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT,
963 "RF calibration value: 0x%04x\n", rf->rf_calib);
964 rf->rf_flags |= BWI_RF_F_INITED;
968 * Restore trashes registers
970 PHY_WRITE(mac, save_phy_regs_comm[0], save_phy_comm[0]);
972 for (i = 0; i < SAVE_RF_MAX; ++i) {
973 int pos = (i + 1) % SAVE_RF_MAX;
975 RF_WRITE(mac, save_rf_regs[pos], save_rf[pos]);
977 for (i = 1; i < SAVE_PHY_COMM_MAX; ++i)
978 PHY_WRITE(mac, save_phy_regs_comm[i], save_phy_comm[i]);
980 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
981 if (phy->phy_version != 0)
982 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, rf_chan_ex);
984 PHY_WRITE(mac, 0x35, phyr_35);
985 bwi_rf_work_around(mac, rf->rf_curchan);
987 if (phy->phy_mode == IEEE80211_MODE_11B) {
988 PHY_WRITE(mac, 0x30, phyr_30);
989 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
990 } else if ((phy->phy_flags & BWI_PHY_F_LINKED) || phy->phy_rev >= 2) {
991 /* XXX Spec only says when PHY is linked (gmode) */
992 CSR_CLRBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
994 for (i = 0; i < SAVE_PHY_11G_MAX; ++i) {
995 PHY_WRITE(mac, save_phy_regs_11g[i],
999 PHY_WRITE(mac, 0x80f, phyr_80f);
1000 PHY_WRITE(mac, 0x810, phyr_810);
1003 #undef SAVE_PHY_11G_MAX
1004 #undef SAVE_PHY_COMM_MAX
1009 bwi_rf_calibval(struct bwi_mac *mac)
1011 /* http://bcm-specs.sipsolutions.net/RCCTable */
1012 static const uint16_t rf_calibvals[] = {
1013 0x2, 0x3, 0x1, 0xf, 0x6, 0x7, 0x5, 0xf,
1014 0xa, 0xb, 0x9, 0xf, 0xe, 0xf, 0xd, 0xf
1016 uint16_t val, calib;
1019 val = RF_READ(mac, BWI_RFR_BBP_ATTEN);
1020 idx = __SHIFTOUT(val, BWI_RFR_BBP_ATTEN_CALIB_IDX);
1021 KASSERT(idx < (int)(sizeof(rf_calibvals) / sizeof(rf_calibvals[0])),
1024 calib = rf_calibvals[idx] << 1;
1025 if (val & BWI_RFR_BBP_ATTEN_CALIB_BIT)
1032 static __inline int32_t
1033 _bwi_adjust_devide(int32_t num, int32_t den)
1038 return (num + den / 2) / den;
1042 * http://bcm-specs.sipsolutions.net/TSSI_to_DBM_Table
1043 * "calculating table entries"
1046 bwi_rf_calc_txpower(int8_t *txpwr, uint8_t idx, const int16_t pa_params[])
1048 int32_t m1, m2, f, dbm;
1051 m1 = _bwi_adjust_devide(16 * pa_params[0] + idx * pa_params[1], 32);
1052 m2 = imax(_bwi_adjust_devide(32768 + idx * pa_params[2], 256), 1);
1057 for (i = 0; i < ITER_MAX; ++i) {
1060 q = _bwi_adjust_devide(
1061 f * 4096 - _bwi_adjust_devide(m2 * f, 16) * f, 2048);
1073 dbm = _bwi_adjust_devide(m1 * f, 8192);
1084 bwi_rf_map_txpower(struct bwi_mac *mac)
1086 struct bwi_softc *sc = mac->mac_sc;
1087 struct bwi_rf *rf = &mac->mac_rf;
1088 struct bwi_phy *phy = &mac->mac_phy;
1089 uint16_t sprom_ofs, val, mask;
1090 int16_t pa_params[3];
1091 int error = 0, i, ant_gain, reg_txpower_max;
1094 * Find out max TX power
1096 val = bwi_read_sprom(sc, BWI_SPROM_MAX_TXPWR);
1097 if (phy->phy_mode == IEEE80211_MODE_11A) {
1098 rf->rf_txpower_max = __SHIFTOUT(val,
1099 BWI_SPROM_MAX_TXPWR_MASK_11A);
1101 rf->rf_txpower_max = __SHIFTOUT(val,
1102 BWI_SPROM_MAX_TXPWR_MASK_11BG);
1104 if ((sc->sc_card_flags & BWI_CARD_F_PA_GPIO9) &&
1105 phy->phy_mode == IEEE80211_MODE_11G)
1106 rf->rf_txpower_max -= 3;
1108 if (rf->rf_txpower_max <= 0) {
1109 device_printf(sc->sc_dev, "invalid max txpower in sprom\n");
1110 rf->rf_txpower_max = 74;
1112 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1113 "max txpower from sprom: %d dBm\n", rf->rf_txpower_max);
1116 * Find out region/domain max TX power, which is adjusted
1117 * by antenna gain and 1.5 dBm fluctuation as mentioned
1120 val = bwi_read_sprom(sc, BWI_SPROM_ANT_GAIN);
1121 if (phy->phy_mode == IEEE80211_MODE_11A)
1122 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11A);
1124 ant_gain = __SHIFTOUT(val, BWI_SPROM_ANT_GAIN_MASK_11BG);
1125 if (ant_gain == 0xff) {
1126 device_printf(sc->sc_dev, "invalid antenna gain in sprom\n");
1130 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1131 "ant gain %d dBm\n", ant_gain);
1133 reg_txpower_max = 90 - ant_gain - 6; /* XXX magic number */
1134 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1135 "region/domain max txpower %d dBm\n", reg_txpower_max);
1138 * Force max TX power within region/domain TX power limit
1140 if (rf->rf_txpower_max > reg_txpower_max)
1141 rf->rf_txpower_max = reg_txpower_max;
1142 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1143 "max txpower %d dBm\n", rf->rf_txpower_max);
1146 * Create TSSI to TX power mapping
1149 if (sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1150 rf->rf_type != BWI_RF_T_BCM2050) {
1151 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1152 bcopy(bwi_txpower_map_11b, rf->rf_txpower_map0,
1153 sizeof(rf->rf_txpower_map0));
1157 #define IS_VALID_PA_PARAM(p) ((p) != 0 && (p) != -1)
1158 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
1161 * Extract PA parameters
1163 if (phy->phy_mode == IEEE80211_MODE_11A)
1164 sprom_ofs = BWI_SPROM_PA_PARAM_11A;
1166 sprom_ofs = BWI_SPROM_PA_PARAM_11BG;
1167 for (i = 0; i < N(pa_params); ++i)
1168 pa_params[i] = (int16_t)bwi_read_sprom(sc, sprom_ofs + (i * 2));
1170 for (i = 0; i < N(pa_params); ++i) {
1172 * If one of the PA parameters from SPROM is not valid,
1173 * fall back to the default values, if there are any.
1175 if (!IS_VALID_PA_PARAM(pa_params[i])) {
1176 const int8_t *txpower_map;
1178 if (phy->phy_mode == IEEE80211_MODE_11A) {
1179 device_printf(sc->sc_dev,
1180 "no tssi2dbm table for 11a PHY\n");
1184 if (phy->phy_mode == IEEE80211_MODE_11G) {
1186 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1187 "%s\n", "use default 11g TSSI map");
1188 txpower_map = bwi_txpower_map_11g;
1191 BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1192 "%s\n", "use default 11b TSSI map");
1193 txpower_map = bwi_txpower_map_11b;
1196 rf->rf_idle_tssi0 = BWI_DEFAULT_IDLE_TSSI;
1197 bcopy(txpower_map, rf->rf_txpower_map0,
1198 sizeof(rf->rf_txpower_map0));
1206 * All of the PA parameters from SPROM are valid.
1210 * Extract idle TSSI from SPROM.
1212 val = bwi_read_sprom(sc, BWI_SPROM_IDLE_TSSI);
1213 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1214 "sprom idle tssi: 0x%04x\n", val);
1216 if (phy->phy_mode == IEEE80211_MODE_11A)
1217 mask = BWI_SPROM_IDLE_TSSI_MASK_11A;
1219 mask = BWI_SPROM_IDLE_TSSI_MASK_11BG;
1221 rf->rf_idle_tssi0 = (int)__SHIFTOUT(val, mask);
1222 if (!IS_VALID_PA_PARAM(rf->rf_idle_tssi0))
1223 rf->rf_idle_tssi0 = 62;
1225 #undef IS_VALID_PA_PARAM
1228 * Calculate TX power map, which is indexed by TSSI
1230 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1231 "%s\n", "TSSI-TX power map:");
1232 for (i = 0; i < BWI_TSSI_MAX; ++i) {
1233 error = bwi_rf_calc_txpower(&rf->rf_txpower_map0[i], i,
1236 device_printf(sc->sc_dev,
1237 "bwi_rf_calc_txpower failed\n");
1242 if (i != 0 && i % 8 == 0) {
1244 BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1248 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1249 "%d ", rf->rf_txpower_map0[i]);
1251 _DPRINTF(sc, BWI_DBG_RF | BWI_DBG_ATTACH | BWI_DBG_TXPOWER,
1254 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_TXPOWER | BWI_DBG_ATTACH,
1255 "idle tssi0: %d\n", rf->rf_idle_tssi0);
1260 bwi_rf_lo_update_11g(struct bwi_mac *mac)
1262 struct bwi_softc *sc = mac->mac_sc;
1263 struct ifnet *ifp = sc->sc_ifp;
1264 struct bwi_rf *rf = &mac->mac_rf;
1265 struct bwi_phy *phy = &mac->mac_phy;
1266 struct bwi_tpctl *tpctl = &mac->mac_tpctl;
1267 struct rf_saveregs regs;
1268 uint16_t ant_div, chan_ex;
1273 * Save RF/PHY registers for later restoration
1275 orig_chan = rf->rf_curchan;
1276 bzero(®s, sizeof(regs));
1278 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1279 SAVE_PHY_REG(mac, ®s, 429);
1280 SAVE_PHY_REG(mac, ®s, 802);
1282 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1283 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1286 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1287 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div | 0x8000);
1288 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1290 SAVE_PHY_REG(mac, ®s, 15);
1291 SAVE_PHY_REG(mac, ®s, 2a);
1292 SAVE_PHY_REG(mac, ®s, 35);
1293 SAVE_PHY_REG(mac, ®s, 60);
1294 SAVE_RF_REG(mac, ®s, 43);
1295 SAVE_RF_REG(mac, ®s, 7a);
1296 SAVE_RF_REG(mac, ®s, 52);
1297 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1298 SAVE_PHY_REG(mac, ®s, 811);
1299 SAVE_PHY_REG(mac, ®s, 812);
1300 SAVE_PHY_REG(mac, ®s, 814);
1301 SAVE_PHY_REG(mac, ®s, 815);
1304 /* Force to channel 6 */
1305 bwi_rf_set_chan(mac, 6, 0);
1307 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1308 PHY_WRITE(mac, 0x429, regs.phy_429 & 0x7fff);
1309 PHY_WRITE(mac, 0x802, regs.phy_802 & 0xfffc);
1310 bwi_mac_dummy_xmit(mac);
1312 RF_WRITE(mac, 0x43, 0x6);
1314 bwi_phy_set_bbp_atten(mac, 2);
1316 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0);
1318 PHY_WRITE(mac, 0x2e, 0x7f);
1319 PHY_WRITE(mac, 0x80f, 0x78);
1320 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
1321 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
1322 PHY_WRITE(mac, 0x2b, 0x203);
1323 PHY_WRITE(mac, 0x2a, 0x8a3);
1325 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1326 PHY_WRITE(mac, 0x814, regs.phy_814 | 0x3);
1327 PHY_WRITE(mac, 0x815, regs.phy_815 & 0xfffc);
1328 PHY_WRITE(mac, 0x811, 0x1b3);
1329 PHY_WRITE(mac, 0x812, 0xb2);
1332 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1333 tpctl->tp_ctrl2 = bwi_rf_get_tp_ctrl2(mac);
1334 PHY_WRITE(mac, 0x80f, 0x8078);
1339 devi_ctrl = _bwi_rf_lo_update_11g(mac, regs.rf_7a);
1342 * Restore saved RF/PHY registers
1344 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1345 PHY_WRITE(mac, 0x15, 0xe300);
1346 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa0);
1348 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa2);
1350 PHY_WRITE(mac, 0x812, (devi_ctrl << 8) | 0xa3);
1352 PHY_WRITE(mac, 0x15, devi_ctrl | 0xefa0);
1355 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1357 bwi_rf_lo_adjust(mac, tpctl);
1359 PHY_WRITE(mac, 0x2e, 0x807f);
1360 if (phy->phy_flags & BWI_PHY_F_LINKED)
1361 PHY_WRITE(mac, 0x2f, 0x202);
1363 PHY_WRITE(mac, 0x2f, 0x101);
1365 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1367 RESTORE_PHY_REG(mac, ®s, 15);
1368 RESTORE_PHY_REG(mac, ®s, 2a);
1369 RESTORE_PHY_REG(mac, ®s, 35);
1370 RESTORE_PHY_REG(mac, ®s, 60);
1372 RESTORE_RF_REG(mac, ®s, 43);
1373 RESTORE_RF_REG(mac, ®s, 7a);
1376 regs.rf_52 |= (RF_READ(mac, 0x52) & 0xf);
1377 RF_WRITE(mac, 0x52, regs.rf_52);
1379 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1381 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1382 RESTORE_PHY_REG(mac, ®s, 811);
1383 RESTORE_PHY_REG(mac, ®s, 812);
1384 RESTORE_PHY_REG(mac, ®s, 814);
1385 RESTORE_PHY_REG(mac, ®s, 815);
1386 RESTORE_PHY_REG(mac, ®s, 429);
1387 RESTORE_PHY_REG(mac, ®s, 802);
1390 bwi_rf_set_chan(mac, orig_chan, 1);
1394 bwi_rf_lo_devi_measure(struct bwi_mac *mac, uint16_t ctrl)
1396 struct bwi_phy *phy = &mac->mac_phy;
1400 if (phy->phy_flags & BWI_PHY_F_LINKED)
1403 for (i = 0; i < 8; ++i) {
1404 if (phy->phy_flags & BWI_PHY_F_LINKED) {
1405 PHY_WRITE(mac, 0x15, 0xe300);
1406 PHY_WRITE(mac, 0x812, ctrl | 0xb0);
1408 PHY_WRITE(mac, 0x812, ctrl | 0xb2);
1410 PHY_WRITE(mac, 0x812, ctrl | 0xb3);
1412 PHY_WRITE(mac, 0x15, 0xf300);
1414 PHY_WRITE(mac, 0x15, ctrl | 0xefa0);
1416 PHY_WRITE(mac, 0x15, ctrl | 0xefe0);
1418 PHY_WRITE(mac, 0x15, ctrl | 0xffe0);
1421 devi += PHY_READ(mac, 0x2d);
1427 bwi_rf_get_tp_ctrl2(struct bwi_mac *mac)
1430 uint16_t tp_ctrl2 = 0;
1433 RF_WRITE(mac, 0x52, 0);
1435 devi_min = bwi_rf_lo_devi_measure(mac, 0);
1437 for (i = 0; i < 16; ++i) {
1440 RF_WRITE(mac, 0x52, i);
1442 devi = bwi_rf_lo_devi_measure(mac, 0);
1444 if (devi < devi_min) {
1453 _bwi_rf_lo_update_11g(struct bwi_mac *mac, uint16_t orig_rf7a)
1455 #define RF_ATTEN_LISTSZ 14
1456 #define BBP_ATTEN_MAX 4 /* half */
1458 static const int rf_atten_list[RF_ATTEN_LISTSZ] =
1459 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 1, 2, 3, 4 };
1460 static const int rf_atten_init_list[RF_ATTEN_LISTSZ] =
1461 { 0, 3, 1, 5, 7, 3, 2, 0, 4, 6, -1, -1, -1, -1 };
1462 static const int rf_lo_measure_order[RF_ATTEN_LISTSZ] =
1463 { 3, 1, 5, 7, 9, 2, 0, 4, 6, 8, 10, 11, 12, 13 };
1465 struct ifnet *ifp = mac->mac_sc->sc_ifp;
1466 struct bwi_rf_lo lo_save, *lo;
1467 uint8_t devi_ctrl = 0;
1468 int idx, adj_rf7a = 0;
1470 bzero(&lo_save, sizeof(lo_save));
1471 for (idx = 0; idx < RF_ATTEN_LISTSZ; ++idx) {
1472 int init_rf_atten = rf_atten_init_list[idx];
1473 int rf_atten = rf_atten_list[idx];
1476 for (bbp_atten = 0; bbp_atten < BBP_ATTEN_MAX; ++bbp_atten) {
1477 uint16_t tp_ctrl2, rf7a;
1479 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1481 bzero(&lo_save, sizeof(lo_save));
1482 } else if (init_rf_atten < 0) {
1483 lo = bwi_get_rf_lo(mac,
1484 rf_atten, 2 * bbp_atten);
1485 bcopy(lo, &lo_save, sizeof(lo_save));
1487 lo = bwi_get_rf_lo(mac,
1489 bcopy(lo, &lo_save, sizeof(lo_save));
1497 * Linux driver overflows 'val'
1499 if (init_rf_atten >= 0) {
1502 val = rf_atten * 2 + bbp_atten;
1512 lo = bwi_get_rf_lo(mac,
1513 rf_atten, 2 * bbp_atten);
1514 if (!bwi_rf_lo_isused(mac, lo))
1516 bcopy(lo, &lo_save, sizeof(lo_save));
1522 RF_WRITE(mac, BWI_RFR_ATTEN, rf_atten);
1524 tp_ctrl2 = mac->mac_tpctl.tp_ctrl2;
1525 if (init_rf_atten < 0)
1526 tp_ctrl2 |= (3 << 4);
1527 RF_WRITE(mac, BWI_RFR_TXPWR, tp_ctrl2);
1531 bwi_phy_set_bbp_atten(mac, bbp_atten * 2);
1533 rf7a = orig_rf7a & 0xfff0;
1536 RF_WRITE(mac, 0x7a, rf7a);
1538 lo = bwi_get_rf_lo(mac,
1539 rf_lo_measure_order[idx], bbp_atten * 2);
1540 bwi_rf_lo_measure_11g(mac, &lo_save, lo, devi_ctrl);
1545 #undef RF_ATTEN_LISTSZ
1546 #undef BBP_ATTEN_MAX
1550 bwi_rf_lo_measure_11g(struct bwi_mac *mac, const struct bwi_rf_lo *src_lo,
1551 struct bwi_rf_lo *dst_lo, uint8_t devi_ctrl)
1553 #define LO_ADJUST_MIN 1
1554 #define LO_ADJUST_MAX 8
1555 #define LO_ADJUST(hi, lo) { .ctrl_hi = hi, .ctrl_lo = lo }
1556 static const struct bwi_rf_lo rf_lo_adjust[LO_ADJUST_MAX] = {
1568 struct bwi_rf_lo lo_min;
1570 int found, loop_count, adjust_state;
1572 bcopy(src_lo, &lo_min, sizeof(lo_min));
1573 RF_LO_WRITE(mac, &lo_min);
1574 devi_min = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1576 loop_count = 12; /* XXX */
1579 struct bwi_rf_lo lo_base;
1583 if (adjust_state == 0) {
1585 fin = LO_ADJUST_MAX;
1586 } else if (adjust_state % 2 == 0) {
1587 i = adjust_state - 1;
1588 fin = adjust_state + 1;
1590 i = adjust_state - 2;
1591 fin = adjust_state + 2;
1594 if (i < LO_ADJUST_MIN)
1596 KASSERT(i <= LO_ADJUST_MAX && i >= LO_ADJUST_MIN, ("i %d", i));
1598 if (fin > LO_ADJUST_MAX)
1599 fin -= LO_ADJUST_MAX;
1600 KASSERT(fin <= LO_ADJUST_MAX && fin >= LO_ADJUST_MIN,
1603 bcopy(&lo_min, &lo_base, sizeof(lo_base));
1605 struct bwi_rf_lo lo;
1607 lo.ctrl_hi = lo_base.ctrl_hi +
1608 rf_lo_adjust[i - 1].ctrl_hi;
1609 lo.ctrl_lo = lo_base.ctrl_lo +
1610 rf_lo_adjust[i - 1].ctrl_lo;
1612 if (abs(lo.ctrl_lo) < 9 && abs(lo.ctrl_hi) < 9) {
1615 RF_LO_WRITE(mac, &lo);
1616 devi = bwi_rf_lo_devi_measure(mac, devi_ctrl);
1617 if (devi < devi_min) {
1621 bcopy(&lo, &lo_min, sizeof(lo_min));
1626 if (i == LO_ADJUST_MAX)
1631 } while (loop_count-- && found);
1633 bcopy(&lo_min, dst_lo, sizeof(*dst_lo));
1635 #undef LO_ADJUST_MIN
1636 #undef LO_ADJUST_MAX
1640 bwi_rf_calc_nrssi_slope_11b(struct bwi_mac *mac)
1642 #define SAVE_RF_MAX 3
1643 #define SAVE_PHY_MAX 8
1645 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1646 { 0x7a, 0x52, 0x43 };
1647 static const uint16_t save_phy_regs[SAVE_PHY_MAX] =
1648 { 0x30, 0x26, 0x15, 0x2a, 0x20, 0x5a, 0x59, 0x58 };
1650 struct bwi_softc *sc = mac->mac_sc;
1651 struct bwi_rf *rf = &mac->mac_rf;
1652 struct bwi_phy *phy = &mac->mac_phy;
1653 uint16_t save_rf[SAVE_RF_MAX];
1654 uint16_t save_phy[SAVE_PHY_MAX];
1655 uint16_t ant_div, bbp_atten, chan_ex;
1660 * Save RF/PHY registers for later restoration
1662 for (i = 0; i < SAVE_RF_MAX; ++i)
1663 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1664 for (i = 0; i < SAVE_PHY_MAX; ++i)
1665 save_phy[i] = PHY_READ(mac, save_phy_regs[i]);
1667 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1668 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1669 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1674 if (phy->phy_rev >= 5)
1675 RF_CLRBITS(mac, 0x7a, 0xff80);
1677 RF_CLRBITS(mac, 0x7a, 0xfff0);
1678 PHY_WRITE(mac, 0x30, 0xff);
1680 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x7f7f);
1682 PHY_WRITE(mac, 0x26, 0);
1683 PHY_SETBITS(mac, 0x15, 0x20);
1684 PHY_WRITE(mac, 0x2a, 0x8a3);
1685 RF_SETBITS(mac, 0x7a, 0x80);
1687 nrssi[0] = (int16_t)PHY_READ(mac, 0x27);
1692 RF_CLRBITS(mac, 0x7a, 0xff80);
1693 if (phy->phy_version >= 2)
1694 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x40);
1695 else if (phy->phy_version == 0)
1696 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0x122);
1698 CSR_CLRBITS_2(sc, BWI_RF_CHAN_EX, 0xdfff);
1700 PHY_WRITE(mac, 0x20, 0x3f3f);
1701 PHY_WRITE(mac, 0x15, 0xf330);
1703 RF_WRITE(mac, 0x5a, 0x60);
1704 RF_CLRBITS(mac, 0x43, 0xff0f);
1706 PHY_WRITE(mac, 0x5a, 0x480);
1707 PHY_WRITE(mac, 0x59, 0x810);
1708 PHY_WRITE(mac, 0x58, 0xd);
1712 nrssi[1] = (int16_t)PHY_READ(mac, 0x27);
1715 * Restore saved RF/PHY registers
1717 PHY_WRITE(mac, save_phy_regs[0], save_phy[0]);
1718 RF_WRITE(mac, save_rf_regs[0], save_rf[0]);
1720 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
1722 for (i = 1; i < 4; ++i)
1723 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1725 bwi_rf_work_around(mac, rf->rf_curchan);
1727 if (phy->phy_version != 0)
1728 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
1730 for (; i < SAVE_PHY_MAX; ++i)
1731 PHY_WRITE(mac, save_phy_regs[i], save_phy[i]);
1733 for (i = 1; i < SAVE_RF_MAX; ++i)
1734 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1737 * Install calculated narrow RSSI values
1739 if (nrssi[0] == nrssi[1])
1740 rf->rf_nrssi_slope = 0x10000;
1742 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
1743 if (nrssi[0] <= -4) {
1744 rf->rf_nrssi[0] = nrssi[0];
1745 rf->rf_nrssi[1] = nrssi[1];
1753 bwi_rf_set_nrssi_ofs_11g(struct bwi_mac *mac)
1755 #define SAVE_RF_MAX 2
1756 #define SAVE_PHY_COMM_MAX 10
1757 #define SAVE_PHY6_MAX 8
1759 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1761 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] = {
1762 0x0001, 0x0811, 0x0812, 0x0814,
1763 0x0815, 0x005a, 0x0059, 0x0058,
1766 static const uint16_t save_phy6_regs[SAVE_PHY6_MAX] = {
1767 0x002e, 0x002f, 0x080f, 0x0810,
1768 0x0801, 0x0060, 0x0014, 0x0478
1771 struct bwi_phy *phy = &mac->mac_phy;
1772 uint16_t save_rf[SAVE_RF_MAX];
1773 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1774 uint16_t save_phy6[SAVE_PHY6_MAX];
1775 uint16_t rf7b = 0xffff;
1777 int i, phy6_idx = 0;
1779 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1780 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1781 for (i = 0; i < SAVE_RF_MAX; ++i)
1782 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1784 PHY_CLRBITS(mac, 0x429, 0x8000);
1785 PHY_FILT_SETBITS(mac, 0x1, 0x3fff, 0x4000);
1786 PHY_SETBITS(mac, 0x811, 0xc);
1787 PHY_FILT_SETBITS(mac, 0x812, 0xfff3, 0x4);
1788 PHY_CLRBITS(mac, 0x802, 0x3);
1790 if (phy->phy_rev >= 6) {
1791 for (i = 0; i < SAVE_PHY6_MAX; ++i)
1792 save_phy6[i] = PHY_READ(mac, save_phy6_regs[i]);
1794 PHY_WRITE(mac, 0x2e, 0);
1795 PHY_WRITE(mac, 0x2f, 0);
1796 PHY_WRITE(mac, 0x80f, 0);
1797 PHY_WRITE(mac, 0x810, 0);
1798 PHY_SETBITS(mac, 0x478, 0x100);
1799 PHY_SETBITS(mac, 0x801, 0x40);
1800 PHY_SETBITS(mac, 0x60, 0x40);
1801 PHY_SETBITS(mac, 0x14, 0x200);
1804 RF_SETBITS(mac, 0x7a, 0x70);
1805 RF_SETBITS(mac, 0x7a, 0x80);
1809 nrssi = bwi_nrssi_11g(mac);
1811 for (i = 7; i >= 4; --i) {
1812 RF_WRITE(mac, 0x7b, i);
1814 nrssi = bwi_nrssi_11g(mac);
1815 if (nrssi < 31 && rf7b == 0xffff)
1821 struct bwi_gains gains;
1823 RF_CLRBITS(mac, 0x7a, 0xff80);
1825 PHY_SETBITS(mac, 0x814, 0x1);
1826 PHY_CLRBITS(mac, 0x815, 0x1);
1827 PHY_SETBITS(mac, 0x811, 0xc);
1828 PHY_SETBITS(mac, 0x812, 0xc);
1829 PHY_SETBITS(mac, 0x811, 0x30);
1830 PHY_SETBITS(mac, 0x812, 0x30);
1831 PHY_WRITE(mac, 0x5a, 0x480);
1832 PHY_WRITE(mac, 0x59, 0x810);
1833 PHY_WRITE(mac, 0x58, 0xd);
1834 if (phy->phy_version == 0)
1835 PHY_WRITE(mac, 0x3, 0x122);
1837 PHY_SETBITS(mac, 0xa, 0x2000);
1838 PHY_SETBITS(mac, 0x814, 0x4);
1839 PHY_CLRBITS(mac, 0x815, 0x4);
1840 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
1841 RF_SETBITS(mac, 0x7a, 0xf);
1843 bzero(&gains, sizeof(gains));
1844 gains.tbl_gain1 = 3;
1845 gains.tbl_gain2 = 0;
1847 bwi_set_gains(mac, &gains);
1849 RF_FILT_SETBITS(mac, 0x43, 0xf0, 0xf);
1852 nrssi = bwi_nrssi_11g(mac);
1854 for (i = 0; i < 4; ++i) {
1855 RF_WRITE(mac, 0x7b, i);
1857 nrssi = bwi_nrssi_11g(mac);
1858 if (nrssi > -31 && rf7b == 0xffff)
1867 RF_WRITE(mac, 0x7b, rf7b);
1870 * Restore saved RF/PHY registers
1872 if (phy->phy_rev >= 6) {
1873 for (phy6_idx = 0; phy6_idx < 4; ++phy6_idx) {
1874 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1875 save_phy6[phy6_idx]);
1879 /* Saved PHY registers 0, 1, 2 are handled later */
1880 for (i = 3; i < SAVE_PHY_COMM_MAX; ++i)
1881 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
1883 for (i = SAVE_RF_MAX - 1; i >= 0; --i)
1884 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
1886 PHY_SETBITS(mac, 0x802, 0x3);
1887 PHY_SETBITS(mac, 0x429, 0x8000);
1889 bwi_set_gains(mac, NULL);
1891 if (phy->phy_rev >= 6) {
1892 for (; phy6_idx < SAVE_PHY6_MAX; ++phy6_idx) {
1893 PHY_WRITE(mac, save_phy6_regs[phy6_idx],
1894 save_phy6[phy6_idx]);
1898 PHY_WRITE(mac, save_phy_comm_regs[0], save_phy_comm[0]);
1899 PHY_WRITE(mac, save_phy_comm_regs[2], save_phy_comm[2]);
1900 PHY_WRITE(mac, save_phy_comm_regs[1], save_phy_comm[1]);
1903 #undef SAVE_PHY_COMM_MAX
1904 #undef SAVE_PHY6_MAX
1908 bwi_rf_calc_nrssi_slope_11g(struct bwi_mac *mac)
1910 #define SAVE_RF_MAX 3
1911 #define SAVE_PHY_COMM_MAX 4
1912 #define SAVE_PHY3_MAX 8
1914 static const uint16_t save_rf_regs[SAVE_RF_MAX] =
1915 { 0x7a, 0x52, 0x43 };
1916 static const uint16_t save_phy_comm_regs[SAVE_PHY_COMM_MAX] =
1917 { 0x15, 0x5a, 0x59, 0x58 };
1918 static const uint16_t save_phy3_regs[SAVE_PHY3_MAX] = {
1919 0x002e, 0x002f, 0x080f, 0x0810,
1920 0x0801, 0x0060, 0x0014, 0x0478
1923 struct bwi_softc *sc = mac->mac_sc;
1924 struct bwi_phy *phy = &mac->mac_phy;
1925 struct bwi_rf *rf = &mac->mac_rf;
1926 uint16_t save_rf[SAVE_RF_MAX];
1927 uint16_t save_phy_comm[SAVE_PHY_COMM_MAX];
1928 uint16_t save_phy3[SAVE_PHY3_MAX];
1929 uint16_t ant_div, bbp_atten, chan_ex;
1930 struct bwi_gains gains;
1932 int i, phy3_idx = 0;
1934 if (rf->rf_rev >= 9)
1936 else if (rf->rf_rev == 8)
1937 bwi_rf_set_nrssi_ofs_11g(mac);
1939 PHY_CLRBITS(mac, 0x429, 0x8000);
1940 PHY_CLRBITS(mac, 0x802, 0x3);
1943 * Save RF/PHY registers for later restoration
1945 ant_div = CSR_READ_2(sc, BWI_RF_ANTDIV);
1946 CSR_SETBITS_2(sc, BWI_RF_ANTDIV, 0x8000);
1948 for (i = 0; i < SAVE_RF_MAX; ++i)
1949 save_rf[i] = RF_READ(mac, save_rf_regs[i]);
1950 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
1951 save_phy_comm[i] = PHY_READ(mac, save_phy_comm_regs[i]);
1953 bbp_atten = CSR_READ_2(sc, BWI_BBP_ATTEN);
1954 chan_ex = CSR_READ_2(sc, BWI_RF_CHAN_EX);
1956 if (phy->phy_rev >= 3) {
1957 for (i = 0; i < SAVE_PHY3_MAX; ++i)
1958 save_phy3[i] = PHY_READ(mac, save_phy3_regs[i]);
1960 PHY_WRITE(mac, 0x2e, 0);
1961 PHY_WRITE(mac, 0x810, 0);
1963 if (phy->phy_rev == 4 || phy->phy_rev == 6 ||
1964 phy->phy_rev == 7) {
1965 PHY_SETBITS(mac, 0x478, 0x100);
1966 PHY_SETBITS(mac, 0x810, 0x40);
1967 } else if (phy->phy_rev == 3 || phy->phy_rev == 5) {
1968 PHY_CLRBITS(mac, 0x810, 0x40);
1971 PHY_SETBITS(mac, 0x60, 0x40);
1972 PHY_SETBITS(mac, 0x14, 0x200);
1978 RF_SETBITS(mac, 0x7a, 0x70);
1980 bzero(&gains, sizeof(gains));
1981 gains.tbl_gain1 = 0;
1982 gains.tbl_gain2 = 8;
1984 bwi_set_gains(mac, &gains);
1986 RF_CLRBITS(mac, 0x7a, 0xff08);
1987 if (phy->phy_rev >= 2) {
1988 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x30);
1989 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x10);
1992 RF_SETBITS(mac, 0x7a, 0x80);
1994 nrssi[0] = bwi_nrssi_11g(mac);
1999 RF_CLRBITS(mac, 0x7a, 0xff80);
2000 if (phy->phy_version >= 2)
2001 PHY_FILT_SETBITS(mac, 0x3, 0xff9f, 0x40);
2002 CSR_SETBITS_2(sc, BWI_RF_CHAN_EX, 0x2000);
2004 RF_SETBITS(mac, 0x7a, 0xf);
2005 PHY_WRITE(mac, 0x15, 0xf330);
2006 if (phy->phy_rev >= 2) {
2007 PHY_FILT_SETBITS(mac, 0x812, 0xffcf, 0x20);
2008 PHY_FILT_SETBITS(mac, 0x811, 0xffcf, 0x20);
2011 bzero(&gains, sizeof(gains));
2012 gains.tbl_gain1 = 3;
2013 gains.tbl_gain2 = 0;
2015 bwi_set_gains(mac, &gains);
2017 if (rf->rf_rev == 8) {
2018 RF_WRITE(mac, 0x43, 0x1f);
2020 RF_FILT_SETBITS(mac, 0x52, 0xff0f, 0x60);
2021 RF_FILT_SETBITS(mac, 0x43, 0xfff0, 0x9);
2023 PHY_WRITE(mac, 0x5a, 0x480);
2024 PHY_WRITE(mac, 0x59, 0x810);
2025 PHY_WRITE(mac, 0x58, 0xd);
2028 nrssi[1] = bwi_nrssi_11g(mac);
2031 * Install calculated narrow RSSI values
2033 if (nrssi[1] == nrssi[0])
2034 rf->rf_nrssi_slope = 0x10000;
2036 rf->rf_nrssi_slope = 0x400000 / (nrssi[0] - nrssi[1]);
2037 if (nrssi[0] >= -4) {
2038 rf->rf_nrssi[0] = nrssi[1];
2039 rf->rf_nrssi[1] = nrssi[0];
2043 * Restore saved RF/PHY registers
2045 if (phy->phy_rev >= 3) {
2046 for (phy3_idx = 0; phy3_idx < 4; ++phy3_idx) {
2047 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2048 save_phy3[phy3_idx]);
2051 if (phy->phy_rev >= 2) {
2052 PHY_CLRBITS(mac, 0x812, 0x30);
2053 PHY_CLRBITS(mac, 0x811, 0x30);
2056 for (i = 0; i < SAVE_RF_MAX; ++i)
2057 RF_WRITE(mac, save_rf_regs[i], save_rf[i]);
2059 CSR_WRITE_2(sc, BWI_RF_ANTDIV, ant_div);
2060 CSR_WRITE_2(sc, BWI_BBP_ATTEN, bbp_atten);
2061 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, chan_ex);
2063 for (i = 0; i < SAVE_PHY_COMM_MAX; ++i)
2064 PHY_WRITE(mac, save_phy_comm_regs[i], save_phy_comm[i]);
2066 bwi_rf_work_around(mac, rf->rf_curchan);
2067 PHY_SETBITS(mac, 0x802, 0x3);
2068 bwi_set_gains(mac, NULL);
2069 PHY_SETBITS(mac, 0x429, 0x8000);
2071 if (phy->phy_rev >= 3) {
2072 for (; phy3_idx < SAVE_PHY3_MAX; ++phy3_idx) {
2073 PHY_WRITE(mac, save_phy3_regs[phy3_idx],
2074 save_phy3[phy3_idx]);
2078 bwi_rf_init_sw_nrssi_table(mac);
2079 bwi_rf_set_nrssi_thr_11g(mac);
2082 #undef SAVE_PHY_COMM_MAX
2083 #undef SAVE_PHY3_MAX
2087 bwi_rf_init_sw_nrssi_table(struct bwi_mac *mac)
2089 struct bwi_rf *rf = &mac->mac_rf;
2092 d = 0x1f - rf->rf_nrssi[0];
2093 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2096 val = (((i - d) * rf->rf_nrssi_slope) / 0x10000) + 0x3a;
2099 else if (val > 0x3f)
2102 rf->rf_nrssi_table[i] = val;
2107 bwi_rf_init_hw_nrssi_table(struct bwi_mac *mac, uint16_t adjust)
2111 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i) {
2114 val = bwi_nrssi_read(mac, i);
2122 bwi_nrssi_write(mac, i, val);
2127 bwi_rf_set_nrssi_thr_11b(struct bwi_mac *mac)
2129 struct bwi_rf *rf = &mac->mac_rf;
2132 if (rf->rf_type != BWI_RF_T_BCM2050 ||
2133 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0)
2137 * Calculate nrssi threshold
2139 if (rf->rf_rev >= 6) {
2140 thr = (rf->rf_nrssi[1] - rf->rf_nrssi[0]) * 32;
2141 thr += 20 * (rf->rf_nrssi[0] + 1);
2144 thr = rf->rf_nrssi[1] - 5;
2148 else if (thr > 0x3e)
2151 PHY_READ(mac, BWI_PHYR_NRSSI_THR_11B); /* dummy read */
2152 PHY_WRITE(mac, BWI_PHYR_NRSSI_THR_11B, (((uint16_t)thr) << 8) | 0x1c);
2154 if (rf->rf_rev >= 6) {
2155 PHY_WRITE(mac, 0x87, 0xe0d);
2156 PHY_WRITE(mac, 0x86, 0xc0b);
2157 PHY_WRITE(mac, 0x85, 0xa09);
2158 PHY_WRITE(mac, 0x84, 0x808);
2159 PHY_WRITE(mac, 0x83, 0x808);
2160 PHY_WRITE(mac, 0x82, 0x604);
2161 PHY_WRITE(mac, 0x81, 0x302);
2162 PHY_WRITE(mac, 0x80, 0x100);
2166 static __inline int32_t
2167 _nrssi_threshold(const struct bwi_rf *rf, int32_t val)
2169 val *= (rf->rf_nrssi[1] - rf->rf_nrssi[0]);
2170 val += (rf->rf_nrssi[0] << 6);
2184 bwi_rf_set_nrssi_thr_11g(struct bwi_mac *mac)
2190 * Find the two nrssi thresholds
2192 if ((mac->mac_phy.phy_flags & BWI_PHY_F_LINKED) == 0 ||
2193 (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) == 0) {
2196 nrssi = bwi_nrssi_read(mac, 0x20);
2208 /* TODO Interfere mode */
2209 thr1 = _nrssi_threshold(&mac->mac_rf, 0x11);
2210 thr2 = _nrssi_threshold(&mac->mac_rf, 0xe);
2213 #define NRSSI_THR1_MASK __BITS(5, 0)
2214 #define NRSSI_THR2_MASK __BITS(11, 6)
2216 thr = __SHIFTIN((uint32_t)thr1, NRSSI_THR1_MASK) |
2217 __SHIFTIN((uint32_t)thr2, NRSSI_THR2_MASK);
2218 PHY_FILT_SETBITS(mac, BWI_PHYR_NRSSI_THR_11G, 0xf000, thr);
2220 #undef NRSSI_THR1_MASK
2221 #undef NRSSI_THR2_MASK
2225 bwi_rf_clear_tssi(struct bwi_mac *mac)
2227 /* XXX use function pointer */
2228 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11A) {
2234 val = __SHIFTIN(BWI_INVALID_TSSI, BWI_LO_TSSI_MASK) |
2235 __SHIFTIN(BWI_INVALID_TSSI, BWI_HI_TSSI_MASK);
2237 for (i = 0; i < 2; ++i) {
2238 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2239 BWI_COMM_MOBJ_TSSI_DS + (i * 2), val);
2242 for (i = 0; i < 2; ++i) {
2243 MOBJ_WRITE_2(mac, BWI_COMM_MOBJ,
2244 BWI_COMM_MOBJ_TSSI_OFDM + (i * 2), val);
2250 bwi_rf_clear_state(struct bwi_rf *rf)
2254 rf->rf_flags &= ~BWI_RF_CLEAR_FLAGS;
2255 bzero(rf->rf_lo, sizeof(rf->rf_lo));
2256 bzero(rf->rf_lo_used, sizeof(rf->rf_lo_used));
2258 rf->rf_nrssi_slope = 0;
2259 rf->rf_nrssi[0] = BWI_INVALID_NRSSI;
2260 rf->rf_nrssi[1] = BWI_INVALID_NRSSI;
2262 for (i = 0; i < BWI_NRSSI_TBLSZ; ++i)
2263 rf->rf_nrssi_table[i] = i;
2268 bcopy(rf->rf_txpower_map0, rf->rf_txpower_map,
2269 sizeof(rf->rf_txpower_map));
2270 rf->rf_idle_tssi = rf->rf_idle_tssi0;
2274 bwi_rf_on_11a(struct bwi_mac *mac)
2280 bwi_rf_on_11bg(struct bwi_mac *mac)
2282 struct bwi_phy *phy = &mac->mac_phy;
2284 PHY_WRITE(mac, 0x15, 0x8000);
2285 PHY_WRITE(mac, 0x15, 0xcc00);
2286 if (phy->phy_flags & BWI_PHY_F_LINKED)
2287 PHY_WRITE(mac, 0x15, 0xc0);
2289 PHY_WRITE(mac, 0x15, 0);
2291 bwi_rf_set_chan(mac, 6 /* XXX */, 1);
2295 bwi_rf_set_ant_mode(struct bwi_mac *mac, int ant_mode)
2297 struct bwi_softc *sc = mac->mac_sc;
2298 struct bwi_phy *phy = &mac->mac_phy;
2301 KASSERT(ant_mode == BWI_ANT_MODE_0 ||
2302 ant_mode == BWI_ANT_MODE_1 ||
2303 ant_mode == BWI_ANT_MODE_AUTO, ("ant_mode %d", ant_mode));
2305 HFLAGS_CLRBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2307 if (phy->phy_mode == IEEE80211_MODE_11B) {
2308 /* NOTE: v4/v3 conflicts, take v3 */
2309 if (mac->mac_rev == 2)
2310 val = BWI_ANT_MODE_AUTO;
2314 PHY_FILT_SETBITS(mac, 0x3e2, 0xfe7f, val);
2315 } else { /* 11a/g */
2316 /* XXX reg/value naming */
2317 val = ant_mode << 7;
2318 PHY_FILT_SETBITS(mac, 0x401, 0x7e7f, val);
2320 if (ant_mode == BWI_ANT_MODE_AUTO)
2321 PHY_CLRBITS(mac, 0x42b, 0x100);
2323 if (phy->phy_mode == IEEE80211_MODE_11A) {
2326 if (ant_mode == BWI_ANT_MODE_AUTO)
2327 PHY_SETBITS(mac, 0x48c, 0x2000);
2329 PHY_CLRBITS(mac, 0x48c, 0x2000);
2331 if (phy->phy_rev >= 2) {
2332 PHY_SETBITS(mac, 0x461, 0x10);
2333 PHY_FILT_SETBITS(mac, 0x4ad, 0xff00, 0x15);
2334 if (phy->phy_rev == 2) {
2335 PHY_WRITE(mac, 0x427, 0x8);
2337 PHY_FILT_SETBITS(mac, 0x427,
2341 if (phy->phy_rev >= 6)
2342 PHY_WRITE(mac, 0x49b, 0xdc);
2347 /* XXX v4 set AUTO_ANTDIV unconditionally */
2348 if (ant_mode == BWI_ANT_MODE_AUTO)
2349 HFLAGS_SETBITS(mac, BWI_HFLAG_AUTO_ANTDIV);
2351 val = ant_mode << 8;
2352 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_BEACON,
2354 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_ACK,
2356 MOBJ_FILT_SETBITS_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_TX_PROBE_RESP,
2359 /* XXX what's these */
2360 if (phy->phy_mode == IEEE80211_MODE_11B)
2361 CSR_SETBITS_2(sc, 0x5e, 0x4);
2363 CSR_WRITE_4(sc, 0x100, 0x1000000);
2364 if (mac->mac_rev < 5)
2365 CSR_WRITE_4(sc, 0x10c, 0x1000000);
2367 mac->mac_rf.rf_ant_mode = ant_mode;
2371 bwi_rf_get_latest_tssi(struct bwi_mac *mac, int8_t tssi[], uint16_t ofs)
2375 for (i = 0; i < 4; ) {
2378 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, ofs + i);
2379 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_LO_TSSI_MASK);
2380 tssi[i++] = (int8_t)__SHIFTOUT(val, BWI_HI_TSSI_MASK);
2383 for (i = 0; i < 4; ++i) {
2384 if (tssi[i] == BWI_INVALID_TSSI)
2391 bwi_rf_tssi2dbm(struct bwi_mac *mac, int8_t tssi, int8_t *txpwr)
2393 struct bwi_rf *rf = &mac->mac_rf;
2396 pwr_idx = rf->rf_idle_tssi + (int)tssi - rf->rf_base_tssi;
2398 if (pwr_idx < 0 || pwr_idx >= BWI_TSSI_MAX)
2403 else if (pwr_idx >= BWI_TSSI_MAX)
2404 pwr_idx = BWI_TSSI_MAX - 1;
2407 *txpwr = rf->rf_txpower_map[pwr_idx];
2412 bwi_rf_calc_rssi_bcm2050(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2414 uint16_t flags1, flags3;
2417 rssi = hdr->rxh_rssi;
2418 flags1 = le16toh(hdr->rxh_flags1);
2419 flags3 = le16toh(hdr->rxh_flags3);
2421 if (flags1 & BWI_RXH_F1_OFDM) {
2424 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2431 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2432 struct bwi_rf *rf = &mac->mac_rf;
2434 if (rssi >= BWI_NRSSI_TBLSZ)
2435 rssi = BWI_NRSSI_TBLSZ - 1;
2437 rssi = ((31 - (int)rf->rf_nrssi_table[rssi]) * -131) / 128;
2440 rssi = ((31 - rssi) * -149) / 128;
2444 if (mac->mac_phy.phy_mode != IEEE80211_MODE_11G)
2447 if (flags3 & BWI_RXH_F3_BCM2050_RSSI)
2450 lna_gain = __SHIFTOUT(le16toh(hdr->rxh_phyinfo),
2451 BWI_RXH_PHYINFO_LNAGAIN);
2452 DPRINTF(mac->mac_sc, BWI_DBG_RF | BWI_DBG_RX,
2453 "lna_gain %d, phyinfo 0x%04x\n",
2454 lna_gain, le16toh(hdr->rxh_phyinfo));
2468 * According to v3 spec, we should do _nothing_ here,
2469 * but it seems that the result RSSI will be too low
2470 * (relative to what ath(4) says). Raise it a little
2476 panic("impossible lna gain %d", lna_gain);
2482 bwi_rf_calc_rssi_bcm2053(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2487 rssi = (((int)hdr->rxh_rssi - 11) * 103) / 64;
2489 flags1 = le16toh(hdr->rxh_flags1);
2490 if (flags1 & BWI_RXH_F1_BCM2053_RSSI)
2498 bwi_rf_calc_rssi_bcm2060(struct bwi_mac *mac, const struct bwi_rxbuf_hdr *hdr)
2502 rssi = hdr->rxh_rssi;
2509 bwi_rf_calc_noise_bcm2050(struct bwi_mac *mac)
2514 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_RF_NOISE);
2515 noise = (int)val; /* XXX check bounds? */
2517 if (mac->mac_sc->sc_card_flags & BWI_CARD_F_SW_NRSSI) {
2518 struct bwi_rf *rf = &mac->mac_rf;
2520 if (noise >= BWI_NRSSI_TBLSZ)
2521 noise = BWI_NRSSI_TBLSZ - 1;
2523 noise = ((31 - (int)rf->rf_nrssi_table[noise]) * -131) / 128;
2526 noise = ((31 - noise) * -149) / 128;
2533 bwi_rf_calc_noise_bcm2053(struct bwi_mac *mac)
2538 val = MOBJ_READ_2(mac, BWI_COMM_MOBJ, BWI_COMM_MOBJ_RF_NOISE);
2539 noise = (int)val; /* XXX check bounds? */
2541 noise = ((noise - 11) * 103) / 64;
2547 bwi_rf_calc_noise_bcm2060(struct bwi_mac *mac)
2549 /* XXX Dont know how to calc */
2550 return (BWI_NOISE_FLOOR);
2554 bwi_rf_lo_measure_11b(struct bwi_mac *mac)
2560 for (i = 0; i < 10; ++i) {
2561 PHY_WRITE(mac, 0x15, 0xafa0);
2563 PHY_WRITE(mac, 0x15, 0xefa0);
2565 PHY_WRITE(mac, 0x15, 0xffa0);
2568 val += PHY_READ(mac, 0x2c);
2574 bwi_rf_lo_update_11b(struct bwi_mac *mac)
2576 struct bwi_softc *sc = mac->mac_sc;
2577 struct bwi_rf *rf = &mac->mac_rf;
2578 struct rf_saveregs regs;
2579 uint16_t rf_val, phy_val, min_val, val;
2580 uint16_t rf52, bphy_ctrl;
2583 DPRINTF(sc, BWI_DBG_RF | BWI_DBG_INIT, "%s enter\n", __func__);
2585 bzero(®s, sizeof(regs));
2589 * Save RF/PHY registers for later restoration
2591 SAVE_PHY_REG(mac, ®s, 15);
2592 rf52 = RF_READ(mac, 0x52) & 0xfff0;
2593 if (rf->rf_type == BWI_RF_T_BCM2050) {
2594 SAVE_PHY_REG(mac, ®s, 0a);
2595 SAVE_PHY_REG(mac, ®s, 2a);
2596 SAVE_PHY_REG(mac, ®s, 35);
2597 SAVE_PHY_REG(mac, ®s, 03);
2598 SAVE_PHY_REG(mac, ®s, 01);
2599 SAVE_PHY_REG(mac, ®s, 30);
2601 SAVE_RF_REG(mac, ®s, 43);
2602 SAVE_RF_REG(mac, ®s, 7a);
2604 bphy_ctrl = CSR_READ_2(sc, BWI_BPHY_CTRL);
2606 SAVE_RF_REG(mac, ®s, 52);
2609 PHY_WRITE(mac, 0x30, 0xff);
2610 CSR_WRITE_2(sc, BWI_PHY_CTRL, 0x3f3f);
2611 PHY_WRITE(mac, 0x35, regs.phy_35 & 0xff7f);
2612 RF_WRITE(mac, 0x7a, regs.rf_7a & 0xfff0);
2615 PHY_WRITE(mac, 0x15, 0xb000);
2617 if (rf->rf_type == BWI_RF_T_BCM2050) {
2618 PHY_WRITE(mac, 0x2b, 0x203);
2619 PHY_WRITE(mac, 0x2a, 0x8a3);
2621 PHY_WRITE(mac, 0x2b, 0x1402);
2628 min_val = UINT16_MAX;
2630 for (i = 0; i < 4; ++i) {
2631 RF_WRITE(mac, 0x52, rf52 | i);
2632 bwi_rf_lo_measure_11b(mac); /* Ignore return value */
2634 for (i = 0; i < 10; ++i) {
2635 RF_WRITE(mac, 0x52, rf52 | i);
2637 val = bwi_rf_lo_measure_11b(mac) / 10;
2638 if (val < min_val) {
2643 RF_WRITE(mac, 0x52, rf52 | rf_val);
2649 min_val = UINT16_MAX;
2651 for (i = -4; i < 5; i += 2) {
2654 for (j = -4; j < 5; j += 2) {
2657 phy2f = (0x100 * i) + j;
2660 PHY_WRITE(mac, 0x2f, phy2f);
2662 val = bwi_rf_lo_measure_11b(mac) / 10;
2663 if (val < min_val) {
2669 PHY_WRITE(mac, 0x2f, phy_val + 0x101);
2672 * Restore saved RF/PHY registers
2674 if (rf->rf_type == BWI_RF_T_BCM2050) {
2675 RESTORE_PHY_REG(mac, ®s, 0a);
2676 RESTORE_PHY_REG(mac, ®s, 2a);
2677 RESTORE_PHY_REG(mac, ®s, 35);
2678 RESTORE_PHY_REG(mac, ®s, 03);
2679 RESTORE_PHY_REG(mac, ®s, 01);
2680 RESTORE_PHY_REG(mac, ®s, 30);
2682 RESTORE_RF_REG(mac, ®s, 43);
2683 RESTORE_RF_REG(mac, ®s, 7a);
2685 RF_FILT_SETBITS(mac, 0x52, 0xf, regs.rf_52);
2687 CSR_WRITE_2(sc, BWI_BPHY_CTRL, bphy_ctrl);
2689 RESTORE_PHY_REG(mac, ®s, 15);
2691 bwi_rf_work_around(mac, rf->rf_curchan);