2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwivar.h,v 1.14 2008/02/15 11:15:38 sephe Exp $
41 #define BWI_ALIGN 0x1000
42 #define BWI_RING_ALIGN BWI_ALIGN
43 #define BWI_BUS_SPACE_MAXADDR 0x3fffffff
45 #define BWI_TX_NRING 6
46 #define BWI_TXRX_NRING 6
47 #define BWI_TX_NDESC 128
48 #define BWI_RX_NDESC 64
49 #define BWI_TXSTATS_NDESC 64
50 #define BWI_TX_NSPRDESC 2
51 #define BWI_TX_DATA_RING 1
53 /* XXX Onoe/Sample/AMRR probably need different configuration */
56 #define BWI_SHRETRY_FB 3
57 #define BWI_LGRETRY_FB 2
59 #define BWI_LED_EVENT_NONE -1
60 #define BWI_LED_EVENT_POLL 0
61 #define BWI_LED_EVENT_TX 1
62 #define BWI_LED_EVENT_RX 2
63 #define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2)
65 enum bwi_txpwrcb_type {
71 #define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
72 #define BWI_FRAME_MIN_LEN(hdr) \
73 ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
75 #define CSR_READ_4(sc, reg) \
76 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
77 #define CSR_READ_2(sc, reg) \
78 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
80 #define CSR_WRITE_4(sc, reg, val) \
81 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
82 #define CSR_WRITE_2(sc, reg, val) \
83 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
85 #define CSR_SETBITS_4(sc, reg, bits) \
86 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
87 #define CSR_SETBITS_2(sc, reg, bits) \
88 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
90 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
91 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
92 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
93 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
95 #define CSR_CLRBITS_4(sc, reg, bits) \
96 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
97 #define CSR_CLRBITS_2(sc, reg, bits) \
98 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
102 #define DPRINTF(sc, dbg, fmt, ...) \
104 if ((sc)->sc_debug & (dbg)) \
105 device_printf((sc)->sc_dev, fmt, __VA_ARGS__); \
108 #define _DPRINTF(sc, dbg, fmt, ...) \
110 if ((sc)->sc_debug & (dbg)) \
111 printf(fmt, __VA_ARGS__); \
114 #else /* !BWI_DEBUG */
116 #define DPRINTF(sc, dbg, fmt, ...) ((void)0)
117 #define _DPRINTF(sc, dbg, fmt, ...) ((void)0)
119 #endif /* BWI_DEBUG */
124 uint32_t addr; /* BWI_DESC32_A_ */
127 #define BWI_DESC32_A_FUNC_TXRX 0x1
128 #define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
129 #define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
131 #define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
132 #define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
133 #define BWI_DESC32_C_EOR __BIT(28)
134 #define BWI_DESC32_C_INTR __BIT(29)
135 #define BWI_DESC32_C_FRAME_END __BIT(30)
136 #define BWI_DESC32_C_FRAME_START __BIT(31)
146 struct bwi_rxbuf_hdr {
148 uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */
150 uint16_t rxh_flags1; /* BWI_RXH_F1_ */
153 uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */
154 uint16_t rxh_flags3; /* BWI_RXH_F3_ */
155 uint16_t rxh_flags2; /* BWI_RXH_F2_ */
157 uint8_t rxh_pad3[14]; /* Padded to 30bytes */
160 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
161 #define BWI_RXH_F1_SHPREAMBLE __BIT(7)
162 #define BWI_RXH_F1_OFDM __BIT(0)
164 #define BWI_RXH_F2_TYPE2FRAME __BIT(2)
166 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
168 #define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
170 struct bwi_txbuf_hdr {
172 uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */
174 uint16_t txh_unknown1;
175 uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */
177 uint8_t txh_addr1[IEEE80211_ADDR_LEN];
178 uint16_t txh_unknown2;
179 uint8_t txh_rts_fb_plcp[4];
180 uint16_t txh_rts_fb_duration;
181 uint8_t txh_fb_plcp[4];
182 uint16_t txh_fb_duration;
184 uint16_t txh_id; /* BWI_TXH_ID_ */
185 uint16_t txh_unknown3;
186 uint8_t txh_rts_plcp[6];
187 uint8_t txh_rts_fc[2];
188 uint16_t txh_rts_duration;
189 uint8_t txh_rts_ra[IEEE80211_ADDR_LEN];
190 uint8_t txh_rts_ta[IEEE80211_ADDR_LEN];
195 #define BWI_TXH_ID_RING_MASK __BITS(15, 13)
196 #define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
198 #define BWI_TXH_PHY_C_OFDM __BIT(0)
199 #define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)
200 #define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
202 #define BWI_TXH_MAC_C_ACK __BIT(0)
203 #define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)
204 #define BWI_TXH_MAC_C_HWSEQ __BIT(4)
205 #define BWI_TXH_MAC_C_FB_OFDM __BIT(8)
211 uint8_t txs_flags; /* BWI_TXS_F_ */
212 uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */
215 uint16_t txs_unknown;
216 uint8_t txs_pad3[2]; /* Padded to 16bytes */
219 #define BWI_TXS_TXCNT_DATA __BITS(7, 4)
221 #define BWI_TXS_F_ACKED __BIT(0)
222 #define BWI_TXS_F_PENDING __BIT(5)
224 struct bwi_ring_data {
225 uint32_t rdata_txrx_ctrl;
226 bus_dmamap_t rdata_dmap;
227 bus_addr_t rdata_paddr;
232 struct mbuf *tb_mbuf;
233 bus_dmamap_t tb_dmap;
235 struct ieee80211_node *tb_ni;
239 struct bwi_txbuf_data {
240 struct bwi_txbuf tbd_buf[BWI_TX_NDESC];
246 struct mbuf *rb_mbuf;
248 bus_dmamap_t rb_dmap;
251 struct bwi_rxbuf_data {
252 struct bwi_rxbuf rbd_buf[BWI_RX_NDESC];
253 bus_dmamap_t rbd_tmp_dmap;
257 struct bwi_txstats_data {
258 bus_dma_tag_t stats_ring_dtag;
259 bus_dmamap_t stats_ring_dmap;
260 bus_addr_t stats_ring_paddr;
263 bus_dma_tag_t stats_dtag;
264 bus_dmamap_t stats_dmap;
265 bus_addr_t stats_paddr;
266 struct bwi_txstats *stats;
268 uint32_t stats_ctrl_base;
274 uint8_t fw_type; /* BWI_FW_T_ */
275 uint8_t fw_gen; /* BWI_FW_GEN */
278 #define fw_iv_cnt fw_size
281 #define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
283 #define BWI_FW_T_UCODE 'u'
284 #define BWI_FW_T_PCM 'p'
285 #define BWI_FW_T_IV 'i'
287 #define BWI_FW_GEN_1 1
289 #define BWI_FW_VERSION3 3
290 #define BWI_FW_VERSION4 4
291 #define BWI_FW_VERSION3_REVMAX 0x128
293 #define BWI_FW_PATH "bwi_v%d_"
294 #define BWI_FW_STUB_PATH BWI_FW_PATH "ucode"
295 #define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d"
296 #define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d"
297 #define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d"
298 #define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d"
309 #define BWI_FW_IV_OFS_MASK __BITS(14, 0)
310 #define BWI_FW_IV_IS_32BIT __BIT(15)
313 uint8_t l_flags; /* BWI_LED_F_ */
314 uint8_t l_act; /* BWI_LED_ACT_ */
318 #define BWI_LED_F_ACTLOW 0x1
319 #define BWI_LED_F_BLINK 0x2
320 #define BWI_LED_F_POLLABLE 0x4
321 #define BWI_LED_F_SLOW 0x8
323 enum bwi_clock_mode {
330 uint32_t rw_flags; /* BWI_REGWIN_F_ */
331 uint16_t rw_type; /* BWI_REGWIN_T_ */
336 #define BWI_REGWIN_F_EXIST 0x1
338 #define BWI_CREATE_REGWIN(rw, id, type, rev) \
340 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \
341 (rw)->rw_type = (type); \
342 (rw)->rw_id = (id); \
343 (rw)->rw_rev = (rev); \
346 #define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
347 #define BWI_GPIO_REGWIN(sc) \
348 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
349 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
354 enum ieee80211_phymode phy_mode;
358 uint32_t phy_flags; /* BWI_PHY_F_ */
359 uint16_t phy_tbl_ctrl;
360 uint16_t phy_tbl_data_lo;
361 uint16_t phy_tbl_data_hi;
363 void (*phy_init)(struct bwi_mac *);
366 #define BWI_PHY_F_CALIBRATED 0x1
367 #define BWI_PHY_F_LINKED 0x2
368 #define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
370 /* TX power control */
372 uint16_t bbp_atten; /* BBP attenuation: 4bits */
373 uint16_t rf_atten; /* RF attenuation */
374 uint16_t tp_ctrl1; /* ??: 3bits */
375 uint16_t tp_ctrl2; /* ??: 4bits */
378 #define BWI_RF_ATTEN_FACTOR 4
379 #define BWI_RF_ATTEN_MAX0 9
380 #define BWI_RF_ATTEN_MAX1 31
381 #define BWI_BBP_ATTEN_MAX 11
382 #define BWI_TPCTL1_MAX 7
390 uint16_t rf_type; /* BWI_RF_T_ */
394 uint32_t rf_flags; /* BWI_RF_F_ */
396 #define BWI_RFLO_MAX 56
397 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX];
398 uint8_t rf_lo_used[8];
400 #define BWI_INVALID_NRSSI -1000
401 int16_t rf_nrssi[2]; /* Narrow RSSI */
402 int32_t rf_nrssi_slope;
404 #define BWI_NRSSI_TBLSZ 64
405 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ];
407 uint16_t rf_lo_gain; /* loopback gain */
408 uint16_t rf_rx_gain; /* TRSW RX gain */
410 uint16_t rf_calib; /* RF calibration value */
411 u_int rf_curchan; /* current channel */
415 void (*rf_off)(struct bwi_mac *);
416 void (*rf_on)(struct bwi_mac *);
418 void (*rf_set_nrssi_thr)(struct bwi_mac *);
419 void (*rf_calc_nrssi_slope)(struct bwi_mac *);
422 const struct bwi_rxbuf_hdr *);
423 int (*rf_calc_noise)(struct bwi_mac *);
425 void (*rf_lo_update)(struct bwi_mac *);
427 #define BWI_TSSI_MAX 64
428 int8_t rf_txpower_map0[BWI_TSSI_MAX];
429 /* Indexed by TSSI */
432 int8_t rf_txpower_map[BWI_TSSI_MAX];
437 int rf_txpower_max; /* dBm */
439 int rf_ant_mode; /* BWI_ANT_MODE_ */
442 #define BWI_RF_F_INITED 0x1
443 #define BWI_RF_F_ON 0x2
444 #define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
446 #define BWI_ANT_MODE_0 0
447 #define BWI_ANT_MODE_1 1
448 #define BWI_ANT_MODE_UNKN 2
449 #define BWI_ANT_MODE_AUTO 3
455 struct bwi_regwin mac_regwin; /* MUST be first field */
456 #define mac_rw_flags mac_regwin.rw_flags
457 #define mac_type mac_regwin.rw_type
458 #define mac_id mac_regwin.rw_id
459 #define mac_rev mac_regwin.rw_rev
461 struct bwi_softc *mac_sc;
463 struct bwi_phy mac_phy; /* PHY I/F */
464 struct bwi_rf mac_rf; /* RF I/F */
466 struct bwi_tpctl mac_tpctl; /* TX power control */
467 uint32_t mac_flags; /* BWI_MAC_F_ */
469 const struct firmware *mac_stub;
470 const struct firmware *mac_ucode;
471 const struct firmware *mac_pcm;
472 const struct firmware *mac_iv;
473 const struct firmware *mac_iv_ext;
476 #define BWI_MAC_F_BSWAP 0x1
477 #define BWI_MAC_F_TPCTL_INITED 0x2
478 #define BWI_MAC_F_HAS_TXSTATS 0x4
479 #define BWI_MAC_F_INITED 0x8
480 #define BWI_MAC_F_ENABLED 0x10
481 #define BWI_MAC_F_LOCKED 0x20 /* for debug */
482 #define BWI_MAC_F_TPCTL_ERROR 0x40
483 #define BWI_MAC_F_PHYE_RESET 0x80
485 #define BWI_CREATE_MAC(mac, sc, id, rev) \
487 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
491 (mac)->mac_sc = (sc); \
494 #define BWI_MAC_MAX 2
495 #define BWI_LED_MAX 4
498 BWI_BUS_SPACE_30BIT = 1,
503 #define BWI_TX_RADIOTAP_PRESENT \
504 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
505 (1 << IEEE80211_RADIOTAP_RATE) | \
506 (1 << IEEE80211_RADIOTAP_CHANNEL))
508 struct bwi_tx_radiotap_hdr {
509 struct ieee80211_radiotap_header wt_ihdr;
512 uint16_t wt_chan_freq;
513 uint16_t wt_chan_flags;
516 #define BWI_RX_RADIOTAP_PRESENT \
517 ((1 << IEEE80211_RADIOTAP_TSFT) | \
518 (1 << IEEE80211_RADIOTAP_FLAGS) | \
519 (1 << IEEE80211_RADIOTAP_RATE) | \
520 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
521 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
522 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
524 struct bwi_rx_radiotap_hdr {
525 struct ieee80211_radiotap_header wr_ihdr;
529 uint16_t wr_chan_freq;
530 uint16_t wr_chan_flags;
537 struct ieee80211vap bv_vap;
538 int (*bv_newstate)(struct ieee80211vap *,
539 enum ieee80211_state, int);
541 #define BWI_VAP(vap) ((struct bwi_vap *)(vap))
544 struct ifnet *sc_ifp;
545 uint32_t sc_flags; /* BWI_F_ */
550 uint32_t sc_cap; /* BWI_CAP_ */
551 uint16_t sc_bbp_id; /* BWI_BBPID_ */
555 uint8_t sc_pci_revid;
557 uint16_t sc_pci_subvid;
558 uint16_t sc_pci_subdid;
560 uint16_t sc_card_flags; /* BWI_CARD_F_ */
561 uint16_t sc_pwron_delay;
565 struct resource *sc_irq_res;
569 struct resource *sc_mem_res;
570 bus_space_tag_t sc_mem_bt;
571 bus_space_handle_t sc_mem_bh;
573 struct callout sc_calib_ch;
574 struct callout sc_watchdog_timer;
576 struct bwi_regwin *sc_cur_regwin;
577 struct bwi_regwin sc_com_regwin;
578 struct bwi_regwin sc_bus_regwin;
581 struct bwi_mac sc_mac[BWI_MAC_MAX];
585 enum bwi_txpwrcb_type sc_txpwrcb_type;
589 struct bwi_led *sc_blink_led;
590 struct callout sc_led_blink_ch;
591 int sc_led_blink_offdur;
592 struct bwi_led sc_leds[BWI_LED_MAX];
594 enum bwi_bus_space sc_bus_space;
595 bus_dma_tag_t sc_parent_dtag;
597 bus_dma_tag_t sc_buf_dtag;
598 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING];
599 struct bwi_rxbuf_data sc_rx_bdata;
601 bus_dma_tag_t sc_txring_dtag;
602 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING];
603 bus_dma_tag_t sc_rxring_dtag;
604 struct bwi_ring_data sc_rx_rdata;
606 struct bwi_txstats_data *sc_txstats;
609 const struct ieee80211_rate_table *sc_rates;
611 struct bwi_tx_radiotap_hdr sc_tx_th;
612 struct bwi_rx_radiotap_hdr sc_rx_th;
614 struct taskqueue *sc_tq;
615 struct task sc_restart_task;
617 int (*sc_init_tx_ring)(struct bwi_softc *, int);
618 void (*sc_free_tx_ring)(struct bwi_softc *, int);
620 int (*sc_init_rx_ring)(struct bwi_softc *);
621 void (*sc_free_rx_ring)(struct bwi_softc *);
623 int (*sc_init_txstats)(struct bwi_softc *);
624 void (*sc_free_txstats)(struct bwi_softc *);
626 void (*sc_setup_rxdesc)
627 (struct bwi_softc *, int, bus_addr_t, int);
628 int (*sc_rxeof)(struct bwi_softc *);
630 void (*sc_setup_txdesc)
631 (struct bwi_softc *, struct bwi_ring_data *,
632 int, bus_addr_t, int);
634 (struct bwi_softc *, uint32_t, int);
636 void (*sc_txeof_status)(struct bwi_softc *);
638 /* Sysctl variables */
639 int sc_fw_version; /* BWI_FW_VERSION[34] */
640 int sc_dwell_time; /* milliseconds */
644 uint32_t sc_debug; /* BWI_DBG_ */
647 #define BWI_F_BUS_INITED 0x1
648 #define BWI_F_PROMISC 0x2
649 #define BWI_F_STOP 0x4
651 #define BWI_DBG_MAC 0x00000001
652 #define BWI_DBG_RF 0x00000002
653 #define BWI_DBG_PHY 0x00000004
654 #define BWI_DBG_MISC 0x00000008
656 #define BWI_DBG_ATTACH 0x00000010
657 #define BWI_DBG_INIT 0x00000020
658 #define BWI_DBG_FIRMWARE 0x00000040
659 #define BWI_DBG_80211 0x00000080
660 #define BWI_DBG_TXPOWER 0x00000100
661 #define BWI_DBG_INTR 0x00000200
662 #define BWI_DBG_RX 0x00000400
663 #define BWI_DBG_TX 0x00000800
664 #define BWI_DBG_TXEOF 0x00001000
665 #define BWI_DBG_LED 0x00002000
667 #define BWI_LOCK_INIT(sc) \
668 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \
669 MTX_NETWORK_LOCK, MTX_DEF | MTX_RECURSE)
670 #define BWI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
671 #define BWI_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
672 #define BWI_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
673 #define BWI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
675 int bwi_attach(struct bwi_softc *);
676 int bwi_detach(struct bwi_softc *);
677 void bwi_suspend(struct bwi_softc *);
678 void bwi_resume(struct bwi_softc *);
679 int bwi_shutdown(struct bwi_softc *);
680 void bwi_intr(void *);
682 int bwi_bus_init(struct bwi_softc *, struct bwi_mac *mac);
684 uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t);
685 int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
686 struct bwi_regwin **);
687 int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
688 void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
690 void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
693 #define abs(a) __builtin_abs(a)
695 /* XXX does not belong here */
696 struct ieee80211_ds_plcp_hdr {
703 #endif /* !_IF_BWIVAR_H */