2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * The Broadcom Wireless LAN controller driver.
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/malloc.h>
44 #include <sys/module.h>
45 #include <sys/endian.h>
46 #include <sys/errno.h>
47 #include <sys/firmware.h>
49 #include <sys/mutex.h>
50 #include <machine/bus.h>
51 #include <machine/resource.h>
54 #include <sys/socket.h>
55 #include <sys/sockio.h>
57 #include <net/ethernet.h>
59 #include <net/if_var.h>
60 #include <net/if_arp.h>
61 #include <net/if_dl.h>
62 #include <net/if_llc.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
66 #include <dev/pci/pcivar.h>
67 #include <dev/pci/pcireg.h>
68 #include <dev/siba/siba_ids.h>
69 #include <dev/siba/sibareg.h>
70 #include <dev/siba/sibavar.h>
72 #include <net80211/ieee80211_var.h>
73 #include <net80211/ieee80211_radiotap.h>
74 #include <net80211/ieee80211_regdomain.h>
75 #include <net80211/ieee80211_phy.h>
76 #include <net80211/ieee80211_ratectl.h>
78 #include <dev/bwn/if_bwnreg.h>
79 #include <dev/bwn/if_bwnvar.h>
81 #include <dev/bwn/if_bwn_debug.h>
82 #include <dev/bwn/if_bwn_misc.h>
83 #include <dev/bwn/if_bwn_util.h>
84 #include <dev/bwn/if_bwn_phy_common.h>
85 #include <dev/bwn/if_bwn_phy_g.h>
86 #include <dev/bwn/if_bwn_phy_lp.h>
87 #include <dev/bwn/if_bwn_phy_n.h>
89 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
90 "Broadcom driver parameters");
93 * Tunable & sysctl variables.
97 static int bwn_debug = 0;
98 SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0,
99 "Broadcom debugging printfs");
102 static int bwn_bfp = 0; /* use "Bad Frames Preemption" */
103 SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0,
104 "uses Bad Frames Preemption");
105 static int bwn_bluetooth = 1;
106 SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
107 "turns on Bluetooth Coexistence");
108 static int bwn_hwpctl = 0;
109 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
110 "uses H/W power control");
111 static int bwn_msi_disable = 0; /* MSI disabled */
112 TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable);
113 static int bwn_usedma = 1;
114 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
116 TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
117 static int bwn_wme = 1;
118 SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
121 static void bwn_attach_pre(struct bwn_softc *);
122 static int bwn_attach_post(struct bwn_softc *);
123 static void bwn_sprom_bugfixes(device_t);
124 static int bwn_init(struct bwn_softc *);
125 static void bwn_parent(struct ieee80211com *);
126 static void bwn_start(struct bwn_softc *);
127 static int bwn_transmit(struct ieee80211com *, struct mbuf *);
128 static int bwn_attach_core(struct bwn_mac *);
129 static int bwn_phy_getinfo(struct bwn_mac *, int);
130 static int bwn_chiptest(struct bwn_mac *);
131 static int bwn_setup_channels(struct bwn_mac *, int, int);
132 static void bwn_shm_ctlword(struct bwn_mac *, uint16_t,
134 static void bwn_addchannels(struct ieee80211_channel [], int, int *,
135 const struct bwn_channelinfo *, const uint8_t []);
136 static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
137 const struct ieee80211_bpf_params *);
138 static void bwn_updateslot(struct ieee80211com *);
139 static void bwn_update_promisc(struct ieee80211com *);
140 static void bwn_wme_init(struct bwn_mac *);
141 static int bwn_wme_update(struct ieee80211com *);
142 static void bwn_wme_clear(struct bwn_softc *);
143 static void bwn_wme_load(struct bwn_mac *);
144 static void bwn_wme_loadparams(struct bwn_mac *,
145 const struct wmeParams *, uint16_t);
146 static void bwn_scan_start(struct ieee80211com *);
147 static void bwn_scan_end(struct ieee80211com *);
148 static void bwn_set_channel(struct ieee80211com *);
149 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
150 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
151 const uint8_t [IEEE80211_ADDR_LEN],
152 const uint8_t [IEEE80211_ADDR_LEN]);
153 static void bwn_vap_delete(struct ieee80211vap *);
154 static void bwn_stop(struct bwn_softc *);
155 static int bwn_core_init(struct bwn_mac *);
156 static void bwn_core_start(struct bwn_mac *);
157 static void bwn_core_exit(struct bwn_mac *);
158 static void bwn_bt_disable(struct bwn_mac *);
159 static int bwn_chip_init(struct bwn_mac *);
160 static void bwn_set_txretry(struct bwn_mac *, int, int);
161 static void bwn_rate_init(struct bwn_mac *);
162 static void bwn_set_phytxctl(struct bwn_mac *);
163 static void bwn_spu_setdelay(struct bwn_mac *, int);
164 static void bwn_bt_enable(struct bwn_mac *);
165 static void bwn_set_macaddr(struct bwn_mac *);
166 static void bwn_crypt_init(struct bwn_mac *);
167 static void bwn_chip_exit(struct bwn_mac *);
168 static int bwn_fw_fillinfo(struct bwn_mac *);
169 static int bwn_fw_loaducode(struct bwn_mac *);
170 static int bwn_gpio_init(struct bwn_mac *);
171 static int bwn_fw_loadinitvals(struct bwn_mac *);
172 static int bwn_phy_init(struct bwn_mac *);
173 static void bwn_set_txantenna(struct bwn_mac *, int);
174 static void bwn_set_opmode(struct bwn_mac *);
175 static void bwn_rate_write(struct bwn_mac *, uint16_t, int);
176 static uint8_t bwn_plcp_getcck(const uint8_t);
177 static uint8_t bwn_plcp_getofdm(const uint8_t);
178 static void bwn_pio_init(struct bwn_mac *);
179 static uint16_t bwn_pio_idx2base(struct bwn_mac *, int);
180 static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
182 static void bwn_pio_setupqueue_rx(struct bwn_mac *,
183 struct bwn_pio_rxqueue *, int);
184 static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *);
185 static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *,
187 static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *);
188 static int bwn_pio_rx(struct bwn_pio_rxqueue *);
189 static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *);
190 static void bwn_pio_handle_txeof(struct bwn_mac *,
191 const struct bwn_txstatus *);
192 static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t);
193 static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t);
194 static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t,
196 static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t,
198 static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *,
200 static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t);
201 static uint32_t bwn_pio_write_multi_4(struct bwn_mac *,
202 struct bwn_pio_txqueue *, uint32_t, const void *, int);
203 static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *,
205 static uint16_t bwn_pio_write_multi_2(struct bwn_mac *,
206 struct bwn_pio_txqueue *, uint16_t, const void *, int);
207 static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *,
208 struct bwn_pio_txqueue *, uint16_t, struct mbuf *);
209 static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
210 uint16_t, struct bwn_pio_txpkt **);
211 static void bwn_dma_init(struct bwn_mac *);
212 static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
213 static int bwn_dma_mask2type(uint64_t);
214 static uint64_t bwn_dma_mask(struct bwn_mac *);
215 static uint16_t bwn_dma_base(int, int);
216 static void bwn_dma_ringfree(struct bwn_dma_ring **);
217 static void bwn_dma_32_getdesc(struct bwn_dma_ring *,
218 int, struct bwn_dmadesc_generic **,
219 struct bwn_dmadesc_meta **);
220 static void bwn_dma_32_setdesc(struct bwn_dma_ring *,
221 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
223 static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int);
224 static void bwn_dma_32_suspend(struct bwn_dma_ring *);
225 static void bwn_dma_32_resume(struct bwn_dma_ring *);
226 static int bwn_dma_32_get_curslot(struct bwn_dma_ring *);
227 static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int);
228 static void bwn_dma_64_getdesc(struct bwn_dma_ring *,
229 int, struct bwn_dmadesc_generic **,
230 struct bwn_dmadesc_meta **);
231 static void bwn_dma_64_setdesc(struct bwn_dma_ring *,
232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
234 static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int);
235 static void bwn_dma_64_suspend(struct bwn_dma_ring *);
236 static void bwn_dma_64_resume(struct bwn_dma_ring *);
237 static int bwn_dma_64_get_curslot(struct bwn_dma_ring *);
238 static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int);
239 static int bwn_dma_allocringmemory(struct bwn_dma_ring *);
240 static void bwn_dma_setup(struct bwn_dma_ring *);
241 static void bwn_dma_free_ringmemory(struct bwn_dma_ring *);
242 static void bwn_dma_cleanup(struct bwn_dma_ring *);
243 static void bwn_dma_free_descbufs(struct bwn_dma_ring *);
244 static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int);
245 static void bwn_dma_rx(struct bwn_dma_ring *);
246 static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
247 static void bwn_dma_free_descbuf(struct bwn_dma_ring *,
248 struct bwn_dmadesc_meta *);
249 static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
250 static int bwn_dma_gettype(struct bwn_mac *);
251 static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
252 static int bwn_dma_freeslot(struct bwn_dma_ring *);
253 static int bwn_dma_nextslot(struct bwn_dma_ring *, int);
254 static void bwn_dma_rxeof(struct bwn_dma_ring *, int *);
255 static int bwn_dma_newbuf(struct bwn_dma_ring *,
256 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *,
258 static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int,
260 static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *);
261 static void bwn_ratectl_tx_complete(const struct ieee80211_node *,
262 const struct bwn_txstatus *);
263 static void bwn_dma_handle_txeof(struct bwn_mac *,
264 const struct bwn_txstatus *);
265 static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *,
267 static int bwn_dma_getslot(struct bwn_dma_ring *);
268 static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
270 static int bwn_dma_attach(struct bwn_mac *);
271 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
273 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
274 const struct bwn_txstatus *, uint16_t, int *);
275 static void bwn_dma_free(struct bwn_mac *);
276 static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype);
277 static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype,
278 const char *, struct bwn_fwfile *);
279 static void bwn_release_firmware(struct bwn_mac *);
280 static void bwn_do_release_fw(struct bwn_fwfile *);
281 static uint16_t bwn_fwcaps_read(struct bwn_mac *);
282 static int bwn_fwinitvals_write(struct bwn_mac *,
283 const struct bwn_fwinitvals *, size_t, size_t);
284 static uint16_t bwn_ant2phy(int);
285 static void bwn_mac_write_bssid(struct bwn_mac *);
286 static void bwn_mac_setfilter(struct bwn_mac *, uint16_t,
288 static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t,
289 const uint8_t *, size_t, const uint8_t *);
290 static void bwn_key_macwrite(struct bwn_mac *, uint8_t,
292 static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t,
294 static void bwn_phy_exit(struct bwn_mac *);
295 static void bwn_core_stop(struct bwn_mac *);
296 static int bwn_switch_band(struct bwn_softc *,
297 struct ieee80211_channel *);
298 static void bwn_phy_reset(struct bwn_mac *);
299 static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
300 static void bwn_set_pretbtt(struct bwn_mac *);
301 static int bwn_intr(void *);
302 static void bwn_intrtask(void *, int);
303 static void bwn_restart(struct bwn_mac *, const char *);
304 static void bwn_intr_ucode_debug(struct bwn_mac *);
305 static void bwn_intr_tbtt_indication(struct bwn_mac *);
306 static void bwn_intr_atim_end(struct bwn_mac *);
307 static void bwn_intr_beacon(struct bwn_mac *);
308 static void bwn_intr_pmq(struct bwn_mac *);
309 static void bwn_intr_noise(struct bwn_mac *);
310 static void bwn_intr_txeof(struct bwn_mac *);
311 static void bwn_hwreset(void *, int);
312 static void bwn_handle_fwpanic(struct bwn_mac *);
313 static void bwn_load_beacon0(struct bwn_mac *);
314 static void bwn_load_beacon1(struct bwn_mac *);
315 static uint32_t bwn_jssi_read(struct bwn_mac *);
316 static void bwn_noise_gensample(struct bwn_mac *);
317 static void bwn_handle_txeof(struct bwn_mac *,
318 const struct bwn_txstatus *);
319 static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *);
320 static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t);
321 static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *,
323 static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *);
324 static int bwn_set_txhdr(struct bwn_mac *,
325 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *,
327 static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t,
329 static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t);
330 static uint8_t bwn_get_fbrate(uint8_t);
331 static void bwn_txpwr(void *, int);
332 static void bwn_tasks(void *);
333 static void bwn_task_15s(struct bwn_mac *);
334 static void bwn_task_30s(struct bwn_mac *);
335 static void bwn_task_60s(struct bwn_mac *);
336 static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *,
338 static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *);
339 static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *,
340 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int,
342 static void bwn_tsf_read(struct bwn_mac *, uint64_t *);
343 static void bwn_set_slot_time(struct bwn_mac *, uint16_t);
344 static void bwn_watchdog(void *);
345 static void bwn_dma_stop(struct bwn_mac *);
346 static void bwn_pio_stop(struct bwn_mac *);
347 static void bwn_dma_ringstop(struct bwn_dma_ring **);
348 static void bwn_led_attach(struct bwn_mac *);
349 static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
350 static void bwn_led_event(struct bwn_mac *, int);
351 static void bwn_led_blink_start(struct bwn_mac *, int, int);
352 static void bwn_led_blink_next(void *);
353 static void bwn_led_blink_end(void *);
354 static void bwn_rfswitch(void *);
355 static void bwn_rf_turnon(struct bwn_mac *);
356 static void bwn_rf_turnoff(struct bwn_mac *);
357 static void bwn_sysctl_node(struct bwn_softc *);
359 static struct resource_spec bwn_res_spec_legacy[] = {
360 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
364 static struct resource_spec bwn_res_spec_msi[] = {
365 { SYS_RES_IRQ, 1, RF_ACTIVE },
369 static const struct bwn_channelinfo bwn_chantable_bg = {
371 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 },
372 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 },
373 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 },
374 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 },
375 { 2472, 13, 30 }, { 2484, 14, 30 } },
379 static const struct bwn_channelinfo bwn_chantable_a = {
381 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 },
382 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 },
383 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 },
384 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 },
385 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 },
386 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 },
387 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 },
388 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 },
389 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 },
390 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 },
391 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 },
392 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 },
398 static const struct bwn_channelinfo bwn_chantable_n = {
400 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 },
401 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 },
402 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 },
403 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 },
404 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 },
405 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 },
406 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 },
407 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 },
408 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 },
409 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 },
410 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 },
411 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 },
412 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 },
413 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 },
414 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 },
415 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 },
416 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 },
417 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 },
418 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 },
419 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 },
420 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 },
421 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 },
422 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 },
423 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 },
424 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 },
425 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 },
426 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 },
427 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 },
428 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 },
429 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 },
430 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 },
431 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 },
432 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 },
433 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 },
434 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 },
435 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 },
436 { 6130, 226, 30 }, { 6140, 228, 30 } },
441 #define VENDOR_LED_ACT(vendor) \
443 .vid = PCI_VENDOR_##vendor, \
444 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \
447 static const struct {
449 uint8_t led_act[BWN_LED_MAX];
450 } bwn_vendor_led_act[] = {
451 VENDOR_LED_ACT(COMPAQ),
452 VENDOR_LED_ACT(ASUSTEK)
455 static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
456 { BWN_VENDOR_LED_ACT_DEFAULT };
458 #undef VENDOR_LED_ACT
460 static const struct {
463 } bwn_led_duration[109] = {
479 static const uint16_t bwn_wme_shm_offsets[] = {
480 [0] = BWN_WME_BESTEFFORT,
481 [1] = BWN_WME_BACKGROUND,
486 static const struct siba_devid bwn_devs[] = {
487 SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"),
488 SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"),
489 SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"),
490 SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"),
491 SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"),
492 SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"),
493 SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"),
494 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"),
495 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"),
496 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16")
500 bwn_probe(device_t dev)
504 for (i = 0; i < nitems(bwn_devs); i++) {
505 if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor &&
506 siba_get_device(dev) == bwn_devs[i].sd_device &&
507 siba_get_revid(dev) == bwn_devs[i].sd_rev)
508 return (BUS_PROBE_DEFAULT);
515 bwn_attach(device_t dev)
518 struct bwn_softc *sc = device_get_softc(dev);
519 int error, i, msic, reg;
523 sc->sc_debug = bwn_debug;
526 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
528 bwn_sprom_bugfixes(dev);
529 sc->sc_flags |= BWN_FLAG_ATTACHED;
532 if (!TAILQ_EMPTY(&sc->sc_maclist)) {
533 if (siba_get_pci_device(dev) != 0x4313 &&
534 siba_get_pci_device(dev) != 0x431a &&
535 siba_get_pci_device(dev) != 0x4321) {
536 device_printf(sc->sc_dev,
537 "skip 802.11 cores\n");
542 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
544 mac->mac_status = BWN_MAC_STATUS_UNINIT;
546 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
548 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
549 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
550 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
552 error = bwn_attach_core(mac);
557 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) "
558 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
559 siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev),
560 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev,
561 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver,
562 mac->mac_phy.rf_rev);
563 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
564 device_printf(sc->sc_dev, "DMA (%d bits)\n",
565 mac->mac_method.dma.dmatype);
567 device_printf(sc->sc_dev, "PIO\n");
570 device_printf(sc->sc_dev,
571 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
575 * setup PCI resources and interrupt.
577 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
578 msic = pci_msi_count(dev);
580 device_printf(sc->sc_dev, "MSI count : %d\n", msic);
584 mac->mac_intr_spec = bwn_res_spec_legacy;
585 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) {
586 if (pci_alloc_msi(dev, &msic) == 0) {
587 device_printf(sc->sc_dev,
588 "Using %d MSI messages\n", msic);
589 mac->mac_intr_spec = bwn_res_spec_msi;
594 error = bus_alloc_resources(dev, mac->mac_intr_spec,
597 device_printf(sc->sc_dev,
598 "couldn't allocate IRQ resources (%d)\n", error);
602 if (mac->mac_msi == 0)
603 error = bus_setup_intr(dev, mac->mac_res_irq[0],
604 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
605 &mac->mac_intrhand[0]);
607 for (i = 0; i < BWN_MSI_MESSAGES; i++) {
608 error = bus_setup_intr(dev, mac->mac_res_irq[i],
609 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
610 &mac->mac_intrhand[i]);
612 device_printf(sc->sc_dev,
613 "couldn't setup interrupt (%d)\n", error);
619 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
622 * calls attach-post routine
624 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0)
629 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0)
630 pci_release_msi(dev);
637 bwn_is_valid_ether_addr(uint8_t *addr)
639 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 };
641 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN)))
648 bwn_attach_post(struct bwn_softc *sc)
650 struct ieee80211com *ic = &sc->sc_ic;
653 ic->ic_name = device_get_nameunit(sc->sc_dev);
654 /* XXX not right but it's not used anywhere important */
655 ic->ic_phytype = IEEE80211_T_OFDM;
656 ic->ic_opmode = IEEE80211_M_STA;
658 IEEE80211_C_STA /* station mode supported */
659 | IEEE80211_C_MONITOR /* monitor mode */
660 | IEEE80211_C_AHDEMO /* adhoc demo mode */
661 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
662 | IEEE80211_C_SHSLOT /* short slot time supported */
663 | IEEE80211_C_WME /* WME/WMM supported */
664 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
666 | IEEE80211_C_BGSCAN /* capable of bg scanning */
668 | IEEE80211_C_TXPMGT /* capable of txpow mgt */
671 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */
673 IEEE80211_ADDR_COPY(ic->ic_macaddr,
674 bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ?
675 siba_sprom_get_mac_80211a(sc->sc_dev) :
676 siba_sprom_get_mac_80211bg(sc->sc_dev));
678 /* call MI attach routine. */
679 ieee80211_ifattach(ic);
681 ic->ic_headroom = sizeof(struct bwn_txhdr);
683 /* override default methods */
684 ic->ic_raw_xmit = bwn_raw_xmit;
685 ic->ic_updateslot = bwn_updateslot;
686 ic->ic_update_promisc = bwn_update_promisc;
687 ic->ic_wme.wme_update = bwn_wme_update;
688 ic->ic_scan_start = bwn_scan_start;
689 ic->ic_scan_end = bwn_scan_end;
690 ic->ic_set_channel = bwn_set_channel;
691 ic->ic_vap_create = bwn_vap_create;
692 ic->ic_vap_delete = bwn_vap_delete;
693 ic->ic_transmit = bwn_transmit;
694 ic->ic_parent = bwn_parent;
696 ieee80211_radiotap_attach(ic,
697 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
698 BWN_TX_RADIOTAP_PRESENT,
699 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
700 BWN_RX_RADIOTAP_PRESENT);
705 ieee80211_announce(ic);
710 bwn_phy_detach(struct bwn_mac *mac)
713 if (mac->mac_phy.detach != NULL)
714 mac->mac_phy.detach(mac);
718 bwn_detach(device_t dev)
720 struct bwn_softc *sc = device_get_softc(dev);
721 struct bwn_mac *mac = sc->sc_curmac;
722 struct ieee80211com *ic = &sc->sc_ic;
725 sc->sc_flags |= BWN_FLAG_INVALID;
727 if (device_is_attached(sc->sc_dev)) {
732 callout_drain(&sc->sc_led_blink_ch);
733 callout_drain(&sc->sc_rfswitch_ch);
734 callout_drain(&sc->sc_task_ch);
735 callout_drain(&sc->sc_watchdog_ch);
737 ieee80211_draintask(ic, &mac->mac_hwreset);
738 ieee80211_draintask(ic, &mac->mac_txpower);
739 ieee80211_ifdetach(ic);
741 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
742 taskqueue_free(sc->sc_tq);
744 for (i = 0; i < BWN_MSI_MESSAGES; i++) {
745 if (mac->mac_intrhand[i] != NULL) {
746 bus_teardown_intr(dev, mac->mac_res_irq[i],
747 mac->mac_intrhand[i]);
748 mac->mac_intrhand[i] = NULL;
751 bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq);
752 if (mac->mac_msi != 0)
753 pci_release_msi(dev);
754 mbufq_drain(&sc->sc_snd);
755 bwn_release_firmware(mac);
756 BWN_LOCK_DESTROY(sc);
761 bwn_attach_pre(struct bwn_softc *sc)
765 TAILQ_INIT(&sc->sc_maclist);
766 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0);
767 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0);
768 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0);
769 mbufq_init(&sc->sc_snd, ifqmaxlen);
770 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT,
771 taskqueue_thread_enqueue, &sc->sc_tq);
772 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
773 "%s taskq", device_get_nameunit(sc->sc_dev));
777 bwn_sprom_bugfixes(device_t dev)
779 #define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \
780 ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \
781 (siba_get_pci_device(dev) == _device) && \
782 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \
783 (siba_get_pci_subdevice(dev) == _subdevice))
785 if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE &&
786 siba_get_pci_subdevice(dev) == 0x4e &&
787 siba_get_pci_revid(dev) > 0x40)
788 siba_sprom_set_bf_lo(dev,
789 siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL);
790 if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL &&
791 siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74)
792 siba_sprom_set_bf_lo(dev,
793 siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST);
794 if (siba_get_type(dev) == SIBA_TYPE_PCI) {
795 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) ||
796 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) ||
797 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) ||
798 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) ||
799 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) ||
800 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) ||
801 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010))
802 siba_sprom_set_bf_lo(dev,
803 siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST);
809 bwn_parent(struct ieee80211com *ic)
811 struct bwn_softc *sc = ic->ic_softc;
815 if (ic->ic_nrunning > 0) {
816 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
820 bwn_update_promisc(ic);
821 } else if (sc->sc_flags & BWN_FLAG_RUNNING)
826 ieee80211_start_all(ic);
830 bwn_transmit(struct ieee80211com *ic, struct mbuf *m)
832 struct bwn_softc *sc = ic->ic_softc;
836 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
840 error = mbufq_enqueue(&sc->sc_snd, m);
851 bwn_start(struct bwn_softc *sc)
853 struct bwn_mac *mac = sc->sc_curmac;
854 struct ieee80211_frame *wh;
855 struct ieee80211_node *ni;
856 struct ieee80211_key *k;
859 BWN_ASSERT_LOCKED(sc);
861 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL ||
862 mac->mac_status < BWN_MAC_STATUS_STARTED)
865 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
866 if (bwn_tx_isfull(sc, m))
868 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
870 device_printf(sc->sc_dev, "unexpected NULL ni\n");
872 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
875 wh = mtod(m, struct ieee80211_frame *);
876 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
877 k = ieee80211_crypto_encap(ni, m);
879 if_inc_counter(ni->ni_vap->iv_ifp,
880 IFCOUNTER_OERRORS, 1);
881 ieee80211_free_node(ni);
886 wh = NULL; /* Catch any invalid use */
887 if (bwn_tx_start(sc, ni, m) != 0) {
889 if_inc_counter(ni->ni_vap->iv_ifp,
890 IFCOUNTER_OERRORS, 1);
891 ieee80211_free_node(ni);
895 sc->sc_watchdog_timer = 5;
900 bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m)
902 struct bwn_dma_ring *dr;
903 struct bwn_mac *mac = sc->sc_curmac;
904 struct bwn_pio_txqueue *tq;
905 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
907 BWN_ASSERT_LOCKED(sc);
909 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
910 dr = bwn_dma_select(mac, M_WME_GETAC(m));
911 if (dr->dr_stop == 1 ||
912 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) {
917 tq = bwn_pio_select(mac, M_WME_GETAC(m));
918 if (tq->tq_free == 0 || pktlen > tq->tq_size ||
919 pktlen > (tq->tq_size - tq->tq_used))
924 mbufq_prepend(&sc->sc_snd, m);
929 bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m)
931 struct bwn_mac *mac = sc->sc_curmac;
934 BWN_ASSERT_LOCKED(sc);
936 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) {
941 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ?
942 bwn_dma_tx_start(mac, ni, m) : bwn_pio_tx_start(mac, ni, m);
951 bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
953 struct bwn_pio_txpkt *tp;
954 struct bwn_pio_txqueue *tq = bwn_pio_select(mac, M_WME_GETAC(m));
955 struct bwn_softc *sc = mac->mac_sc;
956 struct bwn_txhdr txhdr;
962 BWN_ASSERT_LOCKED(sc);
964 /* XXX TODO send packets after DTIM */
966 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__));
967 tp = TAILQ_FIRST(&tq->tq_pktlist);
971 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp));
973 device_printf(sc->sc_dev, "tx fail\n");
977 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
978 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
981 if (siba_get_revid(sc->sc_dev) >= 8) {
983 * XXX please removes m_defrag(9)
985 m_new = m_defrag(m, M_NOWAIT);
987 device_printf(sc->sc_dev,
988 "%s: can't defrag TX buffer\n",
992 if (m_new->m_next != NULL)
993 device_printf(sc->sc_dev,
994 "TODO: fragmented packets for PIO\n");
998 ctl32 = bwn_pio_write_multi_4(mac, tq,
999 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) |
1000 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF,
1001 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1003 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32,
1004 mtod(m_new, const void *), m_new->m_pkthdr.len);
1005 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL,
1006 ctl32 | BWN_PIO8_TXCTL_EOF);
1008 ctl16 = bwn_pio_write_multi_2(mac, tq,
1009 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) |
1010 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF,
1011 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1012 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m);
1013 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL,
1014 ctl16 | BWN_PIO_TXCTL_EOF);
1020 static struct bwn_pio_txqueue *
1021 bwn_pio_select(struct bwn_mac *mac, uint8_t prio)
1024 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
1025 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1029 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1031 return (&mac->mac_method.pio.wme[WME_AC_BK]);
1033 return (&mac->mac_method.pio.wme[WME_AC_VI]);
1035 return (&mac->mac_method.pio.wme[WME_AC_VO]);
1037 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
1042 bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m)
1044 #define BWN_GET_TXHDRCACHE(slot) \
1045 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)])
1046 struct bwn_dma *dma = &mac->mac_method.dma;
1047 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(m));
1048 struct bwn_dmadesc_generic *desc;
1049 struct bwn_dmadesc_meta *mt;
1050 struct bwn_softc *sc = mac->mac_sc;
1051 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache;
1052 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot };
1054 BWN_ASSERT_LOCKED(sc);
1055 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__));
1057 /* XXX send after DTIM */
1059 slot = bwn_dma_getslot(dr);
1060 dr->getdesc(dr, slot, &desc, &mt);
1061 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER,
1062 ("%s:%d: fail", __func__, __LINE__));
1064 error = bwn_set_txhdr(dr->dr_mac, ni, m,
1065 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot),
1066 BWN_DMA_COOKIE(dr, slot));
1069 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap,
1070 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr,
1071 &mt->mt_paddr, BUS_DMA_NOWAIT);
1073 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1077 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap,
1078 BUS_DMASYNC_PREWRITE);
1079 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0);
1080 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1081 BUS_DMASYNC_PREWRITE);
1083 slot = bwn_dma_getslot(dr);
1084 dr->getdesc(dr, slot, &desc, &mt);
1085 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY &&
1086 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__));
1090 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m,
1091 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1092 if (error && error != EFBIG) {
1093 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1097 if (error) { /* error == EFBIG */
1100 m_new = m_defrag(m, M_NOWAIT);
1101 if (m_new == NULL) {
1102 device_printf(sc->sc_dev,
1103 "%s: can't defrag TX buffer\n",
1112 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap,
1113 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1115 device_printf(sc->sc_dev,
1116 "%s: can't load TX buffer (2) %d\n",
1121 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE);
1122 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1);
1123 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1124 BUS_DMASYNC_PREWRITE);
1126 /* XXX send after DTIM */
1128 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot));
1131 dr->dr_curslot = backup[0];
1132 dr->dr_usedslot = backup[1];
1134 #undef BWN_GET_TXHDRCACHE
1138 bwn_watchdog(void *arg)
1140 struct bwn_softc *sc = arg;
1142 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) {
1143 device_printf(sc->sc_dev, "device timeout\n");
1144 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1146 callout_schedule(&sc->sc_watchdog_ch, hz);
1150 bwn_attach_core(struct bwn_mac *mac)
1152 struct bwn_softc *sc = mac->mac_sc;
1153 int error, have_bg = 0, have_a = 0;
1155 KASSERT(siba_get_revid(sc->sc_dev) >= 5,
1156 ("unsupported revision %d", siba_get_revid(sc->sc_dev)));
1158 if (bwn_is_bus_siba(mac)) {
1161 siba_powerup(sc->sc_dev, 0);
1162 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
1163 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0;
1164 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0;
1165 if (high & BWN_TGSHIGH_DUALPHY) {
1170 device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d,"
1171 " deviceid=0x%04x, siba_deviceid=0x%04x\n",
1176 siba_get_pci_device(sc->sc_dev),
1177 siba_get_chipid(sc->sc_dev));
1180 device_printf(sc->sc_dev, "%s: not siba; bailing\n", __func__);
1186 * Guess at whether it has A-PHY or G-PHY.
1187 * This is just used for resetting the core to probe things;
1188 * we will re-guess once it's all up and working.
1190 bwn_reset_core(mac, have_bg);
1193 * Get the PHY version.
1195 error = bwn_phy_getinfo(mac, have_bg);
1200 * This is the whitelist of devices which we "believe"
1201 * the SPROM PHY config from. The rest are "guessed".
1203 if (siba_get_pci_device(sc->sc_dev) != 0x4312 &&
1204 siba_get_pci_device(sc->sc_dev) != 0x4315 &&
1205 siba_get_pci_device(sc->sc_dev) != 0x4319 &&
1206 siba_get_pci_device(sc->sc_dev) != 0x4324 &&
1207 siba_get_pci_device(sc->sc_dev) != 0x4328 &&
1208 siba_get_pci_device(sc->sc_dev) != 0x432b) {
1209 have_a = have_bg = 0;
1210 if (mac->mac_phy.type == BWN_PHYTYPE_A)
1212 else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1213 mac->mac_phy.type == BWN_PHYTYPE_N ||
1214 mac->mac_phy.type == BWN_PHYTYPE_LP)
1217 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__,
1218 mac->mac_phy.type));
1222 * XXX The PHY-G support doesn't do 5GHz operation.
1224 if (mac->mac_phy.type != BWN_PHYTYPE_LP &&
1225 mac->mac_phy.type != BWN_PHYTYPE_N) {
1226 device_printf(sc->sc_dev,
1227 "%s: forcing 2GHz only; no dual-band support for PHY\n",
1233 mac->mac_phy.phy_n = NULL;
1235 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
1236 mac->mac_phy.attach = bwn_phy_g_attach;
1237 mac->mac_phy.detach = bwn_phy_g_detach;
1238 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw;
1239 mac->mac_phy.init_pre = bwn_phy_g_init_pre;
1240 mac->mac_phy.init = bwn_phy_g_init;
1241 mac->mac_phy.exit = bwn_phy_g_exit;
1242 mac->mac_phy.phy_read = bwn_phy_g_read;
1243 mac->mac_phy.phy_write = bwn_phy_g_write;
1244 mac->mac_phy.rf_read = bwn_phy_g_rf_read;
1245 mac->mac_phy.rf_write = bwn_phy_g_rf_write;
1246 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl;
1247 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff;
1248 mac->mac_phy.switch_analog = bwn_phy_switch_analog;
1249 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel;
1250 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan;
1251 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna;
1252 mac->mac_phy.set_im = bwn_phy_g_im;
1253 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr;
1254 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr;
1255 mac->mac_phy.task_15s = bwn_phy_g_task_15s;
1256 mac->mac_phy.task_60s = bwn_phy_g_task_60s;
1257 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) {
1258 mac->mac_phy.init_pre = bwn_phy_lp_init_pre;
1259 mac->mac_phy.init = bwn_phy_lp_init;
1260 mac->mac_phy.phy_read = bwn_phy_lp_read;
1261 mac->mac_phy.phy_write = bwn_phy_lp_write;
1262 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset;
1263 mac->mac_phy.rf_read = bwn_phy_lp_rf_read;
1264 mac->mac_phy.rf_write = bwn_phy_lp_rf_write;
1265 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff;
1266 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog;
1267 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel;
1268 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan;
1269 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna;
1270 mac->mac_phy.task_60s = bwn_phy_lp_task_60s;
1271 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) {
1272 mac->mac_phy.attach = bwn_phy_n_attach;
1273 mac->mac_phy.detach = bwn_phy_n_detach;
1274 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw;
1275 mac->mac_phy.init_pre = bwn_phy_n_init_pre;
1276 mac->mac_phy.init = bwn_phy_n_init;
1277 mac->mac_phy.exit = bwn_phy_n_exit;
1278 mac->mac_phy.phy_read = bwn_phy_n_read;
1279 mac->mac_phy.phy_write = bwn_phy_n_write;
1280 mac->mac_phy.rf_read = bwn_phy_n_rf_read;
1281 mac->mac_phy.rf_write = bwn_phy_n_rf_write;
1282 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl;
1283 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff;
1284 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog;
1285 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel;
1286 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan;
1287 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna;
1288 mac->mac_phy.set_im = bwn_phy_n_im;
1289 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr;
1290 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr;
1291 mac->mac_phy.task_15s = bwn_phy_n_task_15s;
1292 mac->mac_phy.task_60s = bwn_phy_n_task_60s;
1294 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n",
1300 mac->mac_phy.gmode = have_bg;
1301 if (mac->mac_phy.attach != NULL) {
1302 error = mac->mac_phy.attach(mac);
1304 device_printf(sc->sc_dev, "failed\n");
1309 bwn_reset_core(mac, have_bg);
1311 error = bwn_chiptest(mac);
1314 error = bwn_setup_channels(mac, have_bg, have_a);
1316 device_printf(sc->sc_dev, "failed to setup channels\n");
1320 if (sc->sc_curmac == NULL)
1321 sc->sc_curmac = mac;
1323 error = bwn_dma_attach(mac);
1325 device_printf(sc->sc_dev, "failed to initialize DMA\n");
1329 mac->mac_phy.switch_analog(mac, 0);
1331 siba_dev_down(sc->sc_dev, 0);
1333 siba_powerdown(sc->sc_dev);
1334 bwn_release_firmware(mac);
1341 * XXX TODO: implement BCMA version!
1344 bwn_reset_core(struct bwn_mac *mac, int g_mode)
1346 struct bwn_softc *sc = mac->mac_sc;
1350 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
1352 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET);
1354 flags |= BWN_TGSLOW_SUPPORT_G;
1356 /* XXX N-PHY only; and hard-code to 20MHz for now */
1357 if (mac->mac_phy.type == BWN_PHYTYPE_N)
1358 flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ;
1360 siba_dev_up(sc->sc_dev, flags);
1363 /* Take PHY out of reset */
1364 low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) &
1365 ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE);
1366 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
1367 siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1369 low &= ~SIBA_TGSLOW_FGC;
1370 low |= BWN_TGSLOW_PHYCLOCK_ENABLE;
1371 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low);
1372 siba_read_4(sc->sc_dev, SIBA_TGSLOW);
1375 if (mac->mac_phy.switch_analog != NULL)
1376 mac->mac_phy.switch_analog(mac, 1);
1378 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1380 ctl |= BWN_MACCTL_GMODE;
1381 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1385 bwn_phy_getinfo(struct bwn_mac *mac, int gmode)
1387 struct bwn_phy *phy = &mac->mac_phy;
1388 struct bwn_softc *sc = mac->mac_sc;
1392 tmp = BWN_READ_2(mac, BWN_PHYVER);
1395 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1396 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1397 phy->rev = (tmp & BWN_PHYVER_VERSION);
1398 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1399 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1400 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1401 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1402 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) ||
1403 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1407 if (siba_get_chipid(sc->sc_dev) == 0x4317) {
1408 if (siba_get_chiprev(sc->sc_dev) == 0)
1410 else if (siba_get_chiprev(sc->sc_dev) == 1)
1415 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1416 tmp = BWN_READ_2(mac, BWN_RFDATALO);
1417 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1418 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
1420 phy->rf_rev = (tmp & 0xf0000000) >> 28;
1421 phy->rf_ver = (tmp & 0x0ffff000) >> 12;
1422 phy->rf_manuf = (tmp & 0x00000fff);
1425 * For now, just always do full init (ie, what bwn has traditionally
1428 phy->phy_do_full_init = 1;
1430 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */
1432 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 ||
1433 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) ||
1434 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) ||
1435 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) ||
1436 (phy->type == BWN_PHYTYPE_N &&
1437 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) ||
1438 (phy->type == BWN_PHYTYPE_LP &&
1439 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063))
1444 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, "
1446 phy->type, phy->rev, phy->analog);
1449 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, "
1451 phy->rf_manuf, phy->rf_ver, phy->rf_rev);
1456 bwn_chiptest(struct bwn_mac *mac)
1458 #define TESTVAL0 0x55aaaa55
1459 #define TESTVAL1 0xaa5555aa
1460 struct bwn_softc *sc = mac->mac_sc;
1465 backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1467 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1468 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1470 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1471 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1474 bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1476 if ((siba_get_revid(sc->sc_dev) >= 3) &&
1477 (siba_get_revid(sc->sc_dev) <= 10)) {
1478 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1479 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1480 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1482 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1485 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);
1487 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE;
1488 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON))
1495 device_printf(sc->sc_dev, "failed to validate the chipaccess\n");
1500 bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a)
1502 struct bwn_softc *sc = mac->mac_sc;
1503 struct ieee80211com *ic = &sc->sc_ic;
1504 uint8_t bands[IEEE80211_MODE_BYTES];
1506 memset(ic->ic_channels, 0, sizeof(ic->ic_channels));
1509 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n",
1515 memset(bands, 0, sizeof(bands));
1516 setbit(bands, IEEE80211_MODE_11B);
1517 setbit(bands, IEEE80211_MODE_11G);
1518 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1519 &ic->ic_nchans, &bwn_chantable_bg, bands);
1523 memset(bands, 0, sizeof(bands));
1524 setbit(bands, IEEE80211_MODE_11A);
1525 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1526 &ic->ic_nchans, &bwn_chantable_a, bands);
1529 mac->mac_phy.supports_2ghz = have_bg;
1530 mac->mac_phy.supports_5ghz = have_a;
1532 return (ic->ic_nchans == 0 ? ENXIO : 0);
1536 bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1540 BWN_ASSERT_LOCKED(mac->mac_sc);
1542 if (way == BWN_SHARED) {
1543 KASSERT((offset & 0x0001) == 0,
1544 ("%s:%d warn", __func__, __LINE__));
1545 if (offset & 0x0003) {
1546 bwn_shm_ctlword(mac, way, offset >> 2);
1547 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1549 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1550 ret |= BWN_READ_2(mac, BWN_SHM_DATA);
1555 bwn_shm_ctlword(mac, way, offset);
1556 ret = BWN_READ_4(mac, BWN_SHM_DATA);
1562 bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1566 BWN_ASSERT_LOCKED(mac->mac_sc);
1568 if (way == BWN_SHARED) {
1569 KASSERT((offset & 0x0001) == 0,
1570 ("%s:%d warn", __func__, __LINE__));
1571 if (offset & 0x0003) {
1572 bwn_shm_ctlword(mac, way, offset >> 2);
1573 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1578 bwn_shm_ctlword(mac, way, offset);
1579 ret = BWN_READ_2(mac, BWN_SHM_DATA);
1586 bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way,
1594 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control);
1598 bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1601 BWN_ASSERT_LOCKED(mac->mac_sc);
1603 if (way == BWN_SHARED) {
1604 KASSERT((offset & 0x0001) == 0,
1605 ("%s:%d warn", __func__, __LINE__));
1606 if (offset & 0x0003) {
1607 bwn_shm_ctlword(mac, way, offset >> 2);
1608 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED,
1609 (value >> 16) & 0xffff);
1610 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1611 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff);
1616 bwn_shm_ctlword(mac, way, offset);
1617 BWN_WRITE_4(mac, BWN_SHM_DATA, value);
1621 bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1624 BWN_ASSERT_LOCKED(mac->mac_sc);
1626 if (way == BWN_SHARED) {
1627 KASSERT((offset & 0x0001) == 0,
1628 ("%s:%d warn", __func__, __LINE__));
1629 if (offset & 0x0003) {
1630 bwn_shm_ctlword(mac, way, offset >> 2);
1631 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value);
1636 bwn_shm_ctlword(mac, way, offset);
1637 BWN_WRITE_2(mac, BWN_SHM_DATA, value);
1641 bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans,
1642 const struct bwn_channelinfo *ci, const uint8_t bands[])
1646 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) {
1647 const struct bwn_channel *hc = &ci->channels[i];
1649 error = ieee80211_add_channel(chans, maxchans, nchans,
1650 hc->ieee, hc->freq, hc->maxTxPow, 0, bands);
1655 bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1656 const struct ieee80211_bpf_params *params)
1658 struct ieee80211com *ic = ni->ni_ic;
1659 struct bwn_softc *sc = ic->ic_softc;
1660 struct bwn_mac *mac = sc->sc_curmac;
1663 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 ||
1664 mac->mac_status < BWN_MAC_STATUS_STARTED) {
1670 if (bwn_tx_isfull(sc, m)) {
1676 error = bwn_tx_start(sc, ni, m);
1678 sc->sc_watchdog_timer = 5;
1684 * Callback from the 802.11 layer to update the slot time
1685 * based on the current setting. We use it to notify the
1686 * firmware of ERP changes and the f/w takes care of things
1687 * like slot time and preamble.
1690 bwn_updateslot(struct ieee80211com *ic)
1692 struct bwn_softc *sc = ic->ic_softc;
1693 struct bwn_mac *mac;
1696 if (sc->sc_flags & BWN_FLAG_RUNNING) {
1697 mac = (struct bwn_mac *)sc->sc_curmac;
1698 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic));
1704 * Callback from the 802.11 layer after a promiscuous mode change.
1705 * Note this interface does not check the operating mode as this
1706 * is an internal callback and we are expected to honor the current
1707 * state (e.g. this is used for setting the interface in promiscuous
1708 * mode when operating in hostap mode to do ACS).
1711 bwn_update_promisc(struct ieee80211com *ic)
1713 struct bwn_softc *sc = ic->ic_softc;
1714 struct bwn_mac *mac = sc->sc_curmac;
1717 mac = sc->sc_curmac;
1718 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1719 if (ic->ic_promisc > 0)
1720 sc->sc_filters |= BWN_MACCTL_PROMISC;
1722 sc->sc_filters &= ~BWN_MACCTL_PROMISC;
1723 bwn_set_opmode(mac);
1729 * Callback from the 802.11 layer to update WME parameters.
1732 bwn_wme_update(struct ieee80211com *ic)
1734 struct bwn_softc *sc = ic->ic_softc;
1735 struct bwn_mac *mac = sc->sc_curmac;
1736 struct wmeParams *wmep;
1740 mac = sc->sc_curmac;
1741 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1742 bwn_mac_suspend(mac);
1743 for (i = 0; i < N(sc->sc_wmeParams); i++) {
1744 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[i];
1745 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]);
1747 bwn_mac_enable(mac);
1754 bwn_scan_start(struct ieee80211com *ic)
1756 struct bwn_softc *sc = ic->ic_softc;
1757 struct bwn_mac *mac;
1760 mac = sc->sc_curmac;
1761 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1762 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC;
1763 bwn_set_opmode(mac);
1764 /* disable CFP update during scan */
1765 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE);
1771 bwn_scan_end(struct ieee80211com *ic)
1773 struct bwn_softc *sc = ic->ic_softc;
1774 struct bwn_mac *mac;
1777 mac = sc->sc_curmac;
1778 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1779 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC;
1780 bwn_set_opmode(mac);
1781 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE);
1787 bwn_set_channel(struct ieee80211com *ic)
1789 struct bwn_softc *sc = ic->ic_softc;
1790 struct bwn_mac *mac = sc->sc_curmac;
1791 struct bwn_phy *phy = &mac->mac_phy;
1796 error = bwn_switch_band(sc, ic->ic_curchan);
1799 bwn_mac_suspend(mac);
1800 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
1801 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1802 if (chan != phy->chan)
1803 bwn_switch_channel(mac, chan);
1805 /* TX power level */
1806 if (ic->ic_curchan->ic_maxpower != 0 &&
1807 ic->ic_curchan->ic_maxpower != phy->txpower) {
1808 phy->txpower = ic->ic_curchan->ic_maxpower / 2;
1809 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME |
1810 BWN_TXPWR_IGNORE_TSSI);
1813 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
1814 if (phy->set_antenna)
1815 phy->set_antenna(mac, BWN_ANT_DEFAULT);
1817 if (sc->sc_rf_enabled != phy->rf_on) {
1818 if (sc->sc_rf_enabled) {
1820 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON))
1821 device_printf(sc->sc_dev,
1822 "please turn on the RF switch\n");
1824 bwn_rf_turnoff(mac);
1827 bwn_mac_enable(mac);
1831 * Setup radio tap channel freq and flags
1833 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1834 htole16(ic->ic_curchan->ic_freq);
1835 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1836 htole16(ic->ic_curchan->ic_flags & 0xffff);
1841 static struct ieee80211vap *
1842 bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1843 enum ieee80211_opmode opmode, int flags,
1844 const uint8_t bssid[IEEE80211_ADDR_LEN],
1845 const uint8_t mac[IEEE80211_ADDR_LEN])
1847 struct ieee80211vap *vap;
1848 struct bwn_vap *bvp;
1851 case IEEE80211_M_HOSTAP:
1852 case IEEE80211_M_MBSS:
1853 case IEEE80211_M_STA:
1854 case IEEE80211_M_WDS:
1855 case IEEE80211_M_MONITOR:
1856 case IEEE80211_M_IBSS:
1857 case IEEE80211_M_AHDEMO:
1863 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
1865 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
1866 /* override with driver methods */
1867 bvp->bv_newstate = vap->iv_newstate;
1868 vap->iv_newstate = bwn_newstate;
1870 /* override max aid so sta's cannot assoc when we're out of sta id's */
1871 vap->iv_max_aid = BWN_STAID_MAX;
1873 ieee80211_ratectl_init(vap);
1875 /* complete setup */
1876 ieee80211_vap_attach(vap, ieee80211_media_change,
1877 ieee80211_media_status, mac);
1882 bwn_vap_delete(struct ieee80211vap *vap)
1884 struct bwn_vap *bvp = BWN_VAP(vap);
1886 ieee80211_ratectl_deinit(vap);
1887 ieee80211_vap_detach(vap);
1888 free(bvp, M_80211_VAP);
1892 bwn_init(struct bwn_softc *sc)
1894 struct bwn_mac *mac;
1897 BWN_ASSERT_LOCKED(sc);
1899 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
1901 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN);
1902 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP;
1905 sc->sc_beacons[0] = sc->sc_beacons[1] = 0;
1906 sc->sc_rf_enabled = 1;
1908 mac = sc->sc_curmac;
1909 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) {
1910 error = bwn_core_init(mac);
1914 if (mac->mac_status == BWN_MAC_STATUS_INITED)
1915 bwn_core_start(mac);
1917 bwn_set_opmode(mac);
1918 bwn_set_pretbtt(mac);
1919 bwn_spu_setdelay(mac, 0);
1920 bwn_set_macaddr(mac);
1922 sc->sc_flags |= BWN_FLAG_RUNNING;
1923 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc);
1924 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc);
1930 bwn_stop(struct bwn_softc *sc)
1932 struct bwn_mac *mac = sc->sc_curmac;
1934 BWN_ASSERT_LOCKED(sc);
1936 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
1938 if (mac->mac_status >= BWN_MAC_STATUS_INITED) {
1939 /* XXX FIXME opmode not based on VAP */
1940 bwn_set_opmode(mac);
1941 bwn_set_macaddr(mac);
1944 if (mac->mac_status >= BWN_MAC_STATUS_STARTED)
1947 callout_stop(&sc->sc_led_blink_ch);
1948 sc->sc_led_blinking = 0;
1951 sc->sc_rf_enabled = 0;
1953 sc->sc_flags &= ~BWN_FLAG_RUNNING;
1957 bwn_wme_clear(struct bwn_softc *sc)
1959 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
1960 struct wmeParams *p;
1963 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
1964 ("%s:%d: fail", __func__, __LINE__));
1966 for (i = 0; i < N(sc->sc_wmeParams); i++) {
1967 p = &(sc->sc_wmeParams[i]);
1969 switch (bwn_wme_shm_offsets[i]) {
1971 p->wmep_txopLimit = 0;
1973 /* XXX FIXME: log2(cwmin) */
1974 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1975 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
1978 p->wmep_txopLimit = 0;
1980 /* XXX FIXME: log2(cwmin) */
1981 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1982 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
1984 case BWN_WME_BESTEFFORT:
1985 p->wmep_txopLimit = 0;
1987 /* XXX FIXME: log2(cwmin) */
1988 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1989 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
1991 case BWN_WME_BACKGROUND:
1992 p->wmep_txopLimit = 0;
1994 /* XXX FIXME: log2(cwmin) */
1995 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
1996 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
1999 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2005 bwn_core_init(struct bwn_mac *mac)
2007 struct bwn_softc *sc = mac->mac_sc;
2011 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2012 ("%s:%d: fail", __func__, __LINE__));
2014 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2016 siba_powerup(sc->sc_dev, 0);
2017 if (!siba_dev_isup(sc->sc_dev))
2018 bwn_reset_core(mac, mac->mac_phy.gmode);
2020 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
2021 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
2022 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
2023 BWN_GETTIME(mac->mac_phy.nexttime);
2024 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
2025 bzero(&mac->mac_stats, sizeof(mac->mac_stats));
2026 mac->mac_stats.link_noise = -95;
2027 mac->mac_reason_intr = 0;
2028 bzero(mac->mac_reason, sizeof(mac->mac_reason));
2029 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE;
2031 if (sc->sc_debug & BWN_DEBUG_XMIT)
2032 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
2034 mac->mac_suspended = 1;
2035 mac->mac_task_state = 0;
2036 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
2038 mac->mac_phy.init_pre(mac);
2040 siba_pcicore_intr(sc->sc_dev);
2042 siba_fix_imcfglobug(sc->sc_dev);
2043 bwn_bt_disable(mac);
2044 if (mac->mac_phy.prepare_hw) {
2045 error = mac->mac_phy.prepare_hw(mac);
2049 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__);
2050 error = bwn_chip_init(mac);
2053 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
2054 siba_get_revid(sc->sc_dev));
2055 hf = bwn_hf_read(mac);
2056 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
2057 hf |= BWN_HF_GPHY_SYM_WORKAROUND;
2058 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL)
2059 hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
2060 if (mac->mac_phy.rev == 1)
2061 hf |= BWN_HF_GPHY_DC_CANCELFILTER;
2063 if (mac->mac_phy.rf_ver == 0x2050) {
2064 if (mac->mac_phy.rf_rev < 6)
2065 hf |= BWN_HF_FORCE_VCO_RECALC;
2066 if (mac->mac_phy.rf_rev == 6)
2067 hf |= BWN_HF_4318_TSSI;
2069 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)
2070 hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
2071 if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) &&
2072 (siba_get_pcicore_revid(sc->sc_dev) <= 10))
2073 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
2074 hf &= ~BWN_HF_SKIP_CFP_UPDATE;
2075 bwn_hf_write(mac, hf);
2077 /* Tell the firmware about the MAC capabilities */
2078 if (siba_get_revid(sc->sc_dev) >= 13) {
2080 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
2081 DPRINTF(sc, BWN_DEBUG_RESET,
2082 "%s: hw capabilities: 0x%08x\n",
2084 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L,
2086 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H,
2087 (cap >> 16) & 0xffff);
2090 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
2091 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
2092 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
2093 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
2096 bwn_set_phytxctl(mac);
2098 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
2099 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
2100 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
2102 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
2107 bwn_spu_setdelay(mac, 1);
2110 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
2111 siba_powerup(sc->sc_dev,
2112 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW));
2113 bwn_set_macaddr(mac);
2114 bwn_crypt_init(mac);
2116 /* XXX LED initializatin */
2118 mac->mac_status = BWN_MAC_STATUS_INITED;
2120 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__);
2124 siba_powerdown(sc->sc_dev);
2125 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2126 ("%s:%d: fail", __func__, __LINE__));
2127 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
2132 bwn_core_start(struct bwn_mac *mac)
2134 struct bwn_softc *sc = mac->mac_sc;
2137 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
2138 ("%s:%d: fail", __func__, __LINE__));
2140 if (siba_get_revid(sc->sc_dev) < 5)
2144 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
2145 if (!(tmp & 0x00000001))
2147 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
2150 bwn_mac_enable(mac);
2151 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
2152 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
2154 mac->mac_status = BWN_MAC_STATUS_STARTED;
2158 bwn_core_exit(struct bwn_mac *mac)
2160 struct bwn_softc *sc = mac->mac_sc;
2163 BWN_ASSERT_LOCKED(mac->mac_sc);
2165 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
2166 ("%s:%d: fail", __func__, __LINE__));
2168 if (mac->mac_status != BWN_MAC_STATUS_INITED)
2170 mac->mac_status = BWN_MAC_STATUS_UNINIT;
2172 macctl = BWN_READ_4(mac, BWN_MACCTL);
2173 macctl &= ~BWN_MACCTL_MCODE_RUN;
2174 macctl |= BWN_MACCTL_MCODE_JMP0;
2175 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2180 mac->mac_phy.switch_analog(mac, 0);
2181 siba_dev_down(sc->sc_dev, 0);
2182 siba_powerdown(sc->sc_dev);
2186 bwn_bt_disable(struct bwn_mac *mac)
2188 struct bwn_softc *sc = mac->mac_sc;
2191 /* XXX do nothing yet */
2195 bwn_chip_init(struct bwn_mac *mac)
2197 struct bwn_softc *sc = mac->mac_sc;
2198 struct bwn_phy *phy = &mac->mac_phy;
2202 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
2204 macctl |= BWN_MACCTL_GMODE;
2205 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2207 error = bwn_fw_fillinfo(mac);
2210 error = bwn_fw_loaducode(mac);
2214 error = bwn_gpio_init(mac);
2218 error = bwn_fw_loadinitvals(mac);
2220 siba_gpio_set(sc->sc_dev, 0);
2223 phy->switch_analog(mac, 1);
2224 error = bwn_phy_init(mac);
2226 siba_gpio_set(sc->sc_dev, 0);
2230 phy->set_im(mac, BWN_IMMODE_NONE);
2231 if (phy->set_antenna)
2232 phy->set_antenna(mac, BWN_ANT_DEFAULT);
2233 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
2235 if (phy->type == BWN_PHYTYPE_B)
2236 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
2237 BWN_WRITE_4(mac, 0x0100, 0x01000000);
2238 if (siba_get_revid(sc->sc_dev) < 5)
2239 BWN_WRITE_4(mac, 0x010c, 0x01000000);
2241 BWN_WRITE_4(mac, BWN_MACCTL,
2242 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
2243 BWN_WRITE_4(mac, BWN_MACCTL,
2244 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
2245 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
2247 bwn_set_opmode(mac);
2248 if (siba_get_revid(sc->sc_dev) < 3) {
2249 BWN_WRITE_2(mac, 0x060e, 0x0000);
2250 BWN_WRITE_2(mac, 0x0610, 0x8000);
2251 BWN_WRITE_2(mac, 0x0604, 0x0000);
2252 BWN_WRITE_2(mac, 0x0606, 0x0200);
2254 BWN_WRITE_4(mac, 0x0188, 0x80000000);
2255 BWN_WRITE_4(mac, 0x018c, 0x02000000);
2257 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
2258 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
2259 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
2260 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
2261 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
2262 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
2263 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
2265 bwn_mac_phy_clock_set(mac, true);
2268 /* XXX TODO: BCMA powerup */
2269 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev));
2273 /* read hostflags */
2275 bwn_hf_read(struct bwn_mac *mac)
2279 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI);
2281 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI);
2283 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO);
2288 bwn_hf_write(struct bwn_mac *mac, uint64_t value)
2291 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO,
2292 (value & 0x00000000ffffull));
2293 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI,
2294 (value & 0x0000ffff0000ull) >> 16);
2295 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI,
2296 (value & 0xffff00000000ULL) >> 32);
2300 bwn_set_txretry(struct bwn_mac *mac, int s, int l)
2303 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf));
2304 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf));
2308 bwn_rate_init(struct bwn_mac *mac)
2311 switch (mac->mac_phy.type) {
2314 case BWN_PHYTYPE_LP:
2316 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1);
2317 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1);
2318 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1);
2319 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1);
2320 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1);
2321 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1);
2322 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1);
2323 if (mac->mac_phy.type == BWN_PHYTYPE_A)
2327 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0);
2328 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0);
2329 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0);
2330 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0);
2333 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2338 bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm)
2344 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2;
2347 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2;
2349 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20,
2350 bwn_shm_read_2(mac, BWN_SHARED, offset));
2354 bwn_plcp_getcck(const uint8_t bitrate)
2358 case BWN_CCK_RATE_1MB:
2360 case BWN_CCK_RATE_2MB:
2362 case BWN_CCK_RATE_5MB:
2364 case BWN_CCK_RATE_11MB:
2367 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2372 bwn_plcp_getofdm(const uint8_t bitrate)
2376 case BWN_OFDM_RATE_6MB:
2378 case BWN_OFDM_RATE_9MB:
2380 case BWN_OFDM_RATE_12MB:
2382 case BWN_OFDM_RATE_18MB:
2384 case BWN_OFDM_RATE_24MB:
2386 case BWN_OFDM_RATE_36MB:
2388 case BWN_OFDM_RATE_48MB:
2390 case BWN_OFDM_RATE_54MB:
2393 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2398 bwn_set_phytxctl(struct bwn_mac *mac)
2402 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO |
2404 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl);
2405 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl);
2406 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl);
2410 bwn_pio_init(struct bwn_mac *mac)
2412 struct bwn_pio *pio = &mac->mac_method.pio;
2414 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL)
2415 & ~BWN_MACCTL_BIGENDIAN);
2416 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0);
2418 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0);
2419 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1);
2420 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2);
2421 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3);
2422 bwn_pio_set_txqueue(mac, &pio->mcast, 4);
2423 bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
2427 bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2430 struct bwn_pio_txpkt *tp;
2431 struct bwn_softc *sc = mac->mac_sc;
2434 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
2435 tq->tq_index = index;
2437 tq->tq_free = BWN_PIO_MAX_TXPACKETS;
2438 if (siba_get_revid(sc->sc_dev) >= 8)
2441 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
2445 TAILQ_INIT(&tq->tq_pktlist);
2446 for (i = 0; i < N(tq->tq_pkts); i++) {
2447 tp = &(tq->tq_pkts[i]);
2450 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
2455 bwn_pio_idx2base(struct bwn_mac *mac, int index)
2457 struct bwn_softc *sc = mac->mac_sc;
2458 static const uint16_t bases[] = {
2468 static const uint16_t bases_rev11[] = {
2477 if (siba_get_revid(sc->sc_dev) >= 11) {
2478 if (index >= N(bases_rev11))
2479 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2480 return (bases_rev11[index]);
2482 if (index >= N(bases))
2483 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2484 return (bases[index]);
2488 bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
2491 struct bwn_softc *sc = mac->mac_sc;
2494 prq->prq_rev = siba_get_revid(sc->sc_dev);
2495 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
2496 bwn_dma_rxdirectfifo(mac, index, 1);
2500 bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
2504 bwn_pio_cancel_tx_packets(tq);
2508 bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio)
2511 bwn_destroy_pioqueue_tx(pio);
2515 bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2519 return (BWN_READ_2(mac, tq->tq_base + offset));
2523 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
2529 type = bwn_dma_mask2type(bwn_dma_mask(mac));
2530 base = bwn_dma_base(type, idx);
2531 if (type == BWN_DMA_64BIT) {
2532 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
2533 ctl &= ~BWN_DMA64_RXDIRECTFIFO;
2535 ctl |= BWN_DMA64_RXDIRECTFIFO;
2536 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl);
2538 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL);
2539 ctl &= ~BWN_DMA32_RXDIRECTFIFO;
2541 ctl |= BWN_DMA32_RXDIRECTFIFO;
2542 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl);
2547 bwn_dma_mask(struct bwn_mac *mac)
2552 tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
2553 if (tmp & SIBA_TGSHIGH_DMA64)
2554 return (BWN_DMA_BIT_MASK(64));
2555 base = bwn_dma_base(0, 0);
2556 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
2557 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
2558 if (tmp & BWN_DMA32_TXADDREXT_MASK)
2559 return (BWN_DMA_BIT_MASK(32));
2561 return (BWN_DMA_BIT_MASK(30));
2565 bwn_dma_mask2type(uint64_t dmamask)
2568 if (dmamask == BWN_DMA_BIT_MASK(30))
2569 return (BWN_DMA_30BIT);
2570 if (dmamask == BWN_DMA_BIT_MASK(32))
2571 return (BWN_DMA_32BIT);
2572 if (dmamask == BWN_DMA_BIT_MASK(64))
2573 return (BWN_DMA_64BIT);
2574 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2575 return (BWN_DMA_30BIT);
2579 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
2581 struct bwn_pio_txpkt *tp;
2584 for (i = 0; i < N(tq->tq_pkts); i++) {
2585 tp = &(tq->tq_pkts[i]);
2594 bwn_dma_base(int type, int controller_idx)
2596 static const uint16_t map64[] = {
2604 static const uint16_t map32[] = {
2613 if (type == BWN_DMA_64BIT) {
2614 KASSERT(controller_idx >= 0 && controller_idx < N(map64),
2615 ("%s:%d: fail", __func__, __LINE__));
2616 return (map64[controller_idx]);
2618 KASSERT(controller_idx >= 0 && controller_idx < N(map32),
2619 ("%s:%d: fail", __func__, __LINE__));
2620 return (map32[controller_idx]);
2624 bwn_dma_init(struct bwn_mac *mac)
2626 struct bwn_dma *dma = &mac->mac_method.dma;
2628 /* setup TX DMA channels. */
2629 bwn_dma_setup(dma->wme[WME_AC_BK]);
2630 bwn_dma_setup(dma->wme[WME_AC_BE]);
2631 bwn_dma_setup(dma->wme[WME_AC_VI]);
2632 bwn_dma_setup(dma->wme[WME_AC_VO]);
2633 bwn_dma_setup(dma->mcast);
2634 /* setup RX DMA channel. */
2635 bwn_dma_setup(dma->rx);
2638 static struct bwn_dma_ring *
2639 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
2640 int for_tx, int type)
2642 struct bwn_dma *dma = &mac->mac_method.dma;
2643 struct bwn_dma_ring *dr;
2644 struct bwn_dmadesc_generic *desc;
2645 struct bwn_dmadesc_meta *mt;
2646 struct bwn_softc *sc = mac->mac_sc;
2649 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO);
2652 dr->dr_numslots = BWN_RXRING_SLOTS;
2654 dr->dr_numslots = BWN_TXRING_SLOTS;
2656 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta),
2657 M_DEVBUF, M_NOWAIT | M_ZERO);
2658 if (dr->dr_meta == NULL)
2663 dr->dr_base = bwn_dma_base(type, controller_index);
2664 dr->dr_index = controller_index;
2665 if (type == BWN_DMA_64BIT) {
2666 dr->getdesc = bwn_dma_64_getdesc;
2667 dr->setdesc = bwn_dma_64_setdesc;
2668 dr->start_transfer = bwn_dma_64_start_transfer;
2669 dr->suspend = bwn_dma_64_suspend;
2670 dr->resume = bwn_dma_64_resume;
2671 dr->get_curslot = bwn_dma_64_get_curslot;
2672 dr->set_curslot = bwn_dma_64_set_curslot;
2674 dr->getdesc = bwn_dma_32_getdesc;
2675 dr->setdesc = bwn_dma_32_setdesc;
2676 dr->start_transfer = bwn_dma_32_start_transfer;
2677 dr->suspend = bwn_dma_32_suspend;
2678 dr->resume = bwn_dma_32_resume;
2679 dr->get_curslot = bwn_dma_32_get_curslot;
2680 dr->set_curslot = bwn_dma_32_set_curslot;
2684 dr->dr_curslot = -1;
2686 if (dr->dr_index == 0) {
2687 switch (mac->mac_fw.fw_hdr_format) {
2688 case BWN_FW_HDR_351:
2689 case BWN_FW_HDR_410:
2691 BWN_DMA0_RX_BUFFERSIZE_FW351;
2692 dr->dr_frameoffset =
2693 BWN_DMA0_RX_FRAMEOFFSET_FW351;
2695 case BWN_FW_HDR_598:
2697 BWN_DMA0_RX_BUFFERSIZE_FW598;
2698 dr->dr_frameoffset =
2699 BWN_DMA0_RX_FRAMEOFFSET_FW598;
2703 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2706 error = bwn_dma_allocringmemory(dr);
2712 * Assumption: BWN_TXRING_SLOTS can be divided by
2713 * BWN_TX_SLOTS_PER_FRAME
2715 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0,
2716 ("%s:%d: fail", __func__, __LINE__));
2718 dr->dr_txhdr_cache = contigmalloc(
2719 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2720 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO,
2721 0, BUS_SPACE_MAXADDR, 8, 0);
2722 if (dr->dr_txhdr_cache == NULL) {
2723 device_printf(sc->sc_dev,
2724 "can't allocate TX header DMA memory\n");
2729 * Create TX ring DMA stuffs
2731 error = bus_dma_tag_create(dma->parent_dtag,
2738 BUS_SPACE_MAXSIZE_32BIT,
2741 &dr->dr_txring_dtag);
2743 device_printf(sc->sc_dev,
2744 "can't create TX ring DMA tag: TODO frees\n");
2748 for (i = 0; i < dr->dr_numslots; i += 2) {
2749 dr->getdesc(dr, i, &desc, &mt);
2751 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER;
2755 error = bus_dmamap_create(dr->dr_txring_dtag, 0,
2758 device_printf(sc->sc_dev,
2759 "can't create RX buf DMA map\n");
2763 dr->getdesc(dr, i + 1, &desc, &mt);
2765 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY;
2769 error = bus_dmamap_create(dma->txbuf_dtag, 0,
2772 device_printf(sc->sc_dev,
2773 "can't create RX buf DMA map\n");
2778 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2779 &dr->dr_spare_dmap);
2781 device_printf(sc->sc_dev,
2782 "can't create RX buf DMA map\n");
2783 goto out; /* XXX wrong! */
2786 for (i = 0; i < dr->dr_numslots; i++) {
2787 dr->getdesc(dr, i, &desc, &mt);
2789 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2792 device_printf(sc->sc_dev,
2793 "can't create RX buf DMA map\n");
2794 goto out; /* XXX wrong! */
2796 error = bwn_dma_newbuf(dr, desc, mt, 1);
2798 device_printf(sc->sc_dev,
2799 "failed to allocate RX buf\n");
2800 goto out; /* XXX wrong! */
2804 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
2805 BUS_DMASYNC_PREWRITE);
2807 dr->dr_usedslot = dr->dr_numslots;
2814 if (dr->dr_txhdr_cache != NULL) {
2815 contigfree(dr->dr_txhdr_cache,
2816 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2817 BWN_MAXTXHDRSIZE, M_DEVBUF);
2820 free(dr->dr_meta, M_DEVBUF);
2827 bwn_dma_ringfree(struct bwn_dma_ring **dr)
2833 bwn_dma_free_descbufs(*dr);
2834 bwn_dma_free_ringmemory(*dr);
2836 if ((*dr)->dr_txhdr_cache != NULL) {
2837 contigfree((*dr)->dr_txhdr_cache,
2838 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2839 BWN_MAXTXHDRSIZE, M_DEVBUF);
2841 free((*dr)->dr_meta, M_DEVBUF);
2842 free(*dr, M_DEVBUF);
2848 bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot,
2849 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
2851 struct bwn_dmadesc32 *desc;
2853 *meta = &(dr->dr_meta[slot]);
2854 desc = dr->dr_ring_descbase;
2855 desc = &(desc[slot]);
2857 *gdesc = (struct bwn_dmadesc_generic *)desc;
2861 bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
2862 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
2863 int start, int end, int irq)
2865 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase;
2866 struct bwn_softc *sc = dr->dr_mac->mac_sc;
2867 uint32_t addr, addrext, ctl;
2870 slot = (int)(&(desc->dma.dma32) - descbase);
2871 KASSERT(slot >= 0 && slot < dr->dr_numslots,
2872 ("%s:%d: fail", __func__, __LINE__));
2874 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK);
2875 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30;
2876 addr |= siba_dma_translation(sc->sc_dev);
2877 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
2878 if (slot == dr->dr_numslots - 1)
2879 ctl |= BWN_DMA32_DCTL_DTABLEEND;
2881 ctl |= BWN_DMA32_DCTL_FRAMESTART;
2883 ctl |= BWN_DMA32_DCTL_FRAMEEND;
2885 ctl |= BWN_DMA32_DCTL_IRQ;
2886 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT)
2887 & BWN_DMA32_DCTL_ADDREXT_MASK;
2889 desc->dma.dma32.control = htole32(ctl);
2890 desc->dma.dma32.address = htole32(addr);
2894 bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot)
2897 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX,
2898 (uint32_t)(slot * sizeof(struct bwn_dmadesc32)));
2902 bwn_dma_32_suspend(struct bwn_dma_ring *dr)
2905 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
2906 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND);
2910 bwn_dma_32_resume(struct bwn_dma_ring *dr)
2913 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
2914 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND);
2918 bwn_dma_32_get_curslot(struct bwn_dma_ring *dr)
2922 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS);
2923 val &= BWN_DMA32_RXDPTR;
2925 return (val / sizeof(struct bwn_dmadesc32));
2929 bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot)
2932 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX,
2933 (uint32_t) (slot * sizeof(struct bwn_dmadesc32)));
2937 bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot,
2938 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
2940 struct bwn_dmadesc64 *desc;
2942 *meta = &(dr->dr_meta[slot]);
2943 desc = dr->dr_ring_descbase;
2944 desc = &(desc[slot]);
2946 *gdesc = (struct bwn_dmadesc_generic *)desc;
2950 bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
2951 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
2952 int start, int end, int irq)
2954 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase;
2955 struct bwn_softc *sc = dr->dr_mac->mac_sc;
2957 uint32_t ctl0 = 0, ctl1 = 0;
2958 uint32_t addrlo, addrhi;
2961 slot = (int)(&(desc->dma.dma64) - descbase);
2962 KASSERT(slot >= 0 && slot < dr->dr_numslots,
2963 ("%s:%d: fail", __func__, __LINE__));
2965 addrlo = (uint32_t) (dmaaddr & 0xffffffff);
2966 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK);
2967 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >>
2969 addrhi |= (siba_dma_translation(sc->sc_dev) << 1);
2970 if (slot == dr->dr_numslots - 1)
2971 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
2973 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
2975 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
2977 ctl0 |= BWN_DMA64_DCTL0_IRQ;
2978 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
2979 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
2980 & BWN_DMA64_DCTL1_ADDREXT_MASK;
2982 desc->dma.dma64.control0 = htole32(ctl0);
2983 desc->dma.dma64.control1 = htole32(ctl1);
2984 desc->dma.dma64.address_low = htole32(addrlo);
2985 desc->dma.dma64.address_high = htole32(addrhi);
2989 bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot)
2992 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX,
2993 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
2997 bwn_dma_64_suspend(struct bwn_dma_ring *dr)
3000 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3001 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND);
3005 bwn_dma_64_resume(struct bwn_dma_ring *dr)
3008 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3009 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND);
3013 bwn_dma_64_get_curslot(struct bwn_dma_ring *dr)
3017 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS);
3018 val &= BWN_DMA64_RXSTATDPTR;
3020 return (val / sizeof(struct bwn_dmadesc64));
3024 bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot)
3027 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX,
3028 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3032 bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
3034 struct bwn_mac *mac = dr->dr_mac;
3035 struct bwn_dma *dma = &mac->mac_method.dma;
3036 struct bwn_softc *sc = mac->mac_sc;
3039 error = bus_dma_tag_create(dma->parent_dtag,
3044 BWN_DMA_RINGMEMSIZE,
3046 BUS_SPACE_MAXSIZE_32BIT,
3051 device_printf(sc->sc_dev,
3052 "can't create TX ring DMA tag: TODO frees\n");
3056 error = bus_dmamem_alloc(dr->dr_ring_dtag,
3057 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3060 device_printf(sc->sc_dev,
3061 "can't allocate DMA mem: TODO frees\n");
3064 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap,
3065 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE,
3066 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT);
3068 device_printf(sc->sc_dev,
3069 "can't load DMA mem: TODO free\n");
3077 bwn_dma_setup(struct bwn_dma_ring *dr)
3079 struct bwn_softc *sc = dr->dr_mac->mac_sc;
3081 uint32_t addrext, ring32, value;
3082 uint32_t trans = siba_dma_translation(sc->sc_dev);
3085 dr->dr_curslot = -1;
3087 if (dr->dr_type == BWN_DMA_64BIT) {
3088 ring64 = (uint64_t)(dr->dr_ring_dmabase);
3089 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK)
3091 value = BWN_DMA64_TXENABLE;
3092 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
3093 & BWN_DMA64_TXADDREXT_MASK;
3094 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
3095 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO,
3096 (ring64 & 0xffffffff));
3097 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI,
3099 ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1));
3101 ring32 = (uint32_t)(dr->dr_ring_dmabase);
3102 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
3103 value = BWN_DMA32_TXENABLE;
3104 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
3105 & BWN_DMA32_TXADDREXT_MASK;
3106 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
3107 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING,
3108 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
3116 dr->dr_usedslot = dr->dr_numslots;
3118 if (dr->dr_type == BWN_DMA_64BIT) {
3119 ring64 = (uint64_t)(dr->dr_ring_dmabase);
3120 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30;
3121 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
3122 value |= BWN_DMA64_RXENABLE;
3123 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
3124 & BWN_DMA64_RXADDREXT_MASK;
3125 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
3126 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff));
3127 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI,
3128 ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK)
3130 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
3131 sizeof(struct bwn_dmadesc64));
3133 ring32 = (uint32_t)(dr->dr_ring_dmabase);
3134 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30;
3135 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
3136 value |= BWN_DMA32_RXENABLE;
3137 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
3138 & BWN_DMA32_RXADDREXT_MASK;
3139 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
3140 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING,
3141 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans);
3142 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
3143 sizeof(struct bwn_dmadesc32));
3148 bwn_dma_free_ringmemory(struct bwn_dma_ring *dr)
3151 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap);
3152 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase,
3157 bwn_dma_cleanup(struct bwn_dma_ring *dr)
3161 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3162 if (dr->dr_type == BWN_DMA_64BIT) {
3163 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
3164 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
3166 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
3168 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3169 if (dr->dr_type == BWN_DMA_64BIT) {
3170 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
3171 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
3173 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0);
3178 bwn_dma_free_descbufs(struct bwn_dma_ring *dr)
3180 struct bwn_dmadesc_generic *desc;
3181 struct bwn_dmadesc_meta *meta;
3182 struct bwn_mac *mac = dr->dr_mac;
3183 struct bwn_dma *dma = &mac->mac_method.dma;
3184 struct bwn_softc *sc = mac->mac_sc;
3187 if (!dr->dr_usedslot)
3189 for (i = 0; i < dr->dr_numslots; i++) {
3190 dr->getdesc(dr, i, &desc, &meta);
3192 if (meta->mt_m == NULL) {
3194 device_printf(sc->sc_dev, "%s: not TX?\n",
3199 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
3200 bus_dmamap_unload(dr->dr_txring_dtag,
3202 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
3203 bus_dmamap_unload(dma->txbuf_dtag,
3206 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
3207 bwn_dma_free_descbuf(dr, meta);
3212 bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
3215 struct bwn_softc *sc = mac->mac_sc;
3220 for (i = 0; i < 10; i++) {
3221 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
3223 value = BWN_READ_4(mac, base + offset);
3224 if (type == BWN_DMA_64BIT) {
3225 value &= BWN_DMA64_TXSTAT;
3226 if (value == BWN_DMA64_TXSTAT_DISABLED ||
3227 value == BWN_DMA64_TXSTAT_IDLEWAIT ||
3228 value == BWN_DMA64_TXSTAT_STOPPED)
3231 value &= BWN_DMA32_TXSTATE;
3232 if (value == BWN_DMA32_TXSTAT_DISABLED ||
3233 value == BWN_DMA32_TXSTAT_IDLEWAIT ||
3234 value == BWN_DMA32_TXSTAT_STOPPED)
3239 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL;
3240 BWN_WRITE_4(mac, base + offset, 0);
3241 for (i = 0; i < 10; i++) {
3242 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS :
3244 value = BWN_READ_4(mac, base + offset);
3245 if (type == BWN_DMA_64BIT) {
3246 value &= BWN_DMA64_TXSTAT;
3247 if (value == BWN_DMA64_TXSTAT_DISABLED) {
3252 value &= BWN_DMA32_TXSTATE;
3253 if (value == BWN_DMA32_TXSTAT_DISABLED) {
3261 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3270 bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
3273 struct bwn_softc *sc = mac->mac_sc;
3278 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL;
3279 BWN_WRITE_4(mac, base + offset, 0);
3280 for (i = 0; i < 10; i++) {
3281 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS :
3283 value = BWN_READ_4(mac, base + offset);
3284 if (type == BWN_DMA_64BIT) {
3285 value &= BWN_DMA64_RXSTAT;
3286 if (value == BWN_DMA64_RXSTAT_DISABLED) {
3291 value &= BWN_DMA32_RXSTATE;
3292 if (value == BWN_DMA32_RXSTAT_DISABLED) {
3300 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3308 bwn_dma_free_descbuf(struct bwn_dma_ring *dr,
3309 struct bwn_dmadesc_meta *meta)
3312 if (meta->mt_m != NULL) {
3313 m_freem(meta->mt_m);
3316 if (meta->mt_ni != NULL) {
3317 ieee80211_free_node(meta->mt_ni);
3323 bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3325 struct bwn_rxhdr4 *rxhdr;
3326 unsigned char *frame;
3328 rxhdr = mtod(m, struct bwn_rxhdr4 *);
3329 rxhdr->frame_len = 0;
3331 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset +
3332 sizeof(struct bwn_plcp6) + 2,
3333 ("%s:%d: fail", __func__, __LINE__));
3334 frame = mtod(m, char *) + dr->dr_frameoffset;
3335 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */);
3339 bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3341 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset;
3343 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7])
3348 bwn_wme_init(struct bwn_mac *mac)
3353 /* enable WME support. */
3354 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF);
3355 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) |
3356 BWN_IFSCTL_USE_EDCF);
3360 bwn_spu_setdelay(struct bwn_mac *mac, int idle)
3362 struct bwn_softc *sc = mac->mac_sc;
3363 struct ieee80211com *ic = &sc->sc_ic;
3364 uint16_t delay; /* microsec */
3366 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050;
3367 if (ic->ic_opmode == IEEE80211_M_IBSS || idle)
3369 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8))
3370 delay = max(delay, (uint16_t)2400);
3372 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
3376 bwn_bt_enable(struct bwn_mac *mac)
3378 struct bwn_softc *sc = mac->mac_sc;
3381 if (bwn_bluetooth == 0)
3383 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0)
3385 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
3388 hf = bwn_hf_read(mac);
3389 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD)
3390 hf |= BWN_HF_BT_COEXISTALT;
3392 hf |= BWN_HF_BT_COEXIST;
3393 bwn_hf_write(mac, hf);
3397 bwn_set_macaddr(struct bwn_mac *mac)
3400 bwn_mac_write_bssid(mac);
3401 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF,
3402 mac->mac_sc->sc_ic.ic_macaddr);
3406 bwn_clear_keys(struct bwn_mac *mac)
3410 for (i = 0; i < mac->mac_max_nr_keys; i++) {
3411 KASSERT(i >= 0 && i < mac->mac_max_nr_keys,
3412 ("%s:%d: fail", __func__, __LINE__));
3414 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE,
3415 NULL, BWN_SEC_KEYSIZE, NULL);
3416 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) {
3417 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE,
3418 NULL, BWN_SEC_KEYSIZE, NULL);
3420 mac->mac_key[i].keyconf = NULL;
3425 bwn_crypt_init(struct bwn_mac *mac)
3427 struct bwn_softc *sc = mac->mac_sc;
3429 mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20;
3430 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
3431 ("%s:%d: fail", __func__, __LINE__));
3432 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
3434 if (siba_get_revid(sc->sc_dev) >= 5)
3435 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
3436 bwn_clear_keys(mac);
3440 bwn_chip_exit(struct bwn_mac *mac)
3442 struct bwn_softc *sc = mac->mac_sc;
3445 siba_gpio_set(sc->sc_dev, 0);
3449 bwn_fw_fillinfo(struct bwn_mac *mac)
3453 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
3456 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
3463 bwn_gpio_init(struct bwn_mac *mac)
3465 struct bwn_softc *sc = mac->mac_sc;
3466 uint32_t mask = 0x1f, set = 0xf, value;
3468 BWN_WRITE_4(mac, BWN_MACCTL,
3469 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
3470 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3471 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f);
3473 if (siba_get_chipid(sc->sc_dev) == 0x4301) {
3477 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) {
3478 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3479 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200);
3483 if (siba_get_revid(sc->sc_dev) >= 2)
3486 value = siba_gpio_get(sc->sc_dev);
3489 siba_gpio_set(sc->sc_dev, (value & mask) | set);
3495 bwn_fw_loadinitvals(struct bwn_mac *mac)
3497 #define GETFWOFFSET(fwp, offset) \
3498 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset))
3499 const size_t hdr_len = sizeof(struct bwn_fwhdr);
3500 const struct bwn_fwhdr *hdr;
3501 struct bwn_fw *fw = &mac->mac_fw;
3504 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data);
3505 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len),
3506 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len);
3509 if (fw->initvals_band.fw) {
3510 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data);
3511 error = bwn_fwinitvals_write(mac,
3512 GETFWOFFSET(fw->initvals_band, hdr_len),
3514 fw->initvals_band.fw->datasize - hdr_len);
3521 bwn_phy_init(struct bwn_mac *mac)
3523 struct bwn_softc *sc = mac->mac_sc;
3526 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac);
3527 mac->mac_phy.rf_onoff(mac, 1);
3528 error = mac->mac_phy.init(mac);
3530 device_printf(sc->sc_dev, "PHY init failed\n");
3533 error = bwn_switch_channel(mac,
3534 mac->mac_phy.get_default_chan(mac));
3536 device_printf(sc->sc_dev,
3537 "failed to switch default channel\n");
3542 if (mac->mac_phy.exit)
3543 mac->mac_phy.exit(mac);
3545 mac->mac_phy.rf_onoff(mac, 0);
3551 bwn_set_txantenna(struct bwn_mac *mac, int antenna)
3556 ant = bwn_ant2phy(antenna);
3559 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL);
3560 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3561 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp);
3562 /* For Probe Resposes */
3563 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL);
3564 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3565 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp);
3569 bwn_set_opmode(struct bwn_mac *mac)
3571 struct bwn_softc *sc = mac->mac_sc;
3572 struct ieee80211com *ic = &sc->sc_ic;
3574 uint16_t cfp_pretbtt;
3576 ctl = BWN_READ_4(mac, BWN_MACCTL);
3577 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL |
3578 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS |
3579 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC);
3580 ctl |= BWN_MACCTL_STA;
3582 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3583 ic->ic_opmode == IEEE80211_M_MBSS)
3584 ctl |= BWN_MACCTL_HOSTAP;
3585 else if (ic->ic_opmode == IEEE80211_M_IBSS)
3586 ctl &= ~BWN_MACCTL_STA;
3587 ctl |= sc->sc_filters;
3589 if (siba_get_revid(sc->sc_dev) <= 4)
3590 ctl |= BWN_MACCTL_PROMISC;
3592 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
3595 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
3596 if (siba_get_chipid(sc->sc_dev) == 0x4306 &&
3597 siba_get_chiprev(sc->sc_dev) == 3)
3602 BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
3606 bwn_dma_gettype(struct bwn_mac *mac)
3611 tmp = BWN_READ_4(mac, SIBA_TGSHIGH);
3612 if (tmp & SIBA_TGSHIGH_DMA64)
3613 return (BWN_DMA_64BIT);
3614 base = bwn_dma_base(0, 0);
3615 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK);
3616 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
3617 if (tmp & BWN_DMA32_TXADDREXT_MASK)
3618 return (BWN_DMA_32BIT);
3620 return (BWN_DMA_30BIT);
3624 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3627 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
3628 *((bus_addr_t *)arg) = seg->ds_addr;
3633 bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
3635 struct bwn_phy *phy = &mac->mac_phy;
3636 struct bwn_softc *sc = mac->mac_sc;
3637 unsigned int i, max_loop;
3639 uint32_t buffer[5] = {
3640 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
3645 buffer[0] = 0x000201cc;
3648 buffer[0] = 0x000b846e;
3651 BWN_ASSERT_LOCKED(mac->mac_sc);
3653 for (i = 0; i < 5; i++)
3654 bwn_ram_write(mac, i * 4, buffer[i]);
3656 BWN_WRITE_2(mac, 0x0568, 0x0000);
3657 BWN_WRITE_2(mac, 0x07c0,
3658 (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
3660 value = (ofdm ? 0x41 : 0x40);
3661 BWN_WRITE_2(mac, 0x050c, value);
3663 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP ||
3664 phy->type == BWN_PHYTYPE_LCN)
3665 BWN_WRITE_2(mac, 0x0514, 0x1a02);
3666 BWN_WRITE_2(mac, 0x0508, 0x0000);
3667 BWN_WRITE_2(mac, 0x050a, 0x0000);
3668 BWN_WRITE_2(mac, 0x054c, 0x0000);
3669 BWN_WRITE_2(mac, 0x056a, 0x0014);
3670 BWN_WRITE_2(mac, 0x0568, 0x0826);
3671 BWN_WRITE_2(mac, 0x0500, 0x0000);
3673 /* XXX TODO: n phy pa override? */
3675 switch (phy->type) {
3677 case BWN_PHYTYPE_LCN:
3678 BWN_WRITE_2(mac, 0x0502, 0x00d0);
3680 case BWN_PHYTYPE_LP:
3681 BWN_WRITE_2(mac, 0x0502, 0x0050);
3684 BWN_WRITE_2(mac, 0x0502, 0x0030);
3689 BWN_READ_2(mac, 0x0502);
3691 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3692 BWN_RF_WRITE(mac, 0x0051, 0x0017);
3693 for (i = 0x00; i < max_loop; i++) {
3694 value = BWN_READ_2(mac, 0x050e);
3699 for (i = 0x00; i < 0x0a; i++) {
3700 value = BWN_READ_2(mac, 0x050e);
3705 for (i = 0x00; i < 0x19; i++) {
3706 value = BWN_READ_2(mac, 0x0690);
3707 if (!(value & 0x0100))
3711 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3712 BWN_RF_WRITE(mac, 0x0051, 0x0037);
3716 bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
3720 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__));
3722 macctl = BWN_READ_4(mac, BWN_MACCTL);
3723 if (macctl & BWN_MACCTL_BIGENDIAN)
3724 printf("TODO: need swap\n");
3726 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
3727 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
3728 BWN_WRITE_4(mac, BWN_RAM_DATA, val);
3732 bwn_mac_suspend(struct bwn_mac *mac)
3734 struct bwn_softc *sc = mac->mac_sc;
3738 KASSERT(mac->mac_suspended >= 0,
3739 ("%s:%d: fail", __func__, __LINE__));
3741 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3742 __func__, mac->mac_suspended);
3744 if (mac->mac_suspended == 0) {
3745 bwn_psctl(mac, BWN_PS_AWAKE);
3746 BWN_WRITE_4(mac, BWN_MACCTL,
3747 BWN_READ_4(mac, BWN_MACCTL)
3749 BWN_READ_4(mac, BWN_MACCTL);
3750 for (i = 35; i; i--) {
3751 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3752 if (tmp & BWN_INTR_MAC_SUSPENDED)
3756 for (i = 40; i; i--) {
3757 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3758 if (tmp & BWN_INTR_MAC_SUSPENDED)
3762 device_printf(sc->sc_dev, "MAC suspend failed\n");
3765 mac->mac_suspended++;
3769 bwn_mac_enable(struct bwn_mac *mac)
3771 struct bwn_softc *sc = mac->mac_sc;
3774 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3775 __func__, mac->mac_suspended);
3777 state = bwn_shm_read_2(mac, BWN_SHARED,
3778 BWN_SHARED_UCODESTAT);
3779 if (state != BWN_SHARED_UCODESTAT_SUSPEND &&
3780 state != BWN_SHARED_UCODESTAT_SLEEP) {
3781 DPRINTF(sc, BWN_DEBUG_FW,
3782 "%s: warn: firmware state (%d)\n",
3786 mac->mac_suspended--;
3787 KASSERT(mac->mac_suspended >= 0,
3788 ("%s:%d: fail", __func__, __LINE__));
3789 if (mac->mac_suspended == 0) {
3790 BWN_WRITE_4(mac, BWN_MACCTL,
3791 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON);
3792 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED);
3793 BWN_READ_4(mac, BWN_MACCTL);
3794 BWN_READ_4(mac, BWN_INTR_REASON);
3800 bwn_psctl(struct bwn_mac *mac, uint32_t flags)
3802 struct bwn_softc *sc = mac->mac_sc;
3806 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
3807 ("%s:%d: fail", __func__, __LINE__));
3808 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
3809 ("%s:%d: fail", __func__, __LINE__));
3811 /* XXX forcibly awake and hwps-off */
3813 BWN_WRITE_4(mac, BWN_MACCTL,
3814 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
3816 BWN_READ_4(mac, BWN_MACCTL);
3817 if (siba_get_revid(sc->sc_dev) >= 5) {
3818 for (i = 0; i < 100; i++) {
3819 ucstat = bwn_shm_read_2(mac, BWN_SHARED,
3820 BWN_SHARED_UCODESTAT);
3821 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
3826 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__,
3831 bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
3833 struct bwn_softc *sc = mac->mac_sc;
3834 struct bwn_fw *fw = &mac->mac_fw;
3835 const uint8_t rev = siba_get_revid(sc->sc_dev);
3836 const char *filename;
3844 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
3845 filename = "ucode42";
3848 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
3849 filename = "ucode40";
3852 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40)
3853 filename = "ucode33_lcn40";
3856 if (mac->mac_phy.type == BWN_PHYTYPE_N)
3857 filename = "ucode30_mimo";
3860 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
3861 filename = "ucode29_mimo";
3864 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
3865 filename = "ucode26_mimo";
3869 if (mac->mac_phy.type == BWN_PHYTYPE_N)
3870 filename = "ucode25_mimo";
3871 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
3872 filename = "ucode25_lcn";
3875 if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
3876 filename = "ucode24_lcn";
3879 if (mac->mac_phy.type == BWN_PHYTYPE_N)
3880 filename = "ucode16_mimo";
3886 if (mac->mac_phy.type == BWN_PHYTYPE_N)
3887 filename = "ucode16_mimo";
3888 else if (mac->mac_phy.type == BWN_PHYTYPE_LP)
3889 filename = "ucode16_lp";
3892 filename = "ucode15";
3895 filename = "ucode14";
3898 filename = "ucode13";
3902 filename = "ucode11";
3910 filename = "ucode5";
3913 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev);
3914 bwn_release_firmware(mac);
3915 return (EOPNOTSUPP);
3918 device_printf(sc->sc_dev, "ucode fw: %s\n", filename);
3919 error = bwn_fw_get(mac, type, filename, &fw->ucode);
3921 bwn_release_firmware(mac);
3926 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__));
3927 if (rev >= 5 && rev <= 10) {
3928 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm);
3929 if (error == ENOENT)
3932 bwn_release_firmware(mac);
3935 } else if (rev < 11) {
3936 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
3937 bwn_release_firmware(mac);
3938 return (EOPNOTSUPP);
3942 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH);
3943 switch (mac->mac_phy.type) {
3945 if (rev < 5 || rev > 10)
3947 if (high & BWN_TGSHIGH_HAVE_2GHZ)
3948 filename = "a0g1initvals5";
3950 filename = "a0g0initvals5";
3953 if (rev >= 5 && rev <= 10)
3954 filename = "b0g0initvals5";
3956 filename = "b0g0initvals13";
3960 case BWN_PHYTYPE_LP:
3962 filename = "lp0initvals13";
3964 filename = "lp0initvals14";
3966 filename = "lp0initvals15";
3972 filename = "n16initvals30";
3973 else if (rev == 28 || rev == 25)
3974 filename = "n0initvals25";
3976 filename = "n0initvals24";
3978 filename = "n0initvals16";
3979 else if (rev >= 16 && rev <= 18)
3980 filename = "n0initvals16";
3981 else if (rev >= 11 && rev <= 12)
3982 filename = "n0initvals11";
3989 error = bwn_fw_get(mac, type, filename, &fw->initvals);
3991 bwn_release_firmware(mac);
3995 /* bandswitch initvals */
3996 switch (mac->mac_phy.type) {
3998 if (rev >= 5 && rev <= 10) {
3999 if (high & BWN_TGSHIGH_HAVE_2GHZ)
4000 filename = "a0g1bsinitvals5";
4002 filename = "a0g0bsinitvals5";
4003 } else if (rev >= 11)
4009 if (rev >= 5 && rev <= 10)
4010 filename = "b0g0bsinitvals5";
4016 case BWN_PHYTYPE_LP:
4018 filename = "lp0bsinitvals13";
4020 filename = "lp0bsinitvals14";
4022 filename = "lp0bsinitvals15";
4028 filename = "n16bsinitvals30";
4029 else if (rev == 28 || rev == 25)
4030 filename = "n0bsinitvals25";
4032 filename = "n0bsinitvals24";
4034 filename = "n0bsinitvals16";
4035 else if (rev >= 16 && rev <= 18)
4036 filename = "n0bsinitvals16";
4037 else if (rev >= 11 && rev <= 12)
4038 filename = "n0bsinitvals11";
4043 device_printf(sc->sc_dev, "unknown phy (%d)\n",
4047 error = bwn_fw_get(mac, type, filename, &fw->initvals_band);
4049 bwn_release_firmware(mac);
4054 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n",
4055 rev, mac->mac_phy.type);
4056 bwn_release_firmware(mac);
4057 return (EOPNOTSUPP);
4061 bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type,
4062 const char *name, struct bwn_fwfile *bfw)
4064 const struct bwn_fwhdr *hdr;
4065 struct bwn_softc *sc = mac->mac_sc;
4066 const struct firmware *fw;
4070 bwn_do_release_fw(bfw);
4073 if (bfw->filename != NULL) {
4074 if (bfw->type == type && (strcmp(bfw->filename, name) == 0))
4076 bwn_do_release_fw(bfw);
4079 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s",
4080 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "",
4081 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name);
4082 /* XXX Sleeping on "fwload" with the non-sleepable locks held */
4083 fw = firmware_get(namebuf);
4085 device_printf(sc->sc_dev, "the fw file(%s) not found\n",
4089 if (fw->datasize < sizeof(struct bwn_fwhdr))
4091 hdr = (const struct bwn_fwhdr *)(fw->data);
4092 switch (hdr->type) {
4093 case BWN_FWTYPE_UCODE:
4094 case BWN_FWTYPE_PCM:
4095 if (be32toh(hdr->size) !=
4096 (fw->datasize - sizeof(struct bwn_fwhdr)))
4106 bfw->filename = name;
4111 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf);
4113 firmware_put(fw, FIRMWARE_UNLOAD);
4118 bwn_release_firmware(struct bwn_mac *mac)
4121 bwn_do_release_fw(&mac->mac_fw.ucode);
4122 bwn_do_release_fw(&mac->mac_fw.pcm);
4123 bwn_do_release_fw(&mac->mac_fw.initvals);
4124 bwn_do_release_fw(&mac->mac_fw.initvals_band);
4128 bwn_do_release_fw(struct bwn_fwfile *bfw)
4131 if (bfw->fw != NULL)
4132 firmware_put(bfw->fw, FIRMWARE_UNLOAD);
4134 bfw->filename = NULL;
4138 bwn_fw_loaducode(struct bwn_mac *mac)
4140 #define GETFWOFFSET(fwp, offset) \
4141 ((const uint32_t *)((const char *)fwp.fw->data + offset))
4142 #define GETFWSIZE(fwp, offset) \
4143 ((fwp.fw->datasize - offset) / sizeof(uint32_t))
4144 struct bwn_softc *sc = mac->mac_sc;
4145 const uint32_t *data;
4148 uint16_t date, fwcaps, time;
4151 ctl = BWN_READ_4(mac, BWN_MACCTL);
4152 ctl |= BWN_MACCTL_MCODE_JMP0;
4153 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__,
4155 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4156 for (i = 0; i < 64; i++)
4157 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0);
4158 for (i = 0; i < 4096; i += 2)
4159 bwn_shm_write_2(mac, BWN_SHARED, i, 0);
4161 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4162 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000);
4163 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4165 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4169 if (mac->mac_fw.pcm.fw) {
4170 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr));
4171 bwn_shm_ctlword(mac, BWN_HW, 0x01ea);
4172 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000);
4173 bwn_shm_ctlword(mac, BWN_HW, 0x01eb);
4174 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm,
4175 sizeof(struct bwn_fwhdr)); i++) {
4176 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4181 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL);
4182 BWN_WRITE_4(mac, BWN_MACCTL,
4183 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) |
4184 BWN_MACCTL_MCODE_RUN);
4186 for (i = 0; i < 21; i++) {
4187 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED)
4190 device_printf(sc->sc_dev, "ucode timeout\n");
4196 BWN_READ_4(mac, BWN_INTR_REASON);
4198 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV);
4199 if (mac->mac_fw.rev <= 0x128) {
4200 device_printf(sc->sc_dev, "the firmware is too old\n");
4206 * Determine firmware header version; needed for TX/RX packet
4209 if (mac->mac_fw.rev >= 598)
4210 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598;
4211 else if (mac->mac_fw.rev >= 410)
4212 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410;
4214 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351;
4217 * We don't support rev 598 or later; that requires
4218 * another round of changes to the TX/RX descriptor
4219 * and status layout.
4221 * So, complain this is the case and exit out, rather
4222 * than attaching and then failing.
4225 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) {
4226 device_printf(sc->sc_dev,
4227 "firmware is too new (>=598); not supported\n");
4233 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED,
4234 BWN_SHARED_UCODE_PATCH);
4235 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE);
4236 mac->mac_fw.opensource = (date == 0xffff);
4238 mac->mac_flags |= BWN_MAC_FLAG_WME;
4239 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO;
4241 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME);
4242 if (mac->mac_fw.opensource == 0) {
4243 device_printf(sc->sc_dev,
4244 "firmware version (rev %u patch %u date %#x time %#x)\n",
4245 mac->mac_fw.rev, mac->mac_fw.patch, date, time);
4246 if (mac->mac_fw.no_pcmfile)
4247 device_printf(sc->sc_dev,
4248 "no HW crypto acceleration due to pcm5\n");
4250 mac->mac_fw.patch = time;
4251 fwcaps = bwn_fwcaps_read(mac);
4252 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) {
4253 device_printf(sc->sc_dev,
4254 "disabling HW crypto acceleration\n");
4255 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO;
4257 if (!(fwcaps & BWN_FWCAPS_WME)) {
4258 device_printf(sc->sc_dev, "disabling WME support\n");
4259 mac->mac_flags &= ~BWN_MAC_FLAG_WME;
4263 if (BWN_ISOLDFMT(mac))
4264 device_printf(sc->sc_dev, "using old firmware image\n");
4269 BWN_WRITE_4(mac, BWN_MACCTL,
4270 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) |
4271 BWN_MACCTL_MCODE_JMP0);
4278 /* OpenFirmware only */
4280 bwn_fwcaps_read(struct bwn_mac *mac)
4283 KASSERT(mac->mac_fw.opensource == 1,
4284 ("%s:%d: fail", __func__, __LINE__));
4285 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS));
4289 bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals,
4290 size_t count, size_t array_size)
4292 #define GET_NEXTIV16(iv) \
4293 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4294 sizeof(uint16_t) + sizeof(uint16_t)))
4295 #define GET_NEXTIV32(iv) \
4296 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4297 sizeof(uint16_t) + sizeof(uint32_t)))
4298 struct bwn_softc *sc = mac->mac_sc;
4299 const struct bwn_fwinitvals *iv;
4304 KASSERT(sizeof(struct bwn_fwinitvals) == 6,
4305 ("%s:%d: fail", __func__, __LINE__));
4307 for (i = 0; i < count; i++) {
4308 if (array_size < sizeof(iv->offset_size))
4310 array_size -= sizeof(iv->offset_size);
4311 offset = be16toh(iv->offset_size);
4312 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0;
4313 offset &= BWN_FWINITVALS_OFFSET_MASK;
4314 if (offset >= 0x1000)
4317 if (array_size < sizeof(iv->data.d32))
4319 array_size -= sizeof(iv->data.d32);
4320 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32));
4321 iv = GET_NEXTIV32(iv);
4324 if (array_size < sizeof(iv->data.d16))
4326 array_size -= sizeof(iv->data.d16);
4327 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16));
4329 iv = GET_NEXTIV16(iv);
4332 if (array_size != 0)
4336 device_printf(sc->sc_dev, "initvals: invalid format\n");
4343 bwn_switch_channel(struct bwn_mac *mac, int chan)
4345 struct bwn_phy *phy = &(mac->mac_phy);
4346 struct bwn_softc *sc = mac->mac_sc;
4347 struct ieee80211com *ic = &sc->sc_ic;
4348 uint16_t channelcookie, savedcookie;
4352 chan = phy->get_default_chan(mac);
4354 channelcookie = chan;
4355 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4356 channelcookie |= 0x100;
4357 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN);
4358 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie);
4359 error = phy->switch_channel(mac, chan);
4363 mac->mac_phy.chan = chan;
4367 device_printf(sc->sc_dev, "failed to switch channel\n");
4368 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie);
4373 bwn_ant2phy(int antenna)
4378 return (BWN_TX_PHY_ANT0);
4380 return (BWN_TX_PHY_ANT1);
4382 return (BWN_TX_PHY_ANT2);
4384 return (BWN_TX_PHY_ANT3);
4386 return (BWN_TX_PHY_ANT01AUTO);
4388 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4393 bwn_wme_load(struct bwn_mac *mac)
4395 struct bwn_softc *sc = mac->mac_sc;
4398 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
4399 ("%s:%d: fail", __func__, __LINE__));
4401 bwn_mac_suspend(mac);
4402 for (i = 0; i < N(sc->sc_wmeParams); i++)
4403 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]),
4404 bwn_wme_shm_offsets[i]);
4405 bwn_mac_enable(mac);
4409 bwn_wme_loadparams(struct bwn_mac *mac,
4410 const struct wmeParams *p, uint16_t shm_offset)
4412 #define SM(_v, _f) (((_v) << _f##_S) & _f)
4413 struct bwn_softc *sc = mac->mac_sc;
4414 uint16_t params[BWN_NR_WMEPARAMS];
4418 slot = BWN_READ_2(mac, BWN_RNG) &
4419 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4421 memset(¶ms, 0, sizeof(params));
4423 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d "
4424 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit,
4425 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn);
4427 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32;
4428 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4429 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX);
4430 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4431 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn;
4432 params[BWN_WMEPARAM_BSLOTS] = slot;
4433 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn;
4435 for (i = 0; i < N(params); i++) {
4436 if (i == BWN_WMEPARAM_STATUS) {
4437 tmp = bwn_shm_read_2(mac, BWN_SHARED,
4438 shm_offset + (i * 2));
4440 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4443 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4450 bwn_mac_write_bssid(struct bwn_mac *mac)
4452 struct bwn_softc *sc = mac->mac_sc;
4455 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2];
4457 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid);
4458 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN);
4459 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid,
4460 IEEE80211_ADDR_LEN);
4462 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) {
4463 tmp = (uint32_t) (mac_bssid[i + 0]);
4464 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8;
4465 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16;
4466 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24;
4467 bwn_ram_write(mac, 0x20 + i, tmp);
4472 bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset,
4473 const uint8_t *macaddr)
4475 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 };
4482 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset);
4485 data |= macaddr[1] << 8;
4486 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4488 data |= macaddr[3] << 8;
4489 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4491 data |= macaddr[5] << 8;
4492 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4496 bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4497 const uint8_t *key, size_t key_len, const uint8_t *mac_addr)
4499 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, };
4500 uint8_t per_sta_keys_start = 8;
4502 if (BWN_SEC_NEWAPI(mac))
4503 per_sta_keys_start = 4;
4505 KASSERT(index < mac->mac_max_nr_keys,
4506 ("%s:%d: fail", __func__, __LINE__));
4507 KASSERT(key_len <= BWN_SEC_KEYSIZE,
4508 ("%s:%d: fail", __func__, __LINE__));
4510 if (index >= per_sta_keys_start)
4511 bwn_key_macwrite(mac, index, NULL);
4513 memcpy(buf, key, key_len);
4514 bwn_key_write(mac, index, algorithm, buf);
4515 if (index >= per_sta_keys_start)
4516 bwn_key_macwrite(mac, index, mac_addr);
4518 mac->mac_key[index].algorithm = algorithm;
4522 bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
4524 struct bwn_softc *sc = mac->mac_sc;
4525 uint32_t addrtmp[2] = { 0, 0 };
4528 if (BWN_SEC_NEWAPI(mac))
4531 KASSERT(index >= start,
4532 ("%s:%d: fail", __func__, __LINE__));
4536 addrtmp[0] = addr[0];
4537 addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
4538 addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
4539 addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
4540 addrtmp[1] = addr[4];
4541 addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
4544 if (siba_get_revid(sc->sc_dev) >= 5) {
4545 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
4546 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
4549 bwn_shm_write_4(mac, BWN_SHARED,
4550 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
4551 bwn_shm_write_2(mac, BWN_SHARED,
4552 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);
4558 bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4563 uint16_t kidx, value;
4565 kidx = BWN_SEC_KEY2FW(mac, index);
4566 bwn_shm_write_2(mac, BWN_SHARED,
4567 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm);
4569 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE);
4570 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) {
4572 value |= (uint16_t)(key[i + 1]) << 8;
4573 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value);
4578 bwn_phy_exit(struct bwn_mac *mac)
4581 mac->mac_phy.rf_onoff(mac, 0);
4582 if (mac->mac_phy.exit != NULL)
4583 mac->mac_phy.exit(mac);
4587 bwn_dma_free(struct bwn_mac *mac)
4589 struct bwn_dma *dma;
4591 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
4593 dma = &mac->mac_method.dma;
4595 bwn_dma_ringfree(&dma->rx);
4596 bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
4597 bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
4598 bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
4599 bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
4600 bwn_dma_ringfree(&dma->mcast);
4604 bwn_core_stop(struct bwn_mac *mac)
4606 struct bwn_softc *sc = mac->mac_sc;
4608 BWN_ASSERT_LOCKED(sc);
4610 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
4613 callout_stop(&sc->sc_rfswitch_ch);
4614 callout_stop(&sc->sc_task_ch);
4615 callout_stop(&sc->sc_watchdog_ch);
4616 sc->sc_watchdog_timer = 0;
4617 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4618 BWN_READ_4(mac, BWN_INTR_MASK);
4619 bwn_mac_suspend(mac);
4621 mac->mac_status = BWN_MAC_STATUS_INITED;
4625 bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
4627 struct bwn_mac *up_dev = NULL;
4628 struct bwn_mac *down_dev;
4629 struct bwn_mac *mac;
4633 BWN_ASSERT_LOCKED(sc);
4635 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) {
4636 if (IEEE80211_IS_CHAN_2GHZ(chan) &&
4637 mac->mac_phy.supports_2ghz) {
4640 } else if (IEEE80211_IS_CHAN_5GHZ(chan) &&
4641 mac->mac_phy.supports_5ghz) {
4645 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4651 if (up_dev == NULL) {
4652 device_printf(sc->sc_dev, "Could not find a device\n");
4655 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode)
4658 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET,
4659 "switching to %s-GHz band\n",
4660 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4662 down_dev = sc->sc_curmac;
4663 status = down_dev->mac_status;
4664 if (status >= BWN_MAC_STATUS_STARTED)
4665 bwn_core_stop(down_dev);
4666 if (status >= BWN_MAC_STATUS_INITED)
4667 bwn_core_exit(down_dev);
4669 if (down_dev != up_dev)
4670 bwn_phy_reset(down_dev);
4672 up_dev->mac_phy.gmode = gmode;
4673 if (status >= BWN_MAC_STATUS_INITED) {
4674 err = bwn_core_init(up_dev);
4676 device_printf(sc->sc_dev,
4677 "fatal: failed to initialize for %s-GHz\n",
4678 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4682 if (status >= BWN_MAC_STATUS_STARTED)
4683 bwn_core_start(up_dev);
4684 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__));
4685 sc->sc_curmac = up_dev;
4689 sc->sc_curmac = NULL;
4694 bwn_rf_turnon(struct bwn_mac *mac)
4697 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4699 bwn_mac_suspend(mac);
4700 mac->mac_phy.rf_onoff(mac, 1);
4701 mac->mac_phy.rf_on = 1;
4702 bwn_mac_enable(mac);
4706 bwn_rf_turnoff(struct bwn_mac *mac)
4709 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4711 bwn_mac_suspend(mac);
4712 mac->mac_phy.rf_onoff(mac, 0);
4713 mac->mac_phy.rf_on = 0;
4714 bwn_mac_enable(mac);
4721 bwn_phy_reset_siba(struct bwn_mac *mac)
4723 struct bwn_softc *sc = mac->mac_sc;
4725 siba_write_4(sc->sc_dev, SIBA_TGSLOW,
4726 ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) |
4727 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC);
4729 siba_write_4(sc->sc_dev, SIBA_TGSLOW,
4730 (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC));
4735 bwn_phy_reset(struct bwn_mac *mac)
4738 if (bwn_is_bus_siba(mac)) {
4739 bwn_phy_reset_siba(mac);
4741 BWN_ERRPRINTF(mac->mac_sc, "%s: unknown bus!\n", __func__);
4746 bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
4748 struct bwn_vap *bvp = BWN_VAP(vap);
4749 struct ieee80211com *ic= vap->iv_ic;
4750 enum ieee80211_state ostate = vap->iv_state;
4751 struct bwn_softc *sc = ic->ic_softc;
4752 struct bwn_mac *mac = sc->sc_curmac;
4755 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4756 ieee80211_state_name[vap->iv_state],
4757 ieee80211_state_name[nstate]);
4759 error = bvp->bv_newstate(vap, nstate, arg);
4765 bwn_led_newstate(mac, nstate);
4768 * Clear the BSSID when we stop a STA
4770 if (vap->iv_opmode == IEEE80211_M_STA) {
4771 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
4773 * Clear out the BSSID. If we reassociate to
4774 * the same AP, this will reinialize things
4777 if (ic->ic_opmode == IEEE80211_M_STA &&
4778 (sc->sc_flags & BWN_FLAG_INVALID) == 0) {
4779 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN);
4780 bwn_set_macaddr(mac);
4785 if (vap->iv_opmode == IEEE80211_M_MONITOR ||
4786 vap->iv_opmode == IEEE80211_M_AHDEMO) {
4787 /* XXX nothing to do? */
4788 } else if (nstate == IEEE80211_S_RUN) {
4789 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN);
4790 bwn_set_opmode(mac);
4791 bwn_set_pretbtt(mac);
4792 bwn_spu_setdelay(mac, 0);
4793 bwn_set_macaddr(mac);
4802 bwn_set_pretbtt(struct bwn_mac *mac)
4804 struct bwn_softc *sc = mac->mac_sc;
4805 struct ieee80211com *ic = &sc->sc_ic;
4808 if (ic->ic_opmode == IEEE80211_M_IBSS)
4811 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250;
4812 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt);
4813 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
4819 struct bwn_mac *mac = arg;
4820 struct bwn_softc *sc = mac->mac_sc;
4823 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
4824 (sc->sc_flags & BWN_FLAG_INVALID))
4825 return (FILTER_STRAY);
4827 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__);
4829 reason = BWN_READ_4(mac, BWN_INTR_REASON);
4830 if (reason == 0xffffffff) /* shared IRQ */
4831 return (FILTER_STRAY);
4832 reason &= mac->mac_intr_mask;
4834 return (FILTER_HANDLED);
4835 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason);
4837 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00;
4838 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00;
4839 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00;
4840 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00;
4841 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00;
4842 BWN_WRITE_4(mac, BWN_INTR_REASON, reason);
4843 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]);
4844 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]);
4845 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]);
4846 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]);
4847 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]);
4849 /* Disable interrupts. */
4850 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4852 mac->mac_reason_intr = reason;
4854 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
4855 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
4857 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
4858 return (FILTER_HANDLED);
4862 bwn_intrtask(void *arg, int npending)
4864 struct bwn_mac *mac = arg;
4865 struct bwn_softc *sc = mac->mac_sc;
4866 uint32_t merged = 0;
4867 int i, tx = 0, rx = 0;
4870 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
4871 (sc->sc_flags & BWN_FLAG_INVALID)) {
4876 for (i = 0; i < N(mac->mac_reason); i++)
4877 merged |= mac->mac_reason[i];
4879 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)
4880 device_printf(sc->sc_dev, "MAC trans error\n");
4882 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) {
4883 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__);
4884 mac->mac_phy.txerrors--;
4885 if (mac->mac_phy.txerrors == 0) {
4886 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
4887 bwn_restart(mac, "PHY TX errors");
4891 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) {
4892 if (merged & BWN_DMAINTR_FATALMASK) {
4893 device_printf(sc->sc_dev,
4894 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n",
4895 mac->mac_reason[0], mac->mac_reason[1],
4896 mac->mac_reason[2], mac->mac_reason[3],
4897 mac->mac_reason[4], mac->mac_reason[5]);
4898 bwn_restart(mac, "DMA error");
4902 if (merged & BWN_DMAINTR_NONFATALMASK) {
4903 device_printf(sc->sc_dev,
4904 "DMA error: %#x %#x %#x %#x %#x %#x\n",
4905 mac->mac_reason[0], mac->mac_reason[1],
4906 mac->mac_reason[2], mac->mac_reason[3],
4907 mac->mac_reason[4], mac->mac_reason[5]);
4911 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG)
4912 bwn_intr_ucode_debug(mac);
4913 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI)
4914 bwn_intr_tbtt_indication(mac);
4915 if (mac->mac_reason_intr & BWN_INTR_ATIM_END)
4916 bwn_intr_atim_end(mac);
4917 if (mac->mac_reason_intr & BWN_INTR_BEACON)
4918 bwn_intr_beacon(mac);
4919 if (mac->mac_reason_intr & BWN_INTR_PMQ)
4921 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK)
4922 bwn_intr_noise(mac);
4924 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
4925 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) {
4926 bwn_dma_rx(mac->mac_method.dma.rx);
4930 rx = bwn_pio_rx(&mac->mac_method.pio.rx);
4932 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4933 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4934 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4935 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4936 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
4938 if (mac->mac_reason_intr & BWN_INTR_TX_OK) {
4939 bwn_intr_txeof(mac);
4943 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
4945 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
4946 int evt = BWN_LED_EVENT_NONE;
4949 if (sc->sc_rx_rate > sc->sc_tx_rate)
4950 evt = BWN_LED_EVENT_RX;
4952 evt = BWN_LED_EVENT_TX;
4954 evt = BWN_LED_EVENT_TX;
4956 evt = BWN_LED_EVENT_RX;
4957 } else if (rx == 0) {
4958 evt = BWN_LED_EVENT_POLL;
4961 if (evt != BWN_LED_EVENT_NONE)
4962 bwn_led_event(mac, evt);
4965 if (mbufq_first(&sc->sc_snd) != NULL)
4968 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ);
4969 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE);
4975 bwn_restart(struct bwn_mac *mac, const char *msg)
4977 struct bwn_softc *sc = mac->mac_sc;
4978 struct ieee80211com *ic = &sc->sc_ic;
4980 if (mac->mac_status < BWN_MAC_STATUS_INITED)
4983 device_printf(sc->sc_dev, "HW reset: %s\n", msg);
4984 ieee80211_runtask(ic, &mac->mac_hwreset);
4988 bwn_intr_ucode_debug(struct bwn_mac *mac)
4990 struct bwn_softc *sc = mac->mac_sc;
4993 if (mac->mac_fw.opensource == 0)
4996 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG);
4998 case BWN_DEBUGINTR_PANIC:
4999 bwn_handle_fwpanic(mac);
5001 case BWN_DEBUGINTR_DUMP_SHM:
5002 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n");
5004 case BWN_DEBUGINTR_DUMP_REGS:
5005 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n");
5007 case BWN_DEBUGINTR_MARKER:
5008 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n");
5011 device_printf(sc->sc_dev,
5012 "ucode debug unknown reason: %#x\n", reason);
5015 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG,
5020 bwn_intr_tbtt_indication(struct bwn_mac *mac)
5022 struct bwn_softc *sc = mac->mac_sc;
5023 struct ieee80211com *ic = &sc->sc_ic;
5025 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
5027 if (ic->ic_opmode == IEEE80211_M_IBSS)
5028 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID;
5032 bwn_intr_atim_end(struct bwn_mac *mac)
5035 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) {
5036 BWN_WRITE_4(mac, BWN_MACCMD,
5037 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID);
5038 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
5043 bwn_intr_beacon(struct bwn_mac *mac)
5045 struct bwn_softc *sc = mac->mac_sc;
5046 struct ieee80211com *ic = &sc->sc_ic;
5047 uint32_t cmd, beacon0, beacon1;
5049 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
5050 ic->ic_opmode == IEEE80211_M_MBSS)
5053 mac->mac_intr_mask &= ~BWN_INTR_BEACON;
5055 cmd = BWN_READ_4(mac, BWN_MACCMD);
5056 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID);
5057 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID);
5059 if (beacon0 && beacon1) {
5060 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON);
5061 mac->mac_intr_mask |= BWN_INTR_BEACON;
5065 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) {
5066 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP;
5067 bwn_load_beacon0(mac);
5068 bwn_load_beacon1(mac);
5069 cmd = BWN_READ_4(mac, BWN_MACCMD);
5070 cmd |= BWN_MACCMD_BEACON0_VALID;
5071 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5074 bwn_load_beacon0(mac);
5075 cmd = BWN_READ_4(mac, BWN_MACCMD);
5076 cmd |= BWN_MACCMD_BEACON0_VALID;
5077 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5078 } else if (!beacon1) {
5079 bwn_load_beacon1(mac);
5080 cmd = BWN_READ_4(mac, BWN_MACCMD);
5081 cmd |= BWN_MACCMD_BEACON1_VALID;
5082 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5088 bwn_intr_pmq(struct bwn_mac *mac)
5093 tmp = BWN_READ_4(mac, BWN_PS_STATUS);
5094 if (!(tmp & 0x00000008))
5097 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002);
5101 bwn_intr_noise(struct bwn_mac *mac)
5103 struct bwn_phy_g *pg = &mac->mac_phy.phy_g;
5109 if (mac->mac_phy.type != BWN_PHYTYPE_G)
5112 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__));
5113 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac));
5114 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f ||
5118 KASSERT(mac->mac_noise.noi_nsamples < 8,
5119 ("%s:%d: fail", __func__, __LINE__));
5120 i = mac->mac_noise.noi_nsamples;
5121 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1);
5122 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1);
5123 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1);
5124 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1);
5125 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]];
5126 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]];
5127 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]];
5128 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]];
5129 mac->mac_noise.noi_nsamples++;
5130 if (mac->mac_noise.noi_nsamples == 8) {
5132 for (i = 0; i < 8; i++) {
5133 for (j = 0; j < 4; j++)
5134 average += mac->mac_noise.noi_samples[i][j];
5136 average = (((average / 32) * 125) + 64) / 128;
5137 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f;
5142 average -= (tmp == 8) ? 72 : 48;
5144 mac->mac_stats.link_noise = average;
5145 mac->mac_noise.noi_running = 0;
5149 bwn_noise_gensample(mac);
5153 bwn_pio_rx(struct bwn_pio_rxqueue *prq)
5155 struct bwn_mac *mac = prq->prq_mac;
5156 struct bwn_softc *sc = mac->mac_sc;
5159 BWN_ASSERT_LOCKED(sc);
5161 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
5164 for (i = 0; i < 5000; i++) {
5165 if (bwn_pio_rxeof(prq) == 0)
5169 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n");
5170 return ((i > 0) ? 1 : 0);
5174 bwn_dma_rx(struct bwn_dma_ring *dr)
5178 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5179 curslot = dr->get_curslot(dr);
5180 KASSERT(curslot >= 0 && curslot < dr->dr_numslots,
5181 ("%s:%d: fail", __func__, __LINE__));
5183 slot = dr->dr_curslot;
5184 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot))
5185 bwn_dma_rxeof(dr, &slot);
5187 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
5188 BUS_DMASYNC_PREWRITE);
5190 dr->set_curslot(dr, slot);
5191 dr->dr_curslot = slot;
5195 bwn_intr_txeof(struct bwn_mac *mac)
5197 struct bwn_txstatus stat;
5198 uint32_t stat0, stat1;
5201 BWN_ASSERT_LOCKED(mac->mac_sc);
5204 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0);
5205 if (!(stat0 & 0x00000001))
5207 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1);
5209 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5210 "%s: stat0=0x%08x, stat1=0x%08x\n",
5215 stat.cookie = (stat0 >> 16);
5216 stat.seq = (stat1 & 0x0000ffff);
5217 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16);
5218 tmp = (stat0 & 0x0000ffff);
5219 stat.framecnt = ((tmp & 0xf000) >> 12);
5220 stat.rtscnt = ((tmp & 0x0f00) >> 8);
5221 stat.sreason = ((tmp & 0x001c) >> 2);
5222 stat.pm = (tmp & 0x0080) ? 1 : 0;
5223 stat.im = (tmp & 0x0040) ? 1 : 0;
5224 stat.ampdu = (tmp & 0x0020) ? 1 : 0;
5225 stat.ack = (tmp & 0x0002) ? 1 : 0;
5227 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5228 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, "
5229 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n",
5242 bwn_handle_txeof(mac, &stat);
5247 bwn_hwreset(void *arg, int npending)
5249 struct bwn_mac *mac = arg;
5250 struct bwn_softc *sc = mac->mac_sc;
5256 prev_status = mac->mac_status;
5257 if (prev_status >= BWN_MAC_STATUS_STARTED)
5259 if (prev_status >= BWN_MAC_STATUS_INITED)
5262 if (prev_status >= BWN_MAC_STATUS_INITED) {
5263 error = bwn_core_init(mac);
5267 if (prev_status >= BWN_MAC_STATUS_STARTED)
5268 bwn_core_start(mac);
5271 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error);
5272 sc->sc_curmac = NULL;
5278 bwn_handle_fwpanic(struct bwn_mac *mac)
5280 struct bwn_softc *sc = mac->mac_sc;
5283 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG);
5284 device_printf(sc->sc_dev,"fw panic (%u)\n", reason);
5286 if (reason == BWN_FWPANIC_RESTART)
5287 bwn_restart(mac, "ucode panic");
5291 bwn_load_beacon0(struct bwn_mac *mac)
5294 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5298 bwn_load_beacon1(struct bwn_mac *mac)
5301 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5305 bwn_jssi_read(struct bwn_mac *mac)
5309 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a);
5311 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088);
5317 bwn_noise_gensample(struct bwn_mac *mac)
5319 uint32_t jssi = 0x7f7f7f7f;
5321 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff));
5322 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16);
5323 BWN_WRITE_4(mac, BWN_MACCMD,
5324 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE);
5328 bwn_dma_freeslot(struct bwn_dma_ring *dr)
5330 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5332 return (dr->dr_numslots - dr->dr_usedslot);
5336 bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot)
5338 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5340 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1,
5341 ("%s:%d: fail", __func__, __LINE__));
5342 if (slot == dr->dr_numslots - 1)
5348 bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot)
5350 struct bwn_mac *mac = dr->dr_mac;
5351 struct bwn_softc *sc = mac->mac_sc;
5352 struct bwn_dma *dma = &mac->mac_method.dma;
5353 struct bwn_dmadesc_generic *desc;
5354 struct bwn_dmadesc_meta *meta;
5355 struct bwn_rxhdr4 *rxhdr;
5362 dr->getdesc(dr, *slot, &desc, &meta);
5364 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD);
5367 if (bwn_dma_newbuf(dr, desc, meta, 0)) {
5368 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5372 rxhdr = mtod(m, struct bwn_rxhdr4 *);
5373 len = le16toh(rxhdr->frame_len);
5375 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5378 if (bwn_dma_check_redzone(dr, m)) {
5379 device_printf(sc->sc_dev, "redzone error.\n");
5380 bwn_dma_set_redzone(dr, m);
5381 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5382 BUS_DMASYNC_PREWRITE);
5385 if (len > dr->dr_rx_bufsize) {
5388 dr->getdesc(dr, *slot, &desc, &meta);
5389 bwn_dma_set_redzone(dr, meta->mt_m);
5390 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5391 BUS_DMASYNC_PREWRITE);
5392 *slot = bwn_dma_nextslot(dr, *slot);
5394 tmp -= dr->dr_rx_bufsize;
5398 device_printf(sc->sc_dev, "too small buffer "
5399 "(len %u buffer %u dropped %d)\n",
5400 len, dr->dr_rx_bufsize, cnt);
5404 switch (mac->mac_fw.fw_hdr_format) {
5405 case BWN_FW_HDR_351:
5406 case BWN_FW_HDR_410:
5407 macstat = le32toh(rxhdr->ps4.r351.mac_status);
5409 case BWN_FW_HDR_598:
5410 macstat = le32toh(rxhdr->ps4.r598.mac_status);
5414 if (macstat & BWN_RX_MAC_FCSERR) {
5415 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5416 device_printf(sc->sc_dev, "RX drop\n");
5421 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset;
5422 m_adj(m, dr->dr_frameoffset);
5424 bwn_rxeof(dr->dr_mac, m, rxhdr);
5428 bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status)
5430 struct bwn_softc *sc = mac->mac_sc;
5431 struct bwn_stats *stats = &mac->mac_stats;
5433 BWN_ASSERT_LOCKED(mac->mac_sc);
5436 device_printf(sc->sc_dev, "TODO: STATUS IM\n");
5438 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n");
5439 if (status->rtscnt) {
5440 if (status->rtscnt == 0xf)
5446 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5447 bwn_dma_handle_txeof(mac, status);
5449 bwn_pio_handle_txeof(mac, status);
5452 bwn_phy_txpower_check(mac, 0);
5456 bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
5458 struct bwn_mac *mac = prq->prq_mac;
5459 struct bwn_softc *sc = mac->mac_sc;
5460 struct bwn_rxhdr4 rxhdr;
5462 uint32_t ctl32, macstat, v32;
5463 unsigned int i, padding;
5464 uint16_t ctl16, len, totlen, v16;
5468 memset(&rxhdr, 0, sizeof(rxhdr));
5470 if (prq->prq_rev >= 8) {
5471 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5472 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY))
5474 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5475 BWN_PIO8_RXCTL_FRAMEREADY);
5476 for (i = 0; i < 10; i++) {
5477 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5478 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY)
5483 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5484 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY))
5486 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL,
5487 BWN_PIO_RXCTL_FRAMEREADY);
5488 for (i = 0; i < 10; i++) {
5489 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5490 if (ctl16 & BWN_PIO_RXCTL_DATAREADY)
5495 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
5498 if (prq->prq_rev >= 8)
5499 siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr),
5500 prq->prq_base + BWN_PIO8_RXDATA);
5502 siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr),
5503 prq->prq_base + BWN_PIO_RXDATA);
5504 len = le16toh(rxhdr.frame_len);
5506 device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
5510 device_printf(sc->sc_dev, "%s: len is 0\n", __func__);
5514 switch (mac->mac_fw.fw_hdr_format) {
5515 case BWN_FW_HDR_351:
5516 case BWN_FW_HDR_410:
5517 macstat = le32toh(rxhdr.ps4.r351.mac_status);
5519 case BWN_FW_HDR_598:
5520 macstat = le32toh(rxhdr.ps4.r598.mac_status);
5524 if (macstat & BWN_RX_MAC_FCSERR) {
5525 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5526 device_printf(sc->sc_dev, "%s: FCS error", __func__);
5531 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5532 totlen = len + padding;
5533 KASSERT(totlen <= MCLBYTES, ("too big..\n"));
5534 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5536 device_printf(sc->sc_dev, "%s: out of memory", __func__);
5539 mp = mtod(m, unsigned char *);
5540 if (prq->prq_rev >= 8) {
5541 siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3),
5542 prq->prq_base + BWN_PIO8_RXDATA);
5544 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
5545 data = &(mp[totlen - 1]);
5546 switch (totlen & 3) {
5548 *data = (v32 >> 16);
5558 siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1),
5559 prq->prq_base + BWN_PIO_RXDATA);
5561 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
5562 mp[totlen - 1] = v16;
5566 m->m_len = m->m_pkthdr.len = totlen;
5568 bwn_rxeof(prq->prq_mac, m, &rxhdr);
5572 if (prq->prq_rev >= 8)
5573 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5574 BWN_PIO8_RXCTL_DATAREADY);
5576 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY);
5581 bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc,
5582 struct bwn_dmadesc_meta *meta, int init)
5584 struct bwn_mac *mac = dr->dr_mac;
5585 struct bwn_dma *dma = &mac->mac_method.dma;
5586 struct bwn_rxhdr4 *hdr;
5592 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5597 * If the NIC is up and running, we need to:
5598 * - Clear RX buffer's header.
5599 * - Restore RX descriptor settings.
5606 m->m_len = m->m_pkthdr.len = MCLBYTES;
5608 bwn_dma_set_redzone(dr, m);
5611 * Try to load RX buf into temporary DMA map
5613 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m,
5614 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
5619 * See the comment above
5628 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
5630 meta->mt_paddr = paddr;
5633 * Swap RX buf's DMA map with the loaded temporary one
5635 map = meta->mt_dmap;
5636 meta->mt_dmap = dr->dr_spare_dmap;
5637 dr->dr_spare_dmap = map;
5641 * Clear RX buf header
5643 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *);
5644 bzero(hdr, sizeof(*hdr));
5645 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5646 BUS_DMASYNC_PREWRITE);
5649 * Setup RX buf descriptor
5651 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len -
5652 sizeof(*hdr), 0, 0, 0);
5657 bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
5658 bus_size_t mapsz __unused, int error)
5662 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
5663 *((bus_addr_t *)arg) = seg->ds_addr;
5668 bwn_hwrate2ieeerate(int rate)
5672 case BWN_CCK_RATE_1MB:
5674 case BWN_CCK_RATE_2MB:
5676 case BWN_CCK_RATE_5MB:
5678 case BWN_CCK_RATE_11MB:
5680 case BWN_OFDM_RATE_6MB:
5682 case BWN_OFDM_RATE_9MB:
5684 case BWN_OFDM_RATE_12MB:
5686 case BWN_OFDM_RATE_18MB:
5688 case BWN_OFDM_RATE_24MB:
5690 case BWN_OFDM_RATE_36MB:
5692 case BWN_OFDM_RATE_48MB:
5694 case BWN_OFDM_RATE_54MB:
5703 * Post process the RX provided RSSI.
5705 * Valid for A, B, G, LP PHYs.
5708 bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
5709 int ofdm, int adjust_2053, int adjust_2050)
5711 struct bwn_phy *phy = &mac->mac_phy;
5712 struct bwn_phy_g *gphy = &phy->phy_g;
5715 switch (phy->rf_ver) {
5721 tmp = tmp * 73 / 64;
5727 if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev)
5731 tmp = gphy->pg_nrssi_lt[in_rssi];
5732 tmp = (31 - tmp) * -131 / 128 - 57;
5735 tmp = (31 - tmp) * -149 / 128 - 68;
5737 if (phy->type == BWN_PHYTYPE_G && adjust_2050)
5743 tmp = in_rssi - 256;
5749 tmp = (tmp - 11) * 103 / 64;
5760 bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr)
5762 const struct bwn_rxhdr4 *rxhdr = _rxhdr;
5763 struct bwn_plcp6 *plcp;
5764 struct bwn_softc *sc = mac->mac_sc;
5765 struct ieee80211_frame_min *wh;
5766 struct ieee80211_node *ni;
5767 struct ieee80211com *ic = &sc->sc_ic;
5769 int padding, rate, rssi = 0, noise = 0, type;
5770 uint16_t phytype, phystat0, phystat3, chanstat;
5771 unsigned char *mp = mtod(m, unsigned char *);
5772 static int rx_mac_dec_rpt = 0;
5774 BWN_ASSERT_LOCKED(sc);
5776 phystat0 = le16toh(rxhdr->phy_status0);
5779 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only
5782 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3);
5784 switch (mac->mac_fw.fw_hdr_format) {
5785 case BWN_FW_HDR_351:
5786 case BWN_FW_HDR_410:
5787 macstat = le32toh(rxhdr->ps4.r351.mac_status);
5788 chanstat = le16toh(rxhdr->ps4.r351.channel);
5790 case BWN_FW_HDR_598:
5791 macstat = le32toh(rxhdr->ps4.r598.mac_status);
5792 chanstat = le16toh(rxhdr->ps4.r598.channel);
5797 phytype = chanstat & BWN_RX_CHAN_PHYTYPE;
5799 if (macstat & BWN_RX_MAC_FCSERR)
5800 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n");
5801 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV))
5802 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n");
5803 if (macstat & BWN_RX_MAC_DECERR)
5806 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5807 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) {
5808 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
5812 plcp = (struct bwn_plcp6 *)(mp + padding);
5813 m_adj(m, sizeof(struct bwn_plcp6) + padding);
5814 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) {
5815 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
5819 wh = mtod(m, struct ieee80211_frame_min *);
5821 if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50)
5822 device_printf(sc->sc_dev,
5823 "RX decryption attempted (old %d keyidx %#x)\n",
5825 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT);
5827 if (phystat0 & BWN_RX_PHYST0_OFDM)
5828 rate = bwn_plcp_get_ofdmrate(mac, plcp,
5829 phytype == BWN_PHYTYPE_A);
5831 rate = bwn_plcp_get_cckrate(mac, plcp);
5833 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP))
5836 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate);
5843 case BWN_PHYTYPE_LP:
5844 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi,
5845 !! (phystat0 & BWN_RX_PHYST0_OFDM),
5846 !! (phystat0 & BWN_RX_PHYST0_GAINCTL),
5847 !! (phystat3 & BWN_RX_PHYST3_TRSTATE));
5850 /* Broadcom has code for min/avg, but always used max */
5851 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32)
5852 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2);
5854 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1);
5856 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV,
5857 "%s: power0=%d, power1=%d, power2=%d\n",
5859 rxhdr->phy.n.power0,
5860 rxhdr->phy.n.power1,
5861 rxhdr->ps2.n.power2);
5865 /* XXX TODO: implement rssi for other PHYs */
5870 * RSSI here is absolute, not relative to the noise floor.
5872 noise = mac->mac_stats.link_noise;
5873 rssi = rssi - noise;
5876 if (ieee80211_radiotap_active(ic))
5877 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise);
5878 m_adj(m, -IEEE80211_CRC_LEN);
5882 ni = ieee80211_find_rxnode(ic, wh);
5884 type = ieee80211_input(ni, m, rssi, noise);
5885 ieee80211_free_node(ni);
5887 type = ieee80211_input_all(ic, m, rssi, noise);
5892 device_printf(sc->sc_dev, "%s: dropped\n", __func__);
5896 bwn_ratectl_tx_complete(const struct ieee80211_node *ni,
5897 const struct bwn_txstatus *status)
5899 struct ieee80211_ratectl_tx_status txs;
5903 * If we don't get an ACK, then we should log the
5904 * full framecnt. That may be 0 if it's a PHY
5905 * failure, so ensure that gets logged as some
5908 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
5910 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
5911 retrycnt = status->framecnt - 1;
5913 txs.status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
5914 retrycnt = status->framecnt;
5918 txs.long_retries = retrycnt;
5919 ieee80211_ratectl_tx_complete(ni, &txs);
5923 bwn_dma_handle_txeof(struct bwn_mac *mac,
5924 const struct bwn_txstatus *status)
5926 struct bwn_dma *dma = &mac->mac_method.dma;
5927 struct bwn_dma_ring *dr;
5928 struct bwn_dmadesc_generic *desc;
5929 struct bwn_dmadesc_meta *meta;
5930 struct bwn_softc *sc = mac->mac_sc;
5933 BWN_ASSERT_LOCKED(sc);
5935 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot);
5937 device_printf(sc->sc_dev, "failed to parse cookie\n");
5940 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5943 KASSERT(slot >= 0 && slot < dr->dr_numslots,
5944 ("%s:%d: fail", __func__, __LINE__));
5945 dr->getdesc(dr, slot, &desc, &meta);
5947 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
5948 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap);
5949 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
5950 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap);
5952 if (meta->mt_islast) {
5953 KASSERT(meta->mt_m != NULL,
5954 ("%s:%d: fail", __func__, __LINE__));
5956 bwn_ratectl_tx_complete(meta->mt_ni, status);
5957 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0);
5961 KASSERT(meta->mt_m == NULL,
5962 ("%s:%d: fail", __func__, __LINE__));
5965 if (meta->mt_islast)
5967 slot = bwn_dma_nextslot(dr, slot);
5969 sc->sc_watchdog_timer = 0;
5971 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME,
5972 ("%s:%d: fail", __func__, __LINE__));
5978 bwn_pio_handle_txeof(struct bwn_mac *mac,
5979 const struct bwn_txstatus *status)
5981 struct bwn_pio_txqueue *tq;
5982 struct bwn_pio_txpkt *tp = NULL;
5983 struct bwn_softc *sc = mac->mac_sc;
5985 BWN_ASSERT_LOCKED(sc);
5987 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp);
5991 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
5994 /* XXX ieee80211_tx_complete()? */
5995 if (tp->tp_ni != NULL) {
5997 * Do any tx complete callback. Note this must
5998 * be done before releasing the node reference.
6001 bwn_ratectl_tx_complete(tp->tp_ni, status);
6002 if (tp->tp_m->m_flags & M_TXCB)
6003 ieee80211_process_callback(tp->tp_ni, tp->tp_m, 0);
6004 ieee80211_free_node(tp->tp_ni);
6009 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
6011 sc->sc_watchdog_timer = 0;
6015 bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
6017 struct bwn_softc *sc = mac->mac_sc;
6018 struct bwn_phy *phy = &mac->mac_phy;
6019 struct ieee80211com *ic = &sc->sc_ic;
6021 bwn_txpwr_result_t result;
6025 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime))
6027 phy->nexttime = now + 2 * 1000;
6029 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM &&
6030 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306)
6033 if (phy->recalc_txpwr != NULL) {
6034 result = phy->recalc_txpwr(mac,
6035 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
6036 if (result == BWN_TXPWR_RES_DONE)
6038 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,
6039 ("%s: fail", __func__));
6040 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__));
6042 ieee80211_runtask(ic, &mac->mac_txpower);
6047 bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset)
6050 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset));
6054 bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset)
6057 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset));
6061 bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value)
6064 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value);
6068 bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value)
6071 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value);
6075 bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate)
6079 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
6081 return (BWN_OFDM_RATE_6MB);
6083 return (BWN_OFDM_RATE_9MB);
6085 return (BWN_OFDM_RATE_12MB);
6087 return (BWN_OFDM_RATE_18MB);
6089 return (BWN_OFDM_RATE_24MB);
6091 return (BWN_OFDM_RATE_36MB);
6093 return (BWN_OFDM_RATE_48MB);
6095 return (BWN_OFDM_RATE_54MB);
6096 /* CCK rates (NB: not IEEE std, device-specific) */
6098 return (BWN_CCK_RATE_1MB);
6100 return (BWN_CCK_RATE_2MB);
6102 return (BWN_CCK_RATE_5MB);
6104 return (BWN_CCK_RATE_11MB);
6107 device_printf(sc->sc_dev, "unsupported rate %d\n", rate);
6108 return (BWN_CCK_RATE_1MB);
6112 bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate)
6114 struct bwn_phy *phy = &mac->mac_phy;
6115 uint16_t control = 0;
6118 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */
6119 bw = BWN_TXH_PHY1_BW_20;
6121 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) {
6125 /* Figure out coding rate and modulation */
6126 /* XXX TODO: table-ize, for MCS transmit */
6127 /* Note: this is BWN_*_RATE values */
6129 case BWN_CCK_RATE_1MB:
6132 case BWN_CCK_RATE_2MB:
6135 case BWN_CCK_RATE_5MB:
6138 case BWN_CCK_RATE_11MB:
6141 case BWN_OFDM_RATE_6MB:
6142 control |= BWN_TXH_PHY1_CRATE_1_2;
6143 control |= BWN_TXH_PHY1_MODUL_BPSK;
6145 case BWN_OFDM_RATE_9MB:
6146 control |= BWN_TXH_PHY1_CRATE_3_4;
6147 control |= BWN_TXH_PHY1_MODUL_BPSK;
6149 case BWN_OFDM_RATE_12MB:
6150 control |= BWN_TXH_PHY1_CRATE_1_2;
6151 control |= BWN_TXH_PHY1_MODUL_QPSK;
6153 case BWN_OFDM_RATE_18MB:
6154 control |= BWN_TXH_PHY1_CRATE_3_4;
6155 control |= BWN_TXH_PHY1_MODUL_QPSK;
6157 case BWN_OFDM_RATE_24MB:
6158 control |= BWN_TXH_PHY1_CRATE_1_2;
6159 control |= BWN_TXH_PHY1_MODUL_QAM16;
6161 case BWN_OFDM_RATE_36MB:
6162 control |= BWN_TXH_PHY1_CRATE_3_4;
6163 control |= BWN_TXH_PHY1_MODUL_QAM16;
6165 case BWN_OFDM_RATE_48MB:
6166 control |= BWN_TXH_PHY1_CRATE_1_2;
6167 control |= BWN_TXH_PHY1_MODUL_QAM64;
6169 case BWN_OFDM_RATE_54MB:
6170 control |= BWN_TXH_PHY1_CRATE_3_4;
6171 control |= BWN_TXH_PHY1_MODUL_QAM64;
6176 control |= BWN_TXH_PHY1_MODE_SISO;
6183 bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni,
6184 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie)
6186 const struct bwn_phy *phy = &mac->mac_phy;
6187 struct bwn_softc *sc = mac->mac_sc;
6188 struct ieee80211_frame *wh;
6189 struct ieee80211_frame *protwh;
6190 struct ieee80211_frame_cts *cts;
6191 struct ieee80211_frame_rts *rts;
6192 const struct ieee80211_txparam *tp = ni->ni_txparms;
6193 struct ieee80211vap *vap = ni->ni_vap;
6194 struct ieee80211com *ic = &sc->sc_ic;
6197 uint32_t macctl = 0;
6198 int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type;
6199 uint16_t phyctl = 0;
6200 uint8_t rate, rate_fb;
6201 int fill_phy_ctl1 = 0;
6203 wh = mtod(m, struct ieee80211_frame *);
6204 memset(txhdr, 0, sizeof(*txhdr));
6206 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
6207 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6208 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
6210 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP)
6211 || (phy->type == BWN_PHYTYPE_HT))
6217 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL))
6218 rate = rate_fb = tp->mgmtrate;
6220 rate = rate_fb = tp->mcastrate;
6221 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
6222 rate = rate_fb = tp->ucastrate;
6224 rix = ieee80211_ratectl_rate(ni, NULL, 0);
6225 rate = ni->ni_txrate;
6228 rate_fb = ni->ni_rates.rs_rates[rix - 1] &
6234 sc->sc_tx_rate = rate;
6236 /* Note: this maps the select ieee80211 rate to hardware rate */
6237 rate = bwn_ieeerate2hwrate(sc, rate);
6238 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb);
6240 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) :
6241 bwn_plcp_getcck(rate);
6242 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc));
6243 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN);
6245 /* XXX rate/rate_fb is the hardware rate */
6246 if ((rate_fb == rate) ||
6247 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) ||
6248 (*(u_int16_t *)wh->i_dur == htole16(0)))
6249 txhdr->dur_fb = *(u_int16_t *)wh->i_dur;
6251 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt,
6252 m->m_pkthdr.len, rate, isshort);
6254 /* XXX TX encryption */
6256 switch (mac->mac_fw.fw_hdr_format) {
6257 case BWN_FW_HDR_351:
6258 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp),
6259 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6261 case BWN_FW_HDR_410:
6262 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp),
6263 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6265 case BWN_FW_HDR_598:
6266 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp),
6267 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6271 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb),
6272 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb);
6274 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM :
6276 txhdr->chan = phy->chan;
6277 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM :
6279 /* XXX preamble? obey net80211 */
6280 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6281 rate == BWN_CCK_RATE_11MB))
6282 phyctl |= BWN_TX_PHY_SHORTPRMBL;
6285 macctl |= BWN_TX_MAC_5GHZ;
6287 /* XXX TX antenna selection */
6289 switch (bwn_antenna_sanitize(mac, 0)) {
6291 phyctl |= BWN_TX_PHY_ANT01AUTO;
6294 phyctl |= BWN_TX_PHY_ANT0;
6297 phyctl |= BWN_TX_PHY_ANT1;
6300 phyctl |= BWN_TX_PHY_ANT2;
6303 phyctl |= BWN_TX_PHY_ANT3;
6306 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6310 macctl |= BWN_TX_MAC_ACK;
6312 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU);
6313 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
6314 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
6315 macctl |= BWN_TX_MAC_LONGFRAME;
6317 if (ic->ic_flags & IEEE80211_F_USEPROT) {
6318 /* Note: don't fall back to CCK rates for 5G */
6320 rts_rate = BWN_CCK_RATE_1MB;
6322 rts_rate = BWN_OFDM_RATE_6MB;
6323 rts_rate_fb = bwn_get_fbrate(rts_rate);
6325 /* XXX 'rate' here is hardware rate now, not the net80211 rate */
6326 protdur = ieee80211_compute_duration(ic->ic_rt,
6327 m->m_pkthdr.len, rate, isshort) +
6328 + ieee80211_ack_duration(ic->ic_rt, rate, isshort);
6330 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
6332 switch (mac->mac_fw.fw_hdr_format) {
6333 case BWN_FW_HDR_351:
6334 cts = (struct ieee80211_frame_cts *)
6335 txhdr->body.r351.rts_frame;
6337 case BWN_FW_HDR_410:
6338 cts = (struct ieee80211_frame_cts *)
6339 txhdr->body.r410.rts_frame;
6341 case BWN_FW_HDR_598:
6342 cts = (struct ieee80211_frame_cts *)
6343 txhdr->body.r598.rts_frame;
6347 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr,
6349 KASSERT(mprot != NULL, ("failed to alloc mbuf\n"));
6350 bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts,
6351 mprot->m_pkthdr.len);
6353 macctl |= BWN_TX_MAC_SEND_CTSTOSELF;
6354 len = sizeof(struct ieee80211_frame_cts);
6356 switch (mac->mac_fw.fw_hdr_format) {
6357 case BWN_FW_HDR_351:
6358 rts = (struct ieee80211_frame_rts *)
6359 txhdr->body.r351.rts_frame;
6361 case BWN_FW_HDR_410:
6362 rts = (struct ieee80211_frame_rts *)
6363 txhdr->body.r410.rts_frame;
6365 case BWN_FW_HDR_598:
6366 rts = (struct ieee80211_frame_rts *)
6367 txhdr->body.r598.rts_frame;
6371 /* XXX rate/rate_fb is the hardware rate */
6372 protdur += ieee80211_ack_duration(ic->ic_rt, rate,
6374 mprot = ieee80211_alloc_rts(ic, wh->i_addr1,
6375 wh->i_addr2, protdur);
6376 KASSERT(mprot != NULL, ("failed to alloc mbuf\n"));
6377 bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts,
6378 mprot->m_pkthdr.len);
6380 macctl |= BWN_TX_MAC_SEND_RTSCTS;
6381 len = sizeof(struct ieee80211_frame_rts);
6383 len += IEEE80211_CRC_LEN;
6385 switch (mac->mac_fw.fw_hdr_format) {
6386 case BWN_FW_HDR_351:
6387 bwn_plcp_genhdr((struct bwn_plcp4 *)
6388 &txhdr->body.r351.rts_plcp, len, rts_rate);
6390 case BWN_FW_HDR_410:
6391 bwn_plcp_genhdr((struct bwn_plcp4 *)
6392 &txhdr->body.r410.rts_plcp, len, rts_rate);
6394 case BWN_FW_HDR_598:
6395 bwn_plcp_genhdr((struct bwn_plcp4 *)
6396 &txhdr->body.r598.rts_plcp, len, rts_rate);
6400 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len,
6403 switch (mac->mac_fw.fw_hdr_format) {
6404 case BWN_FW_HDR_351:
6405 protwh = (struct ieee80211_frame *)
6406 &txhdr->body.r351.rts_frame;
6408 case BWN_FW_HDR_410:
6409 protwh = (struct ieee80211_frame *)
6410 &txhdr->body.r410.rts_frame;
6412 case BWN_FW_HDR_598:
6413 protwh = (struct ieee80211_frame *)
6414 &txhdr->body.r598.rts_frame;
6418 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur;
6420 if (BWN_ISOFDMRATE(rts_rate)) {
6421 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM;
6422 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate);
6424 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK;
6425 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate);
6427 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ?
6428 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK;
6430 if (fill_phy_ctl1) {
6431 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate));
6432 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb));
6436 if (fill_phy_ctl1) {
6437 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate));
6438 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb));
6441 switch (mac->mac_fw.fw_hdr_format) {
6442 case BWN_FW_HDR_351:
6443 txhdr->body.r351.cookie = htole16(cookie);
6445 case BWN_FW_HDR_410:
6446 txhdr->body.r410.cookie = htole16(cookie);
6448 case BWN_FW_HDR_598:
6449 txhdr->body.r598.cookie = htole16(cookie);
6453 txhdr->macctl = htole32(macctl);
6454 txhdr->phyctl = htole16(phyctl);
6459 if (ieee80211_radiotap_active_vap(vap)) {
6460 sc->sc_tx_th.wt_flags = 0;
6461 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6462 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6464 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6465 rate == BWN_CCK_RATE_11MB))
6466 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6467 sc->sc_tx_th.wt_rate = rate;
6469 ieee80211_radiotap_tx(vap, m);
6476 bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets,
6480 uint8_t *raw = plcp->o.raw;
6482 if (BWN_ISOFDMRATE(rate)) {
6483 d = bwn_plcp_getofdm(rate);
6484 KASSERT(!(octets & 0xf000),
6485 ("%s:%d: fail", __func__, __LINE__));
6487 plcp->o.data = htole32(d);
6489 plen = octets * 16 / rate;
6490 if ((octets * 16 % rate) > 0) {
6492 if ((rate == BWN_CCK_RATE_11MB)
6493 && ((octets * 8 % 11) < 4)) {
6499 plcp->o.data |= htole32(plen << 16);
6500 raw[0] = bwn_plcp_getcck(rate);
6505 bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
6507 struct bwn_softc *sc = mac->mac_sc;
6512 if (mac->mac_phy.gmode)
6513 mask = siba_sprom_get_ant_bg(sc->sc_dev);
6515 mask = siba_sprom_get_ant_a(sc->sc_dev);
6516 if (!(mask & (1 << (n - 1))))
6522 * Return a fallback rate for the given rate.
6524 * Note: Don't fall back from OFDM to CCK.
6527 bwn_get_fbrate(uint8_t bitrate)
6531 case BWN_CCK_RATE_1MB:
6532 return (BWN_CCK_RATE_1MB);
6533 case BWN_CCK_RATE_2MB:
6534 return (BWN_CCK_RATE_1MB);
6535 case BWN_CCK_RATE_5MB:
6536 return (BWN_CCK_RATE_2MB);
6537 case BWN_CCK_RATE_11MB:
6538 return (BWN_CCK_RATE_5MB);
6541 case BWN_OFDM_RATE_6MB:
6542 return (BWN_OFDM_RATE_6MB);
6543 case BWN_OFDM_RATE_9MB:
6544 return (BWN_OFDM_RATE_6MB);
6545 case BWN_OFDM_RATE_12MB:
6546 return (BWN_OFDM_RATE_9MB);
6547 case BWN_OFDM_RATE_18MB:
6548 return (BWN_OFDM_RATE_12MB);
6549 case BWN_OFDM_RATE_24MB:
6550 return (BWN_OFDM_RATE_18MB);
6551 case BWN_OFDM_RATE_36MB:
6552 return (BWN_OFDM_RATE_24MB);
6553 case BWN_OFDM_RATE_48MB:
6554 return (BWN_OFDM_RATE_36MB);
6555 case BWN_OFDM_RATE_54MB:
6556 return (BWN_OFDM_RATE_48MB);
6558 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6563 bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6564 uint32_t ctl, const void *_data, int len)
6566 struct bwn_softc *sc = mac->mac_sc;
6568 const uint8_t *data = _data;
6570 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
6571 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
6572 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6574 siba_write_multi_4(sc->sc_dev, data, (len & ~3),
6575 tq->tq_base + BWN_PIO8_TXDATA);
6577 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
6578 BWN_PIO8_TXCTL_24_31);
6579 data = &(data[len - 1]);
6582 ctl |= BWN_PIO8_TXCTL_16_23;
6583 value |= (uint32_t)(*data) << 16;
6586 ctl |= BWN_PIO8_TXCTL_8_15;
6587 value |= (uint32_t)(*data) << 8;
6590 value |= (uint32_t)(*data);
6592 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6593 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value);
6600 bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6601 uint16_t offset, uint32_t value)
6604 BWN_WRITE_4(mac, tq->tq_base + offset, value);
6608 bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6609 uint16_t ctl, const void *_data, int len)
6611 struct bwn_softc *sc = mac->mac_sc;
6612 const uint8_t *data = _data;
6614 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6615 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6617 siba_write_multi_2(sc->sc_dev, data, (len & ~1),
6618 tq->tq_base + BWN_PIO_TXDATA);
6620 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6621 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6622 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
6629 bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6630 uint16_t ctl, struct mbuf *m0)
6635 struct mbuf *m = m0;
6637 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6638 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6640 for (; m != NULL; m = m->m_next) {
6641 buf = mtod(m, const uint8_t *);
6642 for (i = 0; i < m->m_len; i++) {
6646 data |= (buf[i] << 8);
6647 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6652 if (m0->m_pkthdr.len % 2) {
6653 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6654 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6655 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6662 bwn_set_slot_time(struct bwn_mac *mac, uint16_t time)
6665 /* XXX should exit if 5GHz band .. */
6666 if (mac->mac_phy.type != BWN_PHYTYPE_G)
6669 BWN_WRITE_2(mac, 0x684, 510 + time);
6670 /* Disabled in Linux b43, can adversely effect performance */
6672 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time);
6676 static struct bwn_dma_ring *
6677 bwn_dma_select(struct bwn_mac *mac, uint8_t prio)
6680 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
6681 return (mac->mac_method.dma.wme[WME_AC_BE]);
6685 return (mac->mac_method.dma.wme[WME_AC_VO]);
6687 return (mac->mac_method.dma.wme[WME_AC_VI]);
6689 return (mac->mac_method.dma.wme[WME_AC_BE]);
6691 return (mac->mac_method.dma.wme[WME_AC_BK]);
6693 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6698 bwn_dma_getslot(struct bwn_dma_ring *dr)
6702 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
6704 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6705 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__));
6706 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__));
6708 slot = bwn_dma_nextslot(dr, dr->dr_curslot);
6709 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__));
6710 dr->dr_curslot = slot;
6716 static struct bwn_pio_txqueue *
6717 bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie,
6718 struct bwn_pio_txpkt **pack)
6720 struct bwn_pio *pio = &mac->mac_method.pio;
6721 struct bwn_pio_txqueue *tq = NULL;
6724 switch (cookie & 0xf000) {
6726 tq = &pio->wme[WME_AC_BK];
6729 tq = &pio->wme[WME_AC_BE];
6732 tq = &pio->wme[WME_AC_VI];
6735 tq = &pio->wme[WME_AC_VO];
6741 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__));
6744 index = (cookie & 0x0fff);
6745 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__));
6746 if (index >= N(tq->tq_pkts))
6748 *pack = &tq->tq_pkts[index];
6749 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__));
6754 bwn_txpwr(void *arg, int npending)
6756 struct bwn_mac *mac = arg;
6757 struct bwn_softc *sc;
6765 if (mac->mac_status >= BWN_MAC_STATUS_STARTED &&
6766 mac->mac_phy.set_txpwr != NULL)
6767 mac->mac_phy.set_txpwr(mac);
6772 bwn_task_15s(struct bwn_mac *mac)
6776 if (mac->mac_fw.opensource) {
6777 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);
6779 bwn_restart(mac, "fw watchdog");
6782 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1);
6784 if (mac->mac_phy.task_15s)
6785 mac->mac_phy.task_15s(mac);
6787 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
6791 bwn_task_30s(struct bwn_mac *mac)
6794 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running)
6796 mac->mac_noise.noi_running = 1;
6797 mac->mac_noise.noi_nsamples = 0;
6799 bwn_noise_gensample(mac);
6803 bwn_task_60s(struct bwn_mac *mac)
6806 if (mac->mac_phy.task_60s)
6807 mac->mac_phy.task_60s(mac);
6808 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME);
6812 bwn_tasks(void *arg)
6814 struct bwn_mac *mac = arg;
6815 struct bwn_softc *sc = mac->mac_sc;
6817 BWN_ASSERT_LOCKED(sc);
6818 if (mac->mac_status != BWN_MAC_STATUS_STARTED)
6821 if (mac->mac_task_state % 4 == 0)
6823 if (mac->mac_task_state % 2 == 0)
6827 mac->mac_task_state++;
6828 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
6832 bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a)
6834 struct bwn_softc *sc = mac->mac_sc;
6836 KASSERT(a == 0, ("not support APHY\n"));
6838 switch (plcp->o.raw[0] & 0xf) {
6840 return (BWN_OFDM_RATE_6MB);
6842 return (BWN_OFDM_RATE_9MB);
6844 return (BWN_OFDM_RATE_12MB);
6846 return (BWN_OFDM_RATE_18MB);
6848 return (BWN_OFDM_RATE_24MB);
6850 return (BWN_OFDM_RATE_36MB);
6852 return (BWN_OFDM_RATE_48MB);
6854 return (BWN_OFDM_RATE_54MB);
6856 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n",
6857 plcp->o.raw[0] & 0xf);
6862 bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp)
6864 struct bwn_softc *sc = mac->mac_sc;
6866 switch (plcp->o.raw[0]) {
6868 return (BWN_CCK_RATE_1MB);
6870 return (BWN_CCK_RATE_2MB);
6872 return (BWN_CCK_RATE_5MB);
6874 return (BWN_CCK_RATE_11MB);
6876 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]);
6881 bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m,
6882 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate,
6883 int rssi, int noise)
6885 struct bwn_softc *sc = mac->mac_sc;
6886 const struct ieee80211_frame_min *wh;
6888 uint16_t low_mactime_now;
6891 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL)
6892 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6894 wh = mtod(m, const struct ieee80211_frame_min *);
6895 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6896 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
6898 bwn_tsf_read(mac, &tsf);
6899 low_mactime_now = tsf;
6900 tsf = tsf & ~0xffffULL;
6902 switch (mac->mac_fw.fw_hdr_format) {
6903 case BWN_FW_HDR_351:
6904 case BWN_FW_HDR_410:
6905 mt = le16toh(rxhdr->ps4.r351.mac_time);
6907 case BWN_FW_HDR_598:
6908 mt = le16toh(rxhdr->ps4.r598.mac_time);
6913 if (low_mactime_now < mt)
6916 sc->sc_rx_th.wr_tsf = tsf;
6917 sc->sc_rx_th.wr_rate = rate;
6918 sc->sc_rx_th.wr_antsignal = rssi;
6919 sc->sc_rx_th.wr_antnoise = noise;
6923 bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
6927 KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3,
6928 ("%s:%d: fail", __func__, __LINE__));
6930 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
6931 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
6938 bwn_dma_attach(struct bwn_mac *mac)
6940 struct bwn_dma *dma = &mac->mac_method.dma;
6941 struct bwn_softc *sc = mac->mac_sc;
6942 bus_addr_t lowaddr = 0;
6945 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0)
6948 KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__));
6950 mac->mac_flags |= BWN_MAC_FLAG_DMA;
6952 dma->dmatype = bwn_dma_gettype(mac);
6953 if (dma->dmatype == BWN_DMA_30BIT)
6954 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT;
6955 else if (dma->dmatype == BWN_DMA_32BIT)
6956 lowaddr = BUS_SPACE_MAXADDR_32BIT;
6958 lowaddr = BUS_SPACE_MAXADDR;
6961 * Create top level DMA tag
6963 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
6964 BWN_ALIGN, 0, /* alignment, bounds */
6965 lowaddr, /* lowaddr */
6966 BUS_SPACE_MAXADDR, /* highaddr */
6967 NULL, NULL, /* filter, filterarg */
6968 BUS_SPACE_MAXSIZE, /* maxsize */
6969 BUS_SPACE_UNRESTRICTED, /* nsegments */
6970 BUS_SPACE_MAXSIZE, /* maxsegsize */
6972 NULL, NULL, /* lockfunc, lockarg */
6975 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
6980 * Create TX/RX mbuf DMA tag
6982 error = bus_dma_tag_create(dma->parent_dtag,
6990 BUS_SPACE_MAXSIZE_32BIT,
6995 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
6998 error = bus_dma_tag_create(dma->parent_dtag,
7006 BUS_SPACE_MAXSIZE_32BIT,
7011 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7015 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype);
7016 if (!dma->wme[WME_AC_BK])
7019 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype);
7020 if (!dma->wme[WME_AC_BE])
7023 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype);
7024 if (!dma->wme[WME_AC_VI])
7027 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype);
7028 if (!dma->wme[WME_AC_VO])
7031 dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype);
7034 dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype);
7040 fail7: bwn_dma_ringfree(&dma->mcast);
7041 fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
7042 fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
7043 fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
7044 fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
7045 fail2: bus_dma_tag_destroy(dma->txbuf_dtag);
7046 fail1: bus_dma_tag_destroy(dma->rxbuf_dtag);
7047 fail0: bus_dma_tag_destroy(dma->parent_dtag);
7051 static struct bwn_dma_ring *
7052 bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status,
7053 uint16_t cookie, int *slot)
7055 struct bwn_dma *dma = &mac->mac_method.dma;
7056 struct bwn_dma_ring *dr;
7057 struct bwn_softc *sc = mac->mac_sc;
7059 BWN_ASSERT_LOCKED(mac->mac_sc);
7061 switch (cookie & 0xf000) {
7063 dr = dma->wme[WME_AC_BK];
7066 dr = dma->wme[WME_AC_BE];
7069 dr = dma->wme[WME_AC_VI];
7072 dr = dma->wme[WME_AC_VO];
7080 ("invalid cookie value %d", cookie & 0xf000));
7082 *slot = (cookie & 0x0fff);
7083 if (*slot < 0 || *slot >= dr->dr_numslots) {
7085 * XXX FIXME: sometimes H/W returns TX DONE events duplicately
7086 * that it occurs events which have same H/W sequence numbers.
7087 * When it's occurred just prints a WARNING msgs and ignores.
7089 KASSERT(status->seq == dma->lastseq,
7090 ("%s:%d: fail", __func__, __LINE__));
7091 device_printf(sc->sc_dev,
7092 "out of slot ranges (0 < %d < %d)\n", *slot,
7096 dma->lastseq = status->seq;
7101 bwn_dma_stop(struct bwn_mac *mac)
7103 struct bwn_dma *dma;
7105 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
7107 dma = &mac->mac_method.dma;
7109 bwn_dma_ringstop(&dma->rx);
7110 bwn_dma_ringstop(&dma->wme[WME_AC_BK]);
7111 bwn_dma_ringstop(&dma->wme[WME_AC_BE]);
7112 bwn_dma_ringstop(&dma->wme[WME_AC_VI]);
7113 bwn_dma_ringstop(&dma->wme[WME_AC_VO]);
7114 bwn_dma_ringstop(&dma->mcast);
7118 bwn_dma_ringstop(struct bwn_dma_ring **dr)
7124 bwn_dma_cleanup(*dr);
7128 bwn_pio_stop(struct bwn_mac *mac)
7130 struct bwn_pio *pio;
7132 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
7134 pio = &mac->mac_method.pio;
7136 bwn_destroy_queue_tx(&pio->mcast);
7137 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]);
7138 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]);
7139 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
7140 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
7144 bwn_led_attach(struct bwn_mac *mac)
7146 struct bwn_softc *sc = mac->mac_sc;
7147 const uint8_t *led_act = NULL;
7148 uint16_t val[BWN_LED_MAX];
7151 sc->sc_led_idle = (2350 * hz) / 1000;
7152 sc->sc_led_blink = 1;
7154 for (i = 0; i < N(bwn_vendor_led_act); ++i) {
7155 if (siba_get_pci_subvendor(sc->sc_dev) ==
7156 bwn_vendor_led_act[i].vid) {
7157 led_act = bwn_vendor_led_act[i].led_act;
7161 if (led_act == NULL)
7162 led_act = bwn_default_led_act;
7164 val[0] = siba_sprom_get_gpio0(sc->sc_dev);
7165 val[1] = siba_sprom_get_gpio1(sc->sc_dev);
7166 val[2] = siba_sprom_get_gpio2(sc->sc_dev);
7167 val[3] = siba_sprom_get_gpio3(sc->sc_dev);
7169 for (i = 0; i < BWN_LED_MAX; ++i) {
7170 struct bwn_led *led = &sc->sc_leds[i];
7172 if (val[i] == 0xff) {
7173 led->led_act = led_act[i];
7175 if (val[i] & BWN_LED_ACT_LOW)
7176 led->led_flags |= BWN_LED_F_ACTLOW;
7177 led->led_act = val[i] & BWN_LED_ACT_MASK;
7179 led->led_mask = (1 << i);
7181 if (led->led_act == BWN_LED_ACT_BLINK_SLOW ||
7182 led->led_act == BWN_LED_ACT_BLINK_POLL ||
7183 led->led_act == BWN_LED_ACT_BLINK) {
7184 led->led_flags |= BWN_LED_F_BLINK;
7185 if (led->led_act == BWN_LED_ACT_BLINK_POLL)
7186 led->led_flags |= BWN_LED_F_POLLABLE;
7187 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW)
7188 led->led_flags |= BWN_LED_F_SLOW;
7190 if (sc->sc_blink_led == NULL) {
7191 sc->sc_blink_led = led;
7192 if (led->led_flags & BWN_LED_F_SLOW)
7193 BWN_LED_SLOWDOWN(sc->sc_led_idle);
7197 DPRINTF(sc, BWN_DEBUG_LED,
7198 "%dth led, act %d, lowact %d\n", i,
7199 led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
7201 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
7204 static __inline uint16_t
7205 bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on)
7208 if (led->led_flags & BWN_LED_F_ACTLOW)
7211 val |= led->led_mask;
7213 val &= ~led->led_mask;
7218 bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate)
7220 struct bwn_softc *sc = mac->mac_sc;
7221 struct ieee80211com *ic = &sc->sc_ic;
7225 if (nstate == IEEE80211_S_INIT) {
7226 callout_stop(&sc->sc_led_blink_ch);
7227 sc->sc_led_blinking = 0;
7230 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0)
7233 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7234 for (i = 0; i < BWN_LED_MAX; ++i) {
7235 struct bwn_led *led = &sc->sc_leds[i];
7238 if (led->led_act == BWN_LED_ACT_UNKN ||
7239 led->led_act == BWN_LED_ACT_NULL)
7242 if ((led->led_flags & BWN_LED_F_BLINK) &&
7243 nstate != IEEE80211_S_INIT)
7246 switch (led->led_act) {
7247 case BWN_LED_ACT_ON: /* Always on */
7250 case BWN_LED_ACT_OFF: /* Always off */
7251 case BWN_LED_ACT_5GHZ: /* TODO: 11A */
7257 case IEEE80211_S_INIT:
7260 case IEEE80211_S_RUN:
7261 if (led->led_act == BWN_LED_ACT_11G &&
7262 ic->ic_curmode != IEEE80211_MODE_11G)
7266 if (led->led_act == BWN_LED_ACT_ASSOC)
7273 val = bwn_led_onoff(led, val, on);
7275 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7279 bwn_led_event(struct bwn_mac *mac, int event)
7281 struct bwn_softc *sc = mac->mac_sc;
7282 struct bwn_led *led = sc->sc_blink_led;
7285 if (event == BWN_LED_EVENT_POLL) {
7286 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
7288 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
7292 sc->sc_led_ticks = ticks;
7293 if (sc->sc_led_blinking)
7297 case BWN_LED_EVENT_RX:
7298 rate = sc->sc_rx_rate;
7300 case BWN_LED_EVENT_TX:
7301 rate = sc->sc_tx_rate;
7303 case BWN_LED_EVENT_POLL:
7307 panic("unknown LED event %d\n", event);
7310 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
7311 bwn_led_duration[rate].off_dur);
7315 bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
7317 struct bwn_softc *sc = mac->mac_sc;
7318 struct bwn_led *led = sc->sc_blink_led;
7321 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7322 val = bwn_led_onoff(led, val, 1);
7323 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7325 if (led->led_flags & BWN_LED_F_SLOW) {
7326 BWN_LED_SLOWDOWN(on_dur);
7327 BWN_LED_SLOWDOWN(off_dur);
7330 sc->sc_led_blinking = 1;
7331 sc->sc_led_blink_offdur = off_dur;
7333 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
7337 bwn_led_blink_next(void *arg)
7339 struct bwn_mac *mac = arg;
7340 struct bwn_softc *sc = mac->mac_sc;
7343 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7344 val = bwn_led_onoff(sc->sc_blink_led, val, 0);
7345 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7347 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
7348 bwn_led_blink_end, mac);
7352 bwn_led_blink_end(void *arg)
7354 struct bwn_mac *mac = arg;
7355 struct bwn_softc *sc = mac->mac_sc;
7357 sc->sc_led_blinking = 0;
7361 bwn_suspend(device_t dev)
7363 struct bwn_softc *sc = device_get_softc(dev);
7372 bwn_resume(device_t dev)
7374 struct bwn_softc *sc = device_get_softc(dev);
7375 int error = EDOOFUS;
7378 if (sc->sc_ic.ic_nrunning > 0)
7379 error = bwn_init(sc);
7382 ieee80211_start_all(&sc->sc_ic);
7387 bwn_rfswitch(void *arg)
7389 struct bwn_softc *sc = arg;
7390 struct bwn_mac *mac = sc->sc_curmac;
7391 int cur = 0, prev = 0;
7393 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED,
7394 ("%s: invalid MAC status %d", __func__, mac->mac_status));
7396 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP
7397 || mac->mac_phy.type == BWN_PHYTYPE_N) {
7398 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI)
7399 & BWN_RF_HWENABLED_HI_MASK))
7402 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO)
7403 & BWN_RF_HWENABLED_LO_MASK)
7407 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)
7410 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n",
7411 __func__, cur, prev);
7415 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
7417 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON;
7419 device_printf(sc->sc_dev,
7420 "status of RF switch is changed to %s\n",
7421 cur ? "ON" : "OFF");
7422 if (cur != mac->mac_phy.rf_on) {
7426 bwn_rf_turnoff(mac);
7430 callout_schedule(&sc->sc_rfswitch_ch, hz);
7434 bwn_sysctl_node(struct bwn_softc *sc)
7436 device_t dev = sc->sc_dev;
7437 struct bwn_mac *mac;
7438 struct bwn_stats *stats;
7440 /* XXX assume that count of MAC is only 1. */
7442 if ((mac = sc->sc_curmac) == NULL)
7444 stats = &mac->mac_stats;
7446 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7447 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7448 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level");
7449 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7450 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7451 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS");
7452 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7453 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7454 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send");
7457 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
7458 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7459 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
7463 static device_method_t bwn_methods[] = {
7464 /* Device interface */
7465 DEVMETHOD(device_probe, bwn_probe),
7466 DEVMETHOD(device_attach, bwn_attach),
7467 DEVMETHOD(device_detach, bwn_detach),
7468 DEVMETHOD(device_suspend, bwn_suspend),
7469 DEVMETHOD(device_resume, bwn_resume),
7472 static driver_t bwn_driver = {
7475 sizeof(struct bwn_softc)
7477 static devclass_t bwn_devclass;
7478 DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0);
7479 MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1);
7480 MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */
7481 MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */
7482 MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1);
7483 MODULE_VERSION(bwn, 1);