2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
5 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
6 * Copyright (c) 2017 The FreeBSD Foundation
9 * Portions of this software were developed by Landon Fuller
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
20 * redistribution must be conditioned upon including a substantially
21 * similar Disclaimer requirement for further binary redistribution.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * The Broadcom Wireless LAN controller driver.
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/endian.h>
54 #include <sys/errno.h>
55 #include <sys/firmware.h>
57 #include <sys/mutex.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
65 #include <net/ethernet.h>
67 #include <net/if_var.h>
68 #include <net/if_arp.h>
69 #include <net/if_dl.h>
70 #include <net/if_llc.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
74 #include <net80211/ieee80211_var.h>
75 #include <net80211/ieee80211_radiotap.h>
76 #include <net80211/ieee80211_regdomain.h>
77 #include <net80211/ieee80211_phy.h>
78 #include <net80211/ieee80211_ratectl.h>
80 #include <dev/bhnd/bhnd.h>
81 #include <dev/bhnd/bhnd_ids.h>
83 #include <dev/bhnd/cores/chipc/chipc.h>
84 #include <dev/bhnd/cores/pmu/bhnd_pmu.h>
86 #include <dev/bwn/if_bwnreg.h>
87 #include <dev/bwn/if_bwnvar.h>
89 #include <dev/bwn/if_bwn_debug.h>
90 #include <dev/bwn/if_bwn_misc.h>
91 #include <dev/bwn/if_bwn_util.h>
92 #include <dev/bwn/if_bwn_phy_common.h>
93 #include <dev/bwn/if_bwn_phy_g.h>
94 #include <dev/bwn/if_bwn_phy_lp.h>
95 #include <dev/bwn/if_bwn_phy_n.h>
97 #include "bhnd_nvram_map.h"
101 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
102 "Broadcom driver parameters");
105 * Tunable & sysctl variables.
109 static int bwn_debug = 0;
110 SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0,
111 "Broadcom debugging printfs");
114 static int bwn_bfp = 0; /* use "Bad Frames Preemption" */
115 SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0,
116 "uses Bad Frames Preemption");
117 static int bwn_bluetooth = 1;
118 SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
119 "turns on Bluetooth Coexistence");
120 static int bwn_hwpctl = 0;
121 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
122 "uses H/W power control");
123 static int bwn_usedma = 1;
124 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
126 TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
127 static int bwn_wme = 1;
128 SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
131 static void bwn_attach_pre(struct bwn_softc *);
132 static int bwn_attach_post(struct bwn_softc *);
133 static int bwn_retain_bus_providers(struct bwn_softc *sc);
134 static void bwn_release_bus_providers(struct bwn_softc *sc);
135 static void bwn_sprom_bugfixes(device_t);
136 static int bwn_init(struct bwn_softc *);
137 static void bwn_parent(struct ieee80211com *);
138 static void bwn_start(struct bwn_softc *);
139 static int bwn_transmit(struct ieee80211com *, struct mbuf *);
140 static int bwn_attach_core(struct bwn_mac *);
141 static int bwn_phy_getinfo(struct bwn_mac *, int);
142 static int bwn_chiptest(struct bwn_mac *);
143 static int bwn_setup_channels(struct bwn_mac *, int, int);
144 static void bwn_shm_ctlword(struct bwn_mac *, uint16_t,
146 static void bwn_addchannels(struct ieee80211_channel [], int, int *,
147 const struct bwn_channelinfo *, const uint8_t []);
148 static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
149 const struct ieee80211_bpf_params *);
150 static void bwn_updateslot(struct ieee80211com *);
151 static void bwn_update_promisc(struct ieee80211com *);
152 static void bwn_wme_init(struct bwn_mac *);
153 static int bwn_wme_update(struct ieee80211com *);
154 static void bwn_wme_clear(struct bwn_softc *);
155 static void bwn_wme_load(struct bwn_mac *);
156 static void bwn_wme_loadparams(struct bwn_mac *,
157 const struct wmeParams *, uint16_t);
158 static void bwn_scan_start(struct ieee80211com *);
159 static void bwn_scan_end(struct ieee80211com *);
160 static void bwn_set_channel(struct ieee80211com *);
161 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
162 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
163 const uint8_t [IEEE80211_ADDR_LEN],
164 const uint8_t [IEEE80211_ADDR_LEN]);
165 static void bwn_vap_delete(struct ieee80211vap *);
166 static void bwn_stop(struct bwn_softc *);
167 static int bwn_core_forceclk(struct bwn_mac *, bool);
168 static int bwn_core_init(struct bwn_mac *);
169 static void bwn_core_start(struct bwn_mac *);
170 static void bwn_core_exit(struct bwn_mac *);
171 static void bwn_bt_disable(struct bwn_mac *);
172 static int bwn_chip_init(struct bwn_mac *);
173 static void bwn_set_txretry(struct bwn_mac *, int, int);
174 static void bwn_rate_init(struct bwn_mac *);
175 static void bwn_set_phytxctl(struct bwn_mac *);
176 static void bwn_spu_setdelay(struct bwn_mac *, int);
177 static void bwn_bt_enable(struct bwn_mac *);
178 static void bwn_set_macaddr(struct bwn_mac *);
179 static void bwn_crypt_init(struct bwn_mac *);
180 static void bwn_chip_exit(struct bwn_mac *);
181 static int bwn_fw_fillinfo(struct bwn_mac *);
182 static int bwn_fw_loaducode(struct bwn_mac *);
183 static int bwn_gpio_init(struct bwn_mac *);
184 static int bwn_fw_loadinitvals(struct bwn_mac *);
185 static int bwn_phy_init(struct bwn_mac *);
186 static void bwn_set_txantenna(struct bwn_mac *, int);
187 static void bwn_set_opmode(struct bwn_mac *);
188 static void bwn_rate_write(struct bwn_mac *, uint16_t, int);
189 static uint8_t bwn_plcp_getcck(const uint8_t);
190 static uint8_t bwn_plcp_getofdm(const uint8_t);
191 static void bwn_pio_init(struct bwn_mac *);
192 static uint16_t bwn_pio_idx2base(struct bwn_mac *, int);
193 static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
195 static void bwn_pio_setupqueue_rx(struct bwn_mac *,
196 struct bwn_pio_rxqueue *, int);
197 static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *);
198 static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *,
200 static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *);
201 static int bwn_pio_rx(struct bwn_pio_rxqueue *);
202 static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *);
203 static void bwn_pio_handle_txeof(struct bwn_mac *,
204 const struct bwn_txstatus *);
205 static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t);
206 static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t);
207 static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t,
209 static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t,
211 static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *,
213 static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t);
214 static uint32_t bwn_pio_write_multi_4(struct bwn_mac *,
215 struct bwn_pio_txqueue *, uint32_t, const void *, int);
216 static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *,
218 static uint16_t bwn_pio_write_multi_2(struct bwn_mac *,
219 struct bwn_pio_txqueue *, uint16_t, const void *, int);
220 static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *,
221 struct bwn_pio_txqueue *, uint16_t, struct mbuf *);
222 static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
223 uint16_t, struct bwn_pio_txpkt **);
224 static void bwn_dma_init(struct bwn_mac *);
225 static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
226 static uint16_t bwn_dma_base(int, int);
227 static void bwn_dma_ringfree(struct bwn_dma_ring **);
228 static void bwn_dma_32_getdesc(struct bwn_dma_ring *,
229 int, struct bwn_dmadesc_generic **,
230 struct bwn_dmadesc_meta **);
231 static void bwn_dma_32_setdesc(struct bwn_dma_ring *,
232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
234 static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int);
235 static void bwn_dma_32_suspend(struct bwn_dma_ring *);
236 static void bwn_dma_32_resume(struct bwn_dma_ring *);
237 static int bwn_dma_32_get_curslot(struct bwn_dma_ring *);
238 static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int);
239 static void bwn_dma_64_getdesc(struct bwn_dma_ring *,
240 int, struct bwn_dmadesc_generic **,
241 struct bwn_dmadesc_meta **);
242 static void bwn_dma_64_setdesc(struct bwn_dma_ring *,
243 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
245 static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int);
246 static void bwn_dma_64_suspend(struct bwn_dma_ring *);
247 static void bwn_dma_64_resume(struct bwn_dma_ring *);
248 static int bwn_dma_64_get_curslot(struct bwn_dma_ring *);
249 static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int);
250 static int bwn_dma_allocringmemory(struct bwn_dma_ring *);
251 static void bwn_dma_setup(struct bwn_dma_ring *);
252 static void bwn_dma_free_ringmemory(struct bwn_dma_ring *);
253 static void bwn_dma_cleanup(struct bwn_dma_ring *);
254 static void bwn_dma_free_descbufs(struct bwn_dma_ring *);
255 static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int);
256 static void bwn_dma_rx(struct bwn_dma_ring *);
257 static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
258 static void bwn_dma_free_descbuf(struct bwn_dma_ring *,
259 struct bwn_dmadesc_meta *);
260 static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
261 static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
262 static int bwn_dma_freeslot(struct bwn_dma_ring *);
263 static int bwn_dma_nextslot(struct bwn_dma_ring *, int);
264 static void bwn_dma_rxeof(struct bwn_dma_ring *, int *);
265 static int bwn_dma_newbuf(struct bwn_dma_ring *,
266 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *,
268 static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int,
270 static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *);
271 static void bwn_ratectl_tx_complete(const struct ieee80211_node *,
272 const struct bwn_txstatus *);
273 static void bwn_dma_handle_txeof(struct bwn_mac *,
274 const struct bwn_txstatus *);
275 static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *,
277 static int bwn_dma_getslot(struct bwn_dma_ring *);
278 static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
280 static int bwn_dma_attach(struct bwn_mac *);
281 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
283 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
284 const struct bwn_txstatus *, uint16_t, int *);
285 static void bwn_dma_free(struct bwn_mac *);
286 static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype);
287 static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype,
288 const char *, struct bwn_fwfile *);
289 static void bwn_release_firmware(struct bwn_mac *);
290 static void bwn_do_release_fw(struct bwn_fwfile *);
291 static uint16_t bwn_fwcaps_read(struct bwn_mac *);
292 static int bwn_fwinitvals_write(struct bwn_mac *,
293 const struct bwn_fwinitvals *, size_t, size_t);
294 static uint16_t bwn_ant2phy(int);
295 static void bwn_mac_write_bssid(struct bwn_mac *);
296 static void bwn_mac_setfilter(struct bwn_mac *, uint16_t,
298 static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t,
299 const uint8_t *, size_t, const uint8_t *);
300 static void bwn_key_macwrite(struct bwn_mac *, uint8_t,
302 static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t,
304 static void bwn_phy_exit(struct bwn_mac *);
305 static void bwn_core_stop(struct bwn_mac *);
306 static int bwn_switch_band(struct bwn_softc *,
307 struct ieee80211_channel *);
308 static int bwn_phy_reset(struct bwn_mac *);
309 static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
310 static void bwn_set_pretbtt(struct bwn_mac *);
311 static int bwn_intr(void *);
312 static void bwn_intrtask(void *, int);
313 static void bwn_restart(struct bwn_mac *, const char *);
314 static void bwn_intr_ucode_debug(struct bwn_mac *);
315 static void bwn_intr_tbtt_indication(struct bwn_mac *);
316 static void bwn_intr_atim_end(struct bwn_mac *);
317 static void bwn_intr_beacon(struct bwn_mac *);
318 static void bwn_intr_pmq(struct bwn_mac *);
319 static void bwn_intr_noise(struct bwn_mac *);
320 static void bwn_intr_txeof(struct bwn_mac *);
321 static void bwn_hwreset(void *, int);
322 static void bwn_handle_fwpanic(struct bwn_mac *);
323 static void bwn_load_beacon0(struct bwn_mac *);
324 static void bwn_load_beacon1(struct bwn_mac *);
325 static uint32_t bwn_jssi_read(struct bwn_mac *);
326 static void bwn_noise_gensample(struct bwn_mac *);
327 static void bwn_handle_txeof(struct bwn_mac *,
328 const struct bwn_txstatus *);
329 static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *);
330 static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t);
331 static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *,
333 static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *);
334 static int bwn_set_txhdr(struct bwn_mac *,
335 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *,
337 static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t,
339 static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t);
340 static uint8_t bwn_get_fbrate(uint8_t);
341 static void bwn_txpwr(void *, int);
342 static void bwn_tasks(void *);
343 static void bwn_task_15s(struct bwn_mac *);
344 static void bwn_task_30s(struct bwn_mac *);
345 static void bwn_task_60s(struct bwn_mac *);
346 static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *,
348 static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *);
349 static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *,
350 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int,
352 static void bwn_tsf_read(struct bwn_mac *, uint64_t *);
353 static void bwn_set_slot_time(struct bwn_mac *, uint16_t);
354 static void bwn_watchdog(void *);
355 static void bwn_dma_stop(struct bwn_mac *);
356 static void bwn_pio_stop(struct bwn_mac *);
357 static void bwn_dma_ringstop(struct bwn_dma_ring **);
358 static int bwn_led_attach(struct bwn_mac *);
359 static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
360 static void bwn_led_event(struct bwn_mac *, int);
361 static void bwn_led_blink_start(struct bwn_mac *, int, int);
362 static void bwn_led_blink_next(void *);
363 static void bwn_led_blink_end(void *);
364 static void bwn_rfswitch(void *);
365 static void bwn_rf_turnon(struct bwn_mac *);
366 static void bwn_rf_turnoff(struct bwn_mac *);
367 static void bwn_sysctl_node(struct bwn_softc *);
369 static const struct bwn_channelinfo bwn_chantable_bg = {
371 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 },
372 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 },
373 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 },
374 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 },
375 { 2472, 13, 30 }, { 2484, 14, 30 } },
379 static const struct bwn_channelinfo bwn_chantable_a = {
381 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 },
382 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 },
383 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 },
384 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 },
385 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 },
386 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 },
387 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 },
388 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 },
389 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 },
390 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 },
391 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 },
392 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 },
398 static const struct bwn_channelinfo bwn_chantable_n = {
400 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 },
401 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 },
402 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 },
403 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 },
404 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 },
405 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 },
406 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 },
407 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 },
408 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 },
409 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 },
410 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 },
411 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 },
412 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 },
413 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 },
414 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 },
415 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 },
416 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 },
417 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 },
418 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 },
419 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 },
420 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 },
421 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 },
422 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 },
423 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 },
424 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 },
425 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 },
426 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 },
427 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 },
428 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 },
429 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 },
430 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 },
431 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 },
432 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 },
433 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 },
434 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 },
435 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 },
436 { 6130, 226, 30 }, { 6140, 228, 30 } },
441 #define VENDOR_LED_ACT(vendor) \
443 .vid = PCI_VENDOR_##vendor, \
444 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \
447 static const struct {
449 uint8_t led_act[BWN_LED_MAX];
450 } bwn_vendor_led_act[] = {
451 VENDOR_LED_ACT(HP_COMPAQ),
452 VENDOR_LED_ACT(ASUSTEK)
455 static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
456 { BWN_VENDOR_LED_ACT_DEFAULT };
458 #undef VENDOR_LED_ACT
460 static const char *bwn_led_vars[] = {
467 static const struct {
470 } bwn_led_duration[109] = {
486 static const uint16_t bwn_wme_shm_offsets[] = {
487 [0] = BWN_WME_BESTEFFORT,
488 [1] = BWN_WME_BACKGROUND,
493 /* Supported D11 core revisions */
494 #define BWN_DEV(_hwrev) {{ \
495 BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11), \
496 BHND_MATCH_CORE_REV(_hwrev), \
498 static const struct bhnd_device bwn_devices[] = {
499 BWN_DEV(HWREV_RANGE(5, 16)),
500 BWN_DEV(HWREV_EQ(23)),
504 /* D11 quirks when bridged via a PCI host bridge core */
505 static const struct bhnd_device_quirk pci_bridge_quirks[] = {
506 BHND_CORE_QUIRK (HWREV_LTE(10), BWN_QUIRK_UCODE_SLOWCLOCK_WAR),
507 BHND_DEVICE_QUIRK_END
510 /* D11 quirks when bridged via a PCMCIA host bridge core */
511 static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = {
512 BHND_CORE_QUIRK (HWREV_ANY, BWN_QUIRK_NODMA),
513 BHND_DEVICE_QUIRK_END
516 /* Host bridge cores for which D11 quirk flags should be applied */
517 static const struct bhnd_device bridge_devices[] = {
518 BHND_DEVICE(BCM, PCI, NULL, pci_bridge_quirks),
519 BHND_DEVICE(BCM, PCMCIA, NULL, pcmcia_bridge_quirks),
524 bwn_probe(device_t dev)
526 const struct bhnd_device *id;
528 id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
532 bhnd_set_default_core_desc(dev);
533 return (BUS_PROBE_DEFAULT);
537 bwn_attach(device_t dev)
540 struct bwn_softc *sc;
541 device_t parent, hostb;
542 char chip_name[BHND_CHIPID_MAX_NAMELEN];
545 sc = device_get_softc(dev);
548 sc->sc_debug = bwn_debug;
553 /* Determine the driver quirks applicable to this device, including any
554 * quirks specific to the bus host bridge core (if any) */
555 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices,
556 sizeof(bwn_devices[0]));
558 parent = device_get_parent(dev);
559 if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) {
560 sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices,
561 sizeof(bridge_devices[0]));
564 /* DMA explicitly disabled? */
566 sc->sc_quirks |= BWN_QUIRK_NODMA;
568 /* Fetch our chip identification and board info */
569 sc->sc_cid = *bhnd_get_chipid(dev);
570 if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) {
571 device_printf(sc->sc_dev, "couldn't read board info\n");
575 /* Allocate our D11 register block and PMU state */
577 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
578 &sc->sc_mem_rid, RF_ACTIVE);
579 if (sc->sc_mem_res == NULL) {
580 device_printf(sc->sc_dev, "couldn't allocate registers\n");
584 if ((error = bhnd_alloc_pmu(sc->sc_dev))) {
585 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
586 sc->sc_mem_rid, sc->sc_mem_res);
590 /* Retain references to all required bus service providers */
591 if ((error = bwn_retain_bus_providers(sc)))
594 /* Fetch mask of available antennas */
595 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G,
598 device_printf(sc->sc_dev, "error determining 2GHz antenna "
599 "availability from NVRAM: %d\n", error);
603 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G,
606 device_printf(sc->sc_dev, "error determining 5GHz antenna "
607 "availability from NVRAM: %d\n", error);
611 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
613 bwn_sprom_bugfixes(dev);
614 sc->sc_flags |= BWN_FLAG_ATTACHED;
617 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
619 mac->mac_status = BWN_MAC_STATUS_UNINIT;
621 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
623 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
624 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
625 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
627 error = bwn_attach_core(mac);
630 error = bwn_led_attach(mac);
634 bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id);
635 device_printf(sc->sc_dev, "WLAN (%s rev %u) "
636 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
637 chip_name, bhnd_get_hwrev(sc->sc_dev), mac->mac_phy.analog,
638 mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf,
639 mac->mac_phy.rf_ver, mac->mac_phy.rf_rev);
640 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
641 device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype);
643 device_printf(sc->sc_dev, "PIO\n");
646 device_printf(sc->sc_dev,
647 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
650 mac->mac_rid_irq = 0;
651 mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
652 &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE);
654 if (mac->mac_res_irq == NULL) {
655 device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n");
660 error = bus_setup_intr(dev, mac->mac_res_irq,
661 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
664 device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n",
669 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
672 * calls attach-post routine
674 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0)
679 if (mac != NULL && mac->mac_res_irq != NULL) {
680 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
685 bhnd_release_pmu(dev);
686 bwn_release_bus_providers(sc);
688 if (sc->sc_mem_res != NULL) {
689 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
690 sc->sc_mem_rid, sc->sc_mem_res);
697 bwn_retain_bus_providers(struct bwn_softc *sc)
699 struct chipc_caps *ccaps;
701 sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC);
702 if (sc->sc_chipc == NULL) {
703 device_printf(sc->sc_dev, "ChipCommon device not found\n");
707 ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc);
709 sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO);
710 if (sc->sc_gpio == NULL) {
711 device_printf(sc->sc_dev, "GPIO device not found\n");
716 sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU);
717 if (sc->sc_pmu == NULL) {
718 device_printf(sc->sc_dev, "PMU device not found\n");
726 bwn_release_bus_providers(sc);
731 bwn_release_bus_providers(struct bwn_softc *sc)
733 #define BWN_RELEASE_PROV(_sc, _prov, _service) do { \
734 if ((_sc)-> _prov != NULL) { \
735 bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov, \
737 (_sc)-> _prov = NULL; \
741 BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC);
742 BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO);
743 BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU);
745 #undef BWN_RELEASE_PROV
749 bwn_attach_post(struct bwn_softc *sc)
751 struct ieee80211com *ic;
752 const char *mac_varname;
759 ic->ic_name = device_get_nameunit(sc->sc_dev);
760 /* XXX not right but it's not used anywhere important */
761 ic->ic_phytype = IEEE80211_T_OFDM;
762 ic->ic_opmode = IEEE80211_M_STA;
764 IEEE80211_C_STA /* station mode supported */
765 | IEEE80211_C_MONITOR /* monitor mode */
766 | IEEE80211_C_AHDEMO /* adhoc demo mode */
767 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
768 | IEEE80211_C_SHSLOT /* short slot time supported */
769 | IEEE80211_C_WME /* WME/WMM supported */
770 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
772 | IEEE80211_C_BGSCAN /* capable of bg scanning */
774 | IEEE80211_C_TXPMGT /* capable of txpow mgt */
777 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */
779 /* Determine the NVRAM variable containing our MAC address */
780 core_unit = bhnd_get_core_unit(sc->sc_dev);
782 if (sc->sc_board_info.board_srom_rev <= 2) {
783 if (core_unit == 0) {
784 mac_varname = BHND_NVAR_IL0MACADDR;
785 } else if (core_unit == 1) {
786 mac_varname = BHND_NVAR_ET1MACADDR;
789 if (core_unit == 0) {
790 mac_varname = BHND_NVAR_MACADDR;
794 if (mac_varname == NULL) {
795 device_printf(sc->sc_dev, "missing MAC address variable for "
796 "D11 core %u", core_unit);
800 /* Read the MAC address from NVRAM */
801 error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr,
802 sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY);
804 device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname,
809 /* call MI attach routine. */
810 ieee80211_ifattach(ic);
812 ic->ic_headroom = sizeof(struct bwn_txhdr);
814 /* override default methods */
815 ic->ic_raw_xmit = bwn_raw_xmit;
816 ic->ic_updateslot = bwn_updateslot;
817 ic->ic_update_promisc = bwn_update_promisc;
818 ic->ic_wme.wme_update = bwn_wme_update;
819 ic->ic_scan_start = bwn_scan_start;
820 ic->ic_scan_end = bwn_scan_end;
821 ic->ic_set_channel = bwn_set_channel;
822 ic->ic_vap_create = bwn_vap_create;
823 ic->ic_vap_delete = bwn_vap_delete;
824 ic->ic_transmit = bwn_transmit;
825 ic->ic_parent = bwn_parent;
827 ieee80211_radiotap_attach(ic,
828 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
829 BWN_TX_RADIOTAP_PRESENT,
830 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
831 BWN_RX_RADIOTAP_PRESENT);
836 ieee80211_announce(ic);
841 bwn_phy_detach(struct bwn_mac *mac)
844 if (mac->mac_phy.detach != NULL)
845 mac->mac_phy.detach(mac);
849 bwn_detach(device_t dev)
851 struct bwn_softc *sc = device_get_softc(dev);
852 struct bwn_mac *mac = sc->sc_curmac;
853 struct ieee80211com *ic = &sc->sc_ic;
855 sc->sc_flags |= BWN_FLAG_INVALID;
857 if (device_is_attached(sc->sc_dev)) {
862 callout_drain(&sc->sc_led_blink_ch);
863 callout_drain(&sc->sc_rfswitch_ch);
864 callout_drain(&sc->sc_task_ch);
865 callout_drain(&sc->sc_watchdog_ch);
867 ieee80211_draintask(ic, &mac->mac_hwreset);
868 ieee80211_draintask(ic, &mac->mac_txpower);
869 ieee80211_ifdetach(ic);
871 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
872 taskqueue_free(sc->sc_tq);
874 if (mac->mac_intrhand != NULL) {
875 bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand);
876 mac->mac_intrhand = NULL;
879 bhnd_release_pmu(dev);
880 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
882 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
884 mbufq_drain(&sc->sc_snd);
885 bwn_release_firmware(mac);
886 BWN_LOCK_DESTROY(sc);
888 bwn_release_bus_providers(sc);
894 bwn_attach_pre(struct bwn_softc *sc)
898 TAILQ_INIT(&sc->sc_maclist);
899 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0);
900 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0);
901 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0);
902 mbufq_init(&sc->sc_snd, ifqmaxlen);
903 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT,
904 taskqueue_thread_enqueue, &sc->sc_tq);
905 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
906 "%s taskq", device_get_nameunit(sc->sc_dev));
910 bwn_sprom_bugfixes(device_t dev)
912 struct bwn_softc *sc = device_get_softc(dev);
914 #define BWN_ISDEV(_device, _subvendor, _subdevice) \
915 ((sc->sc_board_info.board_devid == PCI_DEVID_##_device) && \
916 (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) && \
917 (sc->sc_board_info.board_type == _subdevice))
919 /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices
920 * were programmed with a missing PACTRL boardflag */
921 if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
922 sc->sc_board_info.board_type == 0x4e &&
923 sc->sc_board_info.board_rev > 0x40)
924 sc->sc_board_info.board_flags |= BHND_BFL_PACTRL;
926 if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) ||
927 BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) ||
928 BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) ||
929 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) ||
930 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) ||
931 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) ||
932 BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010))
933 sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX;
938 bwn_parent(struct ieee80211com *ic)
940 struct bwn_softc *sc = ic->ic_softc;
944 if (ic->ic_nrunning > 0) {
945 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
949 bwn_update_promisc(ic);
950 } else if (sc->sc_flags & BWN_FLAG_RUNNING)
955 ieee80211_start_all(ic);
959 bwn_transmit(struct ieee80211com *ic, struct mbuf *m)
961 struct bwn_softc *sc = ic->ic_softc;
965 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
969 error = mbufq_enqueue(&sc->sc_snd, m);
980 bwn_start(struct bwn_softc *sc)
982 struct bwn_mac *mac = sc->sc_curmac;
983 struct ieee80211_frame *wh;
984 struct ieee80211_node *ni;
985 struct ieee80211_key *k;
988 BWN_ASSERT_LOCKED(sc);
990 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL ||
991 mac->mac_status < BWN_MAC_STATUS_STARTED)
994 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
995 if (bwn_tx_isfull(sc, m))
997 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
999 device_printf(sc->sc_dev, "unexpected NULL ni\n");
1001 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1004 wh = mtod(m, struct ieee80211_frame *);
1005 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1006 k = ieee80211_crypto_encap(ni, m);
1008 if_inc_counter(ni->ni_vap->iv_ifp,
1009 IFCOUNTER_OERRORS, 1);
1010 ieee80211_free_node(ni);
1015 wh = NULL; /* Catch any invalid use */
1016 if (bwn_tx_start(sc, ni, m) != 0) {
1018 if_inc_counter(ni->ni_vap->iv_ifp,
1019 IFCOUNTER_OERRORS, 1);
1020 ieee80211_free_node(ni);
1024 sc->sc_watchdog_timer = 5;
1029 bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m)
1031 struct bwn_dma_ring *dr;
1032 struct bwn_mac *mac = sc->sc_curmac;
1033 struct bwn_pio_txqueue *tq;
1034 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1036 BWN_ASSERT_LOCKED(sc);
1038 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
1039 dr = bwn_dma_select(mac, M_WME_GETAC(m));
1040 if (dr->dr_stop == 1 ||
1041 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) {
1046 tq = bwn_pio_select(mac, M_WME_GETAC(m));
1047 if (tq->tq_free == 0 || pktlen > tq->tq_size ||
1048 pktlen > (tq->tq_size - tq->tq_used))
1053 mbufq_prepend(&sc->sc_snd, m);
1058 bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m)
1060 struct bwn_mac *mac = sc->sc_curmac;
1063 BWN_ASSERT_LOCKED(sc);
1065 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) {
1070 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ?
1071 bwn_dma_tx_start(mac, ni, &m) : bwn_pio_tx_start(mac, ni, &m);
1080 bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni,
1083 struct bwn_pio_txpkt *tp;
1084 struct bwn_pio_txqueue *tq;
1085 struct bwn_softc *sc = mac->mac_sc;
1086 struct bwn_txhdr txhdr;
1087 struct mbuf *m, *m_new;
1092 BWN_ASSERT_LOCKED(sc);
1094 /* XXX TODO send packets after DTIM */
1097 tq = bwn_pio_select(mac, M_WME_GETAC(m));
1098 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__));
1099 tp = TAILQ_FIRST(&tq->tq_pktlist);
1103 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp));
1105 device_printf(sc->sc_dev, "tx fail\n");
1109 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
1110 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1113 if (bhnd_get_hwrev(sc->sc_dev) >= 8) {
1115 * XXX please removes m_defrag(9)
1117 m_new = m_defrag(*mp, M_NOWAIT);
1118 if (m_new == NULL) {
1119 device_printf(sc->sc_dev,
1120 "%s: can't defrag TX buffer\n",
1125 if (m_new->m_next != NULL)
1126 device_printf(sc->sc_dev,
1127 "TODO: fragmented packets for PIO\n");
1131 ctl32 = bwn_pio_write_multi_4(mac, tq,
1132 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) |
1133 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF,
1134 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1136 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32,
1137 mtod(m_new, const void *), m_new->m_pkthdr.len);
1138 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL,
1139 ctl32 | BWN_PIO8_TXCTL_EOF);
1141 ctl16 = bwn_pio_write_multi_2(mac, tq,
1142 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) |
1143 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF,
1144 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1145 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m);
1146 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL,
1147 ctl16 | BWN_PIO_TXCTL_EOF);
1153 static struct bwn_pio_txqueue *
1154 bwn_pio_select(struct bwn_mac *mac, uint8_t prio)
1157 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
1158 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1162 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1164 return (&mac->mac_method.pio.wme[WME_AC_BK]);
1166 return (&mac->mac_method.pio.wme[WME_AC_VI]);
1168 return (&mac->mac_method.pio.wme[WME_AC_VO]);
1170 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
1175 bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni,
1178 #define BWN_GET_TXHDRCACHE(slot) \
1179 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)])
1180 struct bwn_dma *dma = &mac->mac_method.dma;
1181 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(*mp));
1182 struct bwn_dmadesc_generic *desc;
1183 struct bwn_dmadesc_meta *mt;
1184 struct bwn_softc *sc = mac->mac_sc;
1186 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache;
1187 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot };
1189 BWN_ASSERT_LOCKED(sc);
1190 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__));
1192 /* XXX send after DTIM */
1195 slot = bwn_dma_getslot(dr);
1196 dr->getdesc(dr, slot, &desc, &mt);
1197 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER,
1198 ("%s:%d: fail", __func__, __LINE__));
1200 error = bwn_set_txhdr(dr->dr_mac, ni, m,
1201 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot),
1202 BWN_DMA_COOKIE(dr, slot));
1205 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap,
1206 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr,
1207 &mt->mt_paddr, BUS_DMA_NOWAIT);
1209 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1213 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap,
1214 BUS_DMASYNC_PREWRITE);
1215 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0);
1216 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1217 BUS_DMASYNC_PREWRITE);
1219 slot = bwn_dma_getslot(dr);
1220 dr->getdesc(dr, slot, &desc, &mt);
1221 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY &&
1222 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__));
1226 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m,
1227 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1228 if (error && error != EFBIG) {
1229 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1233 if (error) { /* error == EFBIG */
1236 m_new = m_defrag(m, M_NOWAIT);
1237 if (m_new == NULL) {
1238 device_printf(sc->sc_dev,
1239 "%s: can't defrag TX buffer\n",
1247 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap,
1248 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1250 device_printf(sc->sc_dev,
1251 "%s: can't load TX buffer (2) %d\n",
1256 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE);
1257 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1);
1258 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1259 BUS_DMASYNC_PREWRITE);
1261 /* XXX send after DTIM */
1263 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot));
1266 dr->dr_curslot = backup[0];
1267 dr->dr_usedslot = backup[1];
1269 #undef BWN_GET_TXHDRCACHE
1273 bwn_watchdog(void *arg)
1275 struct bwn_softc *sc = arg;
1277 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) {
1278 device_printf(sc->sc_dev, "device timeout\n");
1279 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1281 callout_schedule(&sc->sc_watchdog_ch, hz);
1285 bwn_attach_core(struct bwn_mac *mac)
1287 struct bwn_softc *sc = mac->mac_sc;
1288 int error, have_bg = 0, have_a = 0;
1291 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5,
1292 ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev)));
1294 if ((error = bwn_core_forceclk(mac, true)))
1297 if ((error = bhnd_read_iost(sc->sc_dev, &iost))) {
1298 device_printf(sc->sc_dev, "error reading I/O status flags: "
1303 have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0;
1304 have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0;
1305 if (iost & BWN_IOST_DUALPHY) {
1312 device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d,"
1313 " deviceid=0x%04x, siba_deviceid=0x%04x\n",
1318 sc->sc_board_info.board_devid,
1319 sc->sc_cid.chip_id);
1323 * Guess at whether it has A-PHY or G-PHY.
1324 * This is just used for resetting the core to probe things;
1325 * we will re-guess once it's all up and working.
1327 error = bwn_reset_core(mac, have_bg);
1332 * Determine the DMA engine type
1334 if (iost & BHND_IOST_DMA64) {
1335 mac->mac_dmatype = BHND_DMA_ADDR_64BIT;
1340 base = bwn_dma_base(0, 0);
1341 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL,
1342 BWN_DMA32_TXADDREXT_MASK);
1343 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
1344 if (tmp & BWN_DMA32_TXADDREXT_MASK) {
1345 mac->mac_dmatype = BHND_DMA_ADDR_32BIT;
1347 mac->mac_dmatype = BHND_DMA_ADDR_30BIT;
1352 * Get the PHY version.
1354 error = bwn_phy_getinfo(mac, have_bg);
1359 * This is the whitelist of devices which we "believe"
1360 * the SPROM PHY config from. The rest are "guessed".
1362 if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL &&
1363 sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G &&
1364 sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL &&
1365 sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL &&
1366 sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N &&
1367 sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) {
1368 have_a = have_bg = 0;
1369 if (mac->mac_phy.type == BWN_PHYTYPE_A)
1371 else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1372 mac->mac_phy.type == BWN_PHYTYPE_N ||
1373 mac->mac_phy.type == BWN_PHYTYPE_LP)
1376 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__,
1377 mac->mac_phy.type));
1381 * XXX The PHY-G support doesn't do 5GHz operation.
1383 if (mac->mac_phy.type != BWN_PHYTYPE_LP &&
1384 mac->mac_phy.type != BWN_PHYTYPE_N) {
1385 device_printf(sc->sc_dev,
1386 "%s: forcing 2GHz only; no dual-band support for PHY\n",
1392 mac->mac_phy.phy_n = NULL;
1394 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
1395 mac->mac_phy.attach = bwn_phy_g_attach;
1396 mac->mac_phy.detach = bwn_phy_g_detach;
1397 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw;
1398 mac->mac_phy.init_pre = bwn_phy_g_init_pre;
1399 mac->mac_phy.init = bwn_phy_g_init;
1400 mac->mac_phy.exit = bwn_phy_g_exit;
1401 mac->mac_phy.phy_read = bwn_phy_g_read;
1402 mac->mac_phy.phy_write = bwn_phy_g_write;
1403 mac->mac_phy.rf_read = bwn_phy_g_rf_read;
1404 mac->mac_phy.rf_write = bwn_phy_g_rf_write;
1405 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl;
1406 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff;
1407 mac->mac_phy.switch_analog = bwn_phy_switch_analog;
1408 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel;
1409 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan;
1410 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna;
1411 mac->mac_phy.set_im = bwn_phy_g_im;
1412 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr;
1413 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr;
1414 mac->mac_phy.task_15s = bwn_phy_g_task_15s;
1415 mac->mac_phy.task_60s = bwn_phy_g_task_60s;
1416 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) {
1417 mac->mac_phy.init_pre = bwn_phy_lp_init_pre;
1418 mac->mac_phy.init = bwn_phy_lp_init;
1419 mac->mac_phy.phy_read = bwn_phy_lp_read;
1420 mac->mac_phy.phy_write = bwn_phy_lp_write;
1421 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset;
1422 mac->mac_phy.rf_read = bwn_phy_lp_rf_read;
1423 mac->mac_phy.rf_write = bwn_phy_lp_rf_write;
1424 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff;
1425 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog;
1426 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel;
1427 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan;
1428 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna;
1429 mac->mac_phy.task_60s = bwn_phy_lp_task_60s;
1430 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) {
1431 mac->mac_phy.attach = bwn_phy_n_attach;
1432 mac->mac_phy.detach = bwn_phy_n_detach;
1433 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw;
1434 mac->mac_phy.init_pre = bwn_phy_n_init_pre;
1435 mac->mac_phy.init = bwn_phy_n_init;
1436 mac->mac_phy.exit = bwn_phy_n_exit;
1437 mac->mac_phy.phy_read = bwn_phy_n_read;
1438 mac->mac_phy.phy_write = bwn_phy_n_write;
1439 mac->mac_phy.rf_read = bwn_phy_n_rf_read;
1440 mac->mac_phy.rf_write = bwn_phy_n_rf_write;
1441 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl;
1442 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff;
1443 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog;
1444 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel;
1445 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan;
1446 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna;
1447 mac->mac_phy.set_im = bwn_phy_n_im;
1448 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr;
1449 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr;
1450 mac->mac_phy.task_15s = bwn_phy_n_task_15s;
1451 mac->mac_phy.task_60s = bwn_phy_n_task_60s;
1453 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n",
1459 mac->mac_phy.gmode = have_bg;
1460 if (mac->mac_phy.attach != NULL) {
1461 error = mac->mac_phy.attach(mac);
1463 device_printf(sc->sc_dev, "failed\n");
1468 error = bwn_reset_core(mac, have_bg);
1472 error = bwn_chiptest(mac);
1475 error = bwn_setup_channels(mac, have_bg, have_a);
1477 device_printf(sc->sc_dev, "failed to setup channels\n");
1481 if (sc->sc_curmac == NULL)
1482 sc->sc_curmac = mac;
1484 error = bwn_dma_attach(mac);
1486 device_printf(sc->sc_dev, "failed to initialize DMA\n");
1490 mac->mac_phy.switch_analog(mac, 0);
1493 bhnd_suspend_hw(sc->sc_dev, 0);
1494 bwn_release_firmware(mac);
1502 bwn_reset_core(struct bwn_mac *mac, int g_mode)
1504 struct bwn_softc *sc;
1506 uint16_t ioctl, ioctl_mask;
1511 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
1514 ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET);
1516 ioctl |= BWN_IOCTL_SUPPORT_G;
1518 /* XXX N-PHY only; and hard-code to 20MHz for now */
1519 if (mac->mac_phy.type == BWN_PHYTYPE_N)
1520 ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ;
1522 if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) {
1523 device_printf(sc->sc_dev, "core reset failed: %d", error);
1529 /* Take PHY out of reset */
1530 ioctl = BHND_IOCTL_CLK_FORCE;
1531 ioctl_mask = BHND_IOCTL_CLK_FORCE |
1532 BWN_IOCTL_PHYRESET |
1533 BWN_IOCTL_PHYCLOCK_ENABLE;
1535 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
1536 device_printf(sc->sc_dev, "failed to set core ioctl flags: "
1543 ioctl = BWN_IOCTL_PHYCLOCK_ENABLE;
1544 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
1545 device_printf(sc->sc_dev, "failed to set core ioctl flags: "
1552 if (mac->mac_phy.switch_analog != NULL)
1553 mac->mac_phy.switch_analog(mac, 1);
1555 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1557 ctl |= BWN_MACCTL_GMODE;
1558 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1564 bwn_phy_getinfo(struct bwn_mac *mac, int gmode)
1566 struct bwn_phy *phy = &mac->mac_phy;
1567 struct bwn_softc *sc = mac->mac_sc;
1571 tmp = BWN_READ_2(mac, BWN_PHYVER);
1574 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1575 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1576 phy->rev = (tmp & BWN_PHYVER_VERSION);
1577 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1578 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1579 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1580 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1581 (phy->type == BWN_PHYTYPE_N && phy->rev > 6) ||
1582 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1586 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1587 tmp = BWN_READ_2(mac, BWN_RFDATALO);
1588 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1589 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
1591 phy->rf_rev = (tmp & 0xf0000000) >> 28;
1592 phy->rf_ver = (tmp & 0x0ffff000) >> 12;
1593 phy->rf_manuf = (tmp & 0x00000fff);
1596 * For now, just always do full init (ie, what bwn has traditionally
1599 phy->phy_do_full_init = 1;
1601 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */
1603 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 ||
1604 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) ||
1605 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) ||
1606 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) ||
1607 (phy->type == BWN_PHYTYPE_N &&
1608 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) ||
1609 (phy->type == BWN_PHYTYPE_LP &&
1610 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063))
1615 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, "
1617 phy->type, phy->rev, phy->analog);
1620 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, "
1622 phy->rf_manuf, phy->rf_ver, phy->rf_rev);
1627 bwn_chiptest(struct bwn_mac *mac)
1629 #define TESTVAL0 0x55aaaa55
1630 #define TESTVAL1 0xaa5555aa
1631 struct bwn_softc *sc = mac->mac_sc;
1636 backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1638 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1639 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1641 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1642 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1645 bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1647 if ((bhnd_get_hwrev(sc->sc_dev) >= 3) &&
1648 (bhnd_get_hwrev(sc->sc_dev) <= 10)) {
1649 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1650 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1651 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1653 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1656 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);
1658 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE;
1659 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON))
1666 device_printf(sc->sc_dev, "failed to validate the chipaccess\n");
1671 bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a)
1673 struct bwn_softc *sc = mac->mac_sc;
1674 struct ieee80211com *ic = &sc->sc_ic;
1675 uint8_t bands[IEEE80211_MODE_BYTES];
1677 memset(ic->ic_channels, 0, sizeof(ic->ic_channels));
1680 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n",
1686 memset(bands, 0, sizeof(bands));
1687 setbit(bands, IEEE80211_MODE_11B);
1688 setbit(bands, IEEE80211_MODE_11G);
1689 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1690 &ic->ic_nchans, &bwn_chantable_bg, bands);
1694 memset(bands, 0, sizeof(bands));
1695 setbit(bands, IEEE80211_MODE_11A);
1696 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1697 &ic->ic_nchans, &bwn_chantable_a, bands);
1700 mac->mac_phy.supports_2ghz = have_bg;
1701 mac->mac_phy.supports_5ghz = have_a;
1703 return (ic->ic_nchans == 0 ? ENXIO : 0);
1707 bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1711 BWN_ASSERT_LOCKED(mac->mac_sc);
1713 if (way == BWN_SHARED) {
1714 KASSERT((offset & 0x0001) == 0,
1715 ("%s:%d warn", __func__, __LINE__));
1716 if (offset & 0x0003) {
1717 bwn_shm_ctlword(mac, way, offset >> 2);
1718 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1720 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1721 ret |= BWN_READ_2(mac, BWN_SHM_DATA);
1726 bwn_shm_ctlword(mac, way, offset);
1727 ret = BWN_READ_4(mac, BWN_SHM_DATA);
1733 bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1737 BWN_ASSERT_LOCKED(mac->mac_sc);
1739 if (way == BWN_SHARED) {
1740 KASSERT((offset & 0x0001) == 0,
1741 ("%s:%d warn", __func__, __LINE__));
1742 if (offset & 0x0003) {
1743 bwn_shm_ctlword(mac, way, offset >> 2);
1744 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1749 bwn_shm_ctlword(mac, way, offset);
1750 ret = BWN_READ_2(mac, BWN_SHM_DATA);
1757 bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way,
1765 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control);
1769 bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1772 BWN_ASSERT_LOCKED(mac->mac_sc);
1774 if (way == BWN_SHARED) {
1775 KASSERT((offset & 0x0001) == 0,
1776 ("%s:%d warn", __func__, __LINE__));
1777 if (offset & 0x0003) {
1778 bwn_shm_ctlword(mac, way, offset >> 2);
1779 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED,
1780 (value >> 16) & 0xffff);
1781 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1782 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff);
1787 bwn_shm_ctlword(mac, way, offset);
1788 BWN_WRITE_4(mac, BWN_SHM_DATA, value);
1792 bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1795 BWN_ASSERT_LOCKED(mac->mac_sc);
1797 if (way == BWN_SHARED) {
1798 KASSERT((offset & 0x0001) == 0,
1799 ("%s:%d warn", __func__, __LINE__));
1800 if (offset & 0x0003) {
1801 bwn_shm_ctlword(mac, way, offset >> 2);
1802 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value);
1807 bwn_shm_ctlword(mac, way, offset);
1808 BWN_WRITE_2(mac, BWN_SHM_DATA, value);
1812 bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans,
1813 const struct bwn_channelinfo *ci, const uint8_t bands[])
1817 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) {
1818 const struct bwn_channel *hc = &ci->channels[i];
1820 error = ieee80211_add_channel(chans, maxchans, nchans,
1821 hc->ieee, hc->freq, hc->maxTxPow, 0, bands);
1826 bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1827 const struct ieee80211_bpf_params *params)
1829 struct ieee80211com *ic = ni->ni_ic;
1830 struct bwn_softc *sc = ic->ic_softc;
1831 struct bwn_mac *mac = sc->sc_curmac;
1834 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 ||
1835 mac->mac_status < BWN_MAC_STATUS_STARTED) {
1841 if (bwn_tx_isfull(sc, m)) {
1847 error = bwn_tx_start(sc, ni, m);
1849 sc->sc_watchdog_timer = 5;
1855 * Callback from the 802.11 layer to update the slot time
1856 * based on the current setting. We use it to notify the
1857 * firmware of ERP changes and the f/w takes care of things
1858 * like slot time and preamble.
1861 bwn_updateslot(struct ieee80211com *ic)
1863 struct bwn_softc *sc = ic->ic_softc;
1864 struct bwn_mac *mac;
1867 if (sc->sc_flags & BWN_FLAG_RUNNING) {
1868 mac = (struct bwn_mac *)sc->sc_curmac;
1869 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic));
1875 * Callback from the 802.11 layer after a promiscuous mode change.
1876 * Note this interface does not check the operating mode as this
1877 * is an internal callback and we are expected to honor the current
1878 * state (e.g. this is used for setting the interface in promiscuous
1879 * mode when operating in hostap mode to do ACS).
1882 bwn_update_promisc(struct ieee80211com *ic)
1884 struct bwn_softc *sc = ic->ic_softc;
1885 struct bwn_mac *mac = sc->sc_curmac;
1888 mac = sc->sc_curmac;
1889 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1890 if (ic->ic_promisc > 0)
1891 sc->sc_filters |= BWN_MACCTL_PROMISC;
1893 sc->sc_filters &= ~BWN_MACCTL_PROMISC;
1894 bwn_set_opmode(mac);
1900 * Callback from the 802.11 layer to update WME parameters.
1903 bwn_wme_update(struct ieee80211com *ic)
1905 struct bwn_softc *sc = ic->ic_softc;
1906 struct bwn_mac *mac = sc->sc_curmac;
1907 struct chanAccParams chp;
1908 struct wmeParams *wmep;
1911 ieee80211_wme_ic_getparams(ic, &chp);
1914 mac = sc->sc_curmac;
1915 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1916 bwn_mac_suspend(mac);
1917 for (i = 0; i < N(sc->sc_wmeParams); i++) {
1918 wmep = &chp.cap_wmeParams[i];
1919 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]);
1921 bwn_mac_enable(mac);
1928 bwn_scan_start(struct ieee80211com *ic)
1930 struct bwn_softc *sc = ic->ic_softc;
1931 struct bwn_mac *mac;
1934 mac = sc->sc_curmac;
1935 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1936 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC;
1937 bwn_set_opmode(mac);
1938 /* disable CFP update during scan */
1939 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE);
1945 bwn_scan_end(struct ieee80211com *ic)
1947 struct bwn_softc *sc = ic->ic_softc;
1948 struct bwn_mac *mac;
1951 mac = sc->sc_curmac;
1952 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1953 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC;
1954 bwn_set_opmode(mac);
1955 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE);
1961 bwn_set_channel(struct ieee80211com *ic)
1963 struct bwn_softc *sc = ic->ic_softc;
1964 struct bwn_mac *mac = sc->sc_curmac;
1965 struct bwn_phy *phy = &mac->mac_phy;
1970 error = bwn_switch_band(sc, ic->ic_curchan);
1973 bwn_mac_suspend(mac);
1974 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
1975 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1976 if (chan != phy->chan)
1977 bwn_switch_channel(mac, chan);
1979 /* TX power level */
1980 if (ic->ic_curchan->ic_maxpower != 0 &&
1981 ic->ic_curchan->ic_maxpower != phy->txpower) {
1982 phy->txpower = ic->ic_curchan->ic_maxpower / 2;
1983 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME |
1984 BWN_TXPWR_IGNORE_TSSI);
1987 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
1988 if (phy->set_antenna)
1989 phy->set_antenna(mac, BWN_ANT_DEFAULT);
1991 if (sc->sc_rf_enabled != phy->rf_on) {
1992 if (sc->sc_rf_enabled) {
1994 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON))
1995 device_printf(sc->sc_dev,
1996 "please turn on the RF switch\n");
1998 bwn_rf_turnoff(mac);
2001 bwn_mac_enable(mac);
2005 * Setup radio tap channel freq and flags
2007 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2008 htole16(ic->ic_curchan->ic_freq);
2009 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2010 htole16(ic->ic_curchan->ic_flags & 0xffff);
2015 static struct ieee80211vap *
2016 bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
2017 enum ieee80211_opmode opmode, int flags,
2018 const uint8_t bssid[IEEE80211_ADDR_LEN],
2019 const uint8_t mac[IEEE80211_ADDR_LEN])
2021 struct ieee80211vap *vap;
2022 struct bwn_vap *bvp;
2025 case IEEE80211_M_HOSTAP:
2026 case IEEE80211_M_MBSS:
2027 case IEEE80211_M_STA:
2028 case IEEE80211_M_WDS:
2029 case IEEE80211_M_MONITOR:
2030 case IEEE80211_M_IBSS:
2031 case IEEE80211_M_AHDEMO:
2037 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
2039 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
2040 /* override with driver methods */
2041 bvp->bv_newstate = vap->iv_newstate;
2042 vap->iv_newstate = bwn_newstate;
2044 /* override max aid so sta's cannot assoc when we're out of sta id's */
2045 vap->iv_max_aid = BWN_STAID_MAX;
2047 ieee80211_ratectl_init(vap);
2049 /* complete setup */
2050 ieee80211_vap_attach(vap, ieee80211_media_change,
2051 ieee80211_media_status, mac);
2056 bwn_vap_delete(struct ieee80211vap *vap)
2058 struct bwn_vap *bvp = BWN_VAP(vap);
2060 ieee80211_ratectl_deinit(vap);
2061 ieee80211_vap_detach(vap);
2062 free(bvp, M_80211_VAP);
2066 bwn_init(struct bwn_softc *sc)
2068 struct bwn_mac *mac;
2071 BWN_ASSERT_LOCKED(sc);
2073 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2075 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN);
2076 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP;
2079 sc->sc_beacons[0] = sc->sc_beacons[1] = 0;
2080 sc->sc_rf_enabled = 1;
2082 mac = sc->sc_curmac;
2083 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) {
2084 error = bwn_core_init(mac);
2088 if (mac->mac_status == BWN_MAC_STATUS_INITED)
2089 bwn_core_start(mac);
2091 bwn_set_opmode(mac);
2092 bwn_set_pretbtt(mac);
2093 bwn_spu_setdelay(mac, 0);
2094 bwn_set_macaddr(mac);
2096 sc->sc_flags |= BWN_FLAG_RUNNING;
2097 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc);
2098 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc);
2104 bwn_stop(struct bwn_softc *sc)
2106 struct bwn_mac *mac = sc->sc_curmac;
2108 BWN_ASSERT_LOCKED(sc);
2110 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2112 if (mac->mac_status >= BWN_MAC_STATUS_INITED) {
2113 /* XXX FIXME opmode not based on VAP */
2114 bwn_set_opmode(mac);
2115 bwn_set_macaddr(mac);
2118 if (mac->mac_status >= BWN_MAC_STATUS_STARTED)
2121 callout_stop(&sc->sc_led_blink_ch);
2122 sc->sc_led_blinking = 0;
2125 sc->sc_rf_enabled = 0;
2127 sc->sc_flags &= ~BWN_FLAG_RUNNING;
2131 bwn_wme_clear(struct bwn_softc *sc)
2133 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
2134 struct wmeParams *p;
2137 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
2138 ("%s:%d: fail", __func__, __LINE__));
2140 for (i = 0; i < N(sc->sc_wmeParams); i++) {
2141 p = &(sc->sc_wmeParams[i]);
2143 switch (bwn_wme_shm_offsets[i]) {
2145 p->wmep_txopLimit = 0;
2147 /* XXX FIXME: log2(cwmin) */
2148 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2149 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
2152 p->wmep_txopLimit = 0;
2154 /* XXX FIXME: log2(cwmin) */
2155 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2156 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
2158 case BWN_WME_BESTEFFORT:
2159 p->wmep_txopLimit = 0;
2161 /* XXX FIXME: log2(cwmin) */
2162 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2163 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
2165 case BWN_WME_BACKGROUND:
2166 p->wmep_txopLimit = 0;
2168 /* XXX FIXME: log2(cwmin) */
2169 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2170 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
2173 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2179 bwn_core_forceclk(struct bwn_mac *mac, bool force)
2181 struct bwn_softc *sc;
2187 /* On PMU equipped devices, we do not need to force the HT clock */
2188 if (sc->sc_pmu != NULL)
2191 /* Issue a PMU clock request */
2193 clock = BHND_CLOCK_HT;
2195 clock = BHND_CLOCK_DYN;
2197 if ((error = bhnd_request_clock(sc->sc_dev, clock))) {
2198 device_printf(sc->sc_dev, "%d clock request failed: %d\n",
2207 bwn_core_init(struct bwn_mac *mac)
2209 struct bwn_softc *sc = mac->mac_sc;
2213 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2214 ("%s:%d: fail", __func__, __LINE__));
2216 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2218 if ((error = bwn_core_forceclk(mac, true)))
2221 if (bhnd_is_hw_suspended(sc->sc_dev)) {
2222 if ((error = bwn_reset_core(mac, mac->mac_phy.gmode)))
2226 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
2227 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
2228 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
2229 BWN_GETTIME(mac->mac_phy.nexttime);
2230 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
2231 bzero(&mac->mac_stats, sizeof(mac->mac_stats));
2232 mac->mac_stats.link_noise = -95;
2233 mac->mac_reason_intr = 0;
2234 bzero(mac->mac_reason, sizeof(mac->mac_reason));
2235 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE;
2237 if (sc->sc_debug & BWN_DEBUG_XMIT)
2238 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
2240 mac->mac_suspended = 1;
2241 mac->mac_task_state = 0;
2242 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
2244 mac->mac_phy.init_pre(mac);
2246 bwn_bt_disable(mac);
2247 if (mac->mac_phy.prepare_hw) {
2248 error = mac->mac_phy.prepare_hw(mac);
2252 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__);
2253 error = bwn_chip_init(mac);
2256 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
2257 bhnd_get_hwrev(sc->sc_dev));
2258 hf = bwn_hf_read(mac);
2259 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
2260 hf |= BWN_HF_GPHY_SYM_WORKAROUND;
2261 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
2262 hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
2263 if (mac->mac_phy.rev == 1)
2264 hf |= BWN_HF_GPHY_DC_CANCELFILTER;
2266 if (mac->mac_phy.rf_ver == 0x2050) {
2267 if (mac->mac_phy.rf_rev < 6)
2268 hf |= BWN_HF_FORCE_VCO_RECALC;
2269 if (mac->mac_phy.rf_rev == 6)
2270 hf |= BWN_HF_4318_TSSI;
2272 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
2273 hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
2274 if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR)
2275 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
2276 hf &= ~BWN_HF_SKIP_CFP_UPDATE;
2277 bwn_hf_write(mac, hf);
2279 /* Tell the firmware about the MAC capabilities */
2280 if (bhnd_get_hwrev(sc->sc_dev) >= 13) {
2282 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
2283 DPRINTF(sc, BWN_DEBUG_RESET,
2284 "%s: hw capabilities: 0x%08x\n",
2286 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L,
2288 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H,
2289 (cap >> 16) & 0xffff);
2292 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
2293 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
2294 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
2295 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
2298 bwn_set_phytxctl(mac);
2300 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
2301 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
2302 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
2304 if (sc->sc_quirks & BWN_QUIRK_NODMA)
2309 bwn_spu_setdelay(mac, 1);
2312 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
2313 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
2314 bwn_core_forceclk(mac, true);
2316 bwn_core_forceclk(mac, false);
2318 bwn_set_macaddr(mac);
2319 bwn_crypt_init(mac);
2321 /* XXX LED initializatin */
2323 mac->mac_status = BWN_MAC_STATUS_INITED;
2325 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__);
2329 bhnd_suspend_hw(sc->sc_dev, 0);
2330 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2331 ("%s:%d: fail", __func__, __LINE__));
2332 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
2337 bwn_core_start(struct bwn_mac *mac)
2339 struct bwn_softc *sc = mac->mac_sc;
2342 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
2343 ("%s:%d: fail", __func__, __LINE__));
2345 if (bhnd_get_hwrev(sc->sc_dev) < 5)
2349 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
2350 if (!(tmp & 0x00000001))
2352 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
2355 bwn_mac_enable(mac);
2356 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
2357 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
2359 mac->mac_status = BWN_MAC_STATUS_STARTED;
2363 bwn_core_exit(struct bwn_mac *mac)
2365 struct bwn_softc *sc = mac->mac_sc;
2368 BWN_ASSERT_LOCKED(mac->mac_sc);
2370 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
2371 ("%s:%d: fail", __func__, __LINE__));
2373 if (mac->mac_status != BWN_MAC_STATUS_INITED)
2375 mac->mac_status = BWN_MAC_STATUS_UNINIT;
2377 macctl = BWN_READ_4(mac, BWN_MACCTL);
2378 macctl &= ~BWN_MACCTL_MCODE_RUN;
2379 macctl |= BWN_MACCTL_MCODE_JMP0;
2380 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2385 mac->mac_phy.switch_analog(mac, 0);
2386 bhnd_suspend_hw(sc->sc_dev, 0);
2390 bwn_bt_disable(struct bwn_mac *mac)
2392 struct bwn_softc *sc = mac->mac_sc;
2395 /* XXX do nothing yet */
2399 bwn_chip_init(struct bwn_mac *mac)
2401 struct bwn_softc *sc = mac->mac_sc;
2402 struct bwn_phy *phy = &mac->mac_phy;
2407 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
2409 macctl |= BWN_MACCTL_GMODE;
2410 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2412 error = bwn_fw_fillinfo(mac);
2415 error = bwn_fw_loaducode(mac);
2419 error = bwn_gpio_init(mac);
2423 error = bwn_fw_loadinitvals(mac);
2427 phy->switch_analog(mac, 1);
2428 error = bwn_phy_init(mac);
2433 phy->set_im(mac, BWN_IMMODE_NONE);
2434 if (phy->set_antenna)
2435 phy->set_antenna(mac, BWN_ANT_DEFAULT);
2436 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
2438 if (phy->type == BWN_PHYTYPE_B)
2439 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
2440 BWN_WRITE_4(mac, 0x0100, 0x01000000);
2441 if (bhnd_get_hwrev(sc->sc_dev) < 5)
2442 BWN_WRITE_4(mac, 0x010c, 0x01000000);
2444 BWN_WRITE_4(mac, BWN_MACCTL,
2445 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
2446 BWN_WRITE_4(mac, BWN_MACCTL,
2447 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
2448 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
2450 bwn_set_opmode(mac);
2451 if (bhnd_get_hwrev(sc->sc_dev) < 3) {
2452 BWN_WRITE_2(mac, 0x060e, 0x0000);
2453 BWN_WRITE_2(mac, 0x0610, 0x8000);
2454 BWN_WRITE_2(mac, 0x0604, 0x0000);
2455 BWN_WRITE_2(mac, 0x0606, 0x0200);
2457 BWN_WRITE_4(mac, 0x0188, 0x80000000);
2458 BWN_WRITE_4(mac, 0x018c, 0x02000000);
2460 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
2461 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
2462 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
2463 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
2464 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
2465 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
2466 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
2468 bwn_mac_phy_clock_set(mac, true);
2470 /* Provide the HT clock transition latency to the MAC core */
2471 error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay);
2473 device_printf(sc->sc_dev, "failed to fetch HT clock latency: "
2478 if (delay > UINT16_MAX) {
2479 device_printf(sc->sc_dev, "invalid HT clock latency: %u\n",
2484 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay);
2488 /* read hostflags */
2490 bwn_hf_read(struct bwn_mac *mac)
2494 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI);
2496 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI);
2498 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO);
2503 bwn_hf_write(struct bwn_mac *mac, uint64_t value)
2506 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO,
2507 (value & 0x00000000ffffull));
2508 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI,
2509 (value & 0x0000ffff0000ull) >> 16);
2510 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI,
2511 (value & 0xffff00000000ULL) >> 32);
2515 bwn_set_txretry(struct bwn_mac *mac, int s, int l)
2518 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf));
2519 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf));
2523 bwn_rate_init(struct bwn_mac *mac)
2526 switch (mac->mac_phy.type) {
2529 case BWN_PHYTYPE_LP:
2531 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1);
2532 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1);
2533 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1);
2534 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1);
2535 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1);
2536 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1);
2537 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1);
2538 if (mac->mac_phy.type == BWN_PHYTYPE_A)
2542 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0);
2543 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0);
2544 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0);
2545 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0);
2548 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2553 bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm)
2559 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2;
2562 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2;
2564 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20,
2565 bwn_shm_read_2(mac, BWN_SHARED, offset));
2569 bwn_plcp_getcck(const uint8_t bitrate)
2573 case BWN_CCK_RATE_1MB:
2575 case BWN_CCK_RATE_2MB:
2577 case BWN_CCK_RATE_5MB:
2579 case BWN_CCK_RATE_11MB:
2582 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2587 bwn_plcp_getofdm(const uint8_t bitrate)
2591 case BWN_OFDM_RATE_6MB:
2593 case BWN_OFDM_RATE_9MB:
2595 case BWN_OFDM_RATE_12MB:
2597 case BWN_OFDM_RATE_18MB:
2599 case BWN_OFDM_RATE_24MB:
2601 case BWN_OFDM_RATE_36MB:
2603 case BWN_OFDM_RATE_48MB:
2605 case BWN_OFDM_RATE_54MB:
2608 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2613 bwn_set_phytxctl(struct bwn_mac *mac)
2617 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO |
2619 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl);
2620 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl);
2621 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl);
2625 bwn_pio_init(struct bwn_mac *mac)
2627 struct bwn_pio *pio = &mac->mac_method.pio;
2629 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL)
2630 & ~BWN_MACCTL_BIGENDIAN);
2631 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0);
2633 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0);
2634 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1);
2635 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2);
2636 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3);
2637 bwn_pio_set_txqueue(mac, &pio->mcast, 4);
2638 bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
2642 bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2645 struct bwn_pio_txpkt *tp;
2646 struct bwn_softc *sc = mac->mac_sc;
2649 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
2650 tq->tq_index = index;
2652 tq->tq_free = BWN_PIO_MAX_TXPACKETS;
2653 if (bhnd_get_hwrev(sc->sc_dev) >= 8)
2656 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
2660 TAILQ_INIT(&tq->tq_pktlist);
2661 for (i = 0; i < N(tq->tq_pkts); i++) {
2662 tp = &(tq->tq_pkts[i]);
2665 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
2670 bwn_pio_idx2base(struct bwn_mac *mac, int index)
2672 struct bwn_softc *sc = mac->mac_sc;
2673 static const uint16_t bases[] = {
2683 static const uint16_t bases_rev11[] = {
2692 if (bhnd_get_hwrev(sc->sc_dev) >= 11) {
2693 if (index >= N(bases_rev11))
2694 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2695 return (bases_rev11[index]);
2697 if (index >= N(bases))
2698 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2699 return (bases[index]);
2703 bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
2706 struct bwn_softc *sc = mac->mac_sc;
2709 prq->prq_rev = bhnd_get_hwrev(sc->sc_dev);
2710 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
2711 bwn_dma_rxdirectfifo(mac, index, 1);
2715 bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
2719 bwn_pio_cancel_tx_packets(tq);
2723 bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio)
2726 bwn_destroy_pioqueue_tx(pio);
2730 bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2734 return (BWN_READ_2(mac, tq->tq_base + offset));
2738 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
2743 base = bwn_dma_base(mac->mac_dmatype, idx);
2744 if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) {
2745 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
2746 ctl &= ~BWN_DMA64_RXDIRECTFIFO;
2748 ctl |= BWN_DMA64_RXDIRECTFIFO;
2749 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl);
2751 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL);
2752 ctl &= ~BWN_DMA32_RXDIRECTFIFO;
2754 ctl |= BWN_DMA32_RXDIRECTFIFO;
2755 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl);
2760 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
2762 struct bwn_pio_txpkt *tp;
2765 for (i = 0; i < N(tq->tq_pkts); i++) {
2766 tp = &(tq->tq_pkts[i]);
2775 bwn_dma_base(int type, int controller_idx)
2777 static const uint16_t map64[] = {
2785 static const uint16_t map32[] = {
2794 if (type == BHND_DMA_ADDR_64BIT) {
2795 KASSERT(controller_idx >= 0 && controller_idx < N(map64),
2796 ("%s:%d: fail", __func__, __LINE__));
2797 return (map64[controller_idx]);
2799 KASSERT(controller_idx >= 0 && controller_idx < N(map32),
2800 ("%s:%d: fail", __func__, __LINE__));
2801 return (map32[controller_idx]);
2805 bwn_dma_init(struct bwn_mac *mac)
2807 struct bwn_dma *dma = &mac->mac_method.dma;
2809 /* setup TX DMA channels. */
2810 bwn_dma_setup(dma->wme[WME_AC_BK]);
2811 bwn_dma_setup(dma->wme[WME_AC_BE]);
2812 bwn_dma_setup(dma->wme[WME_AC_VI]);
2813 bwn_dma_setup(dma->wme[WME_AC_VO]);
2814 bwn_dma_setup(dma->mcast);
2815 /* setup RX DMA channel. */
2816 bwn_dma_setup(dma->rx);
2819 static struct bwn_dma_ring *
2820 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
2823 struct bwn_dma *dma = &mac->mac_method.dma;
2824 struct bwn_dma_ring *dr;
2825 struct bwn_dmadesc_generic *desc;
2826 struct bwn_dmadesc_meta *mt;
2827 struct bwn_softc *sc = mac->mac_sc;
2830 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO);
2833 dr->dr_numslots = BWN_RXRING_SLOTS;
2835 dr->dr_numslots = BWN_TXRING_SLOTS;
2837 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta),
2838 M_DEVBUF, M_NOWAIT | M_ZERO);
2839 if (dr->dr_meta == NULL)
2842 dr->dr_type = mac->mac_dmatype;
2844 dr->dr_base = bwn_dma_base(dr->dr_type, controller_index);
2845 dr->dr_index = controller_index;
2846 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
2847 dr->getdesc = bwn_dma_64_getdesc;
2848 dr->setdesc = bwn_dma_64_setdesc;
2849 dr->start_transfer = bwn_dma_64_start_transfer;
2850 dr->suspend = bwn_dma_64_suspend;
2851 dr->resume = bwn_dma_64_resume;
2852 dr->get_curslot = bwn_dma_64_get_curslot;
2853 dr->set_curslot = bwn_dma_64_set_curslot;
2855 dr->getdesc = bwn_dma_32_getdesc;
2856 dr->setdesc = bwn_dma_32_setdesc;
2857 dr->start_transfer = bwn_dma_32_start_transfer;
2858 dr->suspend = bwn_dma_32_suspend;
2859 dr->resume = bwn_dma_32_resume;
2860 dr->get_curslot = bwn_dma_32_get_curslot;
2861 dr->set_curslot = bwn_dma_32_set_curslot;
2865 dr->dr_curslot = -1;
2867 if (dr->dr_index == 0) {
2868 switch (mac->mac_fw.fw_hdr_format) {
2869 case BWN_FW_HDR_351:
2870 case BWN_FW_HDR_410:
2872 BWN_DMA0_RX_BUFFERSIZE_FW351;
2873 dr->dr_frameoffset =
2874 BWN_DMA0_RX_FRAMEOFFSET_FW351;
2876 case BWN_FW_HDR_598:
2878 BWN_DMA0_RX_BUFFERSIZE_FW598;
2879 dr->dr_frameoffset =
2880 BWN_DMA0_RX_FRAMEOFFSET_FW598;
2884 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2887 error = bwn_dma_allocringmemory(dr);
2893 * Assumption: BWN_TXRING_SLOTS can be divided by
2894 * BWN_TX_SLOTS_PER_FRAME
2896 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0,
2897 ("%s:%d: fail", __func__, __LINE__));
2899 dr->dr_txhdr_cache = contigmalloc(
2900 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2901 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO,
2902 0, BUS_SPACE_MAXADDR, 8, 0);
2903 if (dr->dr_txhdr_cache == NULL) {
2904 device_printf(sc->sc_dev,
2905 "can't allocate TX header DMA memory\n");
2910 * Create TX ring DMA stuffs
2912 error = bus_dma_tag_create(dma->parent_dtag,
2919 BUS_SPACE_MAXSIZE_32BIT,
2922 &dr->dr_txring_dtag);
2924 device_printf(sc->sc_dev,
2925 "can't create TX ring DMA tag: TODO frees\n");
2929 for (i = 0; i < dr->dr_numslots; i += 2) {
2930 dr->getdesc(dr, i, &desc, &mt);
2932 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER;
2936 error = bus_dmamap_create(dr->dr_txring_dtag, 0,
2939 device_printf(sc->sc_dev,
2940 "can't create RX buf DMA map\n");
2944 dr->getdesc(dr, i + 1, &desc, &mt);
2946 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY;
2950 error = bus_dmamap_create(dma->txbuf_dtag, 0,
2953 device_printf(sc->sc_dev,
2954 "can't create RX buf DMA map\n");
2959 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2960 &dr->dr_spare_dmap);
2962 device_printf(sc->sc_dev,
2963 "can't create RX buf DMA map\n");
2964 goto out; /* XXX wrong! */
2967 for (i = 0; i < dr->dr_numslots; i++) {
2968 dr->getdesc(dr, i, &desc, &mt);
2970 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2973 device_printf(sc->sc_dev,
2974 "can't create RX buf DMA map\n");
2975 goto out; /* XXX wrong! */
2977 error = bwn_dma_newbuf(dr, desc, mt, 1);
2979 device_printf(sc->sc_dev,
2980 "failed to allocate RX buf\n");
2981 goto out; /* XXX wrong! */
2985 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
2986 BUS_DMASYNC_PREWRITE);
2988 dr->dr_usedslot = dr->dr_numslots;
2995 if (dr->dr_txhdr_cache != NULL) {
2996 contigfree(dr->dr_txhdr_cache,
2997 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2998 BWN_MAXTXHDRSIZE, M_DEVBUF);
3001 free(dr->dr_meta, M_DEVBUF);
3008 bwn_dma_ringfree(struct bwn_dma_ring **dr)
3014 bwn_dma_free_descbufs(*dr);
3015 bwn_dma_free_ringmemory(*dr);
3017 if ((*dr)->dr_txhdr_cache != NULL) {
3018 contigfree((*dr)->dr_txhdr_cache,
3019 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
3020 BWN_MAXTXHDRSIZE, M_DEVBUF);
3022 free((*dr)->dr_meta, M_DEVBUF);
3023 free(*dr, M_DEVBUF);
3029 bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot,
3030 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
3032 struct bwn_dmadesc32 *desc;
3034 *meta = &(dr->dr_meta[slot]);
3035 desc = dr->dr_ring_descbase;
3036 desc = &(desc[slot]);
3038 *gdesc = (struct bwn_dmadesc_generic *)desc;
3042 bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
3043 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
3044 int start, int end, int irq)
3046 struct bwn_dmadesc32 *descbase;
3047 struct bwn_dma *dma;
3048 struct bhnd_dma_translation *dt;
3049 uint32_t addr, addrext, ctl;
3052 descbase = dr->dr_ring_descbase;
3053 dma = &dr->dr_mac->mac_method.dma;
3054 dt = &dma->translation;
3056 slot = (int)(&(desc->dma.dma32) - descbase);
3057 KASSERT(slot >= 0 && slot < dr->dr_numslots,
3058 ("%s:%d: fail", __func__, __LINE__));
3060 addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
3061 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
3062 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
3063 if (slot == dr->dr_numslots - 1)
3064 ctl |= BWN_DMA32_DCTL_DTABLEEND;
3066 ctl |= BWN_DMA32_DCTL_FRAMESTART;
3068 ctl |= BWN_DMA32_DCTL_FRAMEEND;
3070 ctl |= BWN_DMA32_DCTL_IRQ;
3071 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT)
3072 & BWN_DMA32_DCTL_ADDREXT_MASK;
3074 desc->dma.dma32.control = htole32(ctl);
3075 desc->dma.dma32.address = htole32(addr);
3079 bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot)
3082 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX,
3083 (uint32_t)(slot * sizeof(struct bwn_dmadesc32)));
3087 bwn_dma_32_suspend(struct bwn_dma_ring *dr)
3090 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
3091 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND);
3095 bwn_dma_32_resume(struct bwn_dma_ring *dr)
3098 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
3099 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND);
3103 bwn_dma_32_get_curslot(struct bwn_dma_ring *dr)
3107 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS);
3108 val &= BWN_DMA32_RXDPTR;
3110 return (val / sizeof(struct bwn_dmadesc32));
3114 bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot)
3117 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX,
3118 (uint32_t) (slot * sizeof(struct bwn_dmadesc32)));
3122 bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot,
3123 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
3125 struct bwn_dmadesc64 *desc;
3127 *meta = &(dr->dr_meta[slot]);
3128 desc = dr->dr_ring_descbase;
3129 desc = &(desc[slot]);
3131 *gdesc = (struct bwn_dmadesc_generic *)desc;
3135 bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
3136 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
3137 int start, int end, int irq)
3139 struct bwn_dmadesc64 *descbase;
3140 struct bwn_dma *dma;
3141 struct bhnd_dma_translation *dt;
3143 uint32_t addrhi, addrlo;
3145 uint32_t ctl0, ctl1;
3149 descbase = dr->dr_ring_descbase;
3150 dma = &dr->dr_mac->mac_method.dma;
3151 dt = &dma->translation;
3153 slot = (int)(&(desc->dma.dma64) - descbase);
3154 KASSERT(slot >= 0 && slot < dr->dr_numslots,
3155 ("%s:%d: fail", __func__, __LINE__));
3157 addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
3158 addrhi = (addr >> 32);
3159 addrlo = (addr & UINT32_MAX);
3160 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
3163 if (slot == dr->dr_numslots - 1)
3164 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
3166 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
3168 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
3170 ctl0 |= BWN_DMA64_DCTL0_IRQ;
3173 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
3174 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
3175 & BWN_DMA64_DCTL1_ADDREXT_MASK;
3177 desc->dma.dma64.control0 = htole32(ctl0);
3178 desc->dma.dma64.control1 = htole32(ctl1);
3179 desc->dma.dma64.address_low = htole32(addrlo);
3180 desc->dma.dma64.address_high = htole32(addrhi);
3184 bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot)
3187 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX,
3188 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3192 bwn_dma_64_suspend(struct bwn_dma_ring *dr)
3195 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3196 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND);
3200 bwn_dma_64_resume(struct bwn_dma_ring *dr)
3203 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3204 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND);
3208 bwn_dma_64_get_curslot(struct bwn_dma_ring *dr)
3212 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS);
3213 val &= BWN_DMA64_RXSTATDPTR;
3215 return (val / sizeof(struct bwn_dmadesc64));
3219 bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot)
3222 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX,
3223 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3227 bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
3229 struct bwn_mac *mac = dr->dr_mac;
3230 struct bwn_dma *dma = &mac->mac_method.dma;
3231 struct bwn_softc *sc = mac->mac_sc;
3234 error = bus_dma_tag_create(dma->parent_dtag,
3239 BWN_DMA_RINGMEMSIZE,
3241 BUS_SPACE_MAXSIZE_32BIT,
3246 device_printf(sc->sc_dev,
3247 "can't create TX ring DMA tag: TODO frees\n");
3251 error = bus_dmamem_alloc(dr->dr_ring_dtag,
3252 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3255 device_printf(sc->sc_dev,
3256 "can't allocate DMA mem: TODO frees\n");
3259 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap,
3260 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE,
3261 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT);
3263 device_printf(sc->sc_dev,
3264 "can't load DMA mem: TODO free\n");
3272 bwn_dma_setup(struct bwn_dma_ring *dr)
3274 struct bwn_mac *mac;
3275 struct bwn_dma *dma;
3276 struct bhnd_dma_translation *dt;
3277 bhnd_addr_t addr, paddr;
3278 uint32_t addrhi, addrlo, addrext, value;
3281 dma = &mac->mac_method.dma;
3282 dt = &dma->translation;
3284 paddr = dr->dr_ring_dmabase;
3285 addr = (paddr & dt->addr_mask) | dt->base_addr;
3286 addrhi = (addr >> 32);
3287 addrlo = (addr & UINT32_MAX);
3288 addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift);
3291 dr->dr_curslot = -1;
3293 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3294 value = BWN_DMA64_TXENABLE;
3295 value |= BWN_DMA64_TXPARITY_DISABLE;
3296 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
3297 & BWN_DMA64_TXADDREXT_MASK;
3298 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
3299 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo);
3300 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi);
3302 value = BWN_DMA32_TXENABLE;
3303 value |= BWN_DMA32_TXPARITY_DISABLE;
3304 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
3305 & BWN_DMA32_TXADDREXT_MASK;
3306 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
3307 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo);
3315 dr->dr_usedslot = dr->dr_numslots;
3317 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3318 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
3319 value |= BWN_DMA64_RXENABLE;
3320 value |= BWN_DMA64_RXPARITY_DISABLE;
3321 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
3322 & BWN_DMA64_RXADDREXT_MASK;
3323 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
3324 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo);
3325 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi);
3326 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
3327 sizeof(struct bwn_dmadesc64));
3329 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
3330 value |= BWN_DMA32_RXENABLE;
3331 value |= BWN_DMA32_RXPARITY_DISABLE;
3332 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
3333 & BWN_DMA32_RXADDREXT_MASK;
3334 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
3335 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo);
3336 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
3337 sizeof(struct bwn_dmadesc32));
3342 bwn_dma_free_ringmemory(struct bwn_dma_ring *dr)
3345 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap);
3346 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase,
3351 bwn_dma_cleanup(struct bwn_dma_ring *dr)
3355 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3356 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3357 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
3358 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
3360 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
3362 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3363 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3364 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
3365 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
3367 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0);
3372 bwn_dma_free_descbufs(struct bwn_dma_ring *dr)
3374 struct bwn_dmadesc_generic *desc;
3375 struct bwn_dmadesc_meta *meta;
3376 struct bwn_mac *mac = dr->dr_mac;
3377 struct bwn_dma *dma = &mac->mac_method.dma;
3378 struct bwn_softc *sc = mac->mac_sc;
3381 if (!dr->dr_usedslot)
3383 for (i = 0; i < dr->dr_numslots; i++) {
3384 dr->getdesc(dr, i, &desc, &meta);
3386 if (meta->mt_m == NULL) {
3388 device_printf(sc->sc_dev, "%s: not TX?\n",
3393 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
3394 bus_dmamap_unload(dr->dr_txring_dtag,
3396 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
3397 bus_dmamap_unload(dma->txbuf_dtag,
3400 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
3401 bwn_dma_free_descbuf(dr, meta);
3406 bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
3409 struct bwn_softc *sc = mac->mac_sc;
3414 for (i = 0; i < 10; i++) {
3415 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
3417 value = BWN_READ_4(mac, base + offset);
3418 if (type == BHND_DMA_ADDR_64BIT) {
3419 value &= BWN_DMA64_TXSTAT;
3420 if (value == BWN_DMA64_TXSTAT_DISABLED ||
3421 value == BWN_DMA64_TXSTAT_IDLEWAIT ||
3422 value == BWN_DMA64_TXSTAT_STOPPED)
3425 value &= BWN_DMA32_TXSTATE;
3426 if (value == BWN_DMA32_TXSTAT_DISABLED ||
3427 value == BWN_DMA32_TXSTAT_IDLEWAIT ||
3428 value == BWN_DMA32_TXSTAT_STOPPED)
3433 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL :
3435 BWN_WRITE_4(mac, base + offset, 0);
3436 for (i = 0; i < 10; i++) {
3437 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
3439 value = BWN_READ_4(mac, base + offset);
3440 if (type == BHND_DMA_ADDR_64BIT) {
3441 value &= BWN_DMA64_TXSTAT;
3442 if (value == BWN_DMA64_TXSTAT_DISABLED) {
3447 value &= BWN_DMA32_TXSTATE;
3448 if (value == BWN_DMA32_TXSTAT_DISABLED) {
3456 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3465 bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
3468 struct bwn_softc *sc = mac->mac_sc;
3473 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL :
3475 BWN_WRITE_4(mac, base + offset, 0);
3476 for (i = 0; i < 10; i++) {
3477 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS :
3479 value = BWN_READ_4(mac, base + offset);
3480 if (type == BHND_DMA_ADDR_64BIT) {
3481 value &= BWN_DMA64_RXSTAT;
3482 if (value == BWN_DMA64_RXSTAT_DISABLED) {
3487 value &= BWN_DMA32_RXSTATE;
3488 if (value == BWN_DMA32_RXSTAT_DISABLED) {
3496 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3504 bwn_dma_free_descbuf(struct bwn_dma_ring *dr,
3505 struct bwn_dmadesc_meta *meta)
3508 if (meta->mt_m != NULL) {
3509 m_freem(meta->mt_m);
3512 if (meta->mt_ni != NULL) {
3513 ieee80211_free_node(meta->mt_ni);
3519 bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3521 struct bwn_rxhdr4 *rxhdr;
3522 unsigned char *frame;
3524 rxhdr = mtod(m, struct bwn_rxhdr4 *);
3525 rxhdr->frame_len = 0;
3527 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset +
3528 sizeof(struct bwn_plcp6) + 2,
3529 ("%s:%d: fail", __func__, __LINE__));
3530 frame = mtod(m, char *) + dr->dr_frameoffset;
3531 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */);
3535 bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3537 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset;
3539 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7])
3544 bwn_wme_init(struct bwn_mac *mac)
3549 /* enable WME support. */
3550 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF);
3551 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) |
3552 BWN_IFSCTL_USE_EDCF);
3556 bwn_spu_setdelay(struct bwn_mac *mac, int idle)
3558 struct bwn_softc *sc = mac->mac_sc;
3559 struct ieee80211com *ic = &sc->sc_ic;
3560 uint16_t delay; /* microsec */
3562 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050;
3563 if (ic->ic_opmode == IEEE80211_M_IBSS || idle)
3565 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8))
3566 delay = max(delay, (uint16_t)2400);
3568 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
3572 bwn_bt_enable(struct bwn_mac *mac)
3574 struct bwn_softc *sc = mac->mac_sc;
3577 if (bwn_bluetooth == 0)
3579 if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0)
3581 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
3584 hf = bwn_hf_read(mac);
3585 if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO)
3586 hf |= BWN_HF_BT_COEXISTALT;
3588 hf |= BWN_HF_BT_COEXIST;
3589 bwn_hf_write(mac, hf);
3593 bwn_set_macaddr(struct bwn_mac *mac)
3596 bwn_mac_write_bssid(mac);
3597 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF,
3598 mac->mac_sc->sc_ic.ic_macaddr);
3602 bwn_clear_keys(struct bwn_mac *mac)
3606 for (i = 0; i < mac->mac_max_nr_keys; i++) {
3607 KASSERT(i >= 0 && i < mac->mac_max_nr_keys,
3608 ("%s:%d: fail", __func__, __LINE__));
3610 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE,
3611 NULL, BWN_SEC_KEYSIZE, NULL);
3612 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) {
3613 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE,
3614 NULL, BWN_SEC_KEYSIZE, NULL);
3616 mac->mac_key[i].keyconf = NULL;
3621 bwn_crypt_init(struct bwn_mac *mac)
3623 struct bwn_softc *sc = mac->mac_sc;
3625 mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20;
3626 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
3627 ("%s:%d: fail", __func__, __LINE__));
3628 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
3630 if (bhnd_get_hwrev(sc->sc_dev) >= 5)
3631 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
3632 bwn_clear_keys(mac);
3636 bwn_chip_exit(struct bwn_mac *mac)
3642 bwn_fw_fillinfo(struct bwn_mac *mac)
3646 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
3649 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
3656 * Request that the GPIO controller tristate all pins set in @p mask, granting
3657 * the MAC core control over the pins.
3659 * @param mac bwn MAC state.
3660 * @param pins If the bit position for a pin number is set to one, tristate the
3664 bwn_gpio_control(struct bwn_mac *mac, uint32_t pins)
3666 struct bwn_softc *sc;
3672 /* Determine desired pin flags */
3673 for (size_t pin = 0; pin < nitems(flags); pin++) {
3674 uint32_t pinbit = (1 << pin);
3676 if (pins & pinbit) {
3677 /* Tristate output */
3678 flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE;
3680 /* Leave unmodified */
3685 /* Configure all pins */
3686 error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags);
3688 device_printf(sc->sc_dev, "error configuring %s pin flags: "
3689 "%d\n", device_get_nameunit(sc->sc_gpio), error);
3698 bwn_gpio_init(struct bwn_mac *mac)
3700 struct bwn_softc *sc;
3707 BWN_WRITE_4(mac, BWN_MACCTL,
3708 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
3709 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3710 BWN_READ_2(mac, BWN_GPIO_MASK) | pins);
3712 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) {
3713 /* MAC core is responsible for toggling PAREF via gpio9 */
3714 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3715 BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL);
3717 pins |= BHND_GPIO_BOARD_PACTRL;
3720 return (bwn_gpio_control(mac, pins));
3724 bwn_fw_loadinitvals(struct bwn_mac *mac)
3726 #define GETFWOFFSET(fwp, offset) \
3727 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset))
3728 const size_t hdr_len = sizeof(struct bwn_fwhdr);
3729 const struct bwn_fwhdr *hdr;
3730 struct bwn_fw *fw = &mac->mac_fw;
3733 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data);
3734 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len),
3735 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len);
3738 if (fw->initvals_band.fw) {
3739 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data);
3740 error = bwn_fwinitvals_write(mac,
3741 GETFWOFFSET(fw->initvals_band, hdr_len),
3743 fw->initvals_band.fw->datasize - hdr_len);
3750 bwn_phy_init(struct bwn_mac *mac)
3752 struct bwn_softc *sc = mac->mac_sc;
3755 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac);
3756 mac->mac_phy.rf_onoff(mac, 1);
3757 error = mac->mac_phy.init(mac);
3759 device_printf(sc->sc_dev, "PHY init failed\n");
3762 error = bwn_switch_channel(mac,
3763 mac->mac_phy.get_default_chan(mac));
3765 device_printf(sc->sc_dev,
3766 "failed to switch default channel\n");
3771 if (mac->mac_phy.exit)
3772 mac->mac_phy.exit(mac);
3774 mac->mac_phy.rf_onoff(mac, 0);
3780 bwn_set_txantenna(struct bwn_mac *mac, int antenna)
3785 ant = bwn_ant2phy(antenna);
3788 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL);
3789 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3790 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp);
3791 /* For Probe Resposes */
3792 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL);
3793 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3794 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp);
3798 bwn_set_opmode(struct bwn_mac *mac)
3800 struct bwn_softc *sc = mac->mac_sc;
3801 struct ieee80211com *ic = &sc->sc_ic;
3803 uint16_t cfp_pretbtt;
3805 ctl = BWN_READ_4(mac, BWN_MACCTL);
3806 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL |
3807 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS |
3808 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC);
3809 ctl |= BWN_MACCTL_STA;
3811 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3812 ic->ic_opmode == IEEE80211_M_MBSS)
3813 ctl |= BWN_MACCTL_HOSTAP;
3814 else if (ic->ic_opmode == IEEE80211_M_IBSS)
3815 ctl &= ~BWN_MACCTL_STA;
3816 ctl |= sc->sc_filters;
3818 if (bhnd_get_hwrev(sc->sc_dev) <= 4)
3819 ctl |= BWN_MACCTL_PROMISC;
3821 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
3824 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
3825 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 &&
3826 sc->sc_cid.chip_rev == 3)
3831 BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
3835 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3838 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
3839 *((bus_addr_t *)arg) = seg->ds_addr;
3844 bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
3846 struct bwn_phy *phy = &mac->mac_phy;
3847 struct bwn_softc *sc = mac->mac_sc;
3848 unsigned int i, max_loop;
3850 uint32_t buffer[5] = {
3851 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
3856 buffer[0] = 0x000201cc;
3859 buffer[0] = 0x000b846e;
3862 BWN_ASSERT_LOCKED(mac->mac_sc);
3864 for (i = 0; i < 5; i++)
3865 bwn_ram_write(mac, i * 4, buffer[i]);
3867 BWN_WRITE_2(mac, 0x0568, 0x0000);
3868 BWN_WRITE_2(mac, 0x07c0,
3869 (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
3871 value = (ofdm ? 0x41 : 0x40);
3872 BWN_WRITE_2(mac, 0x050c, value);
3874 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP ||
3875 phy->type == BWN_PHYTYPE_LCN)
3876 BWN_WRITE_2(mac, 0x0514, 0x1a02);
3877 BWN_WRITE_2(mac, 0x0508, 0x0000);
3878 BWN_WRITE_2(mac, 0x050a, 0x0000);
3879 BWN_WRITE_2(mac, 0x054c, 0x0000);
3880 BWN_WRITE_2(mac, 0x056a, 0x0014);
3881 BWN_WRITE_2(mac, 0x0568, 0x0826);
3882 BWN_WRITE_2(mac, 0x0500, 0x0000);
3884 /* XXX TODO: n phy pa override? */
3886 switch (phy->type) {
3888 case BWN_PHYTYPE_LCN:
3889 BWN_WRITE_2(mac, 0x0502, 0x00d0);
3891 case BWN_PHYTYPE_LP:
3892 BWN_WRITE_2(mac, 0x0502, 0x0050);
3895 BWN_WRITE_2(mac, 0x0502, 0x0030);
3900 BWN_READ_2(mac, 0x0502);
3902 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3903 BWN_RF_WRITE(mac, 0x0051, 0x0017);
3904 for (i = 0x00; i < max_loop; i++) {
3905 value = BWN_READ_2(mac, 0x050e);
3910 for (i = 0x00; i < 0x0a; i++) {
3911 value = BWN_READ_2(mac, 0x050e);
3916 for (i = 0x00; i < 0x19; i++) {
3917 value = BWN_READ_2(mac, 0x0690);
3918 if (!(value & 0x0100))
3922 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3923 BWN_RF_WRITE(mac, 0x0051, 0x0037);
3927 bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
3931 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__));
3933 macctl = BWN_READ_4(mac, BWN_MACCTL);
3934 if (macctl & BWN_MACCTL_BIGENDIAN)
3935 printf("TODO: need swap\n");
3937 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
3938 BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE);
3939 BWN_WRITE_4(mac, BWN_RAM_DATA, val);
3943 bwn_mac_suspend(struct bwn_mac *mac)
3945 struct bwn_softc *sc = mac->mac_sc;
3949 KASSERT(mac->mac_suspended >= 0,
3950 ("%s:%d: fail", __func__, __LINE__));
3952 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3953 __func__, mac->mac_suspended);
3955 if (mac->mac_suspended == 0) {
3956 bwn_psctl(mac, BWN_PS_AWAKE);
3957 BWN_WRITE_4(mac, BWN_MACCTL,
3958 BWN_READ_4(mac, BWN_MACCTL)
3960 BWN_READ_4(mac, BWN_MACCTL);
3961 for (i = 35; i; i--) {
3962 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3963 if (tmp & BWN_INTR_MAC_SUSPENDED)
3967 for (i = 40; i; i--) {
3968 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3969 if (tmp & BWN_INTR_MAC_SUSPENDED)
3973 device_printf(sc->sc_dev, "MAC suspend failed\n");
3976 mac->mac_suspended++;
3980 bwn_mac_enable(struct bwn_mac *mac)
3982 struct bwn_softc *sc = mac->mac_sc;
3985 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3986 __func__, mac->mac_suspended);
3988 state = bwn_shm_read_2(mac, BWN_SHARED,
3989 BWN_SHARED_UCODESTAT);
3990 if (state != BWN_SHARED_UCODESTAT_SUSPEND &&
3991 state != BWN_SHARED_UCODESTAT_SLEEP) {
3992 DPRINTF(sc, BWN_DEBUG_FW,
3993 "%s: warn: firmware state (%d)\n",
3997 mac->mac_suspended--;
3998 KASSERT(mac->mac_suspended >= 0,
3999 ("%s:%d: fail", __func__, __LINE__));
4000 if (mac->mac_suspended == 0) {
4001 BWN_WRITE_4(mac, BWN_MACCTL,
4002 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON);
4003 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED);
4004 BWN_READ_4(mac, BWN_MACCTL);
4005 BWN_READ_4(mac, BWN_INTR_REASON);
4011 bwn_psctl(struct bwn_mac *mac, uint32_t flags)
4013 struct bwn_softc *sc = mac->mac_sc;
4017 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
4018 ("%s:%d: fail", __func__, __LINE__));
4019 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
4020 ("%s:%d: fail", __func__, __LINE__));
4022 /* XXX forcibly awake and hwps-off */
4024 BWN_WRITE_4(mac, BWN_MACCTL,
4025 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
4027 BWN_READ_4(mac, BWN_MACCTL);
4028 if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
4029 for (i = 0; i < 100; i++) {
4030 ucstat = bwn_shm_read_2(mac, BWN_SHARED,
4031 BWN_SHARED_UCODESTAT);
4032 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
4037 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__,
4042 bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
4044 struct bwn_softc *sc = mac->mac_sc;
4045 struct bwn_fw *fw = &mac->mac_fw;
4046 const uint8_t rev = bhnd_get_hwrev(sc->sc_dev);
4047 const char *filename;
4055 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
4056 filename = "ucode42";
4059 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
4060 filename = "ucode40";
4063 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40)
4064 filename = "ucode33_lcn40";
4067 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4068 filename = "ucode30_mimo";
4071 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
4072 filename = "ucode29_mimo";
4075 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
4076 filename = "ucode26_mimo";
4080 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4081 filename = "ucode25_mimo";
4082 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
4083 filename = "ucode25_lcn";
4086 if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
4087 filename = "ucode24_lcn";
4090 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4091 filename = "ucode16_mimo";
4097 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4098 filename = "ucode16_mimo";
4099 else if (mac->mac_phy.type == BWN_PHYTYPE_LP)
4100 filename = "ucode16_lp";
4103 filename = "ucode15";
4106 filename = "ucode14";
4109 filename = "ucode13";
4113 filename = "ucode11";
4121 filename = "ucode5";
4124 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev);
4125 bwn_release_firmware(mac);
4126 return (EOPNOTSUPP);
4129 device_printf(sc->sc_dev, "ucode fw: %s\n", filename);
4130 error = bwn_fw_get(mac, type, filename, &fw->ucode);
4132 bwn_release_firmware(mac);
4137 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__));
4138 if (rev >= 5 && rev <= 10) {
4139 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm);
4140 if (error == ENOENT)
4143 bwn_release_firmware(mac);
4146 } else if (rev < 11) {
4147 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
4148 bwn_release_firmware(mac);
4149 return (EOPNOTSUPP);
4153 error = bhnd_read_iost(sc->sc_dev, &iost);
4157 switch (mac->mac_phy.type) {
4159 if (rev < 5 || rev > 10)
4161 if (iost & BWN_IOST_HAVE_2GHZ)
4162 filename = "a0g1initvals5";
4164 filename = "a0g0initvals5";
4167 if (rev >= 5 && rev <= 10)
4168 filename = "b0g0initvals5";
4170 filename = "b0g0initvals13";
4174 case BWN_PHYTYPE_LP:
4176 filename = "lp0initvals13";
4178 filename = "lp0initvals14";
4180 filename = "lp0initvals15";
4186 filename = "n16initvals30";
4187 else if (rev == 28 || rev == 25)
4188 filename = "n0initvals25";
4190 filename = "n0initvals24";
4192 filename = "n0initvals16";
4193 else if (rev >= 16 && rev <= 18)
4194 filename = "n0initvals16";
4195 else if (rev >= 11 && rev <= 12)
4196 filename = "n0initvals11";
4203 error = bwn_fw_get(mac, type, filename, &fw->initvals);
4205 bwn_release_firmware(mac);
4209 /* bandswitch initvals */
4210 switch (mac->mac_phy.type) {
4212 if (rev >= 5 && rev <= 10) {
4213 if (iost & BWN_IOST_HAVE_2GHZ)
4214 filename = "a0g1bsinitvals5";
4216 filename = "a0g0bsinitvals5";
4217 } else if (rev >= 11)
4223 if (rev >= 5 && rev <= 10)
4224 filename = "b0g0bsinitvals5";
4230 case BWN_PHYTYPE_LP:
4232 filename = "lp0bsinitvals13";
4234 filename = "lp0bsinitvals14";
4236 filename = "lp0bsinitvals15";
4242 filename = "n16bsinitvals30";
4243 else if (rev == 28 || rev == 25)
4244 filename = "n0bsinitvals25";
4246 filename = "n0bsinitvals24";
4248 filename = "n0bsinitvals16";
4249 else if (rev >= 16 && rev <= 18)
4250 filename = "n0bsinitvals16";
4251 else if (rev >= 11 && rev <= 12)
4252 filename = "n0bsinitvals11";
4257 device_printf(sc->sc_dev, "unknown phy (%d)\n",
4261 error = bwn_fw_get(mac, type, filename, &fw->initvals_band);
4263 bwn_release_firmware(mac);
4268 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n",
4269 rev, mac->mac_phy.type);
4270 bwn_release_firmware(mac);
4271 return (EOPNOTSUPP);
4275 bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type,
4276 const char *name, struct bwn_fwfile *bfw)
4278 const struct bwn_fwhdr *hdr;
4279 struct bwn_softc *sc = mac->mac_sc;
4280 const struct firmware *fw;
4284 bwn_do_release_fw(bfw);
4287 if (bfw->filename != NULL) {
4288 if (bfw->type == type && (strcmp(bfw->filename, name) == 0))
4290 bwn_do_release_fw(bfw);
4293 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s",
4294 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "",
4295 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name);
4296 /* XXX Sleeping on "fwload" with the non-sleepable locks held */
4297 fw = firmware_get(namebuf);
4299 device_printf(sc->sc_dev, "the fw file(%s) not found\n",
4303 if (fw->datasize < sizeof(struct bwn_fwhdr))
4305 hdr = (const struct bwn_fwhdr *)(fw->data);
4306 switch (hdr->type) {
4307 case BWN_FWTYPE_UCODE:
4308 case BWN_FWTYPE_PCM:
4309 if (be32toh(hdr->size) !=
4310 (fw->datasize - sizeof(struct bwn_fwhdr)))
4320 bfw->filename = name;
4325 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf);
4327 firmware_put(fw, FIRMWARE_UNLOAD);
4332 bwn_release_firmware(struct bwn_mac *mac)
4335 bwn_do_release_fw(&mac->mac_fw.ucode);
4336 bwn_do_release_fw(&mac->mac_fw.pcm);
4337 bwn_do_release_fw(&mac->mac_fw.initvals);
4338 bwn_do_release_fw(&mac->mac_fw.initvals_band);
4342 bwn_do_release_fw(struct bwn_fwfile *bfw)
4345 if (bfw->fw != NULL)
4346 firmware_put(bfw->fw, FIRMWARE_UNLOAD);
4348 bfw->filename = NULL;
4352 bwn_fw_loaducode(struct bwn_mac *mac)
4354 #define GETFWOFFSET(fwp, offset) \
4355 ((const uint32_t *)((const char *)fwp.fw->data + offset))
4356 #define GETFWSIZE(fwp, offset) \
4357 ((fwp.fw->datasize - offset) / sizeof(uint32_t))
4358 struct bwn_softc *sc = mac->mac_sc;
4359 const uint32_t *data;
4362 uint16_t date, fwcaps, time;
4365 ctl = BWN_READ_4(mac, BWN_MACCTL);
4366 ctl |= BWN_MACCTL_MCODE_JMP0;
4367 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__,
4369 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4370 for (i = 0; i < 64; i++)
4371 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0);
4372 for (i = 0; i < 4096; i += 2)
4373 bwn_shm_write_2(mac, BWN_SHARED, i, 0);
4375 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4376 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000);
4377 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4379 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4383 if (mac->mac_fw.pcm.fw) {
4384 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr));
4385 bwn_shm_ctlword(mac, BWN_HW, 0x01ea);
4386 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000);
4387 bwn_shm_ctlword(mac, BWN_HW, 0x01eb);
4388 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm,
4389 sizeof(struct bwn_fwhdr)); i++) {
4390 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4395 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL);
4396 BWN_WRITE_4(mac, BWN_MACCTL,
4397 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) |
4398 BWN_MACCTL_MCODE_RUN);
4400 for (i = 0; i < 21; i++) {
4401 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED)
4404 device_printf(sc->sc_dev, "ucode timeout\n");
4410 BWN_READ_4(mac, BWN_INTR_REASON);
4412 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV);
4413 if (mac->mac_fw.rev <= 0x128) {
4414 device_printf(sc->sc_dev, "the firmware is too old\n");
4420 * Determine firmware header version; needed for TX/RX packet
4423 if (mac->mac_fw.rev >= 598)
4424 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598;
4425 else if (mac->mac_fw.rev >= 410)
4426 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410;
4428 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351;
4431 * We don't support rev 598 or later; that requires
4432 * another round of changes to the TX/RX descriptor
4433 * and status layout.
4435 * So, complain this is the case and exit out, rather
4436 * than attaching and then failing.
4439 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) {
4440 device_printf(sc->sc_dev,
4441 "firmware is too new (>=598); not supported\n");
4447 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED,
4448 BWN_SHARED_UCODE_PATCH);
4449 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE);
4450 mac->mac_fw.opensource = (date == 0xffff);
4452 mac->mac_flags |= BWN_MAC_FLAG_WME;
4453 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO;
4455 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME);
4456 if (mac->mac_fw.opensource == 0) {
4457 device_printf(sc->sc_dev,
4458 "firmware version (rev %u patch %u date %#x time %#x)\n",
4459 mac->mac_fw.rev, mac->mac_fw.patch, date, time);
4460 if (mac->mac_fw.no_pcmfile)
4461 device_printf(sc->sc_dev,
4462 "no HW crypto acceleration due to pcm5\n");
4464 mac->mac_fw.patch = time;
4465 fwcaps = bwn_fwcaps_read(mac);
4466 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) {
4467 device_printf(sc->sc_dev,
4468 "disabling HW crypto acceleration\n");
4469 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO;
4471 if (!(fwcaps & BWN_FWCAPS_WME)) {
4472 device_printf(sc->sc_dev, "disabling WME support\n");
4473 mac->mac_flags &= ~BWN_MAC_FLAG_WME;
4477 if (BWN_ISOLDFMT(mac))
4478 device_printf(sc->sc_dev, "using old firmware image\n");
4483 BWN_WRITE_4(mac, BWN_MACCTL,
4484 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) |
4485 BWN_MACCTL_MCODE_JMP0);
4492 /* OpenFirmware only */
4494 bwn_fwcaps_read(struct bwn_mac *mac)
4497 KASSERT(mac->mac_fw.opensource == 1,
4498 ("%s:%d: fail", __func__, __LINE__));
4499 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS));
4503 bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals,
4504 size_t count, size_t array_size)
4506 #define GET_NEXTIV16(iv) \
4507 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4508 sizeof(uint16_t) + sizeof(uint16_t)))
4509 #define GET_NEXTIV32(iv) \
4510 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4511 sizeof(uint16_t) + sizeof(uint32_t)))
4512 struct bwn_softc *sc = mac->mac_sc;
4513 const struct bwn_fwinitvals *iv;
4518 KASSERT(sizeof(struct bwn_fwinitvals) == 6,
4519 ("%s:%d: fail", __func__, __LINE__));
4521 for (i = 0; i < count; i++) {
4522 if (array_size < sizeof(iv->offset_size))
4524 array_size -= sizeof(iv->offset_size);
4525 offset = be16toh(iv->offset_size);
4526 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0;
4527 offset &= BWN_FWINITVALS_OFFSET_MASK;
4528 if (offset >= 0x1000)
4531 if (array_size < sizeof(iv->data.d32))
4533 array_size -= sizeof(iv->data.d32);
4534 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32));
4535 iv = GET_NEXTIV32(iv);
4538 if (array_size < sizeof(iv->data.d16))
4540 array_size -= sizeof(iv->data.d16);
4541 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16));
4543 iv = GET_NEXTIV16(iv);
4546 if (array_size != 0)
4550 device_printf(sc->sc_dev, "initvals: invalid format\n");
4557 bwn_switch_channel(struct bwn_mac *mac, int chan)
4559 struct bwn_phy *phy = &(mac->mac_phy);
4560 struct bwn_softc *sc = mac->mac_sc;
4561 struct ieee80211com *ic = &sc->sc_ic;
4562 uint16_t channelcookie, savedcookie;
4566 chan = phy->get_default_chan(mac);
4568 channelcookie = chan;
4569 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4570 channelcookie |= 0x100;
4571 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN);
4572 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie);
4573 error = phy->switch_channel(mac, chan);
4577 mac->mac_phy.chan = chan;
4581 device_printf(sc->sc_dev, "failed to switch channel\n");
4582 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie);
4587 bwn_ant2phy(int antenna)
4592 return (BWN_TX_PHY_ANT0);
4594 return (BWN_TX_PHY_ANT1);
4596 return (BWN_TX_PHY_ANT2);
4598 return (BWN_TX_PHY_ANT3);
4600 return (BWN_TX_PHY_ANT01AUTO);
4602 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4607 bwn_wme_load(struct bwn_mac *mac)
4609 struct bwn_softc *sc = mac->mac_sc;
4612 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
4613 ("%s:%d: fail", __func__, __LINE__));
4615 bwn_mac_suspend(mac);
4616 for (i = 0; i < N(sc->sc_wmeParams); i++)
4617 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]),
4618 bwn_wme_shm_offsets[i]);
4619 bwn_mac_enable(mac);
4623 bwn_wme_loadparams(struct bwn_mac *mac,
4624 const struct wmeParams *p, uint16_t shm_offset)
4626 #define SM(_v, _f) (((_v) << _f##_S) & _f)
4627 struct bwn_softc *sc = mac->mac_sc;
4628 uint16_t params[BWN_NR_WMEPARAMS];
4632 slot = BWN_READ_2(mac, BWN_RNG) &
4633 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4635 memset(¶ms, 0, sizeof(params));
4637 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d "
4638 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit,
4639 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn);
4641 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32;
4642 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4643 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX);
4644 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4645 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn;
4646 params[BWN_WMEPARAM_BSLOTS] = slot;
4647 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn;
4649 for (i = 0; i < N(params); i++) {
4650 if (i == BWN_WMEPARAM_STATUS) {
4651 tmp = bwn_shm_read_2(mac, BWN_SHARED,
4652 shm_offset + (i * 2));
4654 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4657 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4664 bwn_mac_write_bssid(struct bwn_mac *mac)
4666 struct bwn_softc *sc = mac->mac_sc;
4669 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2];
4671 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid);
4672 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN);
4673 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid,
4674 IEEE80211_ADDR_LEN);
4676 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) {
4677 tmp = (uint32_t) (mac_bssid[i + 0]);
4678 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8;
4679 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16;
4680 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24;
4681 bwn_ram_write(mac, 0x20 + i, tmp);
4686 bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset,
4687 const uint8_t *macaddr)
4689 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 };
4696 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset);
4699 data |= macaddr[1] << 8;
4700 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4702 data |= macaddr[3] << 8;
4703 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4705 data |= macaddr[5] << 8;
4706 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4710 bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4711 const uint8_t *key, size_t key_len, const uint8_t *mac_addr)
4713 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, };
4714 uint8_t per_sta_keys_start = 8;
4716 if (BWN_SEC_NEWAPI(mac))
4717 per_sta_keys_start = 4;
4719 KASSERT(index < mac->mac_max_nr_keys,
4720 ("%s:%d: fail", __func__, __LINE__));
4721 KASSERT(key_len <= BWN_SEC_KEYSIZE,
4722 ("%s:%d: fail", __func__, __LINE__));
4724 if (index >= per_sta_keys_start)
4725 bwn_key_macwrite(mac, index, NULL);
4727 memcpy(buf, key, key_len);
4728 bwn_key_write(mac, index, algorithm, buf);
4729 if (index >= per_sta_keys_start)
4730 bwn_key_macwrite(mac, index, mac_addr);
4732 mac->mac_key[index].algorithm = algorithm;
4736 bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
4738 struct bwn_softc *sc = mac->mac_sc;
4739 uint32_t addrtmp[2] = { 0, 0 };
4742 if (BWN_SEC_NEWAPI(mac))
4745 KASSERT(index >= start,
4746 ("%s:%d: fail", __func__, __LINE__));
4750 addrtmp[0] = addr[0];
4751 addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
4752 addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
4753 addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
4754 addrtmp[1] = addr[4];
4755 addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
4758 if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
4759 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
4760 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
4763 bwn_shm_write_4(mac, BWN_SHARED,
4764 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
4765 bwn_shm_write_2(mac, BWN_SHARED,
4766 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);
4772 bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4777 uint16_t kidx, value;
4779 kidx = BWN_SEC_KEY2FW(mac, index);
4780 bwn_shm_write_2(mac, BWN_SHARED,
4781 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm);
4783 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE);
4784 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) {
4786 value |= (uint16_t)(key[i + 1]) << 8;
4787 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value);
4792 bwn_phy_exit(struct bwn_mac *mac)
4795 mac->mac_phy.rf_onoff(mac, 0);
4796 if (mac->mac_phy.exit != NULL)
4797 mac->mac_phy.exit(mac);
4801 bwn_dma_free(struct bwn_mac *mac)
4803 struct bwn_dma *dma;
4805 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
4807 dma = &mac->mac_method.dma;
4809 bwn_dma_ringfree(&dma->rx);
4810 bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
4811 bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
4812 bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
4813 bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
4814 bwn_dma_ringfree(&dma->mcast);
4818 bwn_core_stop(struct bwn_mac *mac)
4820 struct bwn_softc *sc = mac->mac_sc;
4822 BWN_ASSERT_LOCKED(sc);
4824 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
4827 callout_stop(&sc->sc_rfswitch_ch);
4828 callout_stop(&sc->sc_task_ch);
4829 callout_stop(&sc->sc_watchdog_ch);
4830 sc->sc_watchdog_timer = 0;
4831 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4832 BWN_READ_4(mac, BWN_INTR_MASK);
4833 bwn_mac_suspend(mac);
4835 mac->mac_status = BWN_MAC_STATUS_INITED;
4839 bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
4841 struct bwn_mac *up_dev = NULL;
4842 struct bwn_mac *down_dev;
4843 struct bwn_mac *mac;
4847 BWN_ASSERT_LOCKED(sc);
4849 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) {
4850 if (IEEE80211_IS_CHAN_2GHZ(chan) &&
4851 mac->mac_phy.supports_2ghz) {
4854 } else if (IEEE80211_IS_CHAN_5GHZ(chan) &&
4855 mac->mac_phy.supports_5ghz) {
4859 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4865 if (up_dev == NULL) {
4866 device_printf(sc->sc_dev, "Could not find a device\n");
4869 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode)
4872 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET,
4873 "switching to %s-GHz band\n",
4874 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4876 down_dev = sc->sc_curmac;
4877 status = down_dev->mac_status;
4878 if (status >= BWN_MAC_STATUS_STARTED)
4879 bwn_core_stop(down_dev);
4880 if (status >= BWN_MAC_STATUS_INITED)
4881 bwn_core_exit(down_dev);
4883 if (down_dev != up_dev) {
4884 err = bwn_phy_reset(down_dev);
4889 up_dev->mac_phy.gmode = gmode;
4890 if (status >= BWN_MAC_STATUS_INITED) {
4891 err = bwn_core_init(up_dev);
4893 device_printf(sc->sc_dev,
4894 "fatal: failed to initialize for %s-GHz\n",
4895 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4899 if (status >= BWN_MAC_STATUS_STARTED)
4900 bwn_core_start(up_dev);
4901 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__));
4902 sc->sc_curmac = up_dev;
4906 sc->sc_curmac = NULL;
4911 bwn_rf_turnon(struct bwn_mac *mac)
4914 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4916 bwn_mac_suspend(mac);
4917 mac->mac_phy.rf_onoff(mac, 1);
4918 mac->mac_phy.rf_on = 1;
4919 bwn_mac_enable(mac);
4923 bwn_rf_turnoff(struct bwn_mac *mac)
4926 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4928 bwn_mac_suspend(mac);
4929 mac->mac_phy.rf_onoff(mac, 0);
4930 mac->mac_phy.rf_on = 0;
4931 bwn_mac_enable(mac);
4938 bwn_phy_reset(struct bwn_mac *mac)
4940 struct bwn_softc *sc;
4941 uint16_t iost, mask;
4946 iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE;
4947 mask = iost | BWN_IOCTL_SUPPORT_G;
4949 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
4954 iost &= ~BHND_IOCTL_CLK_FORCE;
4956 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
4965 bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
4967 struct bwn_vap *bvp = BWN_VAP(vap);
4968 struct ieee80211com *ic= vap->iv_ic;
4969 enum ieee80211_state ostate = vap->iv_state;
4970 struct bwn_softc *sc = ic->ic_softc;
4971 struct bwn_mac *mac = sc->sc_curmac;
4974 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4975 ieee80211_state_name[vap->iv_state],
4976 ieee80211_state_name[nstate]);
4978 error = bvp->bv_newstate(vap, nstate, arg);
4984 bwn_led_newstate(mac, nstate);
4987 * Clear the BSSID when we stop a STA
4989 if (vap->iv_opmode == IEEE80211_M_STA) {
4990 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
4992 * Clear out the BSSID. If we reassociate to
4993 * the same AP, this will reinialize things
4996 if (ic->ic_opmode == IEEE80211_M_STA &&
4997 (sc->sc_flags & BWN_FLAG_INVALID) == 0) {
4998 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN);
4999 bwn_set_macaddr(mac);
5004 if (vap->iv_opmode == IEEE80211_M_MONITOR ||
5005 vap->iv_opmode == IEEE80211_M_AHDEMO) {
5006 /* XXX nothing to do? */
5007 } else if (nstate == IEEE80211_S_RUN) {
5008 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN);
5009 bwn_set_opmode(mac);
5010 bwn_set_pretbtt(mac);
5011 bwn_spu_setdelay(mac, 0);
5012 bwn_set_macaddr(mac);
5021 bwn_set_pretbtt(struct bwn_mac *mac)
5023 struct bwn_softc *sc = mac->mac_sc;
5024 struct ieee80211com *ic = &sc->sc_ic;
5027 if (ic->ic_opmode == IEEE80211_M_IBSS)
5030 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250;
5031 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt);
5032 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
5038 struct bwn_mac *mac = arg;
5039 struct bwn_softc *sc = mac->mac_sc;
5042 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
5043 (sc->sc_flags & BWN_FLAG_INVALID))
5044 return (FILTER_STRAY);
5046 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__);
5048 reason = BWN_READ_4(mac, BWN_INTR_REASON);
5049 if (reason == 0xffffffff) /* shared IRQ */
5050 return (FILTER_STRAY);
5051 reason &= mac->mac_intr_mask;
5053 return (FILTER_HANDLED);
5054 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason);
5056 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00;
5057 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00;
5058 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00;
5059 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00;
5060 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00;
5061 BWN_WRITE_4(mac, BWN_INTR_REASON, reason);
5062 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]);
5063 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]);
5064 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]);
5065 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]);
5066 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]);
5068 /* Disable interrupts. */
5069 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
5071 mac->mac_reason_intr = reason;
5073 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
5075 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
5076 return (FILTER_HANDLED);
5080 bwn_intrtask(void *arg, int npending)
5082 struct bwn_mac *mac = arg;
5083 struct bwn_softc *sc = mac->mac_sc;
5084 uint32_t merged = 0;
5085 int i, tx = 0, rx = 0;
5088 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
5089 (sc->sc_flags & BWN_FLAG_INVALID)) {
5094 for (i = 0; i < N(mac->mac_reason); i++)
5095 merged |= mac->mac_reason[i];
5097 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)
5098 device_printf(sc->sc_dev, "MAC trans error\n");
5100 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) {
5101 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__);
5102 mac->mac_phy.txerrors--;
5103 if (mac->mac_phy.txerrors == 0) {
5104 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
5105 bwn_restart(mac, "PHY TX errors");
5109 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) {
5110 if (merged & BWN_DMAINTR_FATALMASK) {
5111 device_printf(sc->sc_dev,
5112 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n",
5113 mac->mac_reason[0], mac->mac_reason[1],
5114 mac->mac_reason[2], mac->mac_reason[3],
5115 mac->mac_reason[4], mac->mac_reason[5]);
5116 bwn_restart(mac, "DMA error");
5120 if (merged & BWN_DMAINTR_NONFATALMASK) {
5121 device_printf(sc->sc_dev,
5122 "DMA error: %#x %#x %#x %#x %#x %#x\n",
5123 mac->mac_reason[0], mac->mac_reason[1],
5124 mac->mac_reason[2], mac->mac_reason[3],
5125 mac->mac_reason[4], mac->mac_reason[5]);
5129 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG)
5130 bwn_intr_ucode_debug(mac);
5131 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI)
5132 bwn_intr_tbtt_indication(mac);
5133 if (mac->mac_reason_intr & BWN_INTR_ATIM_END)
5134 bwn_intr_atim_end(mac);
5135 if (mac->mac_reason_intr & BWN_INTR_BEACON)
5136 bwn_intr_beacon(mac);
5137 if (mac->mac_reason_intr & BWN_INTR_PMQ)
5139 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK)
5140 bwn_intr_noise(mac);
5142 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5143 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) {
5144 bwn_dma_rx(mac->mac_method.dma.rx);
5148 rx = bwn_pio_rx(&mac->mac_method.pio.rx);
5150 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5151 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5152 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5153 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5154 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5156 if (mac->mac_reason_intr & BWN_INTR_TX_OK) {
5157 bwn_intr_txeof(mac);
5161 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
5163 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
5164 int evt = BWN_LED_EVENT_NONE;
5167 if (sc->sc_rx_rate > sc->sc_tx_rate)
5168 evt = BWN_LED_EVENT_RX;
5170 evt = BWN_LED_EVENT_TX;
5172 evt = BWN_LED_EVENT_TX;
5174 evt = BWN_LED_EVENT_RX;
5175 } else if (rx == 0) {
5176 evt = BWN_LED_EVENT_POLL;
5179 if (evt != BWN_LED_EVENT_NONE)
5180 bwn_led_event(mac, evt);
5183 if (mbufq_first(&sc->sc_snd) != NULL)
5186 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
5192 bwn_restart(struct bwn_mac *mac, const char *msg)
5194 struct bwn_softc *sc = mac->mac_sc;
5195 struct ieee80211com *ic = &sc->sc_ic;
5197 if (mac->mac_status < BWN_MAC_STATUS_INITED)
5200 device_printf(sc->sc_dev, "HW reset: %s\n", msg);
5201 ieee80211_runtask(ic, &mac->mac_hwreset);
5205 bwn_intr_ucode_debug(struct bwn_mac *mac)
5207 struct bwn_softc *sc = mac->mac_sc;
5210 if (mac->mac_fw.opensource == 0)
5213 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG);
5215 case BWN_DEBUGINTR_PANIC:
5216 bwn_handle_fwpanic(mac);
5218 case BWN_DEBUGINTR_DUMP_SHM:
5219 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n");
5221 case BWN_DEBUGINTR_DUMP_REGS:
5222 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n");
5224 case BWN_DEBUGINTR_MARKER:
5225 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n");
5228 device_printf(sc->sc_dev,
5229 "ucode debug unknown reason: %#x\n", reason);
5232 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG,
5237 bwn_intr_tbtt_indication(struct bwn_mac *mac)
5239 struct bwn_softc *sc = mac->mac_sc;
5240 struct ieee80211com *ic = &sc->sc_ic;
5242 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
5244 if (ic->ic_opmode == IEEE80211_M_IBSS)
5245 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID;
5249 bwn_intr_atim_end(struct bwn_mac *mac)
5252 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) {
5253 BWN_WRITE_4(mac, BWN_MACCMD,
5254 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID);
5255 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
5260 bwn_intr_beacon(struct bwn_mac *mac)
5262 struct bwn_softc *sc = mac->mac_sc;
5263 struct ieee80211com *ic = &sc->sc_ic;
5264 uint32_t cmd, beacon0, beacon1;
5266 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
5267 ic->ic_opmode == IEEE80211_M_MBSS)
5270 mac->mac_intr_mask &= ~BWN_INTR_BEACON;
5272 cmd = BWN_READ_4(mac, BWN_MACCMD);
5273 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID);
5274 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID);
5276 if (beacon0 && beacon1) {
5277 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON);
5278 mac->mac_intr_mask |= BWN_INTR_BEACON;
5282 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) {
5283 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP;
5284 bwn_load_beacon0(mac);
5285 bwn_load_beacon1(mac);
5286 cmd = BWN_READ_4(mac, BWN_MACCMD);
5287 cmd |= BWN_MACCMD_BEACON0_VALID;
5288 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5291 bwn_load_beacon0(mac);
5292 cmd = BWN_READ_4(mac, BWN_MACCMD);
5293 cmd |= BWN_MACCMD_BEACON0_VALID;
5294 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5295 } else if (!beacon1) {
5296 bwn_load_beacon1(mac);
5297 cmd = BWN_READ_4(mac, BWN_MACCMD);
5298 cmd |= BWN_MACCMD_BEACON1_VALID;
5299 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5305 bwn_intr_pmq(struct bwn_mac *mac)
5310 tmp = BWN_READ_4(mac, BWN_PS_STATUS);
5311 if (!(tmp & 0x00000008))
5314 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002);
5318 bwn_intr_noise(struct bwn_mac *mac)
5320 struct bwn_phy_g *pg = &mac->mac_phy.phy_g;
5326 if (mac->mac_phy.type != BWN_PHYTYPE_G)
5329 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__));
5330 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac));
5331 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f ||
5335 KASSERT(mac->mac_noise.noi_nsamples < 8,
5336 ("%s:%d: fail", __func__, __LINE__));
5337 i = mac->mac_noise.noi_nsamples;
5338 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1);
5339 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1);
5340 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1);
5341 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1);
5342 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]];
5343 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]];
5344 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]];
5345 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]];
5346 mac->mac_noise.noi_nsamples++;
5347 if (mac->mac_noise.noi_nsamples == 8) {
5349 for (i = 0; i < 8; i++) {
5350 for (j = 0; j < 4; j++)
5351 average += mac->mac_noise.noi_samples[i][j];
5353 average = (((average / 32) * 125) + 64) / 128;
5354 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f;
5359 average -= (tmp == 8) ? 72 : 48;
5361 mac->mac_stats.link_noise = average;
5362 mac->mac_noise.noi_running = 0;
5366 bwn_noise_gensample(mac);
5370 bwn_pio_rx(struct bwn_pio_rxqueue *prq)
5372 struct bwn_mac *mac = prq->prq_mac;
5373 struct bwn_softc *sc = mac->mac_sc;
5376 BWN_ASSERT_LOCKED(sc);
5378 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
5381 for (i = 0; i < 5000; i++) {
5382 if (bwn_pio_rxeof(prq) == 0)
5386 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n");
5387 return ((i > 0) ? 1 : 0);
5391 bwn_dma_rx(struct bwn_dma_ring *dr)
5395 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5396 curslot = dr->get_curslot(dr);
5397 KASSERT(curslot >= 0 && curslot < dr->dr_numslots,
5398 ("%s:%d: fail", __func__, __LINE__));
5400 slot = dr->dr_curslot;
5401 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot))
5402 bwn_dma_rxeof(dr, &slot);
5404 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
5405 BUS_DMASYNC_PREWRITE);
5407 dr->set_curslot(dr, slot);
5408 dr->dr_curslot = slot;
5412 bwn_intr_txeof(struct bwn_mac *mac)
5414 struct bwn_txstatus stat;
5415 uint32_t stat0, stat1;
5418 BWN_ASSERT_LOCKED(mac->mac_sc);
5421 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0);
5422 if (!(stat0 & 0x00000001))
5424 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1);
5426 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5427 "%s: stat0=0x%08x, stat1=0x%08x\n",
5432 stat.cookie = (stat0 >> 16);
5433 stat.seq = (stat1 & 0x0000ffff);
5434 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16);
5435 tmp = (stat0 & 0x0000ffff);
5436 stat.framecnt = ((tmp & 0xf000) >> 12);
5437 stat.rtscnt = ((tmp & 0x0f00) >> 8);
5438 stat.sreason = ((tmp & 0x001c) >> 2);
5439 stat.pm = (tmp & 0x0080) ? 1 : 0;
5440 stat.im = (tmp & 0x0040) ? 1 : 0;
5441 stat.ampdu = (tmp & 0x0020) ? 1 : 0;
5442 stat.ack = (tmp & 0x0002) ? 1 : 0;
5444 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5445 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, "
5446 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n",
5459 bwn_handle_txeof(mac, &stat);
5464 bwn_hwreset(void *arg, int npending)
5466 struct bwn_mac *mac = arg;
5467 struct bwn_softc *sc = mac->mac_sc;
5473 prev_status = mac->mac_status;
5474 if (prev_status >= BWN_MAC_STATUS_STARTED)
5476 if (prev_status >= BWN_MAC_STATUS_INITED)
5479 if (prev_status >= BWN_MAC_STATUS_INITED) {
5480 error = bwn_core_init(mac);
5484 if (prev_status >= BWN_MAC_STATUS_STARTED)
5485 bwn_core_start(mac);
5488 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error);
5489 sc->sc_curmac = NULL;
5495 bwn_handle_fwpanic(struct bwn_mac *mac)
5497 struct bwn_softc *sc = mac->mac_sc;
5500 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG);
5501 device_printf(sc->sc_dev,"fw panic (%u)\n", reason);
5503 if (reason == BWN_FWPANIC_RESTART)
5504 bwn_restart(mac, "ucode panic");
5508 bwn_load_beacon0(struct bwn_mac *mac)
5511 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5515 bwn_load_beacon1(struct bwn_mac *mac)
5518 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5522 bwn_jssi_read(struct bwn_mac *mac)
5526 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a);
5528 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088);
5534 bwn_noise_gensample(struct bwn_mac *mac)
5536 uint32_t jssi = 0x7f7f7f7f;
5538 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff));
5539 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16);
5540 BWN_WRITE_4(mac, BWN_MACCMD,
5541 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE);
5545 bwn_dma_freeslot(struct bwn_dma_ring *dr)
5547 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5549 return (dr->dr_numslots - dr->dr_usedslot);
5553 bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot)
5555 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5557 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1,
5558 ("%s:%d: fail", __func__, __LINE__));
5559 if (slot == dr->dr_numslots - 1)
5565 bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot)
5567 struct bwn_mac *mac = dr->dr_mac;
5568 struct bwn_softc *sc = mac->mac_sc;
5569 struct bwn_dma *dma = &mac->mac_method.dma;
5570 struct bwn_dmadesc_generic *desc;
5571 struct bwn_dmadesc_meta *meta;
5572 struct bwn_rxhdr4 *rxhdr;
5579 dr->getdesc(dr, *slot, &desc, &meta);
5581 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD);
5584 if (bwn_dma_newbuf(dr, desc, meta, 0)) {
5585 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5589 rxhdr = mtod(m, struct bwn_rxhdr4 *);
5590 len = le16toh(rxhdr->frame_len);
5592 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5595 if (bwn_dma_check_redzone(dr, m)) {
5596 device_printf(sc->sc_dev, "redzone error.\n");
5597 bwn_dma_set_redzone(dr, m);
5598 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5599 BUS_DMASYNC_PREWRITE);
5602 if (len > dr->dr_rx_bufsize) {
5605 dr->getdesc(dr, *slot, &desc, &meta);
5606 bwn_dma_set_redzone(dr, meta->mt_m);
5607 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5608 BUS_DMASYNC_PREWRITE);
5609 *slot = bwn_dma_nextslot(dr, *slot);
5611 tmp -= dr->dr_rx_bufsize;
5615 device_printf(sc->sc_dev, "too small buffer "
5616 "(len %u buffer %u dropped %d)\n",
5617 len, dr->dr_rx_bufsize, cnt);
5621 switch (mac->mac_fw.fw_hdr_format) {
5622 case BWN_FW_HDR_351:
5623 case BWN_FW_HDR_410:
5624 macstat = le32toh(rxhdr->ps4.r351.mac_status);
5626 case BWN_FW_HDR_598:
5627 macstat = le32toh(rxhdr->ps4.r598.mac_status);
5631 if (macstat & BWN_RX_MAC_FCSERR) {
5632 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5633 device_printf(sc->sc_dev, "RX drop\n");
5638 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset;
5639 m_adj(m, dr->dr_frameoffset);
5641 bwn_rxeof(dr->dr_mac, m, rxhdr);
5645 bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status)
5647 struct bwn_softc *sc = mac->mac_sc;
5648 struct bwn_stats *stats = &mac->mac_stats;
5650 BWN_ASSERT_LOCKED(mac->mac_sc);
5653 device_printf(sc->sc_dev, "TODO: STATUS IM\n");
5655 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n");
5656 if (status->rtscnt) {
5657 if (status->rtscnt == 0xf)
5663 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5664 bwn_dma_handle_txeof(mac, status);
5666 bwn_pio_handle_txeof(mac, status);
5669 bwn_phy_txpower_check(mac, 0);
5673 bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
5675 struct bwn_mac *mac = prq->prq_mac;
5676 struct bwn_softc *sc = mac->mac_sc;
5677 struct bwn_rxhdr4 rxhdr;
5679 uint32_t ctl32, macstat, v32;
5680 unsigned int i, padding;
5681 uint16_t ctl16, len, totlen, v16;
5685 memset(&rxhdr, 0, sizeof(rxhdr));
5687 if (prq->prq_rev >= 8) {
5688 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5689 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY))
5691 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5692 BWN_PIO8_RXCTL_FRAMEREADY);
5693 for (i = 0; i < 10; i++) {
5694 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5695 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY)
5700 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5701 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY))
5703 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL,
5704 BWN_PIO_RXCTL_FRAMEREADY);
5705 for (i = 0; i < 10; i++) {
5706 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5707 if (ctl16 & BWN_PIO_RXCTL_DATAREADY)
5712 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
5715 if (prq->prq_rev >= 8) {
5716 bus_read_multi_4(sc->sc_mem_res,
5717 prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr,
5720 bus_read_multi_2(sc->sc_mem_res,
5721 prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr,
5724 len = le16toh(rxhdr.frame_len);
5726 device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
5730 device_printf(sc->sc_dev, "%s: len is 0\n", __func__);
5734 switch (mac->mac_fw.fw_hdr_format) {
5735 case BWN_FW_HDR_351:
5736 case BWN_FW_HDR_410:
5737 macstat = le32toh(rxhdr.ps4.r351.mac_status);
5739 case BWN_FW_HDR_598:
5740 macstat = le32toh(rxhdr.ps4.r598.mac_status);
5744 if (macstat & BWN_RX_MAC_FCSERR) {
5745 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5746 device_printf(sc->sc_dev, "%s: FCS error", __func__);
5751 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5752 totlen = len + padding;
5753 KASSERT(totlen <= MCLBYTES, ("too big..\n"));
5754 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5756 device_printf(sc->sc_dev, "%s: out of memory", __func__);
5759 mp = mtod(m, unsigned char *);
5760 if (prq->prq_rev >= 8) {
5761 bus_read_multi_4(sc->sc_mem_res,
5762 prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3));
5764 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
5765 data = &(mp[totlen - 1]);
5766 switch (totlen & 3) {
5768 *data = (v32 >> 16);
5778 bus_read_multi_2(sc->sc_mem_res,
5779 prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1));
5781 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
5782 mp[totlen - 1] = v16;
5786 m->m_len = m->m_pkthdr.len = totlen;
5788 bwn_rxeof(prq->prq_mac, m, &rxhdr);
5792 if (prq->prq_rev >= 8)
5793 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5794 BWN_PIO8_RXCTL_DATAREADY);
5796 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY);
5801 bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc,
5802 struct bwn_dmadesc_meta *meta, int init)
5804 struct bwn_mac *mac = dr->dr_mac;
5805 struct bwn_dma *dma = &mac->mac_method.dma;
5806 struct bwn_rxhdr4 *hdr;
5812 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5817 * If the NIC is up and running, we need to:
5818 * - Clear RX buffer's header.
5819 * - Restore RX descriptor settings.
5826 m->m_len = m->m_pkthdr.len = MCLBYTES;
5828 bwn_dma_set_redzone(dr, m);
5831 * Try to load RX buf into temporary DMA map
5833 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m,
5834 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
5839 * See the comment above
5848 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
5850 meta->mt_paddr = paddr;
5853 * Swap RX buf's DMA map with the loaded temporary one
5855 map = meta->mt_dmap;
5856 meta->mt_dmap = dr->dr_spare_dmap;
5857 dr->dr_spare_dmap = map;
5861 * Clear RX buf header
5863 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *);
5864 bzero(hdr, sizeof(*hdr));
5865 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5866 BUS_DMASYNC_PREWRITE);
5869 * Setup RX buf descriptor
5871 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len -
5872 sizeof(*hdr), 0, 0, 0);
5877 bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
5878 bus_size_t mapsz __unused, int error)
5882 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
5883 *((bus_addr_t *)arg) = seg->ds_addr;
5888 bwn_hwrate2ieeerate(int rate)
5892 case BWN_CCK_RATE_1MB:
5894 case BWN_CCK_RATE_2MB:
5896 case BWN_CCK_RATE_5MB:
5898 case BWN_CCK_RATE_11MB:
5900 case BWN_OFDM_RATE_6MB:
5902 case BWN_OFDM_RATE_9MB:
5904 case BWN_OFDM_RATE_12MB:
5906 case BWN_OFDM_RATE_18MB:
5908 case BWN_OFDM_RATE_24MB:
5910 case BWN_OFDM_RATE_36MB:
5912 case BWN_OFDM_RATE_48MB:
5914 case BWN_OFDM_RATE_54MB:
5923 * Post process the RX provided RSSI.
5925 * Valid for A, B, G, LP PHYs.
5928 bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
5929 int ofdm, int adjust_2053, int adjust_2050)
5931 struct bwn_phy *phy = &mac->mac_phy;
5932 struct bwn_phy_g *gphy = &phy->phy_g;
5935 switch (phy->rf_ver) {
5941 tmp = tmp * 73 / 64;
5947 if (mac->mac_sc->sc_board_info.board_flags
5948 & BHND_BFL_ADCDIV) {
5951 tmp = gphy->pg_nrssi_lt[in_rssi];
5952 tmp = (31 - tmp) * -131 / 128 - 57;
5955 tmp = (31 - tmp) * -149 / 128 - 68;
5957 if (phy->type == BWN_PHYTYPE_G && adjust_2050)
5963 tmp = in_rssi - 256;
5969 tmp = (tmp - 11) * 103 / 64;
5980 bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr)
5982 const struct bwn_rxhdr4 *rxhdr = _rxhdr;
5983 struct bwn_plcp6 *plcp;
5984 struct bwn_softc *sc = mac->mac_sc;
5985 struct ieee80211_frame_min *wh;
5986 struct ieee80211_node *ni;
5987 struct ieee80211com *ic = &sc->sc_ic;
5989 int padding, rate, rssi = 0, noise = 0, type;
5990 uint16_t phytype, phystat0, phystat3, chanstat;
5991 unsigned char *mp = mtod(m, unsigned char *);
5993 BWN_ASSERT_LOCKED(sc);
5995 phystat0 = le16toh(rxhdr->phy_status0);
5998 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only
6001 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3);
6003 switch (mac->mac_fw.fw_hdr_format) {
6004 case BWN_FW_HDR_351:
6005 case BWN_FW_HDR_410:
6006 macstat = le32toh(rxhdr->ps4.r351.mac_status);
6007 chanstat = le16toh(rxhdr->ps4.r351.channel);
6009 case BWN_FW_HDR_598:
6010 macstat = le32toh(rxhdr->ps4.r598.mac_status);
6011 chanstat = le16toh(rxhdr->ps4.r598.channel);
6016 phytype = chanstat & BWN_RX_CHAN_PHYTYPE;
6018 if (macstat & BWN_RX_MAC_FCSERR)
6019 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n");
6020 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV))
6021 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n");
6022 if (macstat & BWN_RX_MAC_DECERR)
6025 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
6026 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) {
6027 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
6031 plcp = (struct bwn_plcp6 *)(mp + padding);
6032 m_adj(m, sizeof(struct bwn_plcp6) + padding);
6033 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) {
6034 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
6038 wh = mtod(m, struct ieee80211_frame_min *);
6040 if (macstat & BWN_RX_MAC_DEC) {
6041 DPRINTF(sc, BWN_DEBUG_HWCRYPTO,
6042 "RX decryption attempted (old %d keyidx %#x)\n",
6044 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT);
6047 if (phystat0 & BWN_RX_PHYST0_OFDM)
6048 rate = bwn_plcp_get_ofdmrate(mac, plcp,
6049 phytype == BWN_PHYTYPE_A);
6051 rate = bwn_plcp_get_cckrate(mac, plcp);
6053 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP))
6056 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate);
6063 case BWN_PHYTYPE_LP:
6064 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi,
6065 !! (phystat0 & BWN_RX_PHYST0_OFDM),
6066 !! (phystat0 & BWN_RX_PHYST0_GAINCTL),
6067 !! (phystat3 & BWN_RX_PHYST3_TRSTATE));
6070 /* Broadcom has code for min/avg, but always used max */
6071 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32)
6072 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2);
6074 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1);
6076 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV,
6077 "%s: power0=%d, power1=%d, power2=%d\n",
6079 rxhdr->phy.n.power0,
6080 rxhdr->phy.n.power1,
6081 rxhdr->ps2.n.power2);
6085 /* XXX TODO: implement rssi for other PHYs */
6090 * RSSI here is absolute, not relative to the noise floor.
6092 noise = mac->mac_stats.link_noise;
6093 rssi = rssi - noise;
6096 if (ieee80211_radiotap_active(ic))
6097 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise);
6098 m_adj(m, -IEEE80211_CRC_LEN);
6102 ni = ieee80211_find_rxnode(ic, wh);
6104 type = ieee80211_input(ni, m, rssi, noise);
6105 ieee80211_free_node(ni);
6107 type = ieee80211_input_all(ic, m, rssi, noise);
6112 device_printf(sc->sc_dev, "%s: dropped\n", __func__);
6116 bwn_ratectl_tx_complete(const struct ieee80211_node *ni,
6117 const struct bwn_txstatus *status)
6119 struct ieee80211_ratectl_tx_status txs;
6123 * If we don't get an ACK, then we should log the
6124 * full framecnt. That may be 0 if it's a PHY
6125 * failure, so ensure that gets logged as some
6128 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
6130 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
6131 retrycnt = status->framecnt - 1;
6133 txs.status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
6134 retrycnt = status->framecnt;
6138 txs.long_retries = retrycnt;
6139 ieee80211_ratectl_tx_complete(ni, &txs);
6143 bwn_dma_handle_txeof(struct bwn_mac *mac,
6144 const struct bwn_txstatus *status)
6146 struct bwn_dma *dma = &mac->mac_method.dma;
6147 struct bwn_dma_ring *dr;
6148 struct bwn_dmadesc_generic *desc;
6149 struct bwn_dmadesc_meta *meta;
6150 struct bwn_softc *sc = mac->mac_sc;
6153 BWN_ASSERT_LOCKED(sc);
6155 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot);
6157 device_printf(sc->sc_dev, "failed to parse cookie\n");
6160 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6163 KASSERT(slot >= 0 && slot < dr->dr_numslots,
6164 ("%s:%d: fail", __func__, __LINE__));
6165 dr->getdesc(dr, slot, &desc, &meta);
6167 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
6168 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap);
6169 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
6170 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap);
6172 if (meta->mt_islast) {
6173 KASSERT(meta->mt_m != NULL,
6174 ("%s:%d: fail", __func__, __LINE__));
6176 bwn_ratectl_tx_complete(meta->mt_ni, status);
6177 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0);
6181 KASSERT(meta->mt_m == NULL,
6182 ("%s:%d: fail", __func__, __LINE__));
6185 if (meta->mt_islast)
6187 slot = bwn_dma_nextslot(dr, slot);
6189 sc->sc_watchdog_timer = 0;
6191 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME,
6192 ("%s:%d: fail", __func__, __LINE__));
6198 bwn_pio_handle_txeof(struct bwn_mac *mac,
6199 const struct bwn_txstatus *status)
6201 struct bwn_pio_txqueue *tq;
6202 struct bwn_pio_txpkt *tp = NULL;
6203 struct bwn_softc *sc = mac->mac_sc;
6205 BWN_ASSERT_LOCKED(sc);
6207 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp);
6211 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
6214 if (tp->tp_ni != NULL) {
6216 * Do any tx complete callback. Note this must
6217 * be done before releasing the node reference.
6219 bwn_ratectl_tx_complete(tp->tp_ni, status);
6221 ieee80211_tx_complete(tp->tp_ni, tp->tp_m, 0);
6224 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
6226 sc->sc_watchdog_timer = 0;
6230 bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
6232 struct bwn_softc *sc = mac->mac_sc;
6233 struct bwn_phy *phy = &mac->mac_phy;
6234 struct ieee80211com *ic = &sc->sc_ic;
6236 bwn_txpwr_result_t result;
6240 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime))
6242 phy->nexttime = now + 2 * 1000;
6244 if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
6245 sc->sc_board_info.board_type == BHND_BOARD_BU4306)
6248 if (phy->recalc_txpwr != NULL) {
6249 result = phy->recalc_txpwr(mac,
6250 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
6251 if (result == BWN_TXPWR_RES_DONE)
6253 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,
6254 ("%s: fail", __func__));
6255 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__));
6257 ieee80211_runtask(ic, &mac->mac_txpower);
6262 bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset)
6265 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset));
6269 bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset)
6272 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset));
6276 bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value)
6279 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value);
6283 bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value)
6286 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value);
6290 bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate)
6294 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
6296 return (BWN_OFDM_RATE_6MB);
6298 return (BWN_OFDM_RATE_9MB);
6300 return (BWN_OFDM_RATE_12MB);
6302 return (BWN_OFDM_RATE_18MB);
6304 return (BWN_OFDM_RATE_24MB);
6306 return (BWN_OFDM_RATE_36MB);
6308 return (BWN_OFDM_RATE_48MB);
6310 return (BWN_OFDM_RATE_54MB);
6311 /* CCK rates (NB: not IEEE std, device-specific) */
6313 return (BWN_CCK_RATE_1MB);
6315 return (BWN_CCK_RATE_2MB);
6317 return (BWN_CCK_RATE_5MB);
6319 return (BWN_CCK_RATE_11MB);
6322 device_printf(sc->sc_dev, "unsupported rate %d\n", rate);
6323 return (BWN_CCK_RATE_1MB);
6327 bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate)
6329 struct bwn_phy *phy = &mac->mac_phy;
6330 uint16_t control = 0;
6333 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */
6334 bw = BWN_TXH_PHY1_BW_20;
6336 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) {
6340 /* Figure out coding rate and modulation */
6341 /* XXX TODO: table-ize, for MCS transmit */
6342 /* Note: this is BWN_*_RATE values */
6344 case BWN_CCK_RATE_1MB:
6347 case BWN_CCK_RATE_2MB:
6350 case BWN_CCK_RATE_5MB:
6353 case BWN_CCK_RATE_11MB:
6356 case BWN_OFDM_RATE_6MB:
6357 control |= BWN_TXH_PHY1_CRATE_1_2;
6358 control |= BWN_TXH_PHY1_MODUL_BPSK;
6360 case BWN_OFDM_RATE_9MB:
6361 control |= BWN_TXH_PHY1_CRATE_3_4;
6362 control |= BWN_TXH_PHY1_MODUL_BPSK;
6364 case BWN_OFDM_RATE_12MB:
6365 control |= BWN_TXH_PHY1_CRATE_1_2;
6366 control |= BWN_TXH_PHY1_MODUL_QPSK;
6368 case BWN_OFDM_RATE_18MB:
6369 control |= BWN_TXH_PHY1_CRATE_3_4;
6370 control |= BWN_TXH_PHY1_MODUL_QPSK;
6372 case BWN_OFDM_RATE_24MB:
6373 control |= BWN_TXH_PHY1_CRATE_1_2;
6374 control |= BWN_TXH_PHY1_MODUL_QAM16;
6376 case BWN_OFDM_RATE_36MB:
6377 control |= BWN_TXH_PHY1_CRATE_3_4;
6378 control |= BWN_TXH_PHY1_MODUL_QAM16;
6380 case BWN_OFDM_RATE_48MB:
6381 control |= BWN_TXH_PHY1_CRATE_1_2;
6382 control |= BWN_TXH_PHY1_MODUL_QAM64;
6384 case BWN_OFDM_RATE_54MB:
6385 control |= BWN_TXH_PHY1_CRATE_3_4;
6386 control |= BWN_TXH_PHY1_MODUL_QAM64;
6391 control |= BWN_TXH_PHY1_MODE_SISO;
6398 bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni,
6399 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie)
6401 const struct bwn_phy *phy = &mac->mac_phy;
6402 struct bwn_softc *sc = mac->mac_sc;
6403 struct ieee80211_frame *wh;
6404 struct ieee80211_frame *protwh;
6405 const struct ieee80211_txparam *tp = ni->ni_txparms;
6406 struct ieee80211vap *vap = ni->ni_vap;
6407 struct ieee80211com *ic = &sc->sc_ic;
6411 uint32_t macctl = 0;
6412 int rts_rate, rts_rate_fb, ismcast, isshort, rix, type;
6413 uint16_t phyctl = 0;
6414 uint8_t rate, rate_fb;
6415 int fill_phy_ctl1 = 0;
6417 wh = mtod(m, struct ieee80211_frame *);
6418 memset(txhdr, 0, sizeof(*txhdr));
6420 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
6421 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6422 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
6424 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP)
6425 || (phy->type == BWN_PHYTYPE_HT))
6431 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL))
6432 rate = rate_fb = tp->mgmtrate;
6434 rate = rate_fb = tp->mcastrate;
6435 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
6436 rate = rate_fb = tp->ucastrate;
6438 rix = ieee80211_ratectl_rate(ni, NULL, 0);
6439 rate = ni->ni_txrate;
6442 rate_fb = ni->ni_rates.rs_rates[rix - 1] &
6448 sc->sc_tx_rate = rate;
6450 /* Note: this maps the select ieee80211 rate to hardware rate */
6451 rate = bwn_ieeerate2hwrate(sc, rate);
6452 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb);
6454 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) :
6455 bwn_plcp_getcck(rate);
6456 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc));
6457 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN);
6459 /* XXX rate/rate_fb is the hardware rate */
6460 if ((rate_fb == rate) ||
6461 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) ||
6462 (*(u_int16_t *)wh->i_dur == htole16(0)))
6463 txhdr->dur_fb = *(u_int16_t *)wh->i_dur;
6465 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt,
6466 m->m_pkthdr.len, rate, isshort);
6468 /* XXX TX encryption */
6470 switch (mac->mac_fw.fw_hdr_format) {
6471 case BWN_FW_HDR_351:
6472 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp),
6473 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6475 case BWN_FW_HDR_410:
6476 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp),
6477 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6479 case BWN_FW_HDR_598:
6480 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp),
6481 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6485 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb),
6486 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb);
6488 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM :
6490 txhdr->chan = phy->chan;
6491 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM :
6493 /* XXX preamble? obey net80211 */
6494 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6495 rate == BWN_CCK_RATE_11MB))
6496 phyctl |= BWN_TX_PHY_SHORTPRMBL;
6499 macctl |= BWN_TX_MAC_5GHZ;
6501 /* XXX TX antenna selection */
6503 switch (bwn_antenna_sanitize(mac, 0)) {
6505 phyctl |= BWN_TX_PHY_ANT01AUTO;
6508 phyctl |= BWN_TX_PHY_ANT0;
6511 phyctl |= BWN_TX_PHY_ANT1;
6514 phyctl |= BWN_TX_PHY_ANT2;
6517 phyctl |= BWN_TX_PHY_ANT3;
6520 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6524 macctl |= BWN_TX_MAC_ACK;
6526 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU);
6527 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
6528 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
6529 macctl |= BWN_TX_MAC_LONGFRAME;
6531 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
6532 ic->ic_protmode != IEEE80211_PROT_NONE) {
6533 /* Note: don't fall back to CCK rates for 5G */
6535 rts_rate = BWN_CCK_RATE_1MB;
6537 rts_rate = BWN_OFDM_RATE_6MB;
6538 rts_rate_fb = bwn_get_fbrate(rts_rate);
6540 /* XXX 'rate' here is hardware rate now, not the net80211 rate */
6541 mprot = ieee80211_alloc_prot(ni, m, rate, ic->ic_protmode);
6542 if (mprot == NULL) {
6543 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, 1);
6544 device_printf(sc->sc_dev,
6545 "could not allocate mbuf for protection mode %d\n",
6550 switch (mac->mac_fw.fw_hdr_format) {
6551 case BWN_FW_HDR_351:
6552 prot_ptr = txhdr->body.r351.rts_frame;
6554 case BWN_FW_HDR_410:
6555 prot_ptr = txhdr->body.r410.rts_frame;
6557 case BWN_FW_HDR_598:
6558 prot_ptr = txhdr->body.r598.rts_frame;
6562 bcopy(mtod(mprot, uint8_t *), prot_ptr, mprot->m_pkthdr.len);
6565 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
6566 macctl |= BWN_TX_MAC_SEND_CTSTOSELF;
6567 len = sizeof(struct ieee80211_frame_cts);
6569 macctl |= BWN_TX_MAC_SEND_RTSCTS;
6570 len = sizeof(struct ieee80211_frame_rts);
6572 len += IEEE80211_CRC_LEN;
6574 switch (mac->mac_fw.fw_hdr_format) {
6575 case BWN_FW_HDR_351:
6576 bwn_plcp_genhdr((struct bwn_plcp4 *)
6577 &txhdr->body.r351.rts_plcp, len, rts_rate);
6579 case BWN_FW_HDR_410:
6580 bwn_plcp_genhdr((struct bwn_plcp4 *)
6581 &txhdr->body.r410.rts_plcp, len, rts_rate);
6583 case BWN_FW_HDR_598:
6584 bwn_plcp_genhdr((struct bwn_plcp4 *)
6585 &txhdr->body.r598.rts_plcp, len, rts_rate);
6589 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len,
6592 switch (mac->mac_fw.fw_hdr_format) {
6593 case BWN_FW_HDR_351:
6594 protwh = (struct ieee80211_frame *)
6595 &txhdr->body.r351.rts_frame;
6597 case BWN_FW_HDR_410:
6598 protwh = (struct ieee80211_frame *)
6599 &txhdr->body.r410.rts_frame;
6601 case BWN_FW_HDR_598:
6602 protwh = (struct ieee80211_frame *)
6603 &txhdr->body.r598.rts_frame;
6607 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur;
6609 if (BWN_ISOFDMRATE(rts_rate)) {
6610 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM;
6611 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate);
6613 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK;
6614 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate);
6616 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ?
6617 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK;
6619 if (fill_phy_ctl1) {
6620 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate));
6621 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb));
6625 if (fill_phy_ctl1) {
6626 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate));
6627 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb));
6630 switch (mac->mac_fw.fw_hdr_format) {
6631 case BWN_FW_HDR_351:
6632 txhdr->body.r351.cookie = htole16(cookie);
6634 case BWN_FW_HDR_410:
6635 txhdr->body.r410.cookie = htole16(cookie);
6637 case BWN_FW_HDR_598:
6638 txhdr->body.r598.cookie = htole16(cookie);
6642 txhdr->macctl = htole32(macctl);
6643 txhdr->phyctl = htole16(phyctl);
6648 if (ieee80211_radiotap_active_vap(vap)) {
6649 sc->sc_tx_th.wt_flags = 0;
6650 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6651 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6653 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6654 rate == BWN_CCK_RATE_11MB))
6655 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6656 sc->sc_tx_th.wt_rate = rate;
6658 ieee80211_radiotap_tx(vap, m);
6665 bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets,
6669 uint8_t *raw = plcp->o.raw;
6671 if (BWN_ISOFDMRATE(rate)) {
6672 d = bwn_plcp_getofdm(rate);
6673 KASSERT(!(octets & 0xf000),
6674 ("%s:%d: fail", __func__, __LINE__));
6676 plcp->o.data = htole32(d);
6678 plen = octets * 16 / rate;
6679 if ((octets * 16 % rate) > 0) {
6681 if ((rate == BWN_CCK_RATE_11MB)
6682 && ((octets * 8 % 11) < 4)) {
6688 plcp->o.data |= htole32(plen << 16);
6689 raw[0] = bwn_plcp_getcck(rate);
6694 bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
6696 struct bwn_softc *sc = mac->mac_sc;
6701 if (mac->mac_phy.gmode)
6702 mask = sc->sc_ant2g;
6704 mask = sc->sc_ant5g;
6705 if (!(mask & (1 << (n - 1))))
6711 * Return a fallback rate for the given rate.
6713 * Note: Don't fall back from OFDM to CCK.
6716 bwn_get_fbrate(uint8_t bitrate)
6720 case BWN_CCK_RATE_1MB:
6721 return (BWN_CCK_RATE_1MB);
6722 case BWN_CCK_RATE_2MB:
6723 return (BWN_CCK_RATE_1MB);
6724 case BWN_CCK_RATE_5MB:
6725 return (BWN_CCK_RATE_2MB);
6726 case BWN_CCK_RATE_11MB:
6727 return (BWN_CCK_RATE_5MB);
6730 case BWN_OFDM_RATE_6MB:
6731 return (BWN_OFDM_RATE_6MB);
6732 case BWN_OFDM_RATE_9MB:
6733 return (BWN_OFDM_RATE_6MB);
6734 case BWN_OFDM_RATE_12MB:
6735 return (BWN_OFDM_RATE_9MB);
6736 case BWN_OFDM_RATE_18MB:
6737 return (BWN_OFDM_RATE_12MB);
6738 case BWN_OFDM_RATE_24MB:
6739 return (BWN_OFDM_RATE_18MB);
6740 case BWN_OFDM_RATE_36MB:
6741 return (BWN_OFDM_RATE_24MB);
6742 case BWN_OFDM_RATE_48MB:
6743 return (BWN_OFDM_RATE_36MB);
6744 case BWN_OFDM_RATE_54MB:
6745 return (BWN_OFDM_RATE_48MB);
6747 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6752 bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6753 uint32_t ctl, const void *_data, int len)
6755 struct bwn_softc *sc = mac->mac_sc;
6757 const uint8_t *data = _data;
6759 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
6760 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
6761 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6763 bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA,
6764 __DECONST(void *, data), (len & ~3));
6766 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
6767 BWN_PIO8_TXCTL_24_31);
6768 data = &(data[len - 1]);
6771 ctl |= BWN_PIO8_TXCTL_16_23;
6772 value |= (uint32_t)(*data) << 16;
6775 ctl |= BWN_PIO8_TXCTL_8_15;
6776 value |= (uint32_t)(*data) << 8;
6779 value |= (uint32_t)(*data);
6781 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6782 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value);
6789 bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6790 uint16_t offset, uint32_t value)
6793 BWN_WRITE_4(mac, tq->tq_base + offset, value);
6797 bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6798 uint16_t ctl, const void *_data, int len)
6800 struct bwn_softc *sc = mac->mac_sc;
6801 const uint8_t *data = _data;
6803 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6804 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6806 bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA,
6807 __DECONST(void *, data), (len & ~1));
6809 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6810 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6811 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
6818 bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6819 uint16_t ctl, struct mbuf *m0)
6824 struct mbuf *m = m0;
6826 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6827 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6829 for (; m != NULL; m = m->m_next) {
6830 buf = mtod(m, const uint8_t *);
6831 for (i = 0; i < m->m_len; i++) {
6835 data |= (buf[i] << 8);
6836 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6841 if (m0->m_pkthdr.len % 2) {
6842 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6843 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6844 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6851 bwn_set_slot_time(struct bwn_mac *mac, uint16_t time)
6854 /* XXX should exit if 5GHz band .. */
6855 if (mac->mac_phy.type != BWN_PHYTYPE_G)
6858 BWN_WRITE_2(mac, 0x684, 510 + time);
6859 /* Disabled in Linux b43, can adversely effect performance */
6861 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time);
6865 static struct bwn_dma_ring *
6866 bwn_dma_select(struct bwn_mac *mac, uint8_t prio)
6869 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
6870 return (mac->mac_method.dma.wme[WME_AC_BE]);
6874 return (mac->mac_method.dma.wme[WME_AC_VO]);
6876 return (mac->mac_method.dma.wme[WME_AC_VI]);
6878 return (mac->mac_method.dma.wme[WME_AC_BE]);
6880 return (mac->mac_method.dma.wme[WME_AC_BK]);
6882 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6887 bwn_dma_getslot(struct bwn_dma_ring *dr)
6891 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
6893 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6894 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__));
6895 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__));
6897 slot = bwn_dma_nextslot(dr, dr->dr_curslot);
6898 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__));
6899 dr->dr_curslot = slot;
6905 static struct bwn_pio_txqueue *
6906 bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie,
6907 struct bwn_pio_txpkt **pack)
6909 struct bwn_pio *pio = &mac->mac_method.pio;
6910 struct bwn_pio_txqueue *tq = NULL;
6913 switch (cookie & 0xf000) {
6915 tq = &pio->wme[WME_AC_BK];
6918 tq = &pio->wme[WME_AC_BE];
6921 tq = &pio->wme[WME_AC_VI];
6924 tq = &pio->wme[WME_AC_VO];
6930 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__));
6933 index = (cookie & 0x0fff);
6934 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__));
6935 if (index >= N(tq->tq_pkts))
6937 *pack = &tq->tq_pkts[index];
6938 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__));
6943 bwn_txpwr(void *arg, int npending)
6945 struct bwn_mac *mac = arg;
6946 struct bwn_softc *sc;
6954 if (mac->mac_status >= BWN_MAC_STATUS_STARTED &&
6955 mac->mac_phy.set_txpwr != NULL)
6956 mac->mac_phy.set_txpwr(mac);
6961 bwn_task_15s(struct bwn_mac *mac)
6965 if (mac->mac_fw.opensource) {
6966 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);
6968 bwn_restart(mac, "fw watchdog");
6971 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1);
6973 if (mac->mac_phy.task_15s)
6974 mac->mac_phy.task_15s(mac);
6976 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
6980 bwn_task_30s(struct bwn_mac *mac)
6983 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running)
6985 mac->mac_noise.noi_running = 1;
6986 mac->mac_noise.noi_nsamples = 0;
6988 bwn_noise_gensample(mac);
6992 bwn_task_60s(struct bwn_mac *mac)
6995 if (mac->mac_phy.task_60s)
6996 mac->mac_phy.task_60s(mac);
6997 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME);
7001 bwn_tasks(void *arg)
7003 struct bwn_mac *mac = arg;
7004 struct bwn_softc *sc = mac->mac_sc;
7006 BWN_ASSERT_LOCKED(sc);
7007 if (mac->mac_status != BWN_MAC_STATUS_STARTED)
7010 if (mac->mac_task_state % 4 == 0)
7012 if (mac->mac_task_state % 2 == 0)
7016 mac->mac_task_state++;
7017 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
7021 bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a)
7023 struct bwn_softc *sc = mac->mac_sc;
7025 KASSERT(a == 0, ("not support APHY\n"));
7027 switch (plcp->o.raw[0] & 0xf) {
7029 return (BWN_OFDM_RATE_6MB);
7031 return (BWN_OFDM_RATE_9MB);
7033 return (BWN_OFDM_RATE_12MB);
7035 return (BWN_OFDM_RATE_18MB);
7037 return (BWN_OFDM_RATE_24MB);
7039 return (BWN_OFDM_RATE_36MB);
7041 return (BWN_OFDM_RATE_48MB);
7043 return (BWN_OFDM_RATE_54MB);
7045 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n",
7046 plcp->o.raw[0] & 0xf);
7051 bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp)
7053 struct bwn_softc *sc = mac->mac_sc;
7055 switch (plcp->o.raw[0]) {
7057 return (BWN_CCK_RATE_1MB);
7059 return (BWN_CCK_RATE_2MB);
7061 return (BWN_CCK_RATE_5MB);
7063 return (BWN_CCK_RATE_11MB);
7065 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]);
7070 bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m,
7071 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate,
7072 int rssi, int noise)
7074 struct bwn_softc *sc = mac->mac_sc;
7075 const struct ieee80211_frame_min *wh;
7077 uint16_t low_mactime_now;
7080 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL)
7081 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
7083 wh = mtod(m, const struct ieee80211_frame_min *);
7084 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
7085 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
7087 bwn_tsf_read(mac, &tsf);
7088 low_mactime_now = tsf;
7089 tsf = tsf & ~0xffffULL;
7091 switch (mac->mac_fw.fw_hdr_format) {
7092 case BWN_FW_HDR_351:
7093 case BWN_FW_HDR_410:
7094 mt = le16toh(rxhdr->ps4.r351.mac_time);
7096 case BWN_FW_HDR_598:
7097 mt = le16toh(rxhdr->ps4.r598.mac_time);
7102 if (low_mactime_now < mt)
7105 sc->sc_rx_th.wr_tsf = tsf;
7106 sc->sc_rx_th.wr_rate = rate;
7107 sc->sc_rx_th.wr_antsignal = rssi;
7108 sc->sc_rx_th.wr_antnoise = noise;
7112 bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
7116 KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3,
7117 ("%s:%d: fail", __func__, __LINE__));
7119 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
7120 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
7127 bwn_dma_attach(struct bwn_mac *mac)
7129 struct bwn_dma *dma;
7130 struct bwn_softc *sc;
7131 struct bhnd_dma_translation *dt, dma_translation;
7132 bhnd_addr_t addrext_req;
7135 u_int addrext_shift, addr_width;
7138 dma = &mac->mac_method.dma;
7142 if (sc->sc_quirks & BWN_QUIRK_NODMA)
7145 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__));
7147 /* Use the DMA engine's maximum host address width to determine the
7148 * addrext constraints, and supported device address width. */
7149 switch (mac->mac_dmatype) {
7150 case BHND_DMA_ADDR_30BIT:
7151 /* 32-bit engine without addrext support */
7155 /* We can address the full 32-bit device address space */
7156 addr_width = BHND_DMA_ADDR_32BIT;
7159 case BHND_DMA_ADDR_32BIT:
7160 /* 32-bit engine with addrext support */
7161 addrext_req = BWN_DMA32_ADDREXT_MASK;
7162 addrext_shift = BWN_DMA32_ADDREXT_SHIFT;
7163 addr_width = BHND_DMA_ADDR_32BIT;
7166 case BHND_DMA_ADDR_64BIT:
7167 /* 64-bit engine with addrext support */
7168 addrext_req = BWN_DMA64_ADDREXT_MASK;
7169 addrext_shift = BWN_DMA64_ADDREXT_SHIFT;
7170 addr_width = BHND_DMA_ADDR_64BIT;
7174 device_printf(sc->sc_dev, "unsupported DMA address width: %d\n",
7180 /* Fetch our device->host DMA translation and tag */
7181 error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat,
7184 device_printf(sc->sc_dev, "error fetching DMA translation: "
7189 /* Verify that our DMA engine's addrext constraints are compatible with
7190 * our DMA translation */
7191 if (addrext_req != 0x0 &&
7192 (dma_translation.addrext_mask & addrext_req) != addrext_req)
7194 device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible "
7195 "with device addrext mask %#jx, disabling extended address "
7196 "support\n", (uintmax_t)dma_translation.addrext_mask,
7197 (uintmax_t)addrext_req);
7203 /* Apply our addrext translation constraint */
7204 dma_translation.addrext_mask = addrext_req;
7206 /* Initialize our DMA engine configuration */
7207 mac->mac_flags |= BWN_MAC_FLAG_DMA;
7209 dma->addrext_shift = addrext_shift;
7210 dma->translation = dma_translation;
7212 dt = &dma->translation;
7214 /* Dermine our translation's maximum supported address */
7215 lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR);
7218 * Create top level DMA tag
7220 error = bus_dma_tag_create(dmat, /* parent */
7221 BWN_ALIGN, 0, /* alignment, bounds */
7222 lowaddr, /* lowaddr */
7223 BUS_SPACE_MAXADDR, /* highaddr */
7224 NULL, NULL, /* filter, filterarg */
7225 BUS_SPACE_MAXSIZE, /* maxsize */
7226 BUS_SPACE_UNRESTRICTED, /* nsegments */
7227 BUS_SPACE_MAXSIZE, /* maxsegsize */
7229 NULL, NULL, /* lockfunc, lockarg */
7232 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
7237 * Create TX/RX mbuf DMA tag
7239 error = bus_dma_tag_create(dma->parent_dtag,
7247 BUS_SPACE_MAXSIZE_32BIT,
7252 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7255 error = bus_dma_tag_create(dma->parent_dtag,
7263 BUS_SPACE_MAXSIZE_32BIT,
7268 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7272 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1);
7273 if (!dma->wme[WME_AC_BK])
7276 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1);
7277 if (!dma->wme[WME_AC_BE])
7280 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1);
7281 if (!dma->wme[WME_AC_VI])
7284 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1);
7285 if (!dma->wme[WME_AC_VO])
7288 dma->mcast = bwn_dma_ringsetup(mac, 4, 1);
7291 dma->rx = bwn_dma_ringsetup(mac, 0, 0);
7297 fail7: bwn_dma_ringfree(&dma->mcast);
7298 fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
7299 fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
7300 fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
7301 fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
7302 fail2: bus_dma_tag_destroy(dma->txbuf_dtag);
7303 fail1: bus_dma_tag_destroy(dma->rxbuf_dtag);
7304 fail0: bus_dma_tag_destroy(dma->parent_dtag);
7308 static struct bwn_dma_ring *
7309 bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status,
7310 uint16_t cookie, int *slot)
7312 struct bwn_dma *dma = &mac->mac_method.dma;
7313 struct bwn_dma_ring *dr;
7314 struct bwn_softc *sc = mac->mac_sc;
7316 BWN_ASSERT_LOCKED(mac->mac_sc);
7318 switch (cookie & 0xf000) {
7320 dr = dma->wme[WME_AC_BK];
7323 dr = dma->wme[WME_AC_BE];
7326 dr = dma->wme[WME_AC_VI];
7329 dr = dma->wme[WME_AC_VO];
7337 ("invalid cookie value %d", cookie & 0xf000));
7339 *slot = (cookie & 0x0fff);
7340 if (*slot < 0 || *slot >= dr->dr_numslots) {
7342 * XXX FIXME: sometimes H/W returns TX DONE events duplicately
7343 * that it occurs events which have same H/W sequence numbers.
7344 * When it's occurred just prints a WARNING msgs and ignores.
7346 KASSERT(status->seq == dma->lastseq,
7347 ("%s:%d: fail", __func__, __LINE__));
7348 device_printf(sc->sc_dev,
7349 "out of slot ranges (0 < %d < %d)\n", *slot,
7353 dma->lastseq = status->seq;
7358 bwn_dma_stop(struct bwn_mac *mac)
7360 struct bwn_dma *dma;
7362 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
7364 dma = &mac->mac_method.dma;
7366 bwn_dma_ringstop(&dma->rx);
7367 bwn_dma_ringstop(&dma->wme[WME_AC_BK]);
7368 bwn_dma_ringstop(&dma->wme[WME_AC_BE]);
7369 bwn_dma_ringstop(&dma->wme[WME_AC_VI]);
7370 bwn_dma_ringstop(&dma->wme[WME_AC_VO]);
7371 bwn_dma_ringstop(&dma->mcast);
7375 bwn_dma_ringstop(struct bwn_dma_ring **dr)
7381 bwn_dma_cleanup(*dr);
7385 bwn_pio_stop(struct bwn_mac *mac)
7387 struct bwn_pio *pio;
7389 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
7391 pio = &mac->mac_method.pio;
7393 bwn_destroy_queue_tx(&pio->mcast);
7394 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]);
7395 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]);
7396 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
7397 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
7401 bwn_led_attach(struct bwn_mac *mac)
7403 struct bwn_softc *sc = mac->mac_sc;
7404 const uint8_t *led_act = NULL;
7408 sc->sc_led_idle = (2350 * hz) / 1000;
7409 sc->sc_led_blink = 1;
7411 for (i = 0; i < N(bwn_vendor_led_act); ++i) {
7412 if (sc->sc_board_info.board_vendor ==
7413 bwn_vendor_led_act[i].vid) {
7414 led_act = bwn_vendor_led_act[i].led_act;
7418 if (led_act == NULL)
7419 led_act = bwn_default_led_act;
7421 _Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX,
7422 "invalid NVRAM variable name array");
7424 for (i = 0; i < BWN_LED_MAX; ++i) {
7425 struct bwn_led *led;
7428 led = &sc->sc_leds[i];
7430 KASSERT(i < nitems(bwn_led_vars), ("unknown LED index"));
7431 error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i],
7434 if (error != ENOENT) {
7435 device_printf(sc->sc_dev, "NVRAM variable %s "
7436 "unreadable: %d", bwn_led_vars[i], error);
7440 /* Not found; use default */
7441 led->led_act = led_act[i];
7443 if (val & BWN_LED_ACT_LOW)
7444 led->led_flags |= BWN_LED_F_ACTLOW;
7445 led->led_act = val & BWN_LED_ACT_MASK;
7447 led->led_mask = (1 << i);
7449 if (led->led_act == BWN_LED_ACT_BLINK_SLOW ||
7450 led->led_act == BWN_LED_ACT_BLINK_POLL ||
7451 led->led_act == BWN_LED_ACT_BLINK) {
7452 led->led_flags |= BWN_LED_F_BLINK;
7453 if (led->led_act == BWN_LED_ACT_BLINK_POLL)
7454 led->led_flags |= BWN_LED_F_POLLABLE;
7455 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW)
7456 led->led_flags |= BWN_LED_F_SLOW;
7458 if (sc->sc_blink_led == NULL) {
7459 sc->sc_blink_led = led;
7460 if (led->led_flags & BWN_LED_F_SLOW)
7461 BWN_LED_SLOWDOWN(sc->sc_led_idle);
7465 DPRINTF(sc, BWN_DEBUG_LED,
7466 "%dth led, act %d, lowact %d\n", i,
7467 led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
7469 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
7474 static __inline uint16_t
7475 bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on)
7478 if (led->led_flags & BWN_LED_F_ACTLOW)
7481 val |= led->led_mask;
7483 val &= ~led->led_mask;
7488 bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate)
7490 struct bwn_softc *sc = mac->mac_sc;
7491 struct ieee80211com *ic = &sc->sc_ic;
7495 if (nstate == IEEE80211_S_INIT) {
7496 callout_stop(&sc->sc_led_blink_ch);
7497 sc->sc_led_blinking = 0;
7500 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0)
7503 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7504 for (i = 0; i < BWN_LED_MAX; ++i) {
7505 struct bwn_led *led = &sc->sc_leds[i];
7508 if (led->led_act == BWN_LED_ACT_UNKN ||
7509 led->led_act == BWN_LED_ACT_NULL)
7512 if ((led->led_flags & BWN_LED_F_BLINK) &&
7513 nstate != IEEE80211_S_INIT)
7516 switch (led->led_act) {
7517 case BWN_LED_ACT_ON: /* Always on */
7520 case BWN_LED_ACT_OFF: /* Always off */
7521 case BWN_LED_ACT_5GHZ: /* TODO: 11A */
7527 case IEEE80211_S_INIT:
7530 case IEEE80211_S_RUN:
7531 if (led->led_act == BWN_LED_ACT_11G &&
7532 ic->ic_curmode != IEEE80211_MODE_11G)
7536 if (led->led_act == BWN_LED_ACT_ASSOC)
7543 val = bwn_led_onoff(led, val, on);
7545 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7549 bwn_led_event(struct bwn_mac *mac, int event)
7551 struct bwn_softc *sc = mac->mac_sc;
7552 struct bwn_led *led = sc->sc_blink_led;
7555 if (event == BWN_LED_EVENT_POLL) {
7556 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
7558 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
7562 sc->sc_led_ticks = ticks;
7563 if (sc->sc_led_blinking)
7567 case BWN_LED_EVENT_RX:
7568 rate = sc->sc_rx_rate;
7570 case BWN_LED_EVENT_TX:
7571 rate = sc->sc_tx_rate;
7573 case BWN_LED_EVENT_POLL:
7577 panic("unknown LED event %d\n", event);
7580 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
7581 bwn_led_duration[rate].off_dur);
7585 bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
7587 struct bwn_softc *sc = mac->mac_sc;
7588 struct bwn_led *led = sc->sc_blink_led;
7591 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7592 val = bwn_led_onoff(led, val, 1);
7593 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7595 if (led->led_flags & BWN_LED_F_SLOW) {
7596 BWN_LED_SLOWDOWN(on_dur);
7597 BWN_LED_SLOWDOWN(off_dur);
7600 sc->sc_led_blinking = 1;
7601 sc->sc_led_blink_offdur = off_dur;
7603 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
7607 bwn_led_blink_next(void *arg)
7609 struct bwn_mac *mac = arg;
7610 struct bwn_softc *sc = mac->mac_sc;
7613 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7614 val = bwn_led_onoff(sc->sc_blink_led, val, 0);
7615 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7617 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
7618 bwn_led_blink_end, mac);
7622 bwn_led_blink_end(void *arg)
7624 struct bwn_mac *mac = arg;
7625 struct bwn_softc *sc = mac->mac_sc;
7627 sc->sc_led_blinking = 0;
7631 bwn_suspend(device_t dev)
7633 struct bwn_softc *sc = device_get_softc(dev);
7642 bwn_resume(device_t dev)
7644 struct bwn_softc *sc = device_get_softc(dev);
7645 int error = EDOOFUS;
7648 if (sc->sc_ic.ic_nrunning > 0)
7649 error = bwn_init(sc);
7652 ieee80211_start_all(&sc->sc_ic);
7657 bwn_rfswitch(void *arg)
7659 struct bwn_softc *sc = arg;
7660 struct bwn_mac *mac = sc->sc_curmac;
7661 int cur = 0, prev = 0;
7663 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED,
7664 ("%s: invalid MAC status %d", __func__, mac->mac_status));
7666 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP
7667 || mac->mac_phy.type == BWN_PHYTYPE_N) {
7668 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI)
7669 & BWN_RF_HWENABLED_HI_MASK))
7672 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO)
7673 & BWN_RF_HWENABLED_LO_MASK)
7677 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)
7680 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n",
7681 __func__, cur, prev);
7685 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
7687 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON;
7689 device_printf(sc->sc_dev,
7690 "status of RF switch is changed to %s\n",
7691 cur ? "ON" : "OFF");
7692 if (cur != mac->mac_phy.rf_on) {
7696 bwn_rf_turnoff(mac);
7700 callout_schedule(&sc->sc_rfswitch_ch, hz);
7704 bwn_sysctl_node(struct bwn_softc *sc)
7706 device_t dev = sc->sc_dev;
7707 struct bwn_mac *mac;
7708 struct bwn_stats *stats;
7710 /* XXX assume that count of MAC is only 1. */
7712 if ((mac = sc->sc_curmac) == NULL)
7714 stats = &mac->mac_stats;
7716 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7717 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7718 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level");
7719 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7720 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7721 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS");
7722 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7723 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7724 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send");
7727 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
7728 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7729 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
7733 static device_method_t bwn_methods[] = {
7734 /* Device interface */
7735 DEVMETHOD(device_probe, bwn_probe),
7736 DEVMETHOD(device_attach, bwn_attach),
7737 DEVMETHOD(device_detach, bwn_detach),
7738 DEVMETHOD(device_suspend, bwn_suspend),
7739 DEVMETHOD(device_resume, bwn_resume),
7742 static driver_t bwn_driver = {
7745 sizeof(struct bwn_softc)
7747 static devclass_t bwn_devclass;
7748 DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0);
7749 MODULE_DEPEND(bwn, bhnd, 1, 1, 1);
7750 MODULE_DEPEND(bwn, gpiobus, 1, 1, 1);
7751 MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */
7752 MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */
7753 MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1);
7754 MODULE_VERSION(bwn, 1);