2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org>
5 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
6 * Copyright (c) 2017 The FreeBSD Foundation
9 * Portions of this software were developed by Landon Fuller
10 * under sponsorship from the FreeBSD Foundation.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer,
17 * without modification.
18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
20 * redistribution must be conditioned upon including a substantially
21 * similar Disclaimer requirement for further binary redistribution.
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34 * THE POSSIBILITY OF SUCH DAMAGES.
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
41 * The Broadcom Wireless LAN controller driver.
47 #include <sys/param.h>
48 #include <sys/systm.h>
49 #include <sys/kernel.h>
51 #include <sys/malloc.h>
52 #include <sys/module.h>
53 #include <sys/endian.h>
54 #include <sys/errno.h>
55 #include <sys/firmware.h>
57 #include <sys/mutex.h>
58 #include <machine/bus.h>
59 #include <machine/resource.h>
62 #include <sys/socket.h>
63 #include <sys/sockio.h>
65 #include <net/ethernet.h>
67 #include <net/if_var.h>
68 #include <net/if_arp.h>
69 #include <net/if_dl.h>
70 #include <net/if_llc.h>
71 #include <net/if_media.h>
72 #include <net/if_types.h>
74 #include <net80211/ieee80211_var.h>
75 #include <net80211/ieee80211_radiotap.h>
76 #include <net80211/ieee80211_regdomain.h>
77 #include <net80211/ieee80211_phy.h>
78 #include <net80211/ieee80211_ratectl.h>
80 #include <dev/bhnd/bhnd.h>
81 #include <dev/bhnd/bhnd_ids.h>
83 #include <dev/bhnd/cores/chipc/chipc.h>
84 #include <dev/bhnd/cores/pmu/bhnd_pmu.h>
86 #include <dev/bwn/if_bwnreg.h>
87 #include <dev/bwn/if_bwnvar.h>
89 #include <dev/bwn/if_bwn_debug.h>
90 #include <dev/bwn/if_bwn_misc.h>
91 #include <dev/bwn/if_bwn_util.h>
92 #include <dev/bwn/if_bwn_phy_common.h>
93 #include <dev/bwn/if_bwn_phy_g.h>
94 #include <dev/bwn/if_bwn_phy_lp.h>
95 #include <dev/bwn/if_bwn_phy_n.h>
97 #include "bhnd_nvram_map.h"
101 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0,
102 "Broadcom driver parameters");
105 * Tunable & sysctl variables.
109 static int bwn_debug = 0;
110 SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0,
111 "Broadcom debugging printfs");
114 static int bwn_bfp = 0; /* use "Bad Frames Preemption" */
115 SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0,
116 "uses Bad Frames Preemption");
117 static int bwn_bluetooth = 1;
118 SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0,
119 "turns on Bluetooth Coexistence");
120 static int bwn_hwpctl = 0;
121 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0,
122 "uses H/W power control");
123 static int bwn_usedma = 1;
124 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0,
126 TUNABLE_INT("hw.bwn.usedma", &bwn_usedma);
127 static int bwn_wme = 1;
128 SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0,
131 static void bwn_attach_pre(struct bwn_softc *);
132 static int bwn_attach_post(struct bwn_softc *);
133 static int bwn_retain_bus_providers(struct bwn_softc *sc);
134 static void bwn_release_bus_providers(struct bwn_softc *sc);
135 static void bwn_sprom_bugfixes(device_t);
136 static int bwn_init(struct bwn_softc *);
137 static void bwn_parent(struct ieee80211com *);
138 static void bwn_start(struct bwn_softc *);
139 static int bwn_transmit(struct ieee80211com *, struct mbuf *);
140 static int bwn_attach_core(struct bwn_mac *);
141 static int bwn_phy_getinfo(struct bwn_mac *, int);
142 static int bwn_chiptest(struct bwn_mac *);
143 static int bwn_setup_channels(struct bwn_mac *, int, int);
144 static void bwn_shm_ctlword(struct bwn_mac *, uint16_t,
146 static void bwn_addchannels(struct ieee80211_channel [], int, int *,
147 const struct bwn_channelinfo *, const uint8_t []);
148 static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *,
149 const struct ieee80211_bpf_params *);
150 static void bwn_updateslot(struct ieee80211com *);
151 static void bwn_update_promisc(struct ieee80211com *);
152 static void bwn_wme_init(struct bwn_mac *);
153 static int bwn_wme_update(struct ieee80211com *);
154 static void bwn_wme_clear(struct bwn_softc *);
155 static void bwn_wme_load(struct bwn_mac *);
156 static void bwn_wme_loadparams(struct bwn_mac *,
157 const struct wmeParams *, uint16_t);
158 static void bwn_scan_start(struct ieee80211com *);
159 static void bwn_scan_end(struct ieee80211com *);
160 static void bwn_set_channel(struct ieee80211com *);
161 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *,
162 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
163 const uint8_t [IEEE80211_ADDR_LEN],
164 const uint8_t [IEEE80211_ADDR_LEN]);
165 static void bwn_vap_delete(struct ieee80211vap *);
166 static void bwn_stop(struct bwn_softc *);
167 static int bwn_core_forceclk(struct bwn_mac *, bool);
168 static int bwn_core_init(struct bwn_mac *);
169 static void bwn_core_start(struct bwn_mac *);
170 static void bwn_core_exit(struct bwn_mac *);
171 static void bwn_bt_disable(struct bwn_mac *);
172 static int bwn_chip_init(struct bwn_mac *);
173 static void bwn_set_txretry(struct bwn_mac *, int, int);
174 static void bwn_rate_init(struct bwn_mac *);
175 static void bwn_set_phytxctl(struct bwn_mac *);
176 static void bwn_spu_setdelay(struct bwn_mac *, int);
177 static void bwn_bt_enable(struct bwn_mac *);
178 static void bwn_set_macaddr(struct bwn_mac *);
179 static void bwn_crypt_init(struct bwn_mac *);
180 static void bwn_chip_exit(struct bwn_mac *);
181 static int bwn_fw_fillinfo(struct bwn_mac *);
182 static int bwn_fw_loaducode(struct bwn_mac *);
183 static int bwn_gpio_init(struct bwn_mac *);
184 static int bwn_fw_loadinitvals(struct bwn_mac *);
185 static int bwn_phy_init(struct bwn_mac *);
186 static void bwn_set_txantenna(struct bwn_mac *, int);
187 static void bwn_set_opmode(struct bwn_mac *);
188 static void bwn_rate_write(struct bwn_mac *, uint16_t, int);
189 static uint8_t bwn_plcp_getcck(const uint8_t);
190 static uint8_t bwn_plcp_getofdm(const uint8_t);
191 static void bwn_pio_init(struct bwn_mac *);
192 static uint16_t bwn_pio_idx2base(struct bwn_mac *, int);
193 static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *,
195 static void bwn_pio_setupqueue_rx(struct bwn_mac *,
196 struct bwn_pio_rxqueue *, int);
197 static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *);
198 static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *,
200 static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *);
201 static int bwn_pio_rx(struct bwn_pio_rxqueue *);
202 static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *);
203 static void bwn_pio_handle_txeof(struct bwn_mac *,
204 const struct bwn_txstatus *);
205 static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t);
206 static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t);
207 static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t,
209 static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t,
211 static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *,
213 static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t);
214 static uint32_t bwn_pio_write_multi_4(struct bwn_mac *,
215 struct bwn_pio_txqueue *, uint32_t, const void *, int);
216 static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *,
218 static uint16_t bwn_pio_write_multi_2(struct bwn_mac *,
219 struct bwn_pio_txqueue *, uint16_t, const void *, int);
220 static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *,
221 struct bwn_pio_txqueue *, uint16_t, struct mbuf *);
222 static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *,
223 uint16_t, struct bwn_pio_txpkt **);
224 static void bwn_dma_init(struct bwn_mac *);
225 static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t);
226 static uint16_t bwn_dma_base(int, int);
227 static void bwn_dma_ringfree(struct bwn_dma_ring **);
228 static void bwn_dma_32_getdesc(struct bwn_dma_ring *,
229 int, struct bwn_dmadesc_generic **,
230 struct bwn_dmadesc_meta **);
231 static void bwn_dma_32_setdesc(struct bwn_dma_ring *,
232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
234 static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int);
235 static void bwn_dma_32_suspend(struct bwn_dma_ring *);
236 static void bwn_dma_32_resume(struct bwn_dma_ring *);
237 static int bwn_dma_32_get_curslot(struct bwn_dma_ring *);
238 static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int);
239 static void bwn_dma_64_getdesc(struct bwn_dma_ring *,
240 int, struct bwn_dmadesc_generic **,
241 struct bwn_dmadesc_meta **);
242 static void bwn_dma_64_setdesc(struct bwn_dma_ring *,
243 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int,
245 static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int);
246 static void bwn_dma_64_suspend(struct bwn_dma_ring *);
247 static void bwn_dma_64_resume(struct bwn_dma_ring *);
248 static int bwn_dma_64_get_curslot(struct bwn_dma_ring *);
249 static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int);
250 static int bwn_dma_allocringmemory(struct bwn_dma_ring *);
251 static void bwn_dma_setup(struct bwn_dma_ring *);
252 static void bwn_dma_free_ringmemory(struct bwn_dma_ring *);
253 static void bwn_dma_cleanup(struct bwn_dma_ring *);
254 static void bwn_dma_free_descbufs(struct bwn_dma_ring *);
255 static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int);
256 static void bwn_dma_rx(struct bwn_dma_ring *);
257 static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int);
258 static void bwn_dma_free_descbuf(struct bwn_dma_ring *,
259 struct bwn_dmadesc_meta *);
260 static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *);
261 static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
262 static int bwn_dma_freeslot(struct bwn_dma_ring *);
263 static int bwn_dma_nextslot(struct bwn_dma_ring *, int);
264 static void bwn_dma_rxeof(struct bwn_dma_ring *, int *);
265 static int bwn_dma_newbuf(struct bwn_dma_ring *,
266 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *,
268 static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int,
270 static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *);
271 static void bwn_ratectl_tx_complete(const struct ieee80211_node *,
272 const struct bwn_txstatus *);
273 static void bwn_dma_handle_txeof(struct bwn_mac *,
274 const struct bwn_txstatus *);
275 static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *,
277 static int bwn_dma_getslot(struct bwn_dma_ring *);
278 static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *,
280 static int bwn_dma_attach(struct bwn_mac *);
281 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *,
283 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *,
284 const struct bwn_txstatus *, uint16_t, int *);
285 static void bwn_dma_free(struct bwn_mac *);
286 static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype);
287 static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype,
288 const char *, struct bwn_fwfile *);
289 static void bwn_release_firmware(struct bwn_mac *);
290 static void bwn_do_release_fw(struct bwn_fwfile *);
291 static uint16_t bwn_fwcaps_read(struct bwn_mac *);
292 static int bwn_fwinitvals_write(struct bwn_mac *,
293 const struct bwn_fwinitvals *, size_t, size_t);
294 static uint16_t bwn_ant2phy(int);
295 static void bwn_mac_write_bssid(struct bwn_mac *);
296 static void bwn_mac_setfilter(struct bwn_mac *, uint16_t,
298 static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t,
299 const uint8_t *, size_t, const uint8_t *);
300 static void bwn_key_macwrite(struct bwn_mac *, uint8_t,
302 static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t,
304 static void bwn_phy_exit(struct bwn_mac *);
305 static void bwn_core_stop(struct bwn_mac *);
306 static int bwn_switch_band(struct bwn_softc *,
307 struct ieee80211_channel *);
308 static int bwn_phy_reset(struct bwn_mac *);
309 static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int);
310 static void bwn_set_pretbtt(struct bwn_mac *);
311 static int bwn_intr(void *);
312 static void bwn_intrtask(void *, int);
313 static void bwn_restart(struct bwn_mac *, const char *);
314 static void bwn_intr_ucode_debug(struct bwn_mac *);
315 static void bwn_intr_tbtt_indication(struct bwn_mac *);
316 static void bwn_intr_atim_end(struct bwn_mac *);
317 static void bwn_intr_beacon(struct bwn_mac *);
318 static void bwn_intr_pmq(struct bwn_mac *);
319 static void bwn_intr_noise(struct bwn_mac *);
320 static void bwn_intr_txeof(struct bwn_mac *);
321 static void bwn_hwreset(void *, int);
322 static void bwn_handle_fwpanic(struct bwn_mac *);
323 static void bwn_load_beacon0(struct bwn_mac *);
324 static void bwn_load_beacon1(struct bwn_mac *);
325 static uint32_t bwn_jssi_read(struct bwn_mac *);
326 static void bwn_noise_gensample(struct bwn_mac *);
327 static void bwn_handle_txeof(struct bwn_mac *,
328 const struct bwn_txstatus *);
329 static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *);
330 static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t);
331 static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *,
333 static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *);
334 static int bwn_set_txhdr(struct bwn_mac *,
335 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *,
337 static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t,
339 static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t);
340 static uint8_t bwn_get_fbrate(uint8_t);
341 static void bwn_txpwr(void *, int);
342 static void bwn_tasks(void *);
343 static void bwn_task_15s(struct bwn_mac *);
344 static void bwn_task_30s(struct bwn_mac *);
345 static void bwn_task_60s(struct bwn_mac *);
346 static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *,
348 static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *);
349 static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *,
350 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int,
352 static void bwn_tsf_read(struct bwn_mac *, uint64_t *);
353 static void bwn_set_slot_time(struct bwn_mac *, uint16_t);
354 static void bwn_watchdog(void *);
355 static void bwn_dma_stop(struct bwn_mac *);
356 static void bwn_pio_stop(struct bwn_mac *);
357 static void bwn_dma_ringstop(struct bwn_dma_ring **);
358 static int bwn_led_attach(struct bwn_mac *);
359 static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state);
360 static void bwn_led_event(struct bwn_mac *, int);
361 static void bwn_led_blink_start(struct bwn_mac *, int, int);
362 static void bwn_led_blink_next(void *);
363 static void bwn_led_blink_end(void *);
364 static void bwn_rfswitch(void *);
365 static void bwn_rf_turnon(struct bwn_mac *);
366 static void bwn_rf_turnoff(struct bwn_mac *);
367 static void bwn_sysctl_node(struct bwn_softc *);
369 static const struct bwn_channelinfo bwn_chantable_bg = {
371 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 },
372 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 },
373 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 },
374 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 },
375 { 2472, 13, 30 }, { 2484, 14, 30 } },
379 static const struct bwn_channelinfo bwn_chantable_a = {
381 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 },
382 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 },
383 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 },
384 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 },
385 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 },
386 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 },
387 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 },
388 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 },
389 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 },
390 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 },
391 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 },
392 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 },
398 static const struct bwn_channelinfo bwn_chantable_n = {
400 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 },
401 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 },
402 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 },
403 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 },
404 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 },
405 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 },
406 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 },
407 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 },
408 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 },
409 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 },
410 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 },
411 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 },
412 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 },
413 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 },
414 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 },
415 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 },
416 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 },
417 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 },
418 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 },
419 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 },
420 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 },
421 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 },
422 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 },
423 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 },
424 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 },
425 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 },
426 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 },
427 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 },
428 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 },
429 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 },
430 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 },
431 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 },
432 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 },
433 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 },
434 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 },
435 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 },
436 { 6130, 226, 30 }, { 6140, 228, 30 } },
441 #define VENDOR_LED_ACT(vendor) \
443 .vid = PCI_VENDOR_##vendor, \
444 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \
447 static const struct {
449 uint8_t led_act[BWN_LED_MAX];
450 } bwn_vendor_led_act[] = {
451 VENDOR_LED_ACT(HP_COMPAQ),
452 VENDOR_LED_ACT(ASUSTEK)
455 static const uint8_t bwn_default_led_act[BWN_LED_MAX] =
456 { BWN_VENDOR_LED_ACT_DEFAULT };
458 #undef VENDOR_LED_ACT
460 static const char *bwn_led_vars[] = {
467 static const struct {
470 } bwn_led_duration[109] = {
486 static const uint16_t bwn_wme_shm_offsets[] = {
487 [0] = BWN_WME_BESTEFFORT,
488 [1] = BWN_WME_BACKGROUND,
493 /* Supported D11 core revisions */
494 #define BWN_DEV(_hwrev) {{ \
495 BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11), \
496 BHND_MATCH_CORE_REV(_hwrev), \
498 static const struct bhnd_device bwn_devices[] = {
499 BWN_DEV(HWREV_RANGE(5, 16)),
500 BWN_DEV(HWREV_EQ(23)),
504 /* D11 quirks when bridged via a PCI host bridge core */
505 static const struct bhnd_device_quirk pci_bridge_quirks[] = {
506 BHND_CORE_QUIRK (HWREV_LTE(10), BWN_QUIRK_UCODE_SLOWCLOCK_WAR),
507 BHND_DEVICE_QUIRK_END
510 /* D11 quirks when bridged via a PCMCIA host bridge core */
511 static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = {
512 BHND_CORE_QUIRK (HWREV_ANY, BWN_QUIRK_NODMA),
513 BHND_DEVICE_QUIRK_END
516 /* Host bridge cores for which D11 quirk flags should be applied */
517 static const struct bhnd_device bridge_devices[] = {
518 BHND_DEVICE(BCM, PCI, NULL, pci_bridge_quirks),
519 BHND_DEVICE(BCM, PCMCIA, NULL, pcmcia_bridge_quirks),
524 bwn_probe(device_t dev)
526 const struct bhnd_device *id;
528 id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0]));
532 bhnd_set_default_core_desc(dev);
533 return (BUS_PROBE_DEFAULT);
537 bwn_attach(device_t dev)
540 struct bwn_softc *sc;
541 device_t parent, hostb;
542 char chip_name[BHND_CHIPID_MAX_NAMELEN];
545 sc = device_get_softc(dev);
548 sc->sc_debug = bwn_debug;
553 /* Determine the driver quirks applicable to this device, including any
554 * quirks specific to the bus host bridge core (if any) */
555 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices,
556 sizeof(bwn_devices[0]));
558 parent = device_get_parent(dev);
559 if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) {
560 sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices,
561 sizeof(bridge_devices[0]));
564 /* DMA explicitly disabled? */
566 sc->sc_quirks |= BWN_QUIRK_NODMA;
568 /* Fetch our chip identification and board info */
569 sc->sc_cid = *bhnd_get_chipid(dev);
570 if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) {
571 device_printf(sc->sc_dev, "couldn't read board info\n");
575 /* Allocate our D11 register block and PMU state */
577 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
578 &sc->sc_mem_rid, RF_ACTIVE);
579 if (sc->sc_mem_res == NULL) {
580 device_printf(sc->sc_dev, "couldn't allocate registers\n");
584 if ((error = bhnd_alloc_pmu(sc->sc_dev))) {
585 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
586 sc->sc_mem_rid, sc->sc_mem_res);
590 /* Retain references to all required bus service providers */
591 if ((error = bwn_retain_bus_providers(sc)))
594 /* Fetch mask of available antennas */
595 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G,
598 device_printf(sc->sc_dev, "error determining 2GHz antenna "
599 "availability from NVRAM: %d\n", error);
603 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G,
606 device_printf(sc->sc_dev, "error determining 5GHz antenna "
607 "availability from NVRAM: %d\n", error);
611 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) {
613 bwn_sprom_bugfixes(dev);
614 sc->sc_flags |= BWN_FLAG_ATTACHED;
617 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO);
619 mac->mac_status = BWN_MAC_STATUS_UNINIT;
621 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP;
623 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac);
624 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac);
625 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac);
627 error = bwn_attach_core(mac);
630 error = bwn_led_attach(mac);
634 bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id);
635 device_printf(sc->sc_dev, "WLAN (%s rev %u) "
636 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n",
637 chip_name, bhnd_get_hwrev(sc->sc_dev), mac->mac_phy.analog,
638 mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf,
639 mac->mac_phy.rf_ver, mac->mac_phy.rf_rev);
640 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
641 device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype);
643 device_printf(sc->sc_dev, "PIO\n");
646 device_printf(sc->sc_dev,
647 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n");
650 mac->mac_rid_irq = 0;
651 mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
652 &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE);
654 if (mac->mac_res_irq == NULL) {
655 device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n");
660 error = bus_setup_intr(dev, mac->mac_res_irq,
661 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac,
664 device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n",
669 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list);
672 * calls attach-post routine
674 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0)
679 if (mac != NULL && mac->mac_res_irq != NULL) {
680 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
685 bhnd_release_pmu(dev);
686 bwn_release_bus_providers(sc);
688 if (sc->sc_mem_res != NULL) {
689 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
690 sc->sc_mem_rid, sc->sc_mem_res);
697 bwn_retain_bus_providers(struct bwn_softc *sc)
699 struct chipc_caps *ccaps;
701 sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC);
702 if (sc->sc_chipc == NULL) {
703 device_printf(sc->sc_dev, "ChipCommon device not found\n");
707 ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc);
709 sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO);
710 if (sc->sc_gpio == NULL) {
711 device_printf(sc->sc_dev, "GPIO device not found\n");
716 sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU);
717 if (sc->sc_pmu == NULL) {
718 device_printf(sc->sc_dev, "PMU device not found\n");
726 bwn_release_bus_providers(sc);
731 bwn_release_bus_providers(struct bwn_softc *sc)
733 #define BWN_RELEASE_PROV(_sc, _prov, _service) do { \
734 if ((_sc)-> _prov != NULL) { \
735 bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov, \
737 (_sc)-> _prov = NULL; \
741 BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC);
742 BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO);
743 BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU);
745 #undef BWN_RELEASE_PROV
749 bwn_attach_post(struct bwn_softc *sc)
751 struct ieee80211com *ic;
752 const char *mac_varname;
759 ic->ic_name = device_get_nameunit(sc->sc_dev);
760 /* XXX not right but it's not used anywhere important */
761 ic->ic_phytype = IEEE80211_T_OFDM;
762 ic->ic_opmode = IEEE80211_M_STA;
764 IEEE80211_C_STA /* station mode supported */
765 | IEEE80211_C_MONITOR /* monitor mode */
766 | IEEE80211_C_AHDEMO /* adhoc demo mode */
767 | IEEE80211_C_SHPREAMBLE /* short preamble supported */
768 | IEEE80211_C_SHSLOT /* short slot time supported */
769 | IEEE80211_C_WME /* WME/WMM supported */
770 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */
772 | IEEE80211_C_BGSCAN /* capable of bg scanning */
774 | IEEE80211_C_TXPMGT /* capable of txpow mgt */
777 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */
779 /* Determine the NVRAM variable containing our MAC address */
780 core_unit = bhnd_get_core_unit(sc->sc_dev);
782 if (sc->sc_board_info.board_srom_rev <= 2) {
783 if (core_unit == 0) {
784 mac_varname = BHND_NVAR_IL0MACADDR;
785 } else if (core_unit == 1) {
786 mac_varname = BHND_NVAR_ET1MACADDR;
789 if (core_unit == 0) {
790 mac_varname = BHND_NVAR_MACADDR;
794 if (mac_varname == NULL) {
795 device_printf(sc->sc_dev, "missing MAC address variable for "
796 "D11 core %u", core_unit);
800 /* Read the MAC address from NVRAM */
801 error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr,
802 sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY);
804 device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname,
809 /* call MI attach routine. */
810 ieee80211_ifattach(ic);
812 ic->ic_headroom = sizeof(struct bwn_txhdr);
814 /* override default methods */
815 ic->ic_raw_xmit = bwn_raw_xmit;
816 ic->ic_updateslot = bwn_updateslot;
817 ic->ic_update_promisc = bwn_update_promisc;
818 ic->ic_wme.wme_update = bwn_wme_update;
819 ic->ic_scan_start = bwn_scan_start;
820 ic->ic_scan_end = bwn_scan_end;
821 ic->ic_set_channel = bwn_set_channel;
822 ic->ic_vap_create = bwn_vap_create;
823 ic->ic_vap_delete = bwn_vap_delete;
824 ic->ic_transmit = bwn_transmit;
825 ic->ic_parent = bwn_parent;
827 ieee80211_radiotap_attach(ic,
828 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
829 BWN_TX_RADIOTAP_PRESENT,
830 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
831 BWN_RX_RADIOTAP_PRESENT);
836 ieee80211_announce(ic);
841 bwn_phy_detach(struct bwn_mac *mac)
844 if (mac->mac_phy.detach != NULL)
845 mac->mac_phy.detach(mac);
849 bwn_detach(device_t dev)
851 struct bwn_softc *sc = device_get_softc(dev);
852 struct bwn_mac *mac = sc->sc_curmac;
853 struct ieee80211com *ic = &sc->sc_ic;
855 sc->sc_flags |= BWN_FLAG_INVALID;
857 if (device_is_attached(sc->sc_dev)) {
862 callout_drain(&sc->sc_led_blink_ch);
863 callout_drain(&sc->sc_rfswitch_ch);
864 callout_drain(&sc->sc_task_ch);
865 callout_drain(&sc->sc_watchdog_ch);
867 ieee80211_draintask(ic, &mac->mac_hwreset);
868 ieee80211_draintask(ic, &mac->mac_txpower);
869 ieee80211_ifdetach(ic);
871 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask);
872 taskqueue_free(sc->sc_tq);
874 if (mac->mac_intrhand != NULL) {
875 bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand);
876 mac->mac_intrhand = NULL;
879 bhnd_release_pmu(dev);
880 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
882 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq,
884 mbufq_drain(&sc->sc_snd);
885 bwn_release_firmware(mac);
886 BWN_LOCK_DESTROY(sc);
888 bwn_release_bus_providers(sc);
894 bwn_attach_pre(struct bwn_softc *sc)
898 TAILQ_INIT(&sc->sc_maclist);
899 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0);
900 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0);
901 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0);
902 mbufq_init(&sc->sc_snd, ifqmaxlen);
903 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT,
904 taskqueue_thread_enqueue, &sc->sc_tq);
905 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET,
906 "%s taskq", device_get_nameunit(sc->sc_dev));
910 bwn_sprom_bugfixes(device_t dev)
912 struct bwn_softc *sc = device_get_softc(dev);
914 #define BWN_ISDEV(_device, _subvendor, _subdevice) \
915 ((sc->sc_board_info.board_devid == PCI_DEVID_##_device) && \
916 (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) && \
917 (sc->sc_board_info.board_type == _subdevice))
919 /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices
920 * were programmed with a missing PACTRL boardflag */
921 if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE &&
922 sc->sc_board_info.board_type == 0x4e &&
923 sc->sc_board_info.board_rev > 0x40)
924 sc->sc_board_info.board_flags |= BHND_BFL_PACTRL;
926 if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) ||
927 BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) ||
928 BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) ||
929 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) ||
930 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) ||
931 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) ||
932 BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010))
933 sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX;
938 bwn_parent(struct ieee80211com *ic)
940 struct bwn_softc *sc = ic->ic_softc;
944 if (ic->ic_nrunning > 0) {
945 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
949 bwn_update_promisc(ic);
950 } else if (sc->sc_flags & BWN_FLAG_RUNNING)
955 ieee80211_start_all(ic);
959 bwn_transmit(struct ieee80211com *ic, struct mbuf *m)
961 struct bwn_softc *sc = ic->ic_softc;
965 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) {
969 error = mbufq_enqueue(&sc->sc_snd, m);
980 bwn_start(struct bwn_softc *sc)
982 struct bwn_mac *mac = sc->sc_curmac;
983 struct ieee80211_frame *wh;
984 struct ieee80211_node *ni;
985 struct ieee80211_key *k;
988 BWN_ASSERT_LOCKED(sc);
990 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL ||
991 mac->mac_status < BWN_MAC_STATUS_STARTED)
994 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) {
995 if (bwn_tx_isfull(sc, m))
997 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
999 device_printf(sc->sc_dev, "unexpected NULL ni\n");
1001 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1004 wh = mtod(m, struct ieee80211_frame *);
1005 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1006 k = ieee80211_crypto_encap(ni, m);
1008 if_inc_counter(ni->ni_vap->iv_ifp,
1009 IFCOUNTER_OERRORS, 1);
1010 ieee80211_free_node(ni);
1015 wh = NULL; /* Catch any invalid use */
1016 if (bwn_tx_start(sc, ni, m) != 0) {
1018 if_inc_counter(ni->ni_vap->iv_ifp,
1019 IFCOUNTER_OERRORS, 1);
1020 ieee80211_free_node(ni);
1024 sc->sc_watchdog_timer = 5;
1029 bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m)
1031 struct bwn_dma_ring *dr;
1032 struct bwn_mac *mac = sc->sc_curmac;
1033 struct bwn_pio_txqueue *tq;
1034 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1036 BWN_ASSERT_LOCKED(sc);
1038 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
1039 dr = bwn_dma_select(mac, M_WME_GETAC(m));
1040 if (dr->dr_stop == 1 ||
1041 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) {
1046 tq = bwn_pio_select(mac, M_WME_GETAC(m));
1047 if (tq->tq_free == 0 || pktlen > tq->tq_size ||
1048 pktlen > (tq->tq_size - tq->tq_used))
1053 mbufq_prepend(&sc->sc_snd, m);
1058 bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m)
1060 struct bwn_mac *mac = sc->sc_curmac;
1063 BWN_ASSERT_LOCKED(sc);
1065 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) {
1070 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ?
1071 bwn_dma_tx_start(mac, ni, &m) : bwn_pio_tx_start(mac, ni, &m);
1080 bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni,
1083 struct bwn_pio_txpkt *tp;
1084 struct bwn_pio_txqueue *tq;
1085 struct bwn_softc *sc = mac->mac_sc;
1086 struct bwn_txhdr txhdr;
1087 struct mbuf *m, *m_new;
1092 BWN_ASSERT_LOCKED(sc);
1094 /* XXX TODO send packets after DTIM */
1097 tq = bwn_pio_select(mac, M_WME_GETAC(m));
1098 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__));
1099 tp = TAILQ_FIRST(&tq->tq_pktlist);
1103 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp));
1105 device_printf(sc->sc_dev, "tx fail\n");
1109 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list);
1110 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
1113 if (bhnd_get_hwrev(sc->sc_dev) >= 8) {
1115 * XXX please removes m_defrag(9)
1117 m_new = m_defrag(*mp, M_NOWAIT);
1118 if (m_new == NULL) {
1119 device_printf(sc->sc_dev,
1120 "%s: can't defrag TX buffer\n",
1125 if (m_new->m_next != NULL)
1126 device_printf(sc->sc_dev,
1127 "TODO: fragmented packets for PIO\n");
1131 ctl32 = bwn_pio_write_multi_4(mac, tq,
1132 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) |
1133 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF,
1134 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1136 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32,
1137 mtod(m_new, const void *), m_new->m_pkthdr.len);
1138 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL,
1139 ctl32 | BWN_PIO8_TXCTL_EOF);
1141 ctl16 = bwn_pio_write_multi_2(mac, tq,
1142 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) |
1143 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF,
1144 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac));
1145 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m);
1146 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL,
1147 ctl16 | BWN_PIO_TXCTL_EOF);
1153 static struct bwn_pio_txqueue *
1154 bwn_pio_select(struct bwn_mac *mac, uint8_t prio)
1157 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
1158 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1162 return (&mac->mac_method.pio.wme[WME_AC_BE]);
1164 return (&mac->mac_method.pio.wme[WME_AC_BK]);
1166 return (&mac->mac_method.pio.wme[WME_AC_VI]);
1168 return (&mac->mac_method.pio.wme[WME_AC_VO]);
1170 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
1175 bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni,
1178 #define BWN_GET_TXHDRCACHE(slot) \
1179 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)])
1180 struct bwn_dma *dma = &mac->mac_method.dma;
1181 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(*mp));
1182 struct bwn_dmadesc_generic *desc;
1183 struct bwn_dmadesc_meta *mt;
1184 struct bwn_softc *sc = mac->mac_sc;
1186 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache;
1187 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot };
1189 BWN_ASSERT_LOCKED(sc);
1190 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__));
1192 /* XXX send after DTIM */
1195 slot = bwn_dma_getslot(dr);
1196 dr->getdesc(dr, slot, &desc, &mt);
1197 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER,
1198 ("%s:%d: fail", __func__, __LINE__));
1200 error = bwn_set_txhdr(dr->dr_mac, ni, m,
1201 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot),
1202 BWN_DMA_COOKIE(dr, slot));
1205 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap,
1206 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr,
1207 &mt->mt_paddr, BUS_DMA_NOWAIT);
1209 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1213 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap,
1214 BUS_DMASYNC_PREWRITE);
1215 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0);
1216 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1217 BUS_DMASYNC_PREWRITE);
1219 slot = bwn_dma_getslot(dr);
1220 dr->getdesc(dr, slot, &desc, &mt);
1221 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY &&
1222 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__));
1226 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m,
1227 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1228 if (error && error != EFBIG) {
1229 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n",
1233 if (error) { /* error == EFBIG */
1236 m_new = m_defrag(m, M_NOWAIT);
1237 if (m_new == NULL) {
1238 device_printf(sc->sc_dev,
1239 "%s: can't defrag TX buffer\n",
1247 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap,
1248 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT);
1250 device_printf(sc->sc_dev,
1251 "%s: can't load TX buffer (2) %d\n",
1256 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE);
1257 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1);
1258 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
1259 BUS_DMASYNC_PREWRITE);
1261 /* XXX send after DTIM */
1263 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot));
1266 dr->dr_curslot = backup[0];
1267 dr->dr_usedslot = backup[1];
1269 #undef BWN_GET_TXHDRCACHE
1273 bwn_watchdog(void *arg)
1275 struct bwn_softc *sc = arg;
1277 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) {
1278 device_printf(sc->sc_dev, "device timeout\n");
1279 counter_u64_add(sc->sc_ic.ic_oerrors, 1);
1281 callout_schedule(&sc->sc_watchdog_ch, hz);
1285 bwn_attach_core(struct bwn_mac *mac)
1287 struct bwn_softc *sc = mac->mac_sc;
1288 int error, have_bg = 0, have_a = 0;
1291 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5,
1292 ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev)));
1294 if ((error = bwn_core_forceclk(mac, true)))
1297 if ((error = bhnd_read_iost(sc->sc_dev, &iost))) {
1298 device_printf(sc->sc_dev, "error reading I/O status flags: "
1303 have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0;
1304 have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0;
1305 if (iost & BWN_IOST_DUALPHY) {
1312 device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d,"
1313 " deviceid=0x%04x, siba_deviceid=0x%04x\n",
1318 sc->sc_board_info.board_devid,
1319 sc->sc_cid.chip_id);
1323 * Guess at whether it has A-PHY or G-PHY.
1324 * This is just used for resetting the core to probe things;
1325 * we will re-guess once it's all up and working.
1327 error = bwn_reset_core(mac, have_bg);
1332 * Determine the DMA engine type
1334 if (iost & BHND_IOST_DMA64) {
1335 mac->mac_dmatype = BHND_DMA_ADDR_64BIT;
1340 base = bwn_dma_base(0, 0);
1341 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL,
1342 BWN_DMA32_TXADDREXT_MASK);
1343 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL);
1344 if (tmp & BWN_DMA32_TXADDREXT_MASK) {
1345 mac->mac_dmatype = BHND_DMA_ADDR_32BIT;
1347 mac->mac_dmatype = BHND_DMA_ADDR_30BIT;
1352 * Get the PHY version.
1354 error = bwn_phy_getinfo(mac, have_bg);
1359 * This is the whitelist of devices which we "believe"
1360 * the SPROM PHY config from. The rest are "guessed".
1362 if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL &&
1363 sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G &&
1364 sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL &&
1365 sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL &&
1366 sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N &&
1367 sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) {
1368 have_a = have_bg = 0;
1369 if (mac->mac_phy.type == BWN_PHYTYPE_A)
1371 else if (mac->mac_phy.type == BWN_PHYTYPE_G ||
1372 mac->mac_phy.type == BWN_PHYTYPE_N ||
1373 mac->mac_phy.type == BWN_PHYTYPE_LP)
1376 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__,
1377 mac->mac_phy.type));
1381 * XXX The PHY-G support doesn't do 5GHz operation.
1383 if (mac->mac_phy.type != BWN_PHYTYPE_LP &&
1384 mac->mac_phy.type != BWN_PHYTYPE_N) {
1385 device_printf(sc->sc_dev,
1386 "%s: forcing 2GHz only; no dual-band support for PHY\n",
1392 mac->mac_phy.phy_n = NULL;
1394 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
1395 mac->mac_phy.attach = bwn_phy_g_attach;
1396 mac->mac_phy.detach = bwn_phy_g_detach;
1397 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw;
1398 mac->mac_phy.init_pre = bwn_phy_g_init_pre;
1399 mac->mac_phy.init = bwn_phy_g_init;
1400 mac->mac_phy.exit = bwn_phy_g_exit;
1401 mac->mac_phy.phy_read = bwn_phy_g_read;
1402 mac->mac_phy.phy_write = bwn_phy_g_write;
1403 mac->mac_phy.rf_read = bwn_phy_g_rf_read;
1404 mac->mac_phy.rf_write = bwn_phy_g_rf_write;
1405 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl;
1406 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff;
1407 mac->mac_phy.switch_analog = bwn_phy_switch_analog;
1408 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel;
1409 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan;
1410 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna;
1411 mac->mac_phy.set_im = bwn_phy_g_im;
1412 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr;
1413 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr;
1414 mac->mac_phy.task_15s = bwn_phy_g_task_15s;
1415 mac->mac_phy.task_60s = bwn_phy_g_task_60s;
1416 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) {
1417 mac->mac_phy.init_pre = bwn_phy_lp_init_pre;
1418 mac->mac_phy.init = bwn_phy_lp_init;
1419 mac->mac_phy.phy_read = bwn_phy_lp_read;
1420 mac->mac_phy.phy_write = bwn_phy_lp_write;
1421 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset;
1422 mac->mac_phy.rf_read = bwn_phy_lp_rf_read;
1423 mac->mac_phy.rf_write = bwn_phy_lp_rf_write;
1424 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff;
1425 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog;
1426 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel;
1427 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan;
1428 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna;
1429 mac->mac_phy.task_60s = bwn_phy_lp_task_60s;
1430 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) {
1431 mac->mac_phy.attach = bwn_phy_n_attach;
1432 mac->mac_phy.detach = bwn_phy_n_detach;
1433 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw;
1434 mac->mac_phy.init_pre = bwn_phy_n_init_pre;
1435 mac->mac_phy.init = bwn_phy_n_init;
1436 mac->mac_phy.exit = bwn_phy_n_exit;
1437 mac->mac_phy.phy_read = bwn_phy_n_read;
1438 mac->mac_phy.phy_write = bwn_phy_n_write;
1439 mac->mac_phy.rf_read = bwn_phy_n_rf_read;
1440 mac->mac_phy.rf_write = bwn_phy_n_rf_write;
1441 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl;
1442 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff;
1443 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog;
1444 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel;
1445 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan;
1446 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna;
1447 mac->mac_phy.set_im = bwn_phy_n_im;
1448 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr;
1449 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr;
1450 mac->mac_phy.task_15s = bwn_phy_n_task_15s;
1451 mac->mac_phy.task_60s = bwn_phy_n_task_60s;
1453 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n",
1459 mac->mac_phy.gmode = have_bg;
1460 if (mac->mac_phy.attach != NULL) {
1461 error = mac->mac_phy.attach(mac);
1463 device_printf(sc->sc_dev, "failed\n");
1468 error = bwn_reset_core(mac, have_bg);
1472 error = bwn_chiptest(mac);
1475 error = bwn_setup_channels(mac, have_bg, have_a);
1477 device_printf(sc->sc_dev, "failed to setup channels\n");
1481 if (sc->sc_curmac == NULL)
1482 sc->sc_curmac = mac;
1484 error = bwn_dma_attach(mac);
1486 device_printf(sc->sc_dev, "failed to initialize DMA\n");
1490 mac->mac_phy.switch_analog(mac, 0);
1493 bhnd_suspend_hw(sc->sc_dev, 0);
1494 bwn_release_firmware(mac);
1502 bwn_reset_core(struct bwn_mac *mac, int g_mode)
1504 struct bwn_softc *sc;
1506 uint16_t ioctl, ioctl_mask;
1511 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode);
1514 ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET);
1516 ioctl |= BWN_IOCTL_SUPPORT_G;
1518 /* XXX N-PHY only; and hard-code to 20MHz for now */
1519 if (mac->mac_phy.type == BWN_PHYTYPE_N)
1520 ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ;
1522 if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) {
1523 device_printf(sc->sc_dev, "core reset failed: %d", error);
1529 /* Take PHY out of reset */
1530 ioctl = BHND_IOCTL_CLK_FORCE;
1531 ioctl_mask = BHND_IOCTL_CLK_FORCE |
1532 BWN_IOCTL_PHYRESET |
1533 BWN_IOCTL_PHYCLOCK_ENABLE;
1535 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
1536 device_printf(sc->sc_dev, "failed to set core ioctl flags: "
1543 ioctl = BWN_IOCTL_PHYCLOCK_ENABLE;
1544 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) {
1545 device_printf(sc->sc_dev, "failed to set core ioctl flags: "
1552 if (mac->mac_phy.switch_analog != NULL)
1553 mac->mac_phy.switch_analog(mac, 1);
1555 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE;
1557 ctl |= BWN_MACCTL_GMODE;
1558 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON);
1564 bwn_phy_getinfo(struct bwn_mac *mac, int gmode)
1566 struct bwn_phy *phy = &mac->mac_phy;
1567 struct bwn_softc *sc = mac->mac_sc;
1571 tmp = BWN_READ_2(mac, BWN_PHYVER);
1574 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12;
1575 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8;
1576 phy->rev = (tmp & BWN_PHYVER_VERSION);
1577 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) ||
1578 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 &&
1579 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) ||
1580 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) ||
1581 (phy->type == BWN_PHYTYPE_N && phy->rev > 6) ||
1582 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2))
1586 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1587 tmp = BWN_READ_2(mac, BWN_RFDATALO);
1588 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID);
1589 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16;
1591 phy->rf_rev = (tmp & 0xf0000000) >> 28;
1592 phy->rf_ver = (tmp & 0x0ffff000) >> 12;
1593 phy->rf_manuf = (tmp & 0x00000fff);
1596 * For now, just always do full init (ie, what bwn has traditionally
1599 phy->phy_do_full_init = 1;
1601 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */
1603 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 ||
1604 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) ||
1605 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) ||
1606 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) ||
1607 (phy->type == BWN_PHYTYPE_N &&
1608 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) ||
1609 (phy->type == BWN_PHYTYPE_LP &&
1610 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063))
1615 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, "
1617 phy->type, phy->rev, phy->analog);
1620 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, "
1622 phy->rf_manuf, phy->rf_ver, phy->rf_rev);
1627 bwn_chiptest(struct bwn_mac *mac)
1629 #define TESTVAL0 0x55aaaa55
1630 #define TESTVAL1 0xaa5555aa
1631 struct bwn_softc *sc = mac->mac_sc;
1636 backup = bwn_shm_read_4(mac, BWN_SHARED, 0);
1638 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0);
1639 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0)
1641 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1);
1642 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1)
1645 bwn_shm_write_4(mac, BWN_SHARED, 0, backup);
1647 if ((bhnd_get_hwrev(sc->sc_dev) >= 3) &&
1648 (bhnd_get_hwrev(sc->sc_dev) <= 10)) {
1649 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa);
1650 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb);
1651 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb)
1653 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc)
1656 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0);
1658 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE;
1659 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON))
1666 device_printf(sc->sc_dev, "failed to validate the chipaccess\n");
1671 bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a)
1673 struct bwn_softc *sc = mac->mac_sc;
1674 struct ieee80211com *ic = &sc->sc_ic;
1675 uint8_t bands[IEEE80211_MODE_BYTES];
1677 memset(ic->ic_channels, 0, sizeof(ic->ic_channels));
1680 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n",
1686 memset(bands, 0, sizeof(bands));
1687 setbit(bands, IEEE80211_MODE_11B);
1688 setbit(bands, IEEE80211_MODE_11G);
1689 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1690 &ic->ic_nchans, &bwn_chantable_bg, bands);
1694 memset(bands, 0, sizeof(bands));
1695 setbit(bands, IEEE80211_MODE_11A);
1696 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX,
1697 &ic->ic_nchans, &bwn_chantable_a, bands);
1700 mac->mac_phy.supports_2ghz = have_bg;
1701 mac->mac_phy.supports_5ghz = have_a;
1703 return (ic->ic_nchans == 0 ? ENXIO : 0);
1707 bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1711 BWN_ASSERT_LOCKED(mac->mac_sc);
1713 if (way == BWN_SHARED) {
1714 KASSERT((offset & 0x0001) == 0,
1715 ("%s:%d warn", __func__, __LINE__));
1716 if (offset & 0x0003) {
1717 bwn_shm_ctlword(mac, way, offset >> 2);
1718 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1720 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1721 ret |= BWN_READ_2(mac, BWN_SHM_DATA);
1726 bwn_shm_ctlword(mac, way, offset);
1727 ret = BWN_READ_4(mac, BWN_SHM_DATA);
1733 bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset)
1737 BWN_ASSERT_LOCKED(mac->mac_sc);
1739 if (way == BWN_SHARED) {
1740 KASSERT((offset & 0x0001) == 0,
1741 ("%s:%d warn", __func__, __LINE__));
1742 if (offset & 0x0003) {
1743 bwn_shm_ctlword(mac, way, offset >> 2);
1744 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED);
1749 bwn_shm_ctlword(mac, way, offset);
1750 ret = BWN_READ_2(mac, BWN_SHM_DATA);
1757 bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way,
1765 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control);
1769 bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1772 BWN_ASSERT_LOCKED(mac->mac_sc);
1774 if (way == BWN_SHARED) {
1775 KASSERT((offset & 0x0001) == 0,
1776 ("%s:%d warn", __func__, __LINE__));
1777 if (offset & 0x0003) {
1778 bwn_shm_ctlword(mac, way, offset >> 2);
1779 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED,
1780 (value >> 16) & 0xffff);
1781 bwn_shm_ctlword(mac, way, (offset >> 2) + 1);
1782 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff);
1787 bwn_shm_ctlword(mac, way, offset);
1788 BWN_WRITE_4(mac, BWN_SHM_DATA, value);
1792 bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset,
1795 BWN_ASSERT_LOCKED(mac->mac_sc);
1797 if (way == BWN_SHARED) {
1798 KASSERT((offset & 0x0001) == 0,
1799 ("%s:%d warn", __func__, __LINE__));
1800 if (offset & 0x0003) {
1801 bwn_shm_ctlword(mac, way, offset >> 2);
1802 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value);
1807 bwn_shm_ctlword(mac, way, offset);
1808 BWN_WRITE_2(mac, BWN_SHM_DATA, value);
1812 bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans,
1813 const struct bwn_channelinfo *ci, const uint8_t bands[])
1817 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) {
1818 const struct bwn_channel *hc = &ci->channels[i];
1820 error = ieee80211_add_channel(chans, maxchans, nchans,
1821 hc->ieee, hc->freq, hc->maxTxPow, 0, bands);
1826 bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1827 const struct ieee80211_bpf_params *params)
1829 struct ieee80211com *ic = ni->ni_ic;
1830 struct bwn_softc *sc = ic->ic_softc;
1831 struct bwn_mac *mac = sc->sc_curmac;
1834 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 ||
1835 mac->mac_status < BWN_MAC_STATUS_STARTED) {
1841 if (bwn_tx_isfull(sc, m)) {
1847 error = bwn_tx_start(sc, ni, m);
1849 sc->sc_watchdog_timer = 5;
1855 * Callback from the 802.11 layer to update the slot time
1856 * based on the current setting. We use it to notify the
1857 * firmware of ERP changes and the f/w takes care of things
1858 * like slot time and preamble.
1861 bwn_updateslot(struct ieee80211com *ic)
1863 struct bwn_softc *sc = ic->ic_softc;
1864 struct bwn_mac *mac;
1867 if (sc->sc_flags & BWN_FLAG_RUNNING) {
1868 mac = (struct bwn_mac *)sc->sc_curmac;
1869 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic));
1875 * Callback from the 802.11 layer after a promiscuous mode change.
1876 * Note this interface does not check the operating mode as this
1877 * is an internal callback and we are expected to honor the current
1878 * state (e.g. this is used for setting the interface in promiscuous
1879 * mode when operating in hostap mode to do ACS).
1882 bwn_update_promisc(struct ieee80211com *ic)
1884 struct bwn_softc *sc = ic->ic_softc;
1885 struct bwn_mac *mac = sc->sc_curmac;
1888 mac = sc->sc_curmac;
1889 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1890 if (ic->ic_promisc > 0)
1891 sc->sc_filters |= BWN_MACCTL_PROMISC;
1893 sc->sc_filters &= ~BWN_MACCTL_PROMISC;
1894 bwn_set_opmode(mac);
1900 * Callback from the 802.11 layer to update WME parameters.
1903 bwn_wme_update(struct ieee80211com *ic)
1905 struct bwn_softc *sc = ic->ic_softc;
1906 struct bwn_mac *mac = sc->sc_curmac;
1907 struct chanAccParams chp;
1908 struct wmeParams *wmep;
1911 ieee80211_wme_ic_getparams(ic, &chp);
1914 mac = sc->sc_curmac;
1915 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1916 bwn_mac_suspend(mac);
1917 for (i = 0; i < N(sc->sc_wmeParams); i++) {
1918 wmep = &chp.cap_wmeParams[i];
1919 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]);
1921 bwn_mac_enable(mac);
1928 bwn_scan_start(struct ieee80211com *ic)
1930 struct bwn_softc *sc = ic->ic_softc;
1931 struct bwn_mac *mac;
1934 mac = sc->sc_curmac;
1935 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1936 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC;
1937 bwn_set_opmode(mac);
1938 /* disable CFP update during scan */
1939 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE);
1945 bwn_scan_end(struct ieee80211com *ic)
1947 struct bwn_softc *sc = ic->ic_softc;
1948 struct bwn_mac *mac;
1951 mac = sc->sc_curmac;
1952 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) {
1953 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC;
1954 bwn_set_opmode(mac);
1955 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE);
1961 bwn_set_channel(struct ieee80211com *ic)
1963 struct bwn_softc *sc = ic->ic_softc;
1964 struct bwn_mac *mac = sc->sc_curmac;
1965 struct bwn_phy *phy = &mac->mac_phy;
1970 error = bwn_switch_band(sc, ic->ic_curchan);
1973 bwn_mac_suspend(mac);
1974 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
1975 chan = ieee80211_chan2ieee(ic, ic->ic_curchan);
1976 if (chan != phy->chan)
1977 bwn_switch_channel(mac, chan);
1979 /* TX power level */
1980 if (ic->ic_curchan->ic_maxpower != 0 &&
1981 ic->ic_curchan->ic_maxpower != phy->txpower) {
1982 phy->txpower = ic->ic_curchan->ic_maxpower / 2;
1983 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME |
1984 BWN_TXPWR_IGNORE_TSSI);
1987 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
1988 if (phy->set_antenna)
1989 phy->set_antenna(mac, BWN_ANT_DEFAULT);
1991 if (sc->sc_rf_enabled != phy->rf_on) {
1992 if (sc->sc_rf_enabled) {
1994 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON))
1995 device_printf(sc->sc_dev,
1996 "please turn on the RF switch\n");
1998 bwn_rf_turnoff(mac);
2001 bwn_mac_enable(mac);
2007 static struct ieee80211vap *
2008 bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
2009 enum ieee80211_opmode opmode, int flags,
2010 const uint8_t bssid[IEEE80211_ADDR_LEN],
2011 const uint8_t mac[IEEE80211_ADDR_LEN])
2013 struct ieee80211vap *vap;
2014 struct bwn_vap *bvp;
2017 case IEEE80211_M_HOSTAP:
2018 case IEEE80211_M_MBSS:
2019 case IEEE80211_M_STA:
2020 case IEEE80211_M_WDS:
2021 case IEEE80211_M_MONITOR:
2022 case IEEE80211_M_IBSS:
2023 case IEEE80211_M_AHDEMO:
2029 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO);
2031 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid);
2032 /* override with driver methods */
2033 bvp->bv_newstate = vap->iv_newstate;
2034 vap->iv_newstate = bwn_newstate;
2036 /* override max aid so sta's cannot assoc when we're out of sta id's */
2037 vap->iv_max_aid = BWN_STAID_MAX;
2039 ieee80211_ratectl_init(vap);
2041 /* complete setup */
2042 ieee80211_vap_attach(vap, ieee80211_media_change,
2043 ieee80211_media_status, mac);
2048 bwn_vap_delete(struct ieee80211vap *vap)
2050 struct bwn_vap *bvp = BWN_VAP(vap);
2052 ieee80211_ratectl_deinit(vap);
2053 ieee80211_vap_detach(vap);
2054 free(bvp, M_80211_VAP);
2058 bwn_init(struct bwn_softc *sc)
2060 struct bwn_mac *mac;
2063 BWN_ASSERT_LOCKED(sc);
2065 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2067 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN);
2068 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP;
2071 sc->sc_beacons[0] = sc->sc_beacons[1] = 0;
2072 sc->sc_rf_enabled = 1;
2074 mac = sc->sc_curmac;
2075 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) {
2076 error = bwn_core_init(mac);
2080 if (mac->mac_status == BWN_MAC_STATUS_INITED)
2081 bwn_core_start(mac);
2083 bwn_set_opmode(mac);
2084 bwn_set_pretbtt(mac);
2085 bwn_spu_setdelay(mac, 0);
2086 bwn_set_macaddr(mac);
2088 sc->sc_flags |= BWN_FLAG_RUNNING;
2089 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc);
2090 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc);
2096 bwn_stop(struct bwn_softc *sc)
2098 struct bwn_mac *mac = sc->sc_curmac;
2100 BWN_ASSERT_LOCKED(sc);
2102 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2104 if (mac->mac_status >= BWN_MAC_STATUS_INITED) {
2105 /* XXX FIXME opmode not based on VAP */
2106 bwn_set_opmode(mac);
2107 bwn_set_macaddr(mac);
2110 if (mac->mac_status >= BWN_MAC_STATUS_STARTED)
2113 callout_stop(&sc->sc_led_blink_ch);
2114 sc->sc_led_blinking = 0;
2117 sc->sc_rf_enabled = 0;
2119 sc->sc_flags &= ~BWN_FLAG_RUNNING;
2123 bwn_wme_clear(struct bwn_softc *sc)
2125 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
2126 struct wmeParams *p;
2129 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
2130 ("%s:%d: fail", __func__, __LINE__));
2132 for (i = 0; i < N(sc->sc_wmeParams); i++) {
2133 p = &(sc->sc_wmeParams[i]);
2135 switch (bwn_wme_shm_offsets[i]) {
2137 p->wmep_txopLimit = 0;
2139 /* XXX FIXME: log2(cwmin) */
2140 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2141 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
2144 p->wmep_txopLimit = 0;
2146 /* XXX FIXME: log2(cwmin) */
2147 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2148 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX);
2150 case BWN_WME_BESTEFFORT:
2151 p->wmep_txopLimit = 0;
2153 /* XXX FIXME: log2(cwmin) */
2154 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2155 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
2157 case BWN_WME_BACKGROUND:
2158 p->wmep_txopLimit = 0;
2160 /* XXX FIXME: log2(cwmin) */
2161 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN);
2162 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX);
2165 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2171 bwn_core_forceclk(struct bwn_mac *mac, bool force)
2173 struct bwn_softc *sc;
2179 /* On PMU equipped devices, we do not need to force the HT clock */
2180 if (sc->sc_pmu != NULL)
2183 /* Issue a PMU clock request */
2185 clock = BHND_CLOCK_HT;
2187 clock = BHND_CLOCK_DYN;
2189 if ((error = bhnd_request_clock(sc->sc_dev, clock))) {
2190 device_printf(sc->sc_dev, "%d clock request failed: %d\n",
2199 bwn_core_init(struct bwn_mac *mac)
2201 struct bwn_softc *sc = mac->mac_sc;
2205 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2206 ("%s:%d: fail", __func__, __LINE__));
2208 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
2210 if ((error = bwn_core_forceclk(mac, true)))
2213 if (bhnd_is_hw_suspended(sc->sc_dev)) {
2214 if ((error = bwn_reset_core(mac, mac->mac_phy.gmode)))
2218 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
2219 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
2220 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0;
2221 BWN_GETTIME(mac->mac_phy.nexttime);
2222 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
2223 bzero(&mac->mac_stats, sizeof(mac->mac_stats));
2224 mac->mac_stats.link_noise = -95;
2225 mac->mac_reason_intr = 0;
2226 bzero(mac->mac_reason, sizeof(mac->mac_reason));
2227 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE;
2229 if (sc->sc_debug & BWN_DEBUG_XMIT)
2230 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR;
2232 mac->mac_suspended = 1;
2233 mac->mac_task_state = 0;
2234 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise));
2236 mac->mac_phy.init_pre(mac);
2238 bwn_bt_disable(mac);
2239 if (mac->mac_phy.prepare_hw) {
2240 error = mac->mac_phy.prepare_hw(mac);
2244 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__);
2245 error = bwn_chip_init(mac);
2248 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV,
2249 bhnd_get_hwrev(sc->sc_dev));
2250 hf = bwn_hf_read(mac);
2251 if (mac->mac_phy.type == BWN_PHYTYPE_G) {
2252 hf |= BWN_HF_GPHY_SYM_WORKAROUND;
2253 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL)
2254 hf |= BWN_HF_PAGAINBOOST_OFDM_ON;
2255 if (mac->mac_phy.rev == 1)
2256 hf |= BWN_HF_GPHY_DC_CANCELFILTER;
2258 if (mac->mac_phy.rf_ver == 0x2050) {
2259 if (mac->mac_phy.rf_rev < 6)
2260 hf |= BWN_HF_FORCE_VCO_RECALC;
2261 if (mac->mac_phy.rf_rev == 6)
2262 hf |= BWN_HF_4318_TSSI;
2264 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
2265 hf |= BWN_HF_SLOWCLOCK_REQ_OFF;
2266 if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR)
2267 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND;
2268 hf &= ~BWN_HF_SKIP_CFP_UPDATE;
2269 bwn_hf_write(mac, hf);
2271 /* Tell the firmware about the MAC capabilities */
2272 if (bhnd_get_hwrev(sc->sc_dev) >= 13) {
2274 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP);
2275 DPRINTF(sc, BWN_DEBUG_RESET,
2276 "%s: hw capabilities: 0x%08x\n",
2278 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L,
2280 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H,
2281 (cap >> 16) & 0xffff);
2284 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG);
2285 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3);
2286 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2);
2287 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1);
2290 bwn_set_phytxctl(mac);
2292 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN,
2293 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf);
2294 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff);
2296 if (sc->sc_quirks & BWN_QUIRK_NODMA)
2301 bwn_spu_setdelay(mac, 1);
2304 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__);
2305 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN)
2306 bwn_core_forceclk(mac, true);
2308 bwn_core_forceclk(mac, false);
2310 bwn_set_macaddr(mac);
2311 bwn_crypt_init(mac);
2313 /* XXX LED initializatin */
2315 mac->mac_status = BWN_MAC_STATUS_INITED;
2317 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__);
2321 bhnd_suspend_hw(sc->sc_dev, 0);
2322 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT,
2323 ("%s:%d: fail", __func__, __LINE__));
2324 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__);
2329 bwn_core_start(struct bwn_mac *mac)
2331 struct bwn_softc *sc = mac->mac_sc;
2334 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED,
2335 ("%s:%d: fail", __func__, __LINE__));
2337 if (bhnd_get_hwrev(sc->sc_dev) < 5)
2341 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0);
2342 if (!(tmp & 0x00000001))
2344 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1);
2347 bwn_mac_enable(mac);
2348 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
2349 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
2351 mac->mac_status = BWN_MAC_STATUS_STARTED;
2355 bwn_core_exit(struct bwn_mac *mac)
2357 struct bwn_softc *sc = mac->mac_sc;
2360 BWN_ASSERT_LOCKED(mac->mac_sc);
2362 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED,
2363 ("%s:%d: fail", __func__, __LINE__));
2365 if (mac->mac_status != BWN_MAC_STATUS_INITED)
2367 mac->mac_status = BWN_MAC_STATUS_UNINIT;
2369 macctl = BWN_READ_4(mac, BWN_MACCTL);
2370 macctl &= ~BWN_MACCTL_MCODE_RUN;
2371 macctl |= BWN_MACCTL_MCODE_JMP0;
2372 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2377 mac->mac_phy.switch_analog(mac, 0);
2378 bhnd_suspend_hw(sc->sc_dev, 0);
2382 bwn_bt_disable(struct bwn_mac *mac)
2384 struct bwn_softc *sc = mac->mac_sc;
2387 /* XXX do nothing yet */
2391 bwn_chip_init(struct bwn_mac *mac)
2393 struct bwn_softc *sc = mac->mac_sc;
2394 struct bwn_phy *phy = &mac->mac_phy;
2399 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA;
2401 macctl |= BWN_MACCTL_GMODE;
2402 BWN_WRITE_4(mac, BWN_MACCTL, macctl);
2404 error = bwn_fw_fillinfo(mac);
2407 error = bwn_fw_loaducode(mac);
2411 error = bwn_gpio_init(mac);
2415 error = bwn_fw_loadinitvals(mac);
2419 phy->switch_analog(mac, 1);
2420 error = bwn_phy_init(mac);
2425 phy->set_im(mac, BWN_IMMODE_NONE);
2426 if (phy->set_antenna)
2427 phy->set_antenna(mac, BWN_ANT_DEFAULT);
2428 bwn_set_txantenna(mac, BWN_ANT_DEFAULT);
2430 if (phy->type == BWN_PHYTYPE_B)
2431 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004);
2432 BWN_WRITE_4(mac, 0x0100, 0x01000000);
2433 if (bhnd_get_hwrev(sc->sc_dev) < 5)
2434 BWN_WRITE_4(mac, 0x010c, 0x01000000);
2436 BWN_WRITE_4(mac, BWN_MACCTL,
2437 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA);
2438 BWN_WRITE_4(mac, BWN_MACCTL,
2439 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA);
2440 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000);
2442 bwn_set_opmode(mac);
2443 if (bhnd_get_hwrev(sc->sc_dev) < 3) {
2444 BWN_WRITE_2(mac, 0x060e, 0x0000);
2445 BWN_WRITE_2(mac, 0x0610, 0x8000);
2446 BWN_WRITE_2(mac, 0x0604, 0x0000);
2447 BWN_WRITE_2(mac, 0x0606, 0x0200);
2449 BWN_WRITE_4(mac, 0x0188, 0x80000000);
2450 BWN_WRITE_4(mac, 0x018c, 0x02000000);
2452 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000);
2453 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00);
2454 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00);
2455 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00);
2456 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00);
2457 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00);
2458 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00);
2460 bwn_mac_phy_clock_set(mac, true);
2462 /* Provide the HT clock transition latency to the MAC core */
2463 error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay);
2465 device_printf(sc->sc_dev, "failed to fetch HT clock latency: "
2470 if (delay > UINT16_MAX) {
2471 device_printf(sc->sc_dev, "invalid HT clock latency: %u\n",
2476 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay);
2480 /* read hostflags */
2482 bwn_hf_read(struct bwn_mac *mac)
2486 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI);
2488 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI);
2490 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO);
2495 bwn_hf_write(struct bwn_mac *mac, uint64_t value)
2498 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO,
2499 (value & 0x00000000ffffull));
2500 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI,
2501 (value & 0x0000ffff0000ull) >> 16);
2502 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI,
2503 (value & 0xffff00000000ULL) >> 32);
2507 bwn_set_txretry(struct bwn_mac *mac, int s, int l)
2510 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf));
2511 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf));
2515 bwn_rate_init(struct bwn_mac *mac)
2518 switch (mac->mac_phy.type) {
2521 case BWN_PHYTYPE_LP:
2523 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1);
2524 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1);
2525 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1);
2526 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1);
2527 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1);
2528 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1);
2529 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1);
2530 if (mac->mac_phy.type == BWN_PHYTYPE_A)
2534 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0);
2535 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0);
2536 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0);
2537 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0);
2540 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2545 bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm)
2551 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2;
2554 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2;
2556 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20,
2557 bwn_shm_read_2(mac, BWN_SHARED, offset));
2561 bwn_plcp_getcck(const uint8_t bitrate)
2565 case BWN_CCK_RATE_1MB:
2567 case BWN_CCK_RATE_2MB:
2569 case BWN_CCK_RATE_5MB:
2571 case BWN_CCK_RATE_11MB:
2574 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2579 bwn_plcp_getofdm(const uint8_t bitrate)
2583 case BWN_OFDM_RATE_6MB:
2585 case BWN_OFDM_RATE_9MB:
2587 case BWN_OFDM_RATE_12MB:
2589 case BWN_OFDM_RATE_18MB:
2591 case BWN_OFDM_RATE_24MB:
2593 case BWN_OFDM_RATE_36MB:
2595 case BWN_OFDM_RATE_48MB:
2597 case BWN_OFDM_RATE_54MB:
2600 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2605 bwn_set_phytxctl(struct bwn_mac *mac)
2609 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO |
2611 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl);
2612 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl);
2613 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl);
2617 bwn_pio_init(struct bwn_mac *mac)
2619 struct bwn_pio *pio = &mac->mac_method.pio;
2621 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL)
2622 & ~BWN_MACCTL_BIGENDIAN);
2623 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0);
2625 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0);
2626 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1);
2627 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2);
2628 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3);
2629 bwn_pio_set_txqueue(mac, &pio->mcast, 4);
2630 bwn_pio_setupqueue_rx(mac, &pio->rx, 0);
2634 bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2637 struct bwn_pio_txpkt *tp;
2638 struct bwn_softc *sc = mac->mac_sc;
2641 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac);
2642 tq->tq_index = index;
2644 tq->tq_free = BWN_PIO_MAX_TXPACKETS;
2645 if (bhnd_get_hwrev(sc->sc_dev) >= 8)
2648 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE);
2652 TAILQ_INIT(&tq->tq_pktlist);
2653 for (i = 0; i < N(tq->tq_pkts); i++) {
2654 tp = &(tq->tq_pkts[i]);
2657 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
2662 bwn_pio_idx2base(struct bwn_mac *mac, int index)
2664 struct bwn_softc *sc = mac->mac_sc;
2665 static const uint16_t bases[] = {
2675 static const uint16_t bases_rev11[] = {
2684 if (bhnd_get_hwrev(sc->sc_dev) >= 11) {
2685 if (index >= N(bases_rev11))
2686 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2687 return (bases_rev11[index]);
2689 if (index >= N(bases))
2690 device_printf(sc->sc_dev, "%s: warning\n", __func__);
2691 return (bases[index]);
2695 bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq,
2698 struct bwn_softc *sc = mac->mac_sc;
2701 prq->prq_rev = bhnd_get_hwrev(sc->sc_dev);
2702 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac);
2703 bwn_dma_rxdirectfifo(mac, index, 1);
2707 bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq)
2711 bwn_pio_cancel_tx_packets(tq);
2715 bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio)
2718 bwn_destroy_pioqueue_tx(pio);
2722 bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
2726 return (BWN_READ_2(mac, tq->tq_base + offset));
2730 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable)
2735 base = bwn_dma_base(mac->mac_dmatype, idx);
2736 if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) {
2737 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL);
2738 ctl &= ~BWN_DMA64_RXDIRECTFIFO;
2740 ctl |= BWN_DMA64_RXDIRECTFIFO;
2741 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl);
2743 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL);
2744 ctl &= ~BWN_DMA32_RXDIRECTFIFO;
2746 ctl |= BWN_DMA32_RXDIRECTFIFO;
2747 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl);
2752 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq)
2754 struct bwn_pio_txpkt *tp;
2757 for (i = 0; i < N(tq->tq_pkts); i++) {
2758 tp = &(tq->tq_pkts[i]);
2767 bwn_dma_base(int type, int controller_idx)
2769 static const uint16_t map64[] = {
2777 static const uint16_t map32[] = {
2786 if (type == BHND_DMA_ADDR_64BIT) {
2787 KASSERT(controller_idx >= 0 && controller_idx < N(map64),
2788 ("%s:%d: fail", __func__, __LINE__));
2789 return (map64[controller_idx]);
2791 KASSERT(controller_idx >= 0 && controller_idx < N(map32),
2792 ("%s:%d: fail", __func__, __LINE__));
2793 return (map32[controller_idx]);
2797 bwn_dma_init(struct bwn_mac *mac)
2799 struct bwn_dma *dma = &mac->mac_method.dma;
2801 /* setup TX DMA channels. */
2802 bwn_dma_setup(dma->wme[WME_AC_BK]);
2803 bwn_dma_setup(dma->wme[WME_AC_BE]);
2804 bwn_dma_setup(dma->wme[WME_AC_VI]);
2805 bwn_dma_setup(dma->wme[WME_AC_VO]);
2806 bwn_dma_setup(dma->mcast);
2807 /* setup RX DMA channel. */
2808 bwn_dma_setup(dma->rx);
2811 static struct bwn_dma_ring *
2812 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index,
2815 struct bwn_dma *dma = &mac->mac_method.dma;
2816 struct bwn_dma_ring *dr;
2817 struct bwn_dmadesc_generic *desc;
2818 struct bwn_dmadesc_meta *mt;
2819 struct bwn_softc *sc = mac->mac_sc;
2822 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO);
2825 dr->dr_numslots = BWN_RXRING_SLOTS;
2827 dr->dr_numslots = BWN_TXRING_SLOTS;
2829 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta),
2830 M_DEVBUF, M_NOWAIT | M_ZERO);
2831 if (dr->dr_meta == NULL)
2834 dr->dr_type = mac->mac_dmatype;
2836 dr->dr_base = bwn_dma_base(dr->dr_type, controller_index);
2837 dr->dr_index = controller_index;
2838 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
2839 dr->getdesc = bwn_dma_64_getdesc;
2840 dr->setdesc = bwn_dma_64_setdesc;
2841 dr->start_transfer = bwn_dma_64_start_transfer;
2842 dr->suspend = bwn_dma_64_suspend;
2843 dr->resume = bwn_dma_64_resume;
2844 dr->get_curslot = bwn_dma_64_get_curslot;
2845 dr->set_curslot = bwn_dma_64_set_curslot;
2847 dr->getdesc = bwn_dma_32_getdesc;
2848 dr->setdesc = bwn_dma_32_setdesc;
2849 dr->start_transfer = bwn_dma_32_start_transfer;
2850 dr->suspend = bwn_dma_32_suspend;
2851 dr->resume = bwn_dma_32_resume;
2852 dr->get_curslot = bwn_dma_32_get_curslot;
2853 dr->set_curslot = bwn_dma_32_set_curslot;
2857 dr->dr_curslot = -1;
2859 if (dr->dr_index == 0) {
2860 switch (mac->mac_fw.fw_hdr_format) {
2861 case BWN_FW_HDR_351:
2862 case BWN_FW_HDR_410:
2864 BWN_DMA0_RX_BUFFERSIZE_FW351;
2865 dr->dr_frameoffset =
2866 BWN_DMA0_RX_FRAMEOFFSET_FW351;
2868 case BWN_FW_HDR_598:
2870 BWN_DMA0_RX_BUFFERSIZE_FW598;
2871 dr->dr_frameoffset =
2872 BWN_DMA0_RX_FRAMEOFFSET_FW598;
2876 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
2879 error = bwn_dma_allocringmemory(dr);
2885 * Assumption: BWN_TXRING_SLOTS can be divided by
2886 * BWN_TX_SLOTS_PER_FRAME
2888 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0,
2889 ("%s:%d: fail", __func__, __LINE__));
2891 dr->dr_txhdr_cache = contigmalloc(
2892 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2893 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO,
2894 0, BUS_SPACE_MAXADDR, 8, 0);
2895 if (dr->dr_txhdr_cache == NULL) {
2896 device_printf(sc->sc_dev,
2897 "can't allocate TX header DMA memory\n");
2902 * Create TX ring DMA stuffs
2904 error = bus_dma_tag_create(dma->parent_dtag,
2911 BUS_SPACE_MAXSIZE_32BIT,
2914 &dr->dr_txring_dtag);
2916 device_printf(sc->sc_dev,
2917 "can't create TX ring DMA tag: TODO frees\n");
2921 for (i = 0; i < dr->dr_numslots; i += 2) {
2922 dr->getdesc(dr, i, &desc, &mt);
2924 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER;
2928 error = bus_dmamap_create(dr->dr_txring_dtag, 0,
2931 device_printf(sc->sc_dev,
2932 "can't create RX buf DMA map\n");
2936 dr->getdesc(dr, i + 1, &desc, &mt);
2938 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY;
2942 error = bus_dmamap_create(dma->txbuf_dtag, 0,
2945 device_printf(sc->sc_dev,
2946 "can't create RX buf DMA map\n");
2951 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2952 &dr->dr_spare_dmap);
2954 device_printf(sc->sc_dev,
2955 "can't create RX buf DMA map\n");
2956 goto out; /* XXX wrong! */
2959 for (i = 0; i < dr->dr_numslots; i++) {
2960 dr->getdesc(dr, i, &desc, &mt);
2962 error = bus_dmamap_create(dma->rxbuf_dtag, 0,
2965 device_printf(sc->sc_dev,
2966 "can't create RX buf DMA map\n");
2967 goto out; /* XXX wrong! */
2969 error = bwn_dma_newbuf(dr, desc, mt, 1);
2971 device_printf(sc->sc_dev,
2972 "failed to allocate RX buf\n");
2973 goto out; /* XXX wrong! */
2977 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
2978 BUS_DMASYNC_PREWRITE);
2980 dr->dr_usedslot = dr->dr_numslots;
2987 if (dr->dr_txhdr_cache != NULL) {
2988 contigfree(dr->dr_txhdr_cache,
2989 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
2990 BWN_MAXTXHDRSIZE, M_DEVBUF);
2993 free(dr->dr_meta, M_DEVBUF);
3000 bwn_dma_ringfree(struct bwn_dma_ring **dr)
3006 bwn_dma_free_descbufs(*dr);
3007 bwn_dma_free_ringmemory(*dr);
3009 if ((*dr)->dr_txhdr_cache != NULL) {
3010 contigfree((*dr)->dr_txhdr_cache,
3011 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) *
3012 BWN_MAXTXHDRSIZE, M_DEVBUF);
3014 free((*dr)->dr_meta, M_DEVBUF);
3015 free(*dr, M_DEVBUF);
3021 bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot,
3022 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
3024 struct bwn_dmadesc32 *desc;
3026 *meta = &(dr->dr_meta[slot]);
3027 desc = dr->dr_ring_descbase;
3028 desc = &(desc[slot]);
3030 *gdesc = (struct bwn_dmadesc_generic *)desc;
3034 bwn_dma_32_setdesc(struct bwn_dma_ring *dr,
3035 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
3036 int start, int end, int irq)
3038 struct bwn_dmadesc32 *descbase;
3039 struct bwn_dma *dma;
3040 struct bhnd_dma_translation *dt;
3041 uint32_t addr, addrext, ctl;
3044 descbase = dr->dr_ring_descbase;
3045 dma = &dr->dr_mac->mac_method.dma;
3046 dt = &dma->translation;
3048 slot = (int)(&(desc->dma.dma32) - descbase);
3049 KASSERT(slot >= 0 && slot < dr->dr_numslots,
3050 ("%s:%d: fail", __func__, __LINE__));
3052 addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
3053 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
3054 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT;
3055 if (slot == dr->dr_numslots - 1)
3056 ctl |= BWN_DMA32_DCTL_DTABLEEND;
3058 ctl |= BWN_DMA32_DCTL_FRAMESTART;
3060 ctl |= BWN_DMA32_DCTL_FRAMEEND;
3062 ctl |= BWN_DMA32_DCTL_IRQ;
3063 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT)
3064 & BWN_DMA32_DCTL_ADDREXT_MASK;
3066 desc->dma.dma32.control = htole32(ctl);
3067 desc->dma.dma32.address = htole32(addr);
3071 bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot)
3074 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX,
3075 (uint32_t)(slot * sizeof(struct bwn_dmadesc32)));
3079 bwn_dma_32_suspend(struct bwn_dma_ring *dr)
3082 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
3083 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND);
3087 bwn_dma_32_resume(struct bwn_dma_ring *dr)
3090 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL,
3091 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND);
3095 bwn_dma_32_get_curslot(struct bwn_dma_ring *dr)
3099 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS);
3100 val &= BWN_DMA32_RXDPTR;
3102 return (val / sizeof(struct bwn_dmadesc32));
3106 bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot)
3109 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX,
3110 (uint32_t) (slot * sizeof(struct bwn_dmadesc32)));
3114 bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot,
3115 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta)
3117 struct bwn_dmadesc64 *desc;
3119 *meta = &(dr->dr_meta[slot]);
3120 desc = dr->dr_ring_descbase;
3121 desc = &(desc[slot]);
3123 *gdesc = (struct bwn_dmadesc_generic *)desc;
3127 bwn_dma_64_setdesc(struct bwn_dma_ring *dr,
3128 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize,
3129 int start, int end, int irq)
3131 struct bwn_dmadesc64 *descbase;
3132 struct bwn_dma *dma;
3133 struct bhnd_dma_translation *dt;
3135 uint32_t addrhi, addrlo;
3137 uint32_t ctl0, ctl1;
3141 descbase = dr->dr_ring_descbase;
3142 dma = &dr->dr_mac->mac_method.dma;
3143 dt = &dma->translation;
3145 slot = (int)(&(desc->dma.dma64) - descbase);
3146 KASSERT(slot >= 0 && slot < dr->dr_numslots,
3147 ("%s:%d: fail", __func__, __LINE__));
3149 addr = (dmaaddr & dt->addr_mask) | dt->base_addr;
3150 addrhi = (addr >> 32);
3151 addrlo = (addr & UINT32_MAX);
3152 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift);
3155 if (slot == dr->dr_numslots - 1)
3156 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND;
3158 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART;
3160 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND;
3162 ctl0 |= BWN_DMA64_DCTL0_IRQ;
3165 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT;
3166 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT)
3167 & BWN_DMA64_DCTL1_ADDREXT_MASK;
3169 desc->dma.dma64.control0 = htole32(ctl0);
3170 desc->dma.dma64.control1 = htole32(ctl1);
3171 desc->dma.dma64.address_low = htole32(addrlo);
3172 desc->dma.dma64.address_high = htole32(addrhi);
3176 bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot)
3179 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX,
3180 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3184 bwn_dma_64_suspend(struct bwn_dma_ring *dr)
3187 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3188 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND);
3192 bwn_dma_64_resume(struct bwn_dma_ring *dr)
3195 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL,
3196 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND);
3200 bwn_dma_64_get_curslot(struct bwn_dma_ring *dr)
3204 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS);
3205 val &= BWN_DMA64_RXSTATDPTR;
3207 return (val / sizeof(struct bwn_dmadesc64));
3211 bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot)
3214 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX,
3215 (uint32_t)(slot * sizeof(struct bwn_dmadesc64)));
3219 bwn_dma_allocringmemory(struct bwn_dma_ring *dr)
3221 struct bwn_mac *mac = dr->dr_mac;
3222 struct bwn_dma *dma = &mac->mac_method.dma;
3223 struct bwn_softc *sc = mac->mac_sc;
3226 error = bus_dma_tag_create(dma->parent_dtag,
3231 BWN_DMA_RINGMEMSIZE,
3233 BUS_SPACE_MAXSIZE_32BIT,
3238 device_printf(sc->sc_dev,
3239 "can't create TX ring DMA tag: TODO frees\n");
3243 error = bus_dmamem_alloc(dr->dr_ring_dtag,
3244 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO,
3247 device_printf(sc->sc_dev,
3248 "can't allocate DMA mem: TODO frees\n");
3251 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap,
3252 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE,
3253 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT);
3255 device_printf(sc->sc_dev,
3256 "can't load DMA mem: TODO free\n");
3264 bwn_dma_setup(struct bwn_dma_ring *dr)
3266 struct bwn_mac *mac;
3267 struct bwn_dma *dma;
3268 struct bhnd_dma_translation *dt;
3269 bhnd_addr_t addr, paddr;
3270 uint32_t addrhi, addrlo, addrext, value;
3273 dma = &mac->mac_method.dma;
3274 dt = &dma->translation;
3276 paddr = dr->dr_ring_dmabase;
3277 addr = (paddr & dt->addr_mask) | dt->base_addr;
3278 addrhi = (addr >> 32);
3279 addrlo = (addr & UINT32_MAX);
3280 addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift);
3283 dr->dr_curslot = -1;
3285 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3286 value = BWN_DMA64_TXENABLE;
3287 value |= BWN_DMA64_TXPARITY_DISABLE;
3288 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT)
3289 & BWN_DMA64_TXADDREXT_MASK;
3290 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value);
3291 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo);
3292 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi);
3294 value = BWN_DMA32_TXENABLE;
3295 value |= BWN_DMA32_TXPARITY_DISABLE;
3296 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT)
3297 & BWN_DMA32_TXADDREXT_MASK;
3298 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value);
3299 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo);
3307 dr->dr_usedslot = dr->dr_numslots;
3309 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3310 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT);
3311 value |= BWN_DMA64_RXENABLE;
3312 value |= BWN_DMA64_RXPARITY_DISABLE;
3313 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT)
3314 & BWN_DMA64_RXADDREXT_MASK;
3315 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value);
3316 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo);
3317 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi);
3318 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots *
3319 sizeof(struct bwn_dmadesc64));
3321 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT);
3322 value |= BWN_DMA32_RXENABLE;
3323 value |= BWN_DMA32_RXPARITY_DISABLE;
3324 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT)
3325 & BWN_DMA32_RXADDREXT_MASK;
3326 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value);
3327 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo);
3328 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots *
3329 sizeof(struct bwn_dmadesc32));
3334 bwn_dma_free_ringmemory(struct bwn_dma_ring *dr)
3337 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap);
3338 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase,
3343 bwn_dma_cleanup(struct bwn_dma_ring *dr)
3347 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3348 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3349 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0);
3350 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0);
3352 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0);
3354 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type);
3355 if (dr->dr_type == BHND_DMA_ADDR_64BIT) {
3356 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0);
3357 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0);
3359 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0);
3364 bwn_dma_free_descbufs(struct bwn_dma_ring *dr)
3366 struct bwn_dmadesc_generic *desc;
3367 struct bwn_dmadesc_meta *meta;
3368 struct bwn_mac *mac = dr->dr_mac;
3369 struct bwn_dma *dma = &mac->mac_method.dma;
3370 struct bwn_softc *sc = mac->mac_sc;
3373 if (!dr->dr_usedslot)
3375 for (i = 0; i < dr->dr_numslots; i++) {
3376 dr->getdesc(dr, i, &desc, &meta);
3378 if (meta->mt_m == NULL) {
3380 device_printf(sc->sc_dev, "%s: not TX?\n",
3385 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
3386 bus_dmamap_unload(dr->dr_txring_dtag,
3388 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
3389 bus_dmamap_unload(dma->txbuf_dtag,
3392 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
3393 bwn_dma_free_descbuf(dr, meta);
3398 bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base,
3401 struct bwn_softc *sc = mac->mac_sc;
3406 for (i = 0; i < 10; i++) {
3407 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
3409 value = BWN_READ_4(mac, base + offset);
3410 if (type == BHND_DMA_ADDR_64BIT) {
3411 value &= BWN_DMA64_TXSTAT;
3412 if (value == BWN_DMA64_TXSTAT_DISABLED ||
3413 value == BWN_DMA64_TXSTAT_IDLEWAIT ||
3414 value == BWN_DMA64_TXSTAT_STOPPED)
3417 value &= BWN_DMA32_TXSTATE;
3418 if (value == BWN_DMA32_TXSTAT_DISABLED ||
3419 value == BWN_DMA32_TXSTAT_IDLEWAIT ||
3420 value == BWN_DMA32_TXSTAT_STOPPED)
3425 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL :
3427 BWN_WRITE_4(mac, base + offset, 0);
3428 for (i = 0; i < 10; i++) {
3429 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS :
3431 value = BWN_READ_4(mac, base + offset);
3432 if (type == BHND_DMA_ADDR_64BIT) {
3433 value &= BWN_DMA64_TXSTAT;
3434 if (value == BWN_DMA64_TXSTAT_DISABLED) {
3439 value &= BWN_DMA32_TXSTATE;
3440 if (value == BWN_DMA32_TXSTAT_DISABLED) {
3448 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3457 bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base,
3460 struct bwn_softc *sc = mac->mac_sc;
3465 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL :
3467 BWN_WRITE_4(mac, base + offset, 0);
3468 for (i = 0; i < 10; i++) {
3469 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS :
3471 value = BWN_READ_4(mac, base + offset);
3472 if (type == BHND_DMA_ADDR_64BIT) {
3473 value &= BWN_DMA64_RXSTAT;
3474 if (value == BWN_DMA64_RXSTAT_DISABLED) {
3479 value &= BWN_DMA32_RXSTATE;
3480 if (value == BWN_DMA32_RXSTAT_DISABLED) {
3488 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
3496 bwn_dma_free_descbuf(struct bwn_dma_ring *dr,
3497 struct bwn_dmadesc_meta *meta)
3500 if (meta->mt_m != NULL) {
3501 m_freem(meta->mt_m);
3504 if (meta->mt_ni != NULL) {
3505 ieee80211_free_node(meta->mt_ni);
3511 bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3513 struct bwn_rxhdr4 *rxhdr;
3514 unsigned char *frame;
3516 rxhdr = mtod(m, struct bwn_rxhdr4 *);
3517 rxhdr->frame_len = 0;
3519 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset +
3520 sizeof(struct bwn_plcp6) + 2,
3521 ("%s:%d: fail", __func__, __LINE__));
3522 frame = mtod(m, char *) + dr->dr_frameoffset;
3523 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */);
3527 bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m)
3529 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset;
3531 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7])
3536 bwn_wme_init(struct bwn_mac *mac)
3541 /* enable WME support. */
3542 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF);
3543 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) |
3544 BWN_IFSCTL_USE_EDCF);
3548 bwn_spu_setdelay(struct bwn_mac *mac, int idle)
3550 struct bwn_softc *sc = mac->mac_sc;
3551 struct ieee80211com *ic = &sc->sc_ic;
3552 uint16_t delay; /* microsec */
3554 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050;
3555 if (ic->ic_opmode == IEEE80211_M_IBSS || idle)
3557 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8))
3558 delay = max(delay, (uint16_t)2400);
3560 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay);
3564 bwn_bt_enable(struct bwn_mac *mac)
3566 struct bwn_softc *sc = mac->mac_sc;
3569 if (bwn_bluetooth == 0)
3571 if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0)
3573 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode)
3576 hf = bwn_hf_read(mac);
3577 if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO)
3578 hf |= BWN_HF_BT_COEXISTALT;
3580 hf |= BWN_HF_BT_COEXIST;
3581 bwn_hf_write(mac, hf);
3585 bwn_set_macaddr(struct bwn_mac *mac)
3588 bwn_mac_write_bssid(mac);
3589 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF,
3590 mac->mac_sc->sc_ic.ic_macaddr);
3594 bwn_clear_keys(struct bwn_mac *mac)
3598 for (i = 0; i < mac->mac_max_nr_keys; i++) {
3599 KASSERT(i >= 0 && i < mac->mac_max_nr_keys,
3600 ("%s:%d: fail", __func__, __LINE__));
3602 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE,
3603 NULL, BWN_SEC_KEYSIZE, NULL);
3604 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) {
3605 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE,
3606 NULL, BWN_SEC_KEYSIZE, NULL);
3608 mac->mac_key[i].keyconf = NULL;
3613 bwn_crypt_init(struct bwn_mac *mac)
3615 struct bwn_softc *sc = mac->mac_sc;
3617 mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20;
3618 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key),
3619 ("%s:%d: fail", __func__, __LINE__));
3620 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP);
3622 if (bhnd_get_hwrev(sc->sc_dev) >= 5)
3623 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8);
3624 bwn_clear_keys(mac);
3628 bwn_chip_exit(struct bwn_mac *mac)
3634 bwn_fw_fillinfo(struct bwn_mac *mac)
3638 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT);
3641 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE);
3648 * Request that the GPIO controller tristate all pins set in @p mask, granting
3649 * the MAC core control over the pins.
3651 * @param mac bwn MAC state.
3652 * @param pins If the bit position for a pin number is set to one, tristate the
3656 bwn_gpio_control(struct bwn_mac *mac, uint32_t pins)
3658 struct bwn_softc *sc;
3664 /* Determine desired pin flags */
3665 for (size_t pin = 0; pin < nitems(flags); pin++) {
3666 uint32_t pinbit = (1 << pin);
3668 if (pins & pinbit) {
3669 /* Tristate output */
3670 flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE;
3672 /* Leave unmodified */
3677 /* Configure all pins */
3678 error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags);
3680 device_printf(sc->sc_dev, "error configuring %s pin flags: "
3681 "%d\n", device_get_nameunit(sc->sc_gpio), error);
3690 bwn_gpio_init(struct bwn_mac *mac)
3692 struct bwn_softc *sc;
3699 BWN_WRITE_4(mac, BWN_MACCTL,
3700 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK);
3701 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3702 BWN_READ_2(mac, BWN_GPIO_MASK) | pins);
3704 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) {
3705 /* MAC core is responsible for toggling PAREF via gpio9 */
3706 BWN_WRITE_2(mac, BWN_GPIO_MASK,
3707 BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL);
3709 pins |= BHND_GPIO_BOARD_PACTRL;
3712 return (bwn_gpio_control(mac, pins));
3716 bwn_fw_loadinitvals(struct bwn_mac *mac)
3718 #define GETFWOFFSET(fwp, offset) \
3719 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset))
3720 const size_t hdr_len = sizeof(struct bwn_fwhdr);
3721 const struct bwn_fwhdr *hdr;
3722 struct bwn_fw *fw = &mac->mac_fw;
3725 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data);
3726 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len),
3727 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len);
3730 if (fw->initvals_band.fw) {
3731 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data);
3732 error = bwn_fwinitvals_write(mac,
3733 GETFWOFFSET(fw->initvals_band, hdr_len),
3735 fw->initvals_band.fw->datasize - hdr_len);
3742 bwn_phy_init(struct bwn_mac *mac)
3744 struct bwn_softc *sc = mac->mac_sc;
3747 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac);
3748 mac->mac_phy.rf_onoff(mac, 1);
3749 error = mac->mac_phy.init(mac);
3751 device_printf(sc->sc_dev, "PHY init failed\n");
3754 error = bwn_switch_channel(mac,
3755 mac->mac_phy.get_default_chan(mac));
3757 device_printf(sc->sc_dev,
3758 "failed to switch default channel\n");
3763 if (mac->mac_phy.exit)
3764 mac->mac_phy.exit(mac);
3766 mac->mac_phy.rf_onoff(mac, 0);
3772 bwn_set_txantenna(struct bwn_mac *mac, int antenna)
3777 ant = bwn_ant2phy(antenna);
3780 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL);
3781 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3782 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp);
3783 /* For Probe Resposes */
3784 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL);
3785 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant;
3786 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp);
3790 bwn_set_opmode(struct bwn_mac *mac)
3792 struct bwn_softc *sc = mac->mac_sc;
3793 struct ieee80211com *ic = &sc->sc_ic;
3795 uint16_t cfp_pretbtt;
3797 ctl = BWN_READ_4(mac, BWN_MACCTL);
3798 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL |
3799 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS |
3800 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC);
3801 ctl |= BWN_MACCTL_STA;
3803 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
3804 ic->ic_opmode == IEEE80211_M_MBSS)
3805 ctl |= BWN_MACCTL_HOSTAP;
3806 else if (ic->ic_opmode == IEEE80211_M_IBSS)
3807 ctl &= ~BWN_MACCTL_STA;
3808 ctl |= sc->sc_filters;
3810 if (bhnd_get_hwrev(sc->sc_dev) <= 4)
3811 ctl |= BWN_MACCTL_PROMISC;
3813 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
3816 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) {
3817 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 &&
3818 sc->sc_cid.chip_rev == 3)
3823 BWN_WRITE_2(mac, 0x612, cfp_pretbtt);
3827 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
3830 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
3831 *((bus_addr_t *)arg) = seg->ds_addr;
3836 bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon)
3838 struct bwn_phy *phy = &mac->mac_phy;
3839 struct bwn_softc *sc = mac->mac_sc;
3840 unsigned int i, max_loop;
3842 uint32_t buffer[5] = {
3843 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000
3848 buffer[0] = 0x000201cc;
3851 buffer[0] = 0x000b846e;
3854 BWN_ASSERT_LOCKED(mac->mac_sc);
3856 for (i = 0; i < 5; i++)
3857 bwn_ram_write(mac, i * 4, buffer[i]);
3859 BWN_WRITE_2(mac, 0x0568, 0x0000);
3860 BWN_WRITE_2(mac, 0x07c0,
3861 (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100);
3863 value = (ofdm ? 0x41 : 0x40);
3864 BWN_WRITE_2(mac, 0x050c, value);
3866 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP ||
3867 phy->type == BWN_PHYTYPE_LCN)
3868 BWN_WRITE_2(mac, 0x0514, 0x1a02);
3869 BWN_WRITE_2(mac, 0x0508, 0x0000);
3870 BWN_WRITE_2(mac, 0x050a, 0x0000);
3871 BWN_WRITE_2(mac, 0x054c, 0x0000);
3872 BWN_WRITE_2(mac, 0x056a, 0x0014);
3873 BWN_WRITE_2(mac, 0x0568, 0x0826);
3874 BWN_WRITE_2(mac, 0x0500, 0x0000);
3876 /* XXX TODO: n phy pa override? */
3878 switch (phy->type) {
3880 case BWN_PHYTYPE_LCN:
3881 BWN_WRITE_2(mac, 0x0502, 0x00d0);
3883 case BWN_PHYTYPE_LP:
3884 BWN_WRITE_2(mac, 0x0502, 0x0050);
3887 BWN_WRITE_2(mac, 0x0502, 0x0030);
3892 BWN_READ_2(mac, 0x0502);
3894 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3895 BWN_RF_WRITE(mac, 0x0051, 0x0017);
3896 for (i = 0x00; i < max_loop; i++) {
3897 value = BWN_READ_2(mac, 0x050e);
3902 for (i = 0x00; i < 0x0a; i++) {
3903 value = BWN_READ_2(mac, 0x050e);
3908 for (i = 0x00; i < 0x19; i++) {
3909 value = BWN_READ_2(mac, 0x0690);
3910 if (!(value & 0x0100))
3914 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5)
3915 BWN_RF_WRITE(mac, 0x0051, 0x0037);
3919 bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val)
3923 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__));
3925 macctl = BWN_READ_4(mac, BWN_MACCTL);
3926 if (macctl & BWN_MACCTL_BIGENDIAN)
3927 printf("TODO: need swap\n");
3929 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset);
3930 BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE);
3931 BWN_WRITE_4(mac, BWN_RAM_DATA, val);
3935 bwn_mac_suspend(struct bwn_mac *mac)
3937 struct bwn_softc *sc = mac->mac_sc;
3941 KASSERT(mac->mac_suspended >= 0,
3942 ("%s:%d: fail", __func__, __LINE__));
3944 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3945 __func__, mac->mac_suspended);
3947 if (mac->mac_suspended == 0) {
3948 bwn_psctl(mac, BWN_PS_AWAKE);
3949 BWN_WRITE_4(mac, BWN_MACCTL,
3950 BWN_READ_4(mac, BWN_MACCTL)
3952 BWN_READ_4(mac, BWN_MACCTL);
3953 for (i = 35; i; i--) {
3954 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3955 if (tmp & BWN_INTR_MAC_SUSPENDED)
3959 for (i = 40; i; i--) {
3960 tmp = BWN_READ_4(mac, BWN_INTR_REASON);
3961 if (tmp & BWN_INTR_MAC_SUSPENDED)
3965 device_printf(sc->sc_dev, "MAC suspend failed\n");
3968 mac->mac_suspended++;
3972 bwn_mac_enable(struct bwn_mac *mac)
3974 struct bwn_softc *sc = mac->mac_sc;
3977 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n",
3978 __func__, mac->mac_suspended);
3980 state = bwn_shm_read_2(mac, BWN_SHARED,
3981 BWN_SHARED_UCODESTAT);
3982 if (state != BWN_SHARED_UCODESTAT_SUSPEND &&
3983 state != BWN_SHARED_UCODESTAT_SLEEP) {
3984 DPRINTF(sc, BWN_DEBUG_FW,
3985 "%s: warn: firmware state (%d)\n",
3989 mac->mac_suspended--;
3990 KASSERT(mac->mac_suspended >= 0,
3991 ("%s:%d: fail", __func__, __LINE__));
3992 if (mac->mac_suspended == 0) {
3993 BWN_WRITE_4(mac, BWN_MACCTL,
3994 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON);
3995 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED);
3996 BWN_READ_4(mac, BWN_MACCTL);
3997 BWN_READ_4(mac, BWN_INTR_REASON);
4003 bwn_psctl(struct bwn_mac *mac, uint32_t flags)
4005 struct bwn_softc *sc = mac->mac_sc;
4009 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)),
4010 ("%s:%d: fail", __func__, __LINE__));
4011 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)),
4012 ("%s:%d: fail", __func__, __LINE__));
4014 /* XXX forcibly awake and hwps-off */
4016 BWN_WRITE_4(mac, BWN_MACCTL,
4017 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) &
4019 BWN_READ_4(mac, BWN_MACCTL);
4020 if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
4021 for (i = 0; i < 100; i++) {
4022 ucstat = bwn_shm_read_2(mac, BWN_SHARED,
4023 BWN_SHARED_UCODESTAT);
4024 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP)
4029 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__,
4034 bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type)
4036 struct bwn_softc *sc = mac->mac_sc;
4037 struct bwn_fw *fw = &mac->mac_fw;
4038 const uint8_t rev = bhnd_get_hwrev(sc->sc_dev);
4039 const char *filename;
4047 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
4048 filename = "ucode42";
4051 if (mac->mac_phy.type == BWN_PHYTYPE_AC)
4052 filename = "ucode40";
4055 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40)
4056 filename = "ucode33_lcn40";
4059 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4060 filename = "ucode30_mimo";
4063 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
4064 filename = "ucode29_mimo";
4067 if (mac->mac_phy.type == BWN_PHYTYPE_HT)
4068 filename = "ucode26_mimo";
4072 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4073 filename = "ucode25_mimo";
4074 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
4075 filename = "ucode25_lcn";
4078 if (mac->mac_phy.type == BWN_PHYTYPE_LCN)
4079 filename = "ucode24_lcn";
4082 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4083 filename = "ucode16_mimo";
4089 if (mac->mac_phy.type == BWN_PHYTYPE_N)
4090 filename = "ucode16_mimo";
4091 else if (mac->mac_phy.type == BWN_PHYTYPE_LP)
4092 filename = "ucode16_lp";
4095 filename = "ucode15";
4098 filename = "ucode14";
4101 filename = "ucode13";
4105 filename = "ucode11";
4113 filename = "ucode5";
4116 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev);
4117 bwn_release_firmware(mac);
4118 return (EOPNOTSUPP);
4121 device_printf(sc->sc_dev, "ucode fw: %s\n", filename);
4122 error = bwn_fw_get(mac, type, filename, &fw->ucode);
4124 bwn_release_firmware(mac);
4129 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__));
4130 if (rev >= 5 && rev <= 10) {
4131 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm);
4132 if (error == ENOENT)
4135 bwn_release_firmware(mac);
4138 } else if (rev < 11) {
4139 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev);
4140 bwn_release_firmware(mac);
4141 return (EOPNOTSUPP);
4145 error = bhnd_read_iost(sc->sc_dev, &iost);
4149 switch (mac->mac_phy.type) {
4151 if (rev < 5 || rev > 10)
4153 if (iost & BWN_IOST_HAVE_2GHZ)
4154 filename = "a0g1initvals5";
4156 filename = "a0g0initvals5";
4159 if (rev >= 5 && rev <= 10)
4160 filename = "b0g0initvals5";
4162 filename = "b0g0initvals13";
4166 case BWN_PHYTYPE_LP:
4168 filename = "lp0initvals13";
4170 filename = "lp0initvals14";
4172 filename = "lp0initvals15";
4178 filename = "n16initvals30";
4179 else if (rev == 28 || rev == 25)
4180 filename = "n0initvals25";
4182 filename = "n0initvals24";
4184 filename = "n0initvals16";
4185 else if (rev >= 16 && rev <= 18)
4186 filename = "n0initvals16";
4187 else if (rev >= 11 && rev <= 12)
4188 filename = "n0initvals11";
4195 error = bwn_fw_get(mac, type, filename, &fw->initvals);
4197 bwn_release_firmware(mac);
4201 /* bandswitch initvals */
4202 switch (mac->mac_phy.type) {
4204 if (rev >= 5 && rev <= 10) {
4205 if (iost & BWN_IOST_HAVE_2GHZ)
4206 filename = "a0g1bsinitvals5";
4208 filename = "a0g0bsinitvals5";
4209 } else if (rev >= 11)
4215 if (rev >= 5 && rev <= 10)
4216 filename = "b0g0bsinitvals5";
4222 case BWN_PHYTYPE_LP:
4224 filename = "lp0bsinitvals13";
4226 filename = "lp0bsinitvals14";
4228 filename = "lp0bsinitvals15";
4234 filename = "n16bsinitvals30";
4235 else if (rev == 28 || rev == 25)
4236 filename = "n0bsinitvals25";
4238 filename = "n0bsinitvals24";
4240 filename = "n0bsinitvals16";
4241 else if (rev >= 16 && rev <= 18)
4242 filename = "n0bsinitvals16";
4243 else if (rev >= 11 && rev <= 12)
4244 filename = "n0bsinitvals11";
4249 device_printf(sc->sc_dev, "unknown phy (%d)\n",
4253 error = bwn_fw_get(mac, type, filename, &fw->initvals_band);
4255 bwn_release_firmware(mac);
4260 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n",
4261 rev, mac->mac_phy.type);
4262 bwn_release_firmware(mac);
4263 return (EOPNOTSUPP);
4267 bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type,
4268 const char *name, struct bwn_fwfile *bfw)
4270 const struct bwn_fwhdr *hdr;
4271 struct bwn_softc *sc = mac->mac_sc;
4272 const struct firmware *fw;
4276 bwn_do_release_fw(bfw);
4279 if (bfw->filename != NULL) {
4280 if (bfw->type == type && (strcmp(bfw->filename, name) == 0))
4282 bwn_do_release_fw(bfw);
4285 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s",
4286 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "",
4287 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name);
4288 /* XXX Sleeping on "fwload" with the non-sleepable locks held */
4289 fw = firmware_get(namebuf);
4291 device_printf(sc->sc_dev, "the fw file(%s) not found\n",
4295 if (fw->datasize < sizeof(struct bwn_fwhdr))
4297 hdr = (const struct bwn_fwhdr *)(fw->data);
4298 switch (hdr->type) {
4299 case BWN_FWTYPE_UCODE:
4300 case BWN_FWTYPE_PCM:
4301 if (be32toh(hdr->size) !=
4302 (fw->datasize - sizeof(struct bwn_fwhdr)))
4312 bfw->filename = name;
4317 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf);
4319 firmware_put(fw, FIRMWARE_UNLOAD);
4324 bwn_release_firmware(struct bwn_mac *mac)
4327 bwn_do_release_fw(&mac->mac_fw.ucode);
4328 bwn_do_release_fw(&mac->mac_fw.pcm);
4329 bwn_do_release_fw(&mac->mac_fw.initvals);
4330 bwn_do_release_fw(&mac->mac_fw.initvals_band);
4334 bwn_do_release_fw(struct bwn_fwfile *bfw)
4337 if (bfw->fw != NULL)
4338 firmware_put(bfw->fw, FIRMWARE_UNLOAD);
4340 bfw->filename = NULL;
4344 bwn_fw_loaducode(struct bwn_mac *mac)
4346 #define GETFWOFFSET(fwp, offset) \
4347 ((const uint32_t *)((const char *)fwp.fw->data + offset))
4348 #define GETFWSIZE(fwp, offset) \
4349 ((fwp.fw->datasize - offset) / sizeof(uint32_t))
4350 struct bwn_softc *sc = mac->mac_sc;
4351 const uint32_t *data;
4354 uint16_t date, fwcaps, time;
4357 ctl = BWN_READ_4(mac, BWN_MACCTL);
4358 ctl |= BWN_MACCTL_MCODE_JMP0;
4359 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__,
4361 BWN_WRITE_4(mac, BWN_MACCTL, ctl);
4362 for (i = 0; i < 64; i++)
4363 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0);
4364 for (i = 0; i < 4096; i += 2)
4365 bwn_shm_write_2(mac, BWN_SHARED, i, 0);
4367 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4368 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000);
4369 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr));
4371 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4375 if (mac->mac_fw.pcm.fw) {
4376 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr));
4377 bwn_shm_ctlword(mac, BWN_HW, 0x01ea);
4378 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000);
4379 bwn_shm_ctlword(mac, BWN_HW, 0x01eb);
4380 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm,
4381 sizeof(struct bwn_fwhdr)); i++) {
4382 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i]));
4387 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL);
4388 BWN_WRITE_4(mac, BWN_MACCTL,
4389 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) |
4390 BWN_MACCTL_MCODE_RUN);
4392 for (i = 0; i < 21; i++) {
4393 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED)
4396 device_printf(sc->sc_dev, "ucode timeout\n");
4402 BWN_READ_4(mac, BWN_INTR_REASON);
4404 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV);
4405 if (mac->mac_fw.rev <= 0x128) {
4406 device_printf(sc->sc_dev, "the firmware is too old\n");
4412 * Determine firmware header version; needed for TX/RX packet
4415 if (mac->mac_fw.rev >= 598)
4416 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598;
4417 else if (mac->mac_fw.rev >= 410)
4418 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410;
4420 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351;
4423 * We don't support rev 598 or later; that requires
4424 * another round of changes to the TX/RX descriptor
4425 * and status layout.
4427 * So, complain this is the case and exit out, rather
4428 * than attaching and then failing.
4431 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) {
4432 device_printf(sc->sc_dev,
4433 "firmware is too new (>=598); not supported\n");
4439 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED,
4440 BWN_SHARED_UCODE_PATCH);
4441 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE);
4442 mac->mac_fw.opensource = (date == 0xffff);
4444 mac->mac_flags |= BWN_MAC_FLAG_WME;
4445 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO;
4447 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME);
4448 if (mac->mac_fw.opensource == 0) {
4449 device_printf(sc->sc_dev,
4450 "firmware version (rev %u patch %u date %#x time %#x)\n",
4451 mac->mac_fw.rev, mac->mac_fw.patch, date, time);
4452 if (mac->mac_fw.no_pcmfile)
4453 device_printf(sc->sc_dev,
4454 "no HW crypto acceleration due to pcm5\n");
4456 mac->mac_fw.patch = time;
4457 fwcaps = bwn_fwcaps_read(mac);
4458 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) {
4459 device_printf(sc->sc_dev,
4460 "disabling HW crypto acceleration\n");
4461 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO;
4463 if (!(fwcaps & BWN_FWCAPS_WME)) {
4464 device_printf(sc->sc_dev, "disabling WME support\n");
4465 mac->mac_flags &= ~BWN_MAC_FLAG_WME;
4469 if (BWN_ISOLDFMT(mac))
4470 device_printf(sc->sc_dev, "using old firmware image\n");
4475 BWN_WRITE_4(mac, BWN_MACCTL,
4476 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) |
4477 BWN_MACCTL_MCODE_JMP0);
4484 /* OpenFirmware only */
4486 bwn_fwcaps_read(struct bwn_mac *mac)
4489 KASSERT(mac->mac_fw.opensource == 1,
4490 ("%s:%d: fail", __func__, __LINE__));
4491 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS));
4495 bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals,
4496 size_t count, size_t array_size)
4498 #define GET_NEXTIV16(iv) \
4499 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4500 sizeof(uint16_t) + sizeof(uint16_t)))
4501 #define GET_NEXTIV32(iv) \
4502 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \
4503 sizeof(uint16_t) + sizeof(uint32_t)))
4504 struct bwn_softc *sc = mac->mac_sc;
4505 const struct bwn_fwinitvals *iv;
4510 KASSERT(sizeof(struct bwn_fwinitvals) == 6,
4511 ("%s:%d: fail", __func__, __LINE__));
4513 for (i = 0; i < count; i++) {
4514 if (array_size < sizeof(iv->offset_size))
4516 array_size -= sizeof(iv->offset_size);
4517 offset = be16toh(iv->offset_size);
4518 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0;
4519 offset &= BWN_FWINITVALS_OFFSET_MASK;
4520 if (offset >= 0x1000)
4523 if (array_size < sizeof(iv->data.d32))
4525 array_size -= sizeof(iv->data.d32);
4526 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32));
4527 iv = GET_NEXTIV32(iv);
4530 if (array_size < sizeof(iv->data.d16))
4532 array_size -= sizeof(iv->data.d16);
4533 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16));
4535 iv = GET_NEXTIV16(iv);
4538 if (array_size != 0)
4542 device_printf(sc->sc_dev, "initvals: invalid format\n");
4549 bwn_switch_channel(struct bwn_mac *mac, int chan)
4551 struct bwn_phy *phy = &(mac->mac_phy);
4552 struct bwn_softc *sc = mac->mac_sc;
4553 struct ieee80211com *ic = &sc->sc_ic;
4554 uint16_t channelcookie, savedcookie;
4558 chan = phy->get_default_chan(mac);
4560 channelcookie = chan;
4561 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan))
4562 channelcookie |= 0x100;
4563 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN);
4564 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie);
4565 error = phy->switch_channel(mac, chan);
4569 mac->mac_phy.chan = chan;
4573 device_printf(sc->sc_dev, "failed to switch channel\n");
4574 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie);
4579 bwn_ant2phy(int antenna)
4584 return (BWN_TX_PHY_ANT0);
4586 return (BWN_TX_PHY_ANT1);
4588 return (BWN_TX_PHY_ANT2);
4590 return (BWN_TX_PHY_ANT3);
4592 return (BWN_TX_PHY_ANT01AUTO);
4594 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4599 bwn_wme_load(struct bwn_mac *mac)
4601 struct bwn_softc *sc = mac->mac_sc;
4604 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams),
4605 ("%s:%d: fail", __func__, __LINE__));
4607 bwn_mac_suspend(mac);
4608 for (i = 0; i < N(sc->sc_wmeParams); i++)
4609 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]),
4610 bwn_wme_shm_offsets[i]);
4611 bwn_mac_enable(mac);
4615 bwn_wme_loadparams(struct bwn_mac *mac,
4616 const struct wmeParams *p, uint16_t shm_offset)
4618 #define SM(_v, _f) (((_v) << _f##_S) & _f)
4619 struct bwn_softc *sc = mac->mac_sc;
4620 uint16_t params[BWN_NR_WMEPARAMS];
4624 slot = BWN_READ_2(mac, BWN_RNG) &
4625 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4627 memset(¶ms, 0, sizeof(params));
4629 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d "
4630 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit,
4631 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn);
4633 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32;
4634 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4635 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX);
4636 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN);
4637 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn;
4638 params[BWN_WMEPARAM_BSLOTS] = slot;
4639 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn;
4641 for (i = 0; i < N(params); i++) {
4642 if (i == BWN_WMEPARAM_STATUS) {
4643 tmp = bwn_shm_read_2(mac, BWN_SHARED,
4644 shm_offset + (i * 2));
4646 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4649 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2),
4656 bwn_mac_write_bssid(struct bwn_mac *mac)
4658 struct bwn_softc *sc = mac->mac_sc;
4661 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2];
4663 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid);
4664 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN);
4665 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid,
4666 IEEE80211_ADDR_LEN);
4668 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) {
4669 tmp = (uint32_t) (mac_bssid[i + 0]);
4670 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8;
4671 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16;
4672 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24;
4673 bwn_ram_write(mac, 0x20 + i, tmp);
4678 bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset,
4679 const uint8_t *macaddr)
4681 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 };
4688 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset);
4691 data |= macaddr[1] << 8;
4692 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4694 data |= macaddr[3] << 8;
4695 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4697 data |= macaddr[5] << 8;
4698 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data);
4702 bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4703 const uint8_t *key, size_t key_len, const uint8_t *mac_addr)
4705 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, };
4706 uint8_t per_sta_keys_start = 8;
4708 if (BWN_SEC_NEWAPI(mac))
4709 per_sta_keys_start = 4;
4711 KASSERT(index < mac->mac_max_nr_keys,
4712 ("%s:%d: fail", __func__, __LINE__));
4713 KASSERT(key_len <= BWN_SEC_KEYSIZE,
4714 ("%s:%d: fail", __func__, __LINE__));
4716 if (index >= per_sta_keys_start)
4717 bwn_key_macwrite(mac, index, NULL);
4719 memcpy(buf, key, key_len);
4720 bwn_key_write(mac, index, algorithm, buf);
4721 if (index >= per_sta_keys_start)
4722 bwn_key_macwrite(mac, index, mac_addr);
4724 mac->mac_key[index].algorithm = algorithm;
4728 bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr)
4730 struct bwn_softc *sc = mac->mac_sc;
4731 uint32_t addrtmp[2] = { 0, 0 };
4734 if (BWN_SEC_NEWAPI(mac))
4737 KASSERT(index >= start,
4738 ("%s:%d: fail", __func__, __LINE__));
4742 addrtmp[0] = addr[0];
4743 addrtmp[0] |= ((uint32_t) (addr[1]) << 8);
4744 addrtmp[0] |= ((uint32_t) (addr[2]) << 16);
4745 addrtmp[0] |= ((uint32_t) (addr[3]) << 24);
4746 addrtmp[1] = addr[4];
4747 addrtmp[1] |= ((uint32_t) (addr[5]) << 8);
4750 if (bhnd_get_hwrev(sc->sc_dev) >= 5) {
4751 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]);
4752 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]);
4755 bwn_shm_write_4(mac, BWN_SHARED,
4756 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]);
4757 bwn_shm_write_2(mac, BWN_SHARED,
4758 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]);
4764 bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm,
4769 uint16_t kidx, value;
4771 kidx = BWN_SEC_KEY2FW(mac, index);
4772 bwn_shm_write_2(mac, BWN_SHARED,
4773 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm);
4775 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE);
4776 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) {
4778 value |= (uint16_t)(key[i + 1]) << 8;
4779 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value);
4784 bwn_phy_exit(struct bwn_mac *mac)
4787 mac->mac_phy.rf_onoff(mac, 0);
4788 if (mac->mac_phy.exit != NULL)
4789 mac->mac_phy.exit(mac);
4793 bwn_dma_free(struct bwn_mac *mac)
4795 struct bwn_dma *dma;
4797 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
4799 dma = &mac->mac_method.dma;
4801 bwn_dma_ringfree(&dma->rx);
4802 bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
4803 bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
4804 bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
4805 bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
4806 bwn_dma_ringfree(&dma->mcast);
4810 bwn_core_stop(struct bwn_mac *mac)
4812 struct bwn_softc *sc = mac->mac_sc;
4814 BWN_ASSERT_LOCKED(sc);
4816 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
4819 callout_stop(&sc->sc_rfswitch_ch);
4820 callout_stop(&sc->sc_task_ch);
4821 callout_stop(&sc->sc_watchdog_ch);
4822 sc->sc_watchdog_timer = 0;
4823 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
4824 BWN_READ_4(mac, BWN_INTR_MASK);
4825 bwn_mac_suspend(mac);
4827 mac->mac_status = BWN_MAC_STATUS_INITED;
4831 bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan)
4833 struct bwn_mac *up_dev = NULL;
4834 struct bwn_mac *down_dev;
4835 struct bwn_mac *mac;
4839 BWN_ASSERT_LOCKED(sc);
4841 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) {
4842 if (IEEE80211_IS_CHAN_2GHZ(chan) &&
4843 mac->mac_phy.supports_2ghz) {
4846 } else if (IEEE80211_IS_CHAN_5GHZ(chan) &&
4847 mac->mac_phy.supports_5ghz) {
4851 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
4857 if (up_dev == NULL) {
4858 device_printf(sc->sc_dev, "Could not find a device\n");
4861 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode)
4864 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET,
4865 "switching to %s-GHz band\n",
4866 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4868 down_dev = sc->sc_curmac;
4869 status = down_dev->mac_status;
4870 if (status >= BWN_MAC_STATUS_STARTED)
4871 bwn_core_stop(down_dev);
4872 if (status >= BWN_MAC_STATUS_INITED)
4873 bwn_core_exit(down_dev);
4875 if (down_dev != up_dev) {
4876 err = bwn_phy_reset(down_dev);
4881 up_dev->mac_phy.gmode = gmode;
4882 if (status >= BWN_MAC_STATUS_INITED) {
4883 err = bwn_core_init(up_dev);
4885 device_printf(sc->sc_dev,
4886 "fatal: failed to initialize for %s-GHz\n",
4887 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5");
4891 if (status >= BWN_MAC_STATUS_STARTED)
4892 bwn_core_start(up_dev);
4893 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__));
4894 sc->sc_curmac = up_dev;
4898 sc->sc_curmac = NULL;
4903 bwn_rf_turnon(struct bwn_mac *mac)
4906 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4908 bwn_mac_suspend(mac);
4909 mac->mac_phy.rf_onoff(mac, 1);
4910 mac->mac_phy.rf_on = 1;
4911 bwn_mac_enable(mac);
4915 bwn_rf_turnoff(struct bwn_mac *mac)
4918 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__);
4920 bwn_mac_suspend(mac);
4921 mac->mac_phy.rf_onoff(mac, 0);
4922 mac->mac_phy.rf_on = 0;
4923 bwn_mac_enable(mac);
4930 bwn_phy_reset(struct bwn_mac *mac)
4932 struct bwn_softc *sc;
4933 uint16_t iost, mask;
4938 iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE;
4939 mask = iost | BWN_IOCTL_SUPPORT_G;
4941 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
4946 iost &= ~BHND_IOCTL_CLK_FORCE;
4948 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask)))
4957 bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
4959 struct bwn_vap *bvp = BWN_VAP(vap);
4960 struct ieee80211com *ic= vap->iv_ic;
4961 enum ieee80211_state ostate = vap->iv_state;
4962 struct bwn_softc *sc = ic->ic_softc;
4963 struct bwn_mac *mac = sc->sc_curmac;
4966 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__,
4967 ieee80211_state_name[vap->iv_state],
4968 ieee80211_state_name[nstate]);
4970 error = bvp->bv_newstate(vap, nstate, arg);
4976 bwn_led_newstate(mac, nstate);
4979 * Clear the BSSID when we stop a STA
4981 if (vap->iv_opmode == IEEE80211_M_STA) {
4982 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
4984 * Clear out the BSSID. If we reassociate to
4985 * the same AP, this will reinialize things
4988 if (ic->ic_opmode == IEEE80211_M_STA &&
4989 (sc->sc_flags & BWN_FLAG_INVALID) == 0) {
4990 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN);
4991 bwn_set_macaddr(mac);
4996 if (vap->iv_opmode == IEEE80211_M_MONITOR ||
4997 vap->iv_opmode == IEEE80211_M_AHDEMO) {
4998 /* XXX nothing to do? */
4999 } else if (nstate == IEEE80211_S_RUN) {
5000 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN);
5001 bwn_set_opmode(mac);
5002 bwn_set_pretbtt(mac);
5003 bwn_spu_setdelay(mac, 0);
5004 bwn_set_macaddr(mac);
5013 bwn_set_pretbtt(struct bwn_mac *mac)
5015 struct bwn_softc *sc = mac->mac_sc;
5016 struct ieee80211com *ic = &sc->sc_ic;
5019 if (ic->ic_opmode == IEEE80211_M_IBSS)
5022 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250;
5023 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt);
5024 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt);
5030 struct bwn_mac *mac = arg;
5031 struct bwn_softc *sc = mac->mac_sc;
5034 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
5035 (sc->sc_flags & BWN_FLAG_INVALID))
5036 return (FILTER_STRAY);
5038 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__);
5040 reason = BWN_READ_4(mac, BWN_INTR_REASON);
5041 if (reason == 0xffffffff) /* shared IRQ */
5042 return (FILTER_STRAY);
5043 reason &= mac->mac_intr_mask;
5045 return (FILTER_HANDLED);
5046 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason);
5048 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00;
5049 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00;
5050 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00;
5051 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00;
5052 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00;
5053 BWN_WRITE_4(mac, BWN_INTR_REASON, reason);
5054 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]);
5055 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]);
5056 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]);
5057 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]);
5058 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]);
5060 /* Disable interrupts. */
5061 BWN_WRITE_4(mac, BWN_INTR_MASK, 0);
5063 mac->mac_reason_intr = reason;
5065 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
5067 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask);
5068 return (FILTER_HANDLED);
5072 bwn_intrtask(void *arg, int npending)
5074 struct bwn_mac *mac = arg;
5075 struct bwn_softc *sc = mac->mac_sc;
5076 uint32_t merged = 0;
5077 int i, tx = 0, rx = 0;
5080 if (mac->mac_status < BWN_MAC_STATUS_STARTED ||
5081 (sc->sc_flags & BWN_FLAG_INVALID)) {
5086 for (i = 0; i < N(mac->mac_reason); i++)
5087 merged |= mac->mac_reason[i];
5089 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR)
5090 device_printf(sc->sc_dev, "MAC trans error\n");
5092 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) {
5093 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__);
5094 mac->mac_phy.txerrors--;
5095 if (mac->mac_phy.txerrors == 0) {
5096 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
5097 bwn_restart(mac, "PHY TX errors");
5101 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) {
5102 if (merged & BWN_DMAINTR_FATALMASK) {
5103 device_printf(sc->sc_dev,
5104 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n",
5105 mac->mac_reason[0], mac->mac_reason[1],
5106 mac->mac_reason[2], mac->mac_reason[3],
5107 mac->mac_reason[4], mac->mac_reason[5]);
5108 bwn_restart(mac, "DMA error");
5112 if (merged & BWN_DMAINTR_NONFATALMASK) {
5113 device_printf(sc->sc_dev,
5114 "DMA error: %#x %#x %#x %#x %#x %#x\n",
5115 mac->mac_reason[0], mac->mac_reason[1],
5116 mac->mac_reason[2], mac->mac_reason[3],
5117 mac->mac_reason[4], mac->mac_reason[5]);
5121 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG)
5122 bwn_intr_ucode_debug(mac);
5123 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI)
5124 bwn_intr_tbtt_indication(mac);
5125 if (mac->mac_reason_intr & BWN_INTR_ATIM_END)
5126 bwn_intr_atim_end(mac);
5127 if (mac->mac_reason_intr & BWN_INTR_BEACON)
5128 bwn_intr_beacon(mac);
5129 if (mac->mac_reason_intr & BWN_INTR_PMQ)
5131 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK)
5132 bwn_intr_noise(mac);
5134 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5135 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) {
5136 bwn_dma_rx(mac->mac_method.dma.rx);
5140 rx = bwn_pio_rx(&mac->mac_method.pio.rx);
5142 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5143 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5144 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5145 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5146 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__));
5148 if (mac->mac_reason_intr & BWN_INTR_TX_OK) {
5149 bwn_intr_txeof(mac);
5153 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask);
5155 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
5156 int evt = BWN_LED_EVENT_NONE;
5159 if (sc->sc_rx_rate > sc->sc_tx_rate)
5160 evt = BWN_LED_EVENT_RX;
5162 evt = BWN_LED_EVENT_TX;
5164 evt = BWN_LED_EVENT_TX;
5166 evt = BWN_LED_EVENT_RX;
5167 } else if (rx == 0) {
5168 evt = BWN_LED_EVENT_POLL;
5171 if (evt != BWN_LED_EVENT_NONE)
5172 bwn_led_event(mac, evt);
5175 if (mbufq_first(&sc->sc_snd) != NULL)
5178 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE);
5184 bwn_restart(struct bwn_mac *mac, const char *msg)
5186 struct bwn_softc *sc = mac->mac_sc;
5187 struct ieee80211com *ic = &sc->sc_ic;
5189 if (mac->mac_status < BWN_MAC_STATUS_INITED)
5192 device_printf(sc->sc_dev, "HW reset: %s\n", msg);
5193 ieee80211_runtask(ic, &mac->mac_hwreset);
5197 bwn_intr_ucode_debug(struct bwn_mac *mac)
5199 struct bwn_softc *sc = mac->mac_sc;
5202 if (mac->mac_fw.opensource == 0)
5205 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG);
5207 case BWN_DEBUGINTR_PANIC:
5208 bwn_handle_fwpanic(mac);
5210 case BWN_DEBUGINTR_DUMP_SHM:
5211 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n");
5213 case BWN_DEBUGINTR_DUMP_REGS:
5214 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n");
5216 case BWN_DEBUGINTR_MARKER:
5217 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n");
5220 device_printf(sc->sc_dev,
5221 "ucode debug unknown reason: %#x\n", reason);
5224 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG,
5229 bwn_intr_tbtt_indication(struct bwn_mac *mac)
5231 struct bwn_softc *sc = mac->mac_sc;
5232 struct ieee80211com *ic = &sc->sc_ic;
5234 if (ic->ic_opmode != IEEE80211_M_HOSTAP)
5236 if (ic->ic_opmode == IEEE80211_M_IBSS)
5237 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID;
5241 bwn_intr_atim_end(struct bwn_mac *mac)
5244 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) {
5245 BWN_WRITE_4(mac, BWN_MACCMD,
5246 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID);
5247 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID;
5252 bwn_intr_beacon(struct bwn_mac *mac)
5254 struct bwn_softc *sc = mac->mac_sc;
5255 struct ieee80211com *ic = &sc->sc_ic;
5256 uint32_t cmd, beacon0, beacon1;
5258 if (ic->ic_opmode == IEEE80211_M_HOSTAP ||
5259 ic->ic_opmode == IEEE80211_M_MBSS)
5262 mac->mac_intr_mask &= ~BWN_INTR_BEACON;
5264 cmd = BWN_READ_4(mac, BWN_MACCMD);
5265 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID);
5266 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID);
5268 if (beacon0 && beacon1) {
5269 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON);
5270 mac->mac_intr_mask |= BWN_INTR_BEACON;
5274 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) {
5275 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP;
5276 bwn_load_beacon0(mac);
5277 bwn_load_beacon1(mac);
5278 cmd = BWN_READ_4(mac, BWN_MACCMD);
5279 cmd |= BWN_MACCMD_BEACON0_VALID;
5280 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5283 bwn_load_beacon0(mac);
5284 cmd = BWN_READ_4(mac, BWN_MACCMD);
5285 cmd |= BWN_MACCMD_BEACON0_VALID;
5286 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5287 } else if (!beacon1) {
5288 bwn_load_beacon1(mac);
5289 cmd = BWN_READ_4(mac, BWN_MACCMD);
5290 cmd |= BWN_MACCMD_BEACON1_VALID;
5291 BWN_WRITE_4(mac, BWN_MACCMD, cmd);
5297 bwn_intr_pmq(struct bwn_mac *mac)
5302 tmp = BWN_READ_4(mac, BWN_PS_STATUS);
5303 if (!(tmp & 0x00000008))
5306 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002);
5310 bwn_intr_noise(struct bwn_mac *mac)
5312 struct bwn_phy_g *pg = &mac->mac_phy.phy_g;
5318 if (mac->mac_phy.type != BWN_PHYTYPE_G)
5321 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__));
5322 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac));
5323 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f ||
5327 KASSERT(mac->mac_noise.noi_nsamples < 8,
5328 ("%s:%d: fail", __func__, __LINE__));
5329 i = mac->mac_noise.noi_nsamples;
5330 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1);
5331 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1);
5332 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1);
5333 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1);
5334 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]];
5335 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]];
5336 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]];
5337 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]];
5338 mac->mac_noise.noi_nsamples++;
5339 if (mac->mac_noise.noi_nsamples == 8) {
5341 for (i = 0; i < 8; i++) {
5342 for (j = 0; j < 4; j++)
5343 average += mac->mac_noise.noi_samples[i][j];
5345 average = (((average / 32) * 125) + 64) / 128;
5346 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f;
5351 average -= (tmp == 8) ? 72 : 48;
5353 mac->mac_stats.link_noise = average;
5354 mac->mac_noise.noi_running = 0;
5358 bwn_noise_gensample(mac);
5362 bwn_pio_rx(struct bwn_pio_rxqueue *prq)
5364 struct bwn_mac *mac = prq->prq_mac;
5365 struct bwn_softc *sc = mac->mac_sc;
5368 BWN_ASSERT_LOCKED(sc);
5370 if (mac->mac_status < BWN_MAC_STATUS_STARTED)
5373 for (i = 0; i < 5000; i++) {
5374 if (bwn_pio_rxeof(prq) == 0)
5378 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n");
5379 return ((i > 0) ? 1 : 0);
5383 bwn_dma_rx(struct bwn_dma_ring *dr)
5387 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
5388 curslot = dr->get_curslot(dr);
5389 KASSERT(curslot >= 0 && curslot < dr->dr_numslots,
5390 ("%s:%d: fail", __func__, __LINE__));
5392 slot = dr->dr_curslot;
5393 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot))
5394 bwn_dma_rxeof(dr, &slot);
5396 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap,
5397 BUS_DMASYNC_PREWRITE);
5399 dr->set_curslot(dr, slot);
5400 dr->dr_curslot = slot;
5404 bwn_intr_txeof(struct bwn_mac *mac)
5406 struct bwn_txstatus stat;
5407 uint32_t stat0, stat1;
5410 BWN_ASSERT_LOCKED(mac->mac_sc);
5413 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0);
5414 if (!(stat0 & 0x00000001))
5416 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1);
5418 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5419 "%s: stat0=0x%08x, stat1=0x%08x\n",
5424 stat.cookie = (stat0 >> 16);
5425 stat.seq = (stat1 & 0x0000ffff);
5426 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16);
5427 tmp = (stat0 & 0x0000ffff);
5428 stat.framecnt = ((tmp & 0xf000) >> 12);
5429 stat.rtscnt = ((tmp & 0x0f00) >> 8);
5430 stat.sreason = ((tmp & 0x001c) >> 2);
5431 stat.pm = (tmp & 0x0080) ? 1 : 0;
5432 stat.im = (tmp & 0x0040) ? 1 : 0;
5433 stat.ampdu = (tmp & 0x0020) ? 1 : 0;
5434 stat.ack = (tmp & 0x0002) ? 1 : 0;
5436 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT,
5437 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, "
5438 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n",
5451 bwn_handle_txeof(mac, &stat);
5456 bwn_hwreset(void *arg, int npending)
5458 struct bwn_mac *mac = arg;
5459 struct bwn_softc *sc = mac->mac_sc;
5465 prev_status = mac->mac_status;
5466 if (prev_status >= BWN_MAC_STATUS_STARTED)
5468 if (prev_status >= BWN_MAC_STATUS_INITED)
5471 if (prev_status >= BWN_MAC_STATUS_INITED) {
5472 error = bwn_core_init(mac);
5476 if (prev_status >= BWN_MAC_STATUS_STARTED)
5477 bwn_core_start(mac);
5480 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error);
5481 sc->sc_curmac = NULL;
5487 bwn_handle_fwpanic(struct bwn_mac *mac)
5489 struct bwn_softc *sc = mac->mac_sc;
5492 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG);
5493 device_printf(sc->sc_dev,"fw panic (%u)\n", reason);
5495 if (reason == BWN_FWPANIC_RESTART)
5496 bwn_restart(mac, "ucode panic");
5500 bwn_load_beacon0(struct bwn_mac *mac)
5503 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5507 bwn_load_beacon1(struct bwn_mac *mac)
5510 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
5514 bwn_jssi_read(struct bwn_mac *mac)
5518 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a);
5520 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088);
5526 bwn_noise_gensample(struct bwn_mac *mac)
5528 uint32_t jssi = 0x7f7f7f7f;
5530 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff));
5531 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16);
5532 BWN_WRITE_4(mac, BWN_MACCMD,
5533 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE);
5537 bwn_dma_freeslot(struct bwn_dma_ring *dr)
5539 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5541 return (dr->dr_numslots - dr->dr_usedslot);
5545 bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot)
5547 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
5549 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1,
5550 ("%s:%d: fail", __func__, __LINE__));
5551 if (slot == dr->dr_numslots - 1)
5557 bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot)
5559 struct bwn_mac *mac = dr->dr_mac;
5560 struct bwn_softc *sc = mac->mac_sc;
5561 struct bwn_dma *dma = &mac->mac_method.dma;
5562 struct bwn_dmadesc_generic *desc;
5563 struct bwn_dmadesc_meta *meta;
5564 struct bwn_rxhdr4 *rxhdr;
5571 dr->getdesc(dr, *slot, &desc, &meta);
5573 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD);
5576 if (bwn_dma_newbuf(dr, desc, meta, 0)) {
5577 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5581 rxhdr = mtod(m, struct bwn_rxhdr4 *);
5582 len = le16toh(rxhdr->frame_len);
5584 counter_u64_add(sc->sc_ic.ic_ierrors, 1);
5587 if (bwn_dma_check_redzone(dr, m)) {
5588 device_printf(sc->sc_dev, "redzone error.\n");
5589 bwn_dma_set_redzone(dr, m);
5590 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5591 BUS_DMASYNC_PREWRITE);
5594 if (len > dr->dr_rx_bufsize) {
5597 dr->getdesc(dr, *slot, &desc, &meta);
5598 bwn_dma_set_redzone(dr, meta->mt_m);
5599 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5600 BUS_DMASYNC_PREWRITE);
5601 *slot = bwn_dma_nextslot(dr, *slot);
5603 tmp -= dr->dr_rx_bufsize;
5607 device_printf(sc->sc_dev, "too small buffer "
5608 "(len %u buffer %u dropped %d)\n",
5609 len, dr->dr_rx_bufsize, cnt);
5613 switch (mac->mac_fw.fw_hdr_format) {
5614 case BWN_FW_HDR_351:
5615 case BWN_FW_HDR_410:
5616 macstat = le32toh(rxhdr->ps4.r351.mac_status);
5618 case BWN_FW_HDR_598:
5619 macstat = le32toh(rxhdr->ps4.r598.mac_status);
5623 if (macstat & BWN_RX_MAC_FCSERR) {
5624 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5625 device_printf(sc->sc_dev, "RX drop\n");
5630 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset;
5631 m_adj(m, dr->dr_frameoffset);
5633 bwn_rxeof(dr->dr_mac, m, rxhdr);
5637 bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status)
5639 struct bwn_softc *sc = mac->mac_sc;
5640 struct bwn_stats *stats = &mac->mac_stats;
5642 BWN_ASSERT_LOCKED(mac->mac_sc);
5645 device_printf(sc->sc_dev, "TODO: STATUS IM\n");
5647 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n");
5648 if (status->rtscnt) {
5649 if (status->rtscnt == 0xf)
5655 if (mac->mac_flags & BWN_MAC_FLAG_DMA) {
5656 bwn_dma_handle_txeof(mac, status);
5658 bwn_pio_handle_txeof(mac, status);
5661 bwn_phy_txpower_check(mac, 0);
5665 bwn_pio_rxeof(struct bwn_pio_rxqueue *prq)
5667 struct bwn_mac *mac = prq->prq_mac;
5668 struct bwn_softc *sc = mac->mac_sc;
5669 struct bwn_rxhdr4 rxhdr;
5671 uint32_t ctl32, macstat, v32;
5672 unsigned int i, padding;
5673 uint16_t ctl16, len, totlen, v16;
5677 memset(&rxhdr, 0, sizeof(rxhdr));
5679 if (prq->prq_rev >= 8) {
5680 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5681 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY))
5683 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5684 BWN_PIO8_RXCTL_FRAMEREADY);
5685 for (i = 0; i < 10; i++) {
5686 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL);
5687 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY)
5692 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5693 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY))
5695 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL,
5696 BWN_PIO_RXCTL_FRAMEREADY);
5697 for (i = 0; i < 10; i++) {
5698 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL);
5699 if (ctl16 & BWN_PIO_RXCTL_DATAREADY)
5704 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
5707 if (prq->prq_rev >= 8) {
5708 bus_read_multi_4(sc->sc_mem_res,
5709 prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr,
5712 bus_read_multi_2(sc->sc_mem_res,
5713 prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr,
5716 len = le16toh(rxhdr.frame_len);
5718 device_printf(sc->sc_dev, "%s: len is too big\n", __func__);
5722 device_printf(sc->sc_dev, "%s: len is 0\n", __func__);
5726 switch (mac->mac_fw.fw_hdr_format) {
5727 case BWN_FW_HDR_351:
5728 case BWN_FW_HDR_410:
5729 macstat = le32toh(rxhdr.ps4.r351.mac_status);
5731 case BWN_FW_HDR_598:
5732 macstat = le32toh(rxhdr.ps4.r598.mac_status);
5736 if (macstat & BWN_RX_MAC_FCSERR) {
5737 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) {
5738 device_printf(sc->sc_dev, "%s: FCS error", __func__);
5743 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
5744 totlen = len + padding;
5745 KASSERT(totlen <= MCLBYTES, ("too big..\n"));
5746 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5748 device_printf(sc->sc_dev, "%s: out of memory", __func__);
5751 mp = mtod(m, unsigned char *);
5752 if (prq->prq_rev >= 8) {
5753 bus_read_multi_4(sc->sc_mem_res,
5754 prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3));
5756 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA);
5757 data = &(mp[totlen - 1]);
5758 switch (totlen & 3) {
5760 *data = (v32 >> 16);
5770 bus_read_multi_2(sc->sc_mem_res,
5771 prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1));
5773 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA);
5774 mp[totlen - 1] = v16;
5778 m->m_len = m->m_pkthdr.len = totlen;
5780 bwn_rxeof(prq->prq_mac, m, &rxhdr);
5784 if (prq->prq_rev >= 8)
5785 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL,
5786 BWN_PIO8_RXCTL_DATAREADY);
5788 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY);
5793 bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc,
5794 struct bwn_dmadesc_meta *meta, int init)
5796 struct bwn_mac *mac = dr->dr_mac;
5797 struct bwn_dma *dma = &mac->mac_method.dma;
5798 struct bwn_rxhdr4 *hdr;
5804 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
5809 * If the NIC is up and running, we need to:
5810 * - Clear RX buffer's header.
5811 * - Restore RX descriptor settings.
5818 m->m_len = m->m_pkthdr.len = MCLBYTES;
5820 bwn_dma_set_redzone(dr, m);
5823 * Try to load RX buf into temporary DMA map
5825 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m,
5826 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
5831 * See the comment above
5840 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap);
5842 meta->mt_paddr = paddr;
5845 * Swap RX buf's DMA map with the loaded temporary one
5847 map = meta->mt_dmap;
5848 meta->mt_dmap = dr->dr_spare_dmap;
5849 dr->dr_spare_dmap = map;
5853 * Clear RX buf header
5855 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *);
5856 bzero(hdr, sizeof(*hdr));
5857 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap,
5858 BUS_DMASYNC_PREWRITE);
5861 * Setup RX buf descriptor
5863 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len -
5864 sizeof(*hdr), 0, 0, 0);
5869 bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
5870 bus_size_t mapsz __unused, int error)
5874 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
5875 *((bus_addr_t *)arg) = seg->ds_addr;
5880 bwn_hwrate2ieeerate(int rate)
5884 case BWN_CCK_RATE_1MB:
5886 case BWN_CCK_RATE_2MB:
5888 case BWN_CCK_RATE_5MB:
5890 case BWN_CCK_RATE_11MB:
5892 case BWN_OFDM_RATE_6MB:
5894 case BWN_OFDM_RATE_9MB:
5896 case BWN_OFDM_RATE_12MB:
5898 case BWN_OFDM_RATE_18MB:
5900 case BWN_OFDM_RATE_24MB:
5902 case BWN_OFDM_RATE_36MB:
5904 case BWN_OFDM_RATE_48MB:
5906 case BWN_OFDM_RATE_54MB:
5915 * Post process the RX provided RSSI.
5917 * Valid for A, B, G, LP PHYs.
5920 bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi,
5921 int ofdm, int adjust_2053, int adjust_2050)
5923 struct bwn_phy *phy = &mac->mac_phy;
5924 struct bwn_phy_g *gphy = &phy->phy_g;
5927 switch (phy->rf_ver) {
5933 tmp = tmp * 73 / 64;
5939 if (mac->mac_sc->sc_board_info.board_flags
5940 & BHND_BFL_ADCDIV) {
5943 tmp = gphy->pg_nrssi_lt[in_rssi];
5944 tmp = (31 - tmp) * -131 / 128 - 57;
5947 tmp = (31 - tmp) * -149 / 128 - 68;
5949 if (phy->type == BWN_PHYTYPE_G && adjust_2050)
5955 tmp = in_rssi - 256;
5961 tmp = (tmp - 11) * 103 / 64;
5972 bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr)
5974 const struct bwn_rxhdr4 *rxhdr = _rxhdr;
5975 struct bwn_plcp6 *plcp;
5976 struct bwn_softc *sc = mac->mac_sc;
5977 struct ieee80211_frame_min *wh;
5978 struct ieee80211_node *ni;
5979 struct ieee80211com *ic = &sc->sc_ic;
5981 int padding, rate, rssi = 0, noise = 0, type;
5982 uint16_t phytype, phystat0, phystat3, chanstat;
5983 unsigned char *mp = mtod(m, unsigned char *);
5985 BWN_ASSERT_LOCKED(sc);
5987 phystat0 = le16toh(rxhdr->phy_status0);
5990 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only
5993 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3);
5995 switch (mac->mac_fw.fw_hdr_format) {
5996 case BWN_FW_HDR_351:
5997 case BWN_FW_HDR_410:
5998 macstat = le32toh(rxhdr->ps4.r351.mac_status);
5999 chanstat = le16toh(rxhdr->ps4.r351.channel);
6001 case BWN_FW_HDR_598:
6002 macstat = le32toh(rxhdr->ps4.r598.mac_status);
6003 chanstat = le16toh(rxhdr->ps4.r598.channel);
6008 phytype = chanstat & BWN_RX_CHAN_PHYTYPE;
6010 if (macstat & BWN_RX_MAC_FCSERR)
6011 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n");
6012 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV))
6013 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n");
6014 if (macstat & BWN_RX_MAC_DECERR)
6017 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0;
6018 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) {
6019 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
6023 plcp = (struct bwn_plcp6 *)(mp + padding);
6024 m_adj(m, sizeof(struct bwn_plcp6) + padding);
6025 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) {
6026 device_printf(sc->sc_dev, "frame too short (length=%d)\n",
6030 wh = mtod(m, struct ieee80211_frame_min *);
6032 if (macstat & BWN_RX_MAC_DEC) {
6033 DPRINTF(sc, BWN_DEBUG_HWCRYPTO,
6034 "RX decryption attempted (old %d keyidx %#x)\n",
6036 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT);
6039 if (phystat0 & BWN_RX_PHYST0_OFDM)
6040 rate = bwn_plcp_get_ofdmrate(mac, plcp,
6041 phytype == BWN_PHYTYPE_A);
6043 rate = bwn_plcp_get_cckrate(mac, plcp);
6045 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP))
6048 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate);
6055 case BWN_PHYTYPE_LP:
6056 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi,
6057 !! (phystat0 & BWN_RX_PHYST0_OFDM),
6058 !! (phystat0 & BWN_RX_PHYST0_GAINCTL),
6059 !! (phystat3 & BWN_RX_PHYST3_TRSTATE));
6062 /* Broadcom has code for min/avg, but always used max */
6063 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32)
6064 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2);
6066 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1);
6068 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV,
6069 "%s: power0=%d, power1=%d, power2=%d\n",
6071 rxhdr->phy.n.power0,
6072 rxhdr->phy.n.power1,
6073 rxhdr->ps2.n.power2);
6077 /* XXX TODO: implement rssi for other PHYs */
6082 * RSSI here is absolute, not relative to the noise floor.
6084 noise = mac->mac_stats.link_noise;
6085 rssi = rssi - noise;
6088 if (ieee80211_radiotap_active(ic))
6089 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise);
6090 m_adj(m, -IEEE80211_CRC_LEN);
6094 ni = ieee80211_find_rxnode(ic, wh);
6096 type = ieee80211_input(ni, m, rssi, noise);
6097 ieee80211_free_node(ni);
6099 type = ieee80211_input_all(ic, m, rssi, noise);
6104 device_printf(sc->sc_dev, "%s: dropped\n", __func__);
6108 bwn_ratectl_tx_complete(const struct ieee80211_node *ni,
6109 const struct bwn_txstatus *status)
6111 struct ieee80211_ratectl_tx_status txs;
6115 * If we don't get an ACK, then we should log the
6116 * full framecnt. That may be 0 if it's a PHY
6117 * failure, so ensure that gets logged as some
6120 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY;
6122 txs.status = IEEE80211_RATECTL_TX_SUCCESS;
6123 retrycnt = status->framecnt - 1;
6125 txs.status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED;
6126 retrycnt = status->framecnt;
6130 txs.long_retries = retrycnt;
6131 ieee80211_ratectl_tx_complete(ni, &txs);
6135 bwn_dma_handle_txeof(struct bwn_mac *mac,
6136 const struct bwn_txstatus *status)
6138 struct bwn_dma *dma = &mac->mac_method.dma;
6139 struct bwn_dma_ring *dr;
6140 struct bwn_dmadesc_generic *desc;
6141 struct bwn_dmadesc_meta *meta;
6142 struct bwn_softc *sc = mac->mac_sc;
6145 BWN_ASSERT_LOCKED(sc);
6147 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot);
6149 device_printf(sc->sc_dev, "failed to parse cookie\n");
6152 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6155 KASSERT(slot >= 0 && slot < dr->dr_numslots,
6156 ("%s:%d: fail", __func__, __LINE__));
6157 dr->getdesc(dr, slot, &desc, &meta);
6159 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER)
6160 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap);
6161 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY)
6162 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap);
6164 if (meta->mt_islast) {
6165 KASSERT(meta->mt_m != NULL,
6166 ("%s:%d: fail", __func__, __LINE__));
6168 bwn_ratectl_tx_complete(meta->mt_ni, status);
6169 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0);
6173 KASSERT(meta->mt_m == NULL,
6174 ("%s:%d: fail", __func__, __LINE__));
6177 if (meta->mt_islast)
6179 slot = bwn_dma_nextslot(dr, slot);
6181 sc->sc_watchdog_timer = 0;
6183 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME,
6184 ("%s:%d: fail", __func__, __LINE__));
6190 bwn_pio_handle_txeof(struct bwn_mac *mac,
6191 const struct bwn_txstatus *status)
6193 struct bwn_pio_txqueue *tq;
6194 struct bwn_pio_txpkt *tp = NULL;
6195 struct bwn_softc *sc = mac->mac_sc;
6197 BWN_ASSERT_LOCKED(sc);
6199 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp);
6203 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4);
6206 if (tp->tp_ni != NULL) {
6208 * Do any tx complete callback. Note this must
6209 * be done before releasing the node reference.
6211 bwn_ratectl_tx_complete(tp->tp_ni, status);
6213 ieee80211_tx_complete(tp->tp_ni, tp->tp_m, 0);
6216 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list);
6218 sc->sc_watchdog_timer = 0;
6222 bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags)
6224 struct bwn_softc *sc = mac->mac_sc;
6225 struct bwn_phy *phy = &mac->mac_phy;
6226 struct ieee80211com *ic = &sc->sc_ic;
6228 bwn_txpwr_result_t result;
6232 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime))
6234 phy->nexttime = now + 2 * 1000;
6236 if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM &&
6237 sc->sc_board_info.board_type == BHND_BOARD_BU4306)
6240 if (phy->recalc_txpwr != NULL) {
6241 result = phy->recalc_txpwr(mac,
6242 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0);
6243 if (result == BWN_TXPWR_RES_DONE)
6245 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST,
6246 ("%s: fail", __func__));
6247 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__));
6249 ieee80211_runtask(ic, &mac->mac_txpower);
6254 bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset)
6257 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset));
6261 bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset)
6264 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset));
6268 bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value)
6271 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value);
6275 bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value)
6278 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value);
6282 bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate)
6286 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */
6288 return (BWN_OFDM_RATE_6MB);
6290 return (BWN_OFDM_RATE_9MB);
6292 return (BWN_OFDM_RATE_12MB);
6294 return (BWN_OFDM_RATE_18MB);
6296 return (BWN_OFDM_RATE_24MB);
6298 return (BWN_OFDM_RATE_36MB);
6300 return (BWN_OFDM_RATE_48MB);
6302 return (BWN_OFDM_RATE_54MB);
6303 /* CCK rates (NB: not IEEE std, device-specific) */
6305 return (BWN_CCK_RATE_1MB);
6307 return (BWN_CCK_RATE_2MB);
6309 return (BWN_CCK_RATE_5MB);
6311 return (BWN_CCK_RATE_11MB);
6314 device_printf(sc->sc_dev, "unsupported rate %d\n", rate);
6315 return (BWN_CCK_RATE_1MB);
6319 bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate)
6321 struct bwn_phy *phy = &mac->mac_phy;
6322 uint16_t control = 0;
6325 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */
6326 bw = BWN_TXH_PHY1_BW_20;
6328 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) {
6332 /* Figure out coding rate and modulation */
6333 /* XXX TODO: table-ize, for MCS transmit */
6334 /* Note: this is BWN_*_RATE values */
6336 case BWN_CCK_RATE_1MB:
6339 case BWN_CCK_RATE_2MB:
6342 case BWN_CCK_RATE_5MB:
6345 case BWN_CCK_RATE_11MB:
6348 case BWN_OFDM_RATE_6MB:
6349 control |= BWN_TXH_PHY1_CRATE_1_2;
6350 control |= BWN_TXH_PHY1_MODUL_BPSK;
6352 case BWN_OFDM_RATE_9MB:
6353 control |= BWN_TXH_PHY1_CRATE_3_4;
6354 control |= BWN_TXH_PHY1_MODUL_BPSK;
6356 case BWN_OFDM_RATE_12MB:
6357 control |= BWN_TXH_PHY1_CRATE_1_2;
6358 control |= BWN_TXH_PHY1_MODUL_QPSK;
6360 case BWN_OFDM_RATE_18MB:
6361 control |= BWN_TXH_PHY1_CRATE_3_4;
6362 control |= BWN_TXH_PHY1_MODUL_QPSK;
6364 case BWN_OFDM_RATE_24MB:
6365 control |= BWN_TXH_PHY1_CRATE_1_2;
6366 control |= BWN_TXH_PHY1_MODUL_QAM16;
6368 case BWN_OFDM_RATE_36MB:
6369 control |= BWN_TXH_PHY1_CRATE_3_4;
6370 control |= BWN_TXH_PHY1_MODUL_QAM16;
6372 case BWN_OFDM_RATE_48MB:
6373 control |= BWN_TXH_PHY1_CRATE_1_2;
6374 control |= BWN_TXH_PHY1_MODUL_QAM64;
6376 case BWN_OFDM_RATE_54MB:
6377 control |= BWN_TXH_PHY1_CRATE_3_4;
6378 control |= BWN_TXH_PHY1_MODUL_QAM64;
6383 control |= BWN_TXH_PHY1_MODE_SISO;
6390 bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni,
6391 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie)
6393 const struct bwn_phy *phy = &mac->mac_phy;
6394 struct bwn_softc *sc = mac->mac_sc;
6395 struct ieee80211_frame *wh;
6396 struct ieee80211_frame *protwh;
6397 const struct ieee80211_txparam *tp = ni->ni_txparms;
6398 struct ieee80211vap *vap = ni->ni_vap;
6399 struct ieee80211com *ic = &sc->sc_ic;
6403 uint32_t macctl = 0;
6404 int rts_rate, rts_rate_fb, ismcast, isshort, rix, type;
6405 uint16_t phyctl = 0;
6406 uint8_t rate, rate_fb;
6407 int fill_phy_ctl1 = 0;
6409 wh = mtod(m, struct ieee80211_frame *);
6410 memset(txhdr, 0, sizeof(*txhdr));
6412 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
6413 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
6414 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0;
6416 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP)
6417 || (phy->type == BWN_PHYTYPE_HT))
6423 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL))
6424 rate = rate_fb = tp->mgmtrate;
6426 rate = rate_fb = tp->mcastrate;
6427 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
6428 rate = rate_fb = tp->ucastrate;
6430 rix = ieee80211_ratectl_rate(ni, NULL, 0);
6431 rate = ni->ni_txrate;
6434 rate_fb = ni->ni_rates.rs_rates[rix - 1] &
6440 sc->sc_tx_rate = rate;
6442 /* Note: this maps the select ieee80211 rate to hardware rate */
6443 rate = bwn_ieeerate2hwrate(sc, rate);
6444 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb);
6446 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) :
6447 bwn_plcp_getcck(rate);
6448 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc));
6449 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN);
6451 /* XXX rate/rate_fb is the hardware rate */
6452 if ((rate_fb == rate) ||
6453 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) ||
6454 (*(u_int16_t *)wh->i_dur == htole16(0)))
6455 txhdr->dur_fb = *(u_int16_t *)wh->i_dur;
6457 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt,
6458 m->m_pkthdr.len, rate, isshort);
6460 /* XXX TX encryption */
6462 switch (mac->mac_fw.fw_hdr_format) {
6463 case BWN_FW_HDR_351:
6464 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp),
6465 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6467 case BWN_FW_HDR_410:
6468 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp),
6469 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6471 case BWN_FW_HDR_598:
6472 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp),
6473 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate);
6477 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb),
6478 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb);
6480 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM :
6482 txhdr->chan = phy->chan;
6483 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM :
6485 /* XXX preamble? obey net80211 */
6486 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6487 rate == BWN_CCK_RATE_11MB))
6488 phyctl |= BWN_TX_PHY_SHORTPRMBL;
6491 macctl |= BWN_TX_MAC_5GHZ;
6493 /* XXX TX antenna selection */
6495 switch (bwn_antenna_sanitize(mac, 0)) {
6497 phyctl |= BWN_TX_PHY_ANT01AUTO;
6500 phyctl |= BWN_TX_PHY_ANT0;
6503 phyctl |= BWN_TX_PHY_ANT1;
6506 phyctl |= BWN_TX_PHY_ANT2;
6509 phyctl |= BWN_TX_PHY_ANT3;
6512 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6516 macctl |= BWN_TX_MAC_ACK;
6518 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU);
6519 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) &&
6520 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold)
6521 macctl |= BWN_TX_MAC_LONGFRAME;
6523 if ((ic->ic_flags & IEEE80211_F_USEPROT) &&
6524 ic->ic_protmode != IEEE80211_PROT_NONE) {
6525 /* Note: don't fall back to CCK rates for 5G */
6527 rts_rate = BWN_CCK_RATE_1MB;
6529 rts_rate = BWN_OFDM_RATE_6MB;
6530 rts_rate_fb = bwn_get_fbrate(rts_rate);
6532 /* XXX 'rate' here is hardware rate now, not the net80211 rate */
6533 mprot = ieee80211_alloc_prot(ni, m, rate, ic->ic_protmode);
6534 if (mprot == NULL) {
6535 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, 1);
6536 device_printf(sc->sc_dev,
6537 "could not allocate mbuf for protection mode %d\n",
6542 switch (mac->mac_fw.fw_hdr_format) {
6543 case BWN_FW_HDR_351:
6544 prot_ptr = txhdr->body.r351.rts_frame;
6546 case BWN_FW_HDR_410:
6547 prot_ptr = txhdr->body.r410.rts_frame;
6549 case BWN_FW_HDR_598:
6550 prot_ptr = txhdr->body.r598.rts_frame;
6554 bcopy(mtod(mprot, uint8_t *), prot_ptr, mprot->m_pkthdr.len);
6557 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) {
6558 macctl |= BWN_TX_MAC_SEND_CTSTOSELF;
6559 len = sizeof(struct ieee80211_frame_cts);
6561 macctl |= BWN_TX_MAC_SEND_RTSCTS;
6562 len = sizeof(struct ieee80211_frame_rts);
6564 len += IEEE80211_CRC_LEN;
6566 switch (mac->mac_fw.fw_hdr_format) {
6567 case BWN_FW_HDR_351:
6568 bwn_plcp_genhdr((struct bwn_plcp4 *)
6569 &txhdr->body.r351.rts_plcp, len, rts_rate);
6571 case BWN_FW_HDR_410:
6572 bwn_plcp_genhdr((struct bwn_plcp4 *)
6573 &txhdr->body.r410.rts_plcp, len, rts_rate);
6575 case BWN_FW_HDR_598:
6576 bwn_plcp_genhdr((struct bwn_plcp4 *)
6577 &txhdr->body.r598.rts_plcp, len, rts_rate);
6581 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len,
6584 switch (mac->mac_fw.fw_hdr_format) {
6585 case BWN_FW_HDR_351:
6586 protwh = (struct ieee80211_frame *)
6587 &txhdr->body.r351.rts_frame;
6589 case BWN_FW_HDR_410:
6590 protwh = (struct ieee80211_frame *)
6591 &txhdr->body.r410.rts_frame;
6593 case BWN_FW_HDR_598:
6594 protwh = (struct ieee80211_frame *)
6595 &txhdr->body.r598.rts_frame;
6599 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur;
6601 if (BWN_ISOFDMRATE(rts_rate)) {
6602 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM;
6603 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate);
6605 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK;
6606 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate);
6608 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ?
6609 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK;
6611 if (fill_phy_ctl1) {
6612 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate));
6613 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb));
6617 if (fill_phy_ctl1) {
6618 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate));
6619 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb));
6622 switch (mac->mac_fw.fw_hdr_format) {
6623 case BWN_FW_HDR_351:
6624 txhdr->body.r351.cookie = htole16(cookie);
6626 case BWN_FW_HDR_410:
6627 txhdr->body.r410.cookie = htole16(cookie);
6629 case BWN_FW_HDR_598:
6630 txhdr->body.r598.cookie = htole16(cookie);
6634 txhdr->macctl = htole32(macctl);
6635 txhdr->phyctl = htole16(phyctl);
6640 if (ieee80211_radiotap_active_vap(vap)) {
6641 sc->sc_tx_th.wt_flags = 0;
6642 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
6643 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
6645 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB ||
6646 rate == BWN_CCK_RATE_11MB))
6647 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
6648 sc->sc_tx_th.wt_rate = rate;
6650 ieee80211_radiotap_tx(vap, m);
6657 bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets,
6661 uint8_t *raw = plcp->o.raw;
6663 if (BWN_ISOFDMRATE(rate)) {
6664 d = bwn_plcp_getofdm(rate);
6665 KASSERT(!(octets & 0xf000),
6666 ("%s:%d: fail", __func__, __LINE__));
6668 plcp->o.data = htole32(d);
6670 plen = octets * 16 / rate;
6671 if ((octets * 16 % rate) > 0) {
6673 if ((rate == BWN_CCK_RATE_11MB)
6674 && ((octets * 8 % 11) < 4)) {
6680 plcp->o.data |= htole32(plen << 16);
6681 raw[0] = bwn_plcp_getcck(rate);
6686 bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n)
6688 struct bwn_softc *sc = mac->mac_sc;
6693 if (mac->mac_phy.gmode)
6694 mask = sc->sc_ant2g;
6696 mask = sc->sc_ant5g;
6697 if (!(mask & (1 << (n - 1))))
6703 * Return a fallback rate for the given rate.
6705 * Note: Don't fall back from OFDM to CCK.
6708 bwn_get_fbrate(uint8_t bitrate)
6712 case BWN_CCK_RATE_1MB:
6713 return (BWN_CCK_RATE_1MB);
6714 case BWN_CCK_RATE_2MB:
6715 return (BWN_CCK_RATE_1MB);
6716 case BWN_CCK_RATE_5MB:
6717 return (BWN_CCK_RATE_2MB);
6718 case BWN_CCK_RATE_11MB:
6719 return (BWN_CCK_RATE_5MB);
6722 case BWN_OFDM_RATE_6MB:
6723 return (BWN_OFDM_RATE_6MB);
6724 case BWN_OFDM_RATE_9MB:
6725 return (BWN_OFDM_RATE_6MB);
6726 case BWN_OFDM_RATE_12MB:
6727 return (BWN_OFDM_RATE_9MB);
6728 case BWN_OFDM_RATE_18MB:
6729 return (BWN_OFDM_RATE_12MB);
6730 case BWN_OFDM_RATE_24MB:
6731 return (BWN_OFDM_RATE_18MB);
6732 case BWN_OFDM_RATE_36MB:
6733 return (BWN_OFDM_RATE_24MB);
6734 case BWN_OFDM_RATE_48MB:
6735 return (BWN_OFDM_RATE_36MB);
6736 case BWN_OFDM_RATE_54MB:
6737 return (BWN_OFDM_RATE_48MB);
6739 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6744 bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6745 uint32_t ctl, const void *_data, int len)
6747 struct bwn_softc *sc = mac->mac_sc;
6749 const uint8_t *data = _data;
6751 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 |
6752 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31;
6753 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6755 bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA,
6756 __DECONST(void *, data), (len & ~3));
6758 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 |
6759 BWN_PIO8_TXCTL_24_31);
6760 data = &(data[len - 1]);
6763 ctl |= BWN_PIO8_TXCTL_16_23;
6764 value |= (uint32_t)(*data) << 16;
6767 ctl |= BWN_PIO8_TXCTL_8_15;
6768 value |= (uint32_t)(*data) << 8;
6771 value |= (uint32_t)(*data);
6773 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl);
6774 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value);
6781 bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6782 uint16_t offset, uint32_t value)
6785 BWN_WRITE_4(mac, tq->tq_base + offset, value);
6789 bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6790 uint16_t ctl, const void *_data, int len)
6792 struct bwn_softc *sc = mac->mac_sc;
6793 const uint8_t *data = _data;
6795 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6796 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6798 bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA,
6799 __DECONST(void *, data), (len & ~1));
6801 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6802 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6803 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]);
6810 bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq,
6811 uint16_t ctl, struct mbuf *m0)
6816 struct mbuf *m = m0;
6818 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI;
6819 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6821 for (; m != NULL; m = m->m_next) {
6822 buf = mtod(m, const uint8_t *);
6823 for (i = 0; i < m->m_len; i++) {
6827 data |= (buf[i] << 8);
6828 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6833 if (m0->m_pkthdr.len % 2) {
6834 ctl &= ~BWN_PIO_TXCTL_WRITEHI;
6835 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl);
6836 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data);
6843 bwn_set_slot_time(struct bwn_mac *mac, uint16_t time)
6846 /* XXX should exit if 5GHz band .. */
6847 if (mac->mac_phy.type != BWN_PHYTYPE_G)
6850 BWN_WRITE_2(mac, 0x684, 510 + time);
6851 /* Disabled in Linux b43, can adversely effect performance */
6853 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time);
6857 static struct bwn_dma_ring *
6858 bwn_dma_select(struct bwn_mac *mac, uint8_t prio)
6861 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0)
6862 return (mac->mac_method.dma.wme[WME_AC_BE]);
6866 return (mac->mac_method.dma.wme[WME_AC_VO]);
6868 return (mac->mac_method.dma.wme[WME_AC_VI]);
6870 return (mac->mac_method.dma.wme[WME_AC_BE]);
6872 return (mac->mac_method.dma.wme[WME_AC_BK]);
6874 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__));
6879 bwn_dma_getslot(struct bwn_dma_ring *dr)
6883 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc);
6885 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__));
6886 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__));
6887 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__));
6889 slot = bwn_dma_nextslot(dr, dr->dr_curslot);
6890 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__));
6891 dr->dr_curslot = slot;
6897 static struct bwn_pio_txqueue *
6898 bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie,
6899 struct bwn_pio_txpkt **pack)
6901 struct bwn_pio *pio = &mac->mac_method.pio;
6902 struct bwn_pio_txqueue *tq = NULL;
6905 switch (cookie & 0xf000) {
6907 tq = &pio->wme[WME_AC_BK];
6910 tq = &pio->wme[WME_AC_BE];
6913 tq = &pio->wme[WME_AC_VI];
6916 tq = &pio->wme[WME_AC_VO];
6922 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__));
6925 index = (cookie & 0x0fff);
6926 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__));
6927 if (index >= N(tq->tq_pkts))
6929 *pack = &tq->tq_pkts[index];
6930 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__));
6935 bwn_txpwr(void *arg, int npending)
6937 struct bwn_mac *mac = arg;
6938 struct bwn_softc *sc;
6946 if (mac->mac_status >= BWN_MAC_STATUS_STARTED &&
6947 mac->mac_phy.set_txpwr != NULL)
6948 mac->mac_phy.set_txpwr(mac);
6953 bwn_task_15s(struct bwn_mac *mac)
6957 if (mac->mac_fw.opensource) {
6958 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG);
6960 bwn_restart(mac, "fw watchdog");
6963 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1);
6965 if (mac->mac_phy.task_15s)
6966 mac->mac_phy.task_15s(mac);
6968 mac->mac_phy.txerrors = BWN_TXERROR_MAX;
6972 bwn_task_30s(struct bwn_mac *mac)
6975 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running)
6977 mac->mac_noise.noi_running = 1;
6978 mac->mac_noise.noi_nsamples = 0;
6980 bwn_noise_gensample(mac);
6984 bwn_task_60s(struct bwn_mac *mac)
6987 if (mac->mac_phy.task_60s)
6988 mac->mac_phy.task_60s(mac);
6989 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME);
6993 bwn_tasks(void *arg)
6995 struct bwn_mac *mac = arg;
6996 struct bwn_softc *sc = mac->mac_sc;
6998 BWN_ASSERT_LOCKED(sc);
6999 if (mac->mac_status != BWN_MAC_STATUS_STARTED)
7002 if (mac->mac_task_state % 4 == 0)
7004 if (mac->mac_task_state % 2 == 0)
7008 mac->mac_task_state++;
7009 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac);
7013 bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a)
7015 struct bwn_softc *sc = mac->mac_sc;
7017 KASSERT(a == 0, ("not support APHY\n"));
7019 switch (plcp->o.raw[0] & 0xf) {
7021 return (BWN_OFDM_RATE_6MB);
7023 return (BWN_OFDM_RATE_9MB);
7025 return (BWN_OFDM_RATE_12MB);
7027 return (BWN_OFDM_RATE_18MB);
7029 return (BWN_OFDM_RATE_24MB);
7031 return (BWN_OFDM_RATE_36MB);
7033 return (BWN_OFDM_RATE_48MB);
7035 return (BWN_OFDM_RATE_54MB);
7037 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n",
7038 plcp->o.raw[0] & 0xf);
7043 bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp)
7045 struct bwn_softc *sc = mac->mac_sc;
7047 switch (plcp->o.raw[0]) {
7049 return (BWN_CCK_RATE_1MB);
7051 return (BWN_CCK_RATE_2MB);
7053 return (BWN_CCK_RATE_5MB);
7055 return (BWN_CCK_RATE_11MB);
7057 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]);
7062 bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m,
7063 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate,
7064 int rssi, int noise)
7066 struct bwn_softc *sc = mac->mac_sc;
7067 const struct ieee80211_frame_min *wh;
7069 uint16_t low_mactime_now;
7072 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL)
7073 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
7075 wh = mtod(m, const struct ieee80211_frame_min *);
7076 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED)
7077 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
7079 bwn_tsf_read(mac, &tsf);
7080 low_mactime_now = tsf;
7081 tsf = tsf & ~0xffffULL;
7083 switch (mac->mac_fw.fw_hdr_format) {
7084 case BWN_FW_HDR_351:
7085 case BWN_FW_HDR_410:
7086 mt = le16toh(rxhdr->ps4.r351.mac_time);
7088 case BWN_FW_HDR_598:
7089 mt = le16toh(rxhdr->ps4.r598.mac_time);
7094 if (low_mactime_now < mt)
7097 sc->sc_rx_th.wr_tsf = tsf;
7098 sc->sc_rx_th.wr_rate = rate;
7099 sc->sc_rx_th.wr_antsignal = rssi;
7100 sc->sc_rx_th.wr_antnoise = noise;
7104 bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf)
7108 KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3,
7109 ("%s:%d: fail", __func__, __LINE__));
7111 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW);
7112 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH);
7119 bwn_dma_attach(struct bwn_mac *mac)
7121 struct bwn_dma *dma;
7122 struct bwn_softc *sc;
7123 struct bhnd_dma_translation *dt, dma_translation;
7124 bhnd_addr_t addrext_req;
7127 u_int addrext_shift, addr_width;
7130 dma = &mac->mac_method.dma;
7134 if (sc->sc_quirks & BWN_QUIRK_NODMA)
7137 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__));
7139 /* Use the DMA engine's maximum host address width to determine the
7140 * addrext constraints, and supported device address width. */
7141 switch (mac->mac_dmatype) {
7142 case BHND_DMA_ADDR_30BIT:
7143 /* 32-bit engine without addrext support */
7147 /* We can address the full 32-bit device address space */
7148 addr_width = BHND_DMA_ADDR_32BIT;
7151 case BHND_DMA_ADDR_32BIT:
7152 /* 32-bit engine with addrext support */
7153 addrext_req = BWN_DMA32_ADDREXT_MASK;
7154 addrext_shift = BWN_DMA32_ADDREXT_SHIFT;
7155 addr_width = BHND_DMA_ADDR_32BIT;
7158 case BHND_DMA_ADDR_64BIT:
7159 /* 64-bit engine with addrext support */
7160 addrext_req = BWN_DMA64_ADDREXT_MASK;
7161 addrext_shift = BWN_DMA64_ADDREXT_SHIFT;
7162 addr_width = BHND_DMA_ADDR_64BIT;
7166 device_printf(sc->sc_dev, "unsupported DMA address width: %d\n",
7172 /* Fetch our device->host DMA translation and tag */
7173 error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat,
7176 device_printf(sc->sc_dev, "error fetching DMA translation: "
7181 /* Verify that our DMA engine's addrext constraints are compatible with
7182 * our DMA translation */
7183 if (addrext_req != 0x0 &&
7184 (dma_translation.addrext_mask & addrext_req) != addrext_req)
7186 device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible "
7187 "with device addrext mask %#jx, disabling extended address "
7188 "support\n", (uintmax_t)dma_translation.addrext_mask,
7189 (uintmax_t)addrext_req);
7195 /* Apply our addrext translation constraint */
7196 dma_translation.addrext_mask = addrext_req;
7198 /* Initialize our DMA engine configuration */
7199 mac->mac_flags |= BWN_MAC_FLAG_DMA;
7201 dma->addrext_shift = addrext_shift;
7202 dma->translation = dma_translation;
7204 dt = &dma->translation;
7206 /* Dermine our translation's maximum supported address */
7207 lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR);
7210 * Create top level DMA tag
7212 error = bus_dma_tag_create(dmat, /* parent */
7213 BWN_ALIGN, 0, /* alignment, bounds */
7214 lowaddr, /* lowaddr */
7215 BUS_SPACE_MAXADDR, /* highaddr */
7216 NULL, NULL, /* filter, filterarg */
7217 BUS_SPACE_MAXSIZE, /* maxsize */
7218 BUS_SPACE_UNRESTRICTED, /* nsegments */
7219 BUS_SPACE_MAXSIZE, /* maxsegsize */
7221 NULL, NULL, /* lockfunc, lockarg */
7224 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
7229 * Create TX/RX mbuf DMA tag
7231 error = bus_dma_tag_create(dma->parent_dtag,
7239 BUS_SPACE_MAXSIZE_32BIT,
7244 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7247 error = bus_dma_tag_create(dma->parent_dtag,
7255 BUS_SPACE_MAXSIZE_32BIT,
7260 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
7264 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1);
7265 if (!dma->wme[WME_AC_BK])
7268 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1);
7269 if (!dma->wme[WME_AC_BE])
7272 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1);
7273 if (!dma->wme[WME_AC_VI])
7276 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1);
7277 if (!dma->wme[WME_AC_VO])
7280 dma->mcast = bwn_dma_ringsetup(mac, 4, 1);
7283 dma->rx = bwn_dma_ringsetup(mac, 0, 0);
7289 fail7: bwn_dma_ringfree(&dma->mcast);
7290 fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]);
7291 fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]);
7292 fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]);
7293 fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]);
7294 fail2: bus_dma_tag_destroy(dma->txbuf_dtag);
7295 fail1: bus_dma_tag_destroy(dma->rxbuf_dtag);
7296 fail0: bus_dma_tag_destroy(dma->parent_dtag);
7300 static struct bwn_dma_ring *
7301 bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status,
7302 uint16_t cookie, int *slot)
7304 struct bwn_dma *dma = &mac->mac_method.dma;
7305 struct bwn_dma_ring *dr;
7306 struct bwn_softc *sc = mac->mac_sc;
7308 BWN_ASSERT_LOCKED(mac->mac_sc);
7310 switch (cookie & 0xf000) {
7312 dr = dma->wme[WME_AC_BK];
7315 dr = dma->wme[WME_AC_BE];
7318 dr = dma->wme[WME_AC_VI];
7321 dr = dma->wme[WME_AC_VO];
7329 ("invalid cookie value %d", cookie & 0xf000));
7331 *slot = (cookie & 0x0fff);
7332 if (*slot < 0 || *slot >= dr->dr_numslots) {
7334 * XXX FIXME: sometimes H/W returns TX DONE events duplicately
7335 * that it occurs events which have same H/W sequence numbers.
7336 * When it's occurred just prints a WARNING msgs and ignores.
7338 KASSERT(status->seq == dma->lastseq,
7339 ("%s:%d: fail", __func__, __LINE__));
7340 device_printf(sc->sc_dev,
7341 "out of slot ranges (0 < %d < %d)\n", *slot,
7345 dma->lastseq = status->seq;
7350 bwn_dma_stop(struct bwn_mac *mac)
7352 struct bwn_dma *dma;
7354 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0)
7356 dma = &mac->mac_method.dma;
7358 bwn_dma_ringstop(&dma->rx);
7359 bwn_dma_ringstop(&dma->wme[WME_AC_BK]);
7360 bwn_dma_ringstop(&dma->wme[WME_AC_BE]);
7361 bwn_dma_ringstop(&dma->wme[WME_AC_VI]);
7362 bwn_dma_ringstop(&dma->wme[WME_AC_VO]);
7363 bwn_dma_ringstop(&dma->mcast);
7367 bwn_dma_ringstop(struct bwn_dma_ring **dr)
7373 bwn_dma_cleanup(*dr);
7377 bwn_pio_stop(struct bwn_mac *mac)
7379 struct bwn_pio *pio;
7381 if (mac->mac_flags & BWN_MAC_FLAG_DMA)
7383 pio = &mac->mac_method.pio;
7385 bwn_destroy_queue_tx(&pio->mcast);
7386 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]);
7387 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]);
7388 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]);
7389 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]);
7393 bwn_led_attach(struct bwn_mac *mac)
7395 struct bwn_softc *sc = mac->mac_sc;
7396 const uint8_t *led_act = NULL;
7400 sc->sc_led_idle = (2350 * hz) / 1000;
7401 sc->sc_led_blink = 1;
7403 for (i = 0; i < N(bwn_vendor_led_act); ++i) {
7404 if (sc->sc_board_info.board_vendor ==
7405 bwn_vendor_led_act[i].vid) {
7406 led_act = bwn_vendor_led_act[i].led_act;
7410 if (led_act == NULL)
7411 led_act = bwn_default_led_act;
7413 _Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX,
7414 "invalid NVRAM variable name array");
7416 for (i = 0; i < BWN_LED_MAX; ++i) {
7417 struct bwn_led *led;
7420 led = &sc->sc_leds[i];
7422 KASSERT(i < nitems(bwn_led_vars), ("unknown LED index"));
7423 error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i],
7426 if (error != ENOENT) {
7427 device_printf(sc->sc_dev, "NVRAM variable %s "
7428 "unreadable: %d", bwn_led_vars[i], error);
7432 /* Not found; use default */
7433 led->led_act = led_act[i];
7435 if (val & BWN_LED_ACT_LOW)
7436 led->led_flags |= BWN_LED_F_ACTLOW;
7437 led->led_act = val & BWN_LED_ACT_MASK;
7439 led->led_mask = (1 << i);
7441 if (led->led_act == BWN_LED_ACT_BLINK_SLOW ||
7442 led->led_act == BWN_LED_ACT_BLINK_POLL ||
7443 led->led_act == BWN_LED_ACT_BLINK) {
7444 led->led_flags |= BWN_LED_F_BLINK;
7445 if (led->led_act == BWN_LED_ACT_BLINK_POLL)
7446 led->led_flags |= BWN_LED_F_POLLABLE;
7447 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW)
7448 led->led_flags |= BWN_LED_F_SLOW;
7450 if (sc->sc_blink_led == NULL) {
7451 sc->sc_blink_led = led;
7452 if (led->led_flags & BWN_LED_F_SLOW)
7453 BWN_LED_SLOWDOWN(sc->sc_led_idle);
7457 DPRINTF(sc, BWN_DEBUG_LED,
7458 "%dth led, act %d, lowact %d\n", i,
7459 led->led_act, led->led_flags & BWN_LED_F_ACTLOW);
7461 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
7466 static __inline uint16_t
7467 bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on)
7470 if (led->led_flags & BWN_LED_F_ACTLOW)
7473 val |= led->led_mask;
7475 val &= ~led->led_mask;
7480 bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate)
7482 struct bwn_softc *sc = mac->mac_sc;
7483 struct ieee80211com *ic = &sc->sc_ic;
7487 if (nstate == IEEE80211_S_INIT) {
7488 callout_stop(&sc->sc_led_blink_ch);
7489 sc->sc_led_blinking = 0;
7492 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0)
7495 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7496 for (i = 0; i < BWN_LED_MAX; ++i) {
7497 struct bwn_led *led = &sc->sc_leds[i];
7500 if (led->led_act == BWN_LED_ACT_UNKN ||
7501 led->led_act == BWN_LED_ACT_NULL)
7504 if ((led->led_flags & BWN_LED_F_BLINK) &&
7505 nstate != IEEE80211_S_INIT)
7508 switch (led->led_act) {
7509 case BWN_LED_ACT_ON: /* Always on */
7512 case BWN_LED_ACT_OFF: /* Always off */
7513 case BWN_LED_ACT_5GHZ: /* TODO: 11A */
7519 case IEEE80211_S_INIT:
7522 case IEEE80211_S_RUN:
7523 if (led->led_act == BWN_LED_ACT_11G &&
7524 ic->ic_curmode != IEEE80211_MODE_11G)
7528 if (led->led_act == BWN_LED_ACT_ASSOC)
7535 val = bwn_led_onoff(led, val, on);
7537 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7541 bwn_led_event(struct bwn_mac *mac, int event)
7543 struct bwn_softc *sc = mac->mac_sc;
7544 struct bwn_led *led = sc->sc_blink_led;
7547 if (event == BWN_LED_EVENT_POLL) {
7548 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0)
7550 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
7554 sc->sc_led_ticks = ticks;
7555 if (sc->sc_led_blinking)
7559 case BWN_LED_EVENT_RX:
7560 rate = sc->sc_rx_rate;
7562 case BWN_LED_EVENT_TX:
7563 rate = sc->sc_tx_rate;
7565 case BWN_LED_EVENT_POLL:
7569 panic("unknown LED event %d\n", event);
7572 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur,
7573 bwn_led_duration[rate].off_dur);
7577 bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur)
7579 struct bwn_softc *sc = mac->mac_sc;
7580 struct bwn_led *led = sc->sc_blink_led;
7583 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7584 val = bwn_led_onoff(led, val, 1);
7585 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7587 if (led->led_flags & BWN_LED_F_SLOW) {
7588 BWN_LED_SLOWDOWN(on_dur);
7589 BWN_LED_SLOWDOWN(off_dur);
7592 sc->sc_led_blinking = 1;
7593 sc->sc_led_blink_offdur = off_dur;
7595 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac);
7599 bwn_led_blink_next(void *arg)
7601 struct bwn_mac *mac = arg;
7602 struct bwn_softc *sc = mac->mac_sc;
7605 val = BWN_READ_2(mac, BWN_GPIO_CONTROL);
7606 val = bwn_led_onoff(sc->sc_blink_led, val, 0);
7607 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val);
7609 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
7610 bwn_led_blink_end, mac);
7614 bwn_led_blink_end(void *arg)
7616 struct bwn_mac *mac = arg;
7617 struct bwn_softc *sc = mac->mac_sc;
7619 sc->sc_led_blinking = 0;
7623 bwn_suspend(device_t dev)
7625 struct bwn_softc *sc = device_get_softc(dev);
7634 bwn_resume(device_t dev)
7636 struct bwn_softc *sc = device_get_softc(dev);
7637 int error = EDOOFUS;
7640 if (sc->sc_ic.ic_nrunning > 0)
7641 error = bwn_init(sc);
7644 ieee80211_start_all(&sc->sc_ic);
7649 bwn_rfswitch(void *arg)
7651 struct bwn_softc *sc = arg;
7652 struct bwn_mac *mac = sc->sc_curmac;
7653 int cur = 0, prev = 0;
7655 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED,
7656 ("%s: invalid MAC status %d", __func__, mac->mac_status));
7658 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP
7659 || mac->mac_phy.type == BWN_PHYTYPE_N) {
7660 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI)
7661 & BWN_RF_HWENABLED_HI_MASK))
7664 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO)
7665 & BWN_RF_HWENABLED_LO_MASK)
7669 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)
7672 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n",
7673 __func__, cur, prev);
7677 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON;
7679 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON;
7681 device_printf(sc->sc_dev,
7682 "status of RF switch is changed to %s\n",
7683 cur ? "ON" : "OFF");
7684 if (cur != mac->mac_phy.rf_on) {
7688 bwn_rf_turnoff(mac);
7692 callout_schedule(&sc->sc_rfswitch_ch, hz);
7696 bwn_sysctl_node(struct bwn_softc *sc)
7698 device_t dev = sc->sc_dev;
7699 struct bwn_mac *mac;
7700 struct bwn_stats *stats;
7702 /* XXX assume that count of MAC is only 1. */
7704 if ((mac = sc->sc_curmac) == NULL)
7706 stats = &mac->mac_stats;
7708 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7709 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7710 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level");
7711 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7712 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7713 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS");
7714 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
7715 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7716 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send");
7719 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
7720 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
7721 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
7725 static device_method_t bwn_methods[] = {
7726 /* Device interface */
7727 DEVMETHOD(device_probe, bwn_probe),
7728 DEVMETHOD(device_attach, bwn_attach),
7729 DEVMETHOD(device_detach, bwn_detach),
7730 DEVMETHOD(device_suspend, bwn_suspend),
7731 DEVMETHOD(device_resume, bwn_resume),
7734 static driver_t bwn_driver = {
7737 sizeof(struct bwn_softc)
7739 static devclass_t bwn_devclass;
7740 DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0);
7741 MODULE_DEPEND(bwn, bhnd, 1, 1, 1);
7742 MODULE_DEPEND(bwn, gpiobus, 1, 1, 1);
7743 MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */
7744 MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */
7745 MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1);
7746 MODULE_VERSION(bwn, 1);