2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/kernel.h>
37 #include <sys/systm.h>
39 #include <sys/mutex.h>
41 #include <sys/module.h>
42 #include <sys/endian.h>
43 #include <sys/types.h>
44 #include <sys/malloc.h>
48 #include <sys/socket.h>
49 #include <sys/sockio.h>
50 #include <sys/sysctl.h>
52 #include <sys/bitstring.h>
53 #include <sys/limits.h>
54 #include <sys/queue.h>
55 #include <sys/taskqueue.h>
59 #include <net/if_types.h>
60 #include <net/if_arp.h>
61 #include <net/ethernet.h>
62 #include <net/if_dl.h>
63 #include <net/if_var.h>
64 #include <net/if_media.h>
65 #include <net/if_vlan_var.h>
68 #include <netinet/in.h>
69 #include <netinet/ip.h>
70 #include <netinet/ip6.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
74 #include <dev/pci/pcireg.h>
75 #include <dev/pci/pcivar.h>
77 #include <machine/atomic.h>
78 #include <machine/resource.h>
79 #include <machine/endian.h>
80 #include <machine/bus.h>
81 #include <machine/in_cksum.h>
83 #include "device_if.h"
87 #if _BYTE_ORDER == _LITTLE_ENDIAN
91 #ifndef __LITTLE_ENDIAN
92 #define __LITTLE_ENDIAN
96 #else /* _BIG_ENDIAN */
104 #undef __LITTLE_ENDIAN
107 #include "ecore_mfw_req.h"
108 #include "ecore_fw_defs.h"
109 #include "ecore_hsi.h"
110 #include "ecore_reg.h"
112 #include "bxe_stats.h"
114 #include "bxe_elink.h"
116 #define VF_MAC_CREDIT_CNT 0
117 #define VF_VLAN_CREDIT_CNT (0)
119 #if __FreeBSD_version < 800054
120 #if defined(__i386__) || defined(__amd64__)
121 #define mb() __asm volatile("mfence;" : : : "memory")
122 #define wmb() __asm volatile("sfence;" : : : "memory")
123 #define rmb() __asm volatile("lfence;" : : : "memory")
124 static __inline void prefetch(void *x)
126 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
136 #if __FreeBSD_version >= 1000000
137 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
138 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
139 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
140 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
141 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
142 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
143 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
144 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
148 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
151 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
154 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
157 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
164 while (x >>= 1) log++;
167 #define ilog2(x) bxe_ilog2(x)
170 #include "ecore_sp.h"
172 #define BRCM_VENDORID 0x14e4
173 #define QLOGIC_VENDORID 0x1077
174 #define PCI_ANY_ID (uint16_t)(~0U)
176 struct bxe_device_type
185 #define BCM_PAGE_SHIFT 12
186 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
187 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
188 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
190 #if BCM_PAGE_SIZE != 4096
191 #error Page sizes other than 4KB are unsupported!
194 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
195 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
196 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
198 #define U64_LO(addr) ((uint32_t)(addr))
199 #define U64_HI(addr) (0)
201 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
203 #define SET_FLAG(value, mask, flag) \
205 (value) &= ~(mask); \
206 (value) |= ((flag) << (mask##_SHIFT)); \
209 #define GET_FLAG(value, mask) \
210 (((value) & (mask)) >> (mask##_SHIFT))
212 #define GET_FIELD(value, fname) \
213 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
215 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */
216 #define BXE_TSO_MAX_SEGMENTS 32
217 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
218 #define BXE_TSO_MAX_SEG_SIZE 4096
220 /* dropless fc FW/HW related params */
221 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
222 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
223 ETH_MAX_AGGREGATION_QUEUES_E1 : \
224 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
225 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
226 #define FW_PREFETCH_CNT 16
227 #define DROPLESS_FC_HEADROOM 100
233 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */
234 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
235 #define RX_SGE_NEXT_PAGE_DESC_CNT 2
236 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
237 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
238 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
239 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
240 #define RX_SGE_MAX (RX_SGE_TOTAL - 1)
241 #define RX_SGE(x) ((x) & RX_SGE_MAX)
243 #define RX_SGE_NEXT(x) \
244 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
245 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
247 #define RX_SGE_MASK_ELEM_SZ 64
248 #define RX_SGE_MASK_ELEM_SHIFT 6
249 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
252 * Creates a bitmask of all ones in less significant bits.
253 * idx - index of the most significant bit in the created mask.
255 #define RX_SGE_ONES_MASK(idx) \
256 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
257 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
259 /* Number of uint64_t elements in SGE mask array. */
260 #define RX_SGE_MASK_LEN \
261 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
262 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
263 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
266 * dropless fc calculations for SGEs
267 * Number of required SGEs is the sum of two:
268 * 1. Number of possible opened aggregations (next packet for
269 * these aggregations will probably consume SGE immidiatelly)
270 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
271 * after placement on BD for new TPA aggregation)
272 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page
274 #define NUM_SGE_REQ(sc) \
275 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
276 #define NUM_SGE_PG_REQ(sc) \
277 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
278 #define SGE_TH_LO(sc) \
279 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
280 #define SGE_TH_HI(sc) \
281 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
283 #define PAGES_PER_SGE_SHIFT 0
284 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
285 #define SGE_PAGE_SIZE BCM_PAGE_SIZE
286 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
287 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
288 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
289 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
295 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */
296 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
297 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
298 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
299 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
300 #define TX_BD_MAX (TX_BD_TOTAL - 1)
302 #define TX_BD_NEXT(x) \
303 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
304 ((x) + 2) : ((x) + 1))
305 #define TX_BD(x) ((x) & TX_BD_MAX)
306 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
307 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
310 * Trigger pending transmits when the number of available BDs is greater
311 * than 1/8 of the total number of usable BDs.
313 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
314 #define BXE_TX_TIMEOUT 5
320 #define RX_BD_NUM_PAGES 8 /* power of 2 */
321 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
322 #define RX_BD_NEXT_PAGE_DESC_CNT 2
323 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
324 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
325 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
326 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
327 #define RX_BD_MAX (RX_BD_TOTAL - 1)
329 #define RX_BD_NEXT(x) \
330 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
331 ((x) + 3) : ((x) + 1))
332 #define RX_BD(x) ((x) & RX_BD_MAX)
333 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
334 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
337 * dropless fc calculations for BDs
338 * Number of BDs should be as number of buffers in BRB:
339 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
340 * "next" elements on each page
342 #define NUM_BD_REQ(sc) \
344 #define NUM_BD_PG_REQ(sc) \
345 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
346 #define BD_TH_LO(sc) \
348 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
350 #define BD_TH_HI(sc) \
351 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
352 #define MIN_RX_AVAIL(sc) \
353 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
354 #define MIN_RX_SIZE_TPA_HW(sc) \
355 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
356 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
357 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
358 #define MIN_RX_SIZE_TPA(sc) \
359 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
360 #define MIN_RX_SIZE_NONTPA(sc) \
361 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
368 * As long as CQE is X times bigger than BD entry we have to allocate X times
369 * more pages for CQ ring in order to keep it balanced with BD ring
371 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
372 sizeof(struct eth_rx_bd))
373 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */
374 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
375 #define RCQ_NEXT_PAGE_DESC_CNT 1
376 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
377 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
378 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
379 #define RCQ_MAX (RCQ_TOTAL - 1)
381 #define RCQ_NEXT(x) \
382 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
383 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
384 #define RCQ(x) ((x) & RCQ_MAX)
385 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
386 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
389 * dropless fc calculations for RCQs
390 * Number of RCQs should be as number of buffers in BRB:
391 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
392 * "next" elements on each page
394 #define NUM_RCQ_REQ(sc) \
396 #define NUM_RCQ_PG_REQ(sc) \
397 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
398 #define RCQ_TH_LO(sc) \
400 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
402 #define RCQ_TH_HI(sc) \
403 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
405 /* This is needed for determening of last_max */
406 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
408 #define __SGE_MASK_SET_BIT(el, bit) \
410 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
413 #define __SGE_MASK_CLEAR_BIT(el, bit) \
415 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
418 #define SGE_MASK_SET_BIT(fp, idx) \
419 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
420 ((idx) & RX_SGE_MASK_ELEM_MASK))
422 #define SGE_MASK_CLEAR_BIT(fp, idx) \
423 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
424 ((idx) & RX_SGE_MASK_ELEM_MASK))
426 /* Load / Unload modes */
427 #define LOAD_NORMAL 0
430 #define LOAD_LOOPBACK_EXT 3
431 #define UNLOAD_NORMAL 0
432 #define UNLOAD_CLOSE 1
433 #define UNLOAD_RECOVERY 2
435 /* Some constants... */
436 //#define MAX_PATH_NUM 2
437 //#define E2_MAX_NUM_OF_VFS 64
438 //#define E1H_FUNC_MAX 8
439 //#define E2_FUNC_MAX 4 /* per path */
440 #define MAX_VNIC_NUM 4
441 #define MAX_FUNC_NUM 8 /* common to all chips */
442 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
443 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
444 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
446 #define ILT_NUM_PAGE_ENTRIES 3072
448 * 57710/11 we use whole table since we have 8 functions.
449 * 57712 we have only 4 functions, but use same size per func, so only half
450 * of the table is used.
452 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
453 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
455 * the phys address is shifted right 12 bits and has an added
456 * 1=valid bit added to the 53rd bit
457 * then since this is a wide register(TM)
458 * we split it into two 32 bit writes
460 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
461 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
463 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
465 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
466 #define ETH_MIN_PACKET_SIZE 60
467 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
468 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
469 /* TCP with Timestamp Option (32) + IPv6 (40) */
470 #define ETH_MAX_TPA_HEADER_SIZE 72
472 /* max supported alignment is 256 (8 shift) */
473 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8)
474 #define BXE_RX_ALIGN_SHIFT 8
475 /* FW uses 2 cache lines alignment for start packet and size */
476 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
477 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
479 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */
482 struct resource *resource;
485 bus_space_handle_t handle;
490 struct resource *resource;
495 /* Used to manage DMA allocations. */
497 struct bxe_softc *sc;
502 bus_dma_segment_t seg;
508 /* attn group wiring */
509 #define MAX_DYNAMIC_ATTN_GRPS 8
523 union bxe_host_hc_status_block {
524 /* pointer to fp status block e2 */
525 struct host_hc_status_block_e2 *e2_sb;
526 /* pointer to fp status block e1x */
527 struct host_hc_status_block_e1x *e1x_sb;
531 struct doorbell_set_prod data;
535 struct bxe_sw_tx_bd {
540 /* set on the first BD descriptor when there is a split BD */
541 #define BXE_TSO_SPLIT_BD (1 << 0)
544 struct bxe_sw_rx_bd {
549 struct bxe_sw_tpa_info {
550 struct bxe_sw_rx_bd bd;
551 bus_dma_segment_t seg;
553 #define BXE_TPA_STATE_START 1
554 #define BXE_TPA_STATE_STOP 2
555 uint8_t placement_offset;
556 uint16_t parsing_flags;
562 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
563 * instances of the fastpath structure when using multiple queues.
565 struct bxe_fastpath {
566 /* pointer back to parent structure */
567 struct bxe_softc *sc;
570 char tx_mtx_name[32];
572 char rx_mtx_name[32];
574 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
575 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
576 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
577 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx)
579 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
580 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
581 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
584 struct bxe_dma sb_dma;
585 union bxe_host_hc_status_block status_block;
587 /* transmit chain (tx bds) */
588 struct bxe_dma tx_dma;
589 union eth_tx_bd_types *tx_chain;
591 /* receive chain (rx bds) */
592 struct bxe_dma rx_dma;
593 struct eth_rx_bd *rx_chain;
595 /* receive completion queue chain (rcq bds) */
596 struct bxe_dma rcq_dma;
597 union eth_rx_cqe *rcq_chain;
599 /* receive scatter/gather entry chain (for TPA) */
600 struct bxe_dma rx_sge_dma;
601 struct eth_rx_sge *rx_sge_chain;
604 bus_dma_tag_t tx_mbuf_tag;
605 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL];
608 bus_dma_tag_t rx_mbuf_tag;
609 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL];
610 bus_dmamap_t rx_mbuf_spare_map;
613 bus_dma_tag_t rx_sge_mbuf_tag;
614 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL];
615 bus_dmamap_t rx_sge_mbuf_spare_map;
617 /* rx tpa mbufs (use the larger size for TPA queue length) */
618 int tpa_enable; /* disabled per fastpath upon error */
619 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
620 bus_dmamap_t rx_tpa_info_mbuf_spare_map;
621 uint64_t rx_tpa_queue_used;
623 uint16_t *sb_index_values;
624 uint16_t *sb_running_index;
625 uint32_t ustorm_rx_prods_offset;
627 uint8_t igu_sb_id; /* status block number in HW */
628 uint8_t fw_sb_id; /* status block number in FW */
630 uint32_t rx_buf_size;
634 #define BXE_FP_STATE_CLOSED 0x01
635 #define BXE_FP_STATE_IRQ 0x02
636 #define BXE_FP_STATE_OPENING 0x04
637 #define BXE_FP_STATE_OPEN 0x08
638 #define BXE_FP_STATE_HALTING 0x10
639 #define BXE_FP_STATE_HALTED 0x20
641 /* reference back to this fastpath queue number */
642 uint8_t index; /* this is also the 'cid' */
643 #define FP_IDX(fp) (fp->index)
645 /* interrupt taskqueue (fast) */
647 struct taskqueue *tq;
651 struct timeout_task tx_timeout_task;
653 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
655 #define FP_CL_ID(fp) (fp->cl_id)
660 /* driver copy of the receive buffer descriptor prod/cons indices */
664 /* driver copy of the receive completion queue prod/cons indices */
668 union bxe_db_prod tx_db;
670 /* Transmit packet producer index (used in eth_tx_bd). */
671 uint16_t tx_pkt_prod;
672 uint16_t tx_pkt_cons;
674 /* Transmit buffer descriptor producer index. */
678 uint64_t sge_mask[RX_SGE_MASK_LEN];
679 uint16_t rx_sge_prod;
681 struct tstorm_per_queue_stats old_tclient;
682 struct ustorm_per_queue_stats old_uclient;
683 struct xstorm_per_queue_stats old_xclient;
684 struct bxe_eth_q_stats eth_q_stats;
685 struct bxe_eth_q_stats_old eth_q_stats_old;
687 /* Pointer to the receive consumer in the status block */
688 uint16_t *rx_cq_cons_sb;
690 /* Pointer to the transmit consumer in the status block */
691 uint16_t *tx_cons_sb;
693 /* transmit timeout until chip reset */
696 /* Free/used buffer descriptor counters. */
697 //uint16_t used_tx_bd;
699 /* Last maximal completed SGE */
700 uint16_t last_max_sge;
702 //uint16_t rx_sge_free_idx;
706 #if __FreeBSD_version >= 800000
707 #define BXE_BR_SIZE 4096
708 struct buf_ring *tx_br;
710 }; /* struct bxe_fastpath */
713 #define BXE_MAX_NUM_OF_VFS 64
714 #define BXE_VF_CID_WND 0
715 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
716 #define BXE_CLIENTS_PER_VF 1
717 #define BXE_FIRST_VF_CID 256
718 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
719 #define BXE_VF_ID_INVALID 0xFF
720 #define IS_SRIOV(sc) 0
722 #define GET_NUM_VFS_PER_PATH(sc) 0
723 #define GET_NUM_VFS_PER_PF(sc) 0
725 /* maximum number of fast-path interrupt contexts */
726 #define FP_SB_MAX_E1x 16
727 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
730 struct eth_context eth;
734 /* CDU host DB constants */
735 #define CDU_ILT_PAGE_SZ_HW 2
736 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
737 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
739 #define CNIC_ISCSI_CID_MAX 256
740 #define CNIC_FCOE_CID_MAX 2048
741 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
742 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
744 #define QM_ILT_PAGE_SZ_HW 0
745 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
746 #define QM_CID_ROUND 1024
748 /* TM (timers) host DB constants */
749 #define TM_ILT_PAGE_SZ_HW 0
750 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
751 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
752 #define TM_CONN_NUM 1024
753 #define TM_ILT_SZ (8 * TM_CONN_NUM)
754 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
756 /* SRC (Searcher) host DB constants */
757 #define SRC_ILT_PAGE_SZ_HW 0
758 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
759 #define SRC_HASH_BITS 10
760 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
761 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
762 #define SRC_T2_SZ SRC_ILT_SZ
763 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
766 struct bxe_dma vcxt_dma;
767 union cdu_context *vcxt;
768 //bus_addr_t cxt_mapping;
775 /* defines for multiple tx priority indices */
776 #define FIRST_TX_ONLY_COS_INDEX 1
777 #define FIRST_TX_COS_INDEX 0
779 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
781 #define HC_INDEX_ETH_RX_CQ_CONS 1
782 #define HC_INDEX_OOO_TX_CQ_CONS 4
783 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
784 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
785 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
786 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
788 /* congestion management fairness mode */
789 #define CMNG_FNS_NONE 0
790 #define CMNG_FNS_MINMAX 1
792 /* CMNG constants, as derived from system spec calculations */
793 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
794 #define DEF_MIN_RATE 100
795 /* resolution of the rate shaping timer - 400 usec */
796 #define RS_PERIODIC_TIMEOUT_USEC 400
797 /* number of bytes in single QM arbitration cycle -
798 * coefficient for calculating the fairness timer */
799 #define QM_ARB_BYTES 160000
800 /* resolution of Min algorithm 1:100 */
802 /* how many bytes above threshold for the minimal credit of Min algorithm*/
803 #define MIN_ABOVE_THRESH 32768
804 /* fairness algorithm integration time coefficient -
805 * for calculating the actual Tfair */
806 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
807 /* memory of fairness algorithm - 2 cycles */
810 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
811 #define HC_SEG_ACCESS_ATTN 4
812 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
815 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
816 * control by the number of fast-path status blocks supported by the
817 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
818 * status block represents an independent interrupts context that can
819 * serve a regular L2 networking queue. However special L2 queues such
820 * as the FCoE queue do not require a FP-SB and other components like
821 * the CNIC may consume FP-SB reducing the number of possible L2 queues
823 * If the maximum number of FP-SB available is X then:
824 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
825 * regular L2 queues is Y=X-1
826 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
827 * c. If the FCoE L2 queue is supported the actual number of L2 queues
829 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
830 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
831 * FP interrupt context for the CNIC).
832 * e. The number of HW context (CID count) is always X or X+1 if FCoE
833 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
835 * So this is quite simple for now as no ULPs are supported yet. :-)
837 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
838 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
839 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
840 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
842 #define FOR_EACH_QUEUE(sc, var) \
843 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
845 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
846 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
848 #define FOR_EACH_ETH_QUEUE(sc, var) \
849 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
851 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
852 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
854 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
855 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
857 #define FOR_EACH_CNIC_QUEUE(sc, var) \
858 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
859 (var) < BXE_NUM_QUEUES(sc); \
868 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
869 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
870 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
871 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
872 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
873 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
875 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
876 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
877 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
878 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
879 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
881 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
882 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
883 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
884 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
885 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
886 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
888 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
889 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
890 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
891 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
892 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
893 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
894 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
900 BXE_FIRST_QUEUE_QUERY_IDX,
903 struct bxe_fw_stats_req {
904 struct stats_query_header hdr;
905 struct stats_query_entry query[FP_SB_MAX_E1x +
906 BXE_FIRST_QUEUE_QUERY_IDX];
909 struct bxe_fw_stats_data {
910 struct stats_counter storm_counters;
911 struct per_port_stats port;
912 struct per_pf_stats pf;
913 //struct fcoe_statistics_params fcoe;
914 struct per_queue_stats queue_stats[1];
917 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
918 #define BXE_IGU_STAS_MSG_VF_CNT 64
919 #define BXE_IGU_STAS_MSG_PF_CNT 4
924 * For the main interface up/down code paths, a not-so-fine-grained CORE
925 * mutex lock is used. Inside this code are various calls to kernel routines
926 * that can cause a sleep to occur. Namely memory allocations and taskqueue
927 * handling. If using an MTX lock we are *not* allowed to sleep but we can
928 * with an SX lock. This define forces the CORE lock to use and SX lock.
929 * Undefine this and an MTX lock will be used instead. Note that the IOCTL
930 * path can cause problems since it's called by a non-sleepable thread. To
931 * alleviate a potential sleep, any IOCTL processing that results in the
932 * chip/interface being started/stopped/reinitialized, the actual work is
933 * offloaded to a taskqueue.
935 #define BXE_CORE_LOCK_SX
938 * This is the slowpath data structure. It is mapped into non-paged memory
939 * so that the hardware can access it's contents directly and must be page
942 struct bxe_slowpath {
944 /* used by the DMAE command executer */
945 struct dmae_cmd dmae[MAX_DMAE_C];
947 /* statistics completion */
950 /* firmware defined statistics blocks */
951 union mac_stats mac_stats;
952 struct nig_stats nig_stats;
953 struct host_port_stats port_stats;
954 struct host_func_stats func_stats;
955 //struct host_func_stats func_stats_base;
957 /* DMAE completion value and data source/sink */
962 struct mac_configuration_cmd e1x;
963 struct eth_classify_rules_ramrod_data e2;
967 struct tstorm_eth_mac_filter_config e1x;
968 struct eth_filter_rules_ramrod_data e2;
971 struct eth_rss_update_ramrod_data rss_rdata;
974 struct mac_configuration_cmd e1;
975 struct eth_multicast_rules_ramrod_data e2;
979 struct function_start_data func_start;
980 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
983 /* Queue State related ramrods */
985 struct client_init_ramrod_data init_data;
986 struct client_update_ramrod_data update_data;
990 * AFEX ramrod can not be a part of func_rdata union because these
991 * events might arrive in parallel to other events from func_rdata.
992 * If they were defined in the same union the data can get corrupted.
994 struct afex_vif_list_ramrod_data func_afex_rdata;
996 union drv_info_to_mcp drv_info_to_mcp;
997 }; /* struct bxe_slowpath */
1000 * Port specifc data structure.
1004 * Port Management Function (for 57711E only).
1005 * When this field is set the driver instance is
1006 * responsible for managing port specifc
1007 * configurations such as handling link attentions.
1011 /* Ethernet maximum transmission unit. */
1014 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
1016 uint32_t ext_phy_config;
1018 /* Port feature config.*/
1021 /* Defines the features supported by the PHY. */
1022 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
1024 /* Defines the features advertised by the PHY. */
1025 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
1026 #define ADVERTISED_10baseT_Half (1 << 1)
1027 #define ADVERTISED_10baseT_Full (1 << 2)
1028 #define ADVERTISED_100baseT_Half (1 << 3)
1029 #define ADVERTISED_100baseT_Full (1 << 4)
1030 #define ADVERTISED_1000baseT_Half (1 << 5)
1031 #define ADVERTISED_1000baseT_Full (1 << 6)
1032 #define ADVERTISED_TP (1 << 7)
1033 #define ADVERTISED_FIBRE (1 << 8)
1034 #define ADVERTISED_Autoneg (1 << 9)
1035 #define ADVERTISED_Asym_Pause (1 << 10)
1036 #define ADVERTISED_Pause (1 << 11)
1037 #define ADVERTISED_2500baseX_Full (1 << 15)
1038 #define ADVERTISED_10000baseT_Full (1 << 16)
1042 /* Used to synchronize phy accesses. */
1044 char phy_mtx_name[32];
1046 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1047 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1048 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1051 * MCP scratchpad address for port specific statistics.
1052 * The device is responsible for writing statistcss
1053 * back to the MCP for use with management firmware such
1058 struct nig_stats old_nig_stats;
1059 }; /* struct bxe_port */
1061 struct bxe_mf_info {
1062 uint32_t mf_config[E1HVN_MAX];
1064 uint32_t vnics_per_port; /* 1, 2 or 4 */
1065 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
1066 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
1068 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1069 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1070 #define VNICS_PER_PATH(sc) \
1071 ((sc)->devinfo.mf_info.vnics_per_port * \
1072 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1074 uint8_t min_bw[MAX_VNIC_NUM];
1075 uint8_t max_bw[MAX_VNIC_NUM];
1077 uint16_t ext_id; /* vnic outer vlan or VIF ID */
1078 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1079 #define INVALID_VIF_ID 0xFFFF
1080 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1081 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1083 uint16_t default_vlan;
1084 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1086 uint8_t niv_allowed_priorities;
1087 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1089 uint8_t niv_default_cos;
1090 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1092 uint8_t niv_mba_enabled;
1094 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1095 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1096 int afex_def_vlan_tag;
1097 uint32_t pending_max;
1100 #define MF_INFO_VALID_MAC 0x0001
1102 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
1104 (IS_MULTI_VNIC(sc) && \
1105 ((sc)->devinfo.mf_info.mf_mode != 0))
1106 #define IS_MF_SD(sc) \
1107 (IS_MULTI_VNIC(sc) && \
1108 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1109 #define IS_MF_SI(sc) \
1110 (IS_MULTI_VNIC(sc) && \
1111 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1112 #define IS_MF_AFEX(sc) \
1113 (IS_MULTI_VNIC(sc) && \
1114 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1115 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1116 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1117 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1119 uint32_t mf_protos_supported;
1120 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1121 #define MF_PROTO_SUPPORT_ISCSI 0x2
1122 #define MF_PROTO_SUPPORT_FCOE 0x4
1123 }; /* struct bxe_mf_info */
1125 /* Device information data structure. */
1126 struct bxe_devinfo {
1130 uint16_t subvendor_id;
1131 uint16_t subdevice_id;
1134 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
1135 * C = Chip Number (bits 16-31)
1136 * R = Chip Revision (bits 12-15)
1137 * M = Chip Metal (bits 4-11)
1138 * B = Chip Bond ID (bits 0-3)
1141 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1142 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1144 #define CHIP_NUM_57710 0x164e
1145 #define CHIP_NUM_57711 0x164f
1146 #define CHIP_NUM_57711E 0x1650
1147 #define CHIP_NUM_57712 0x1662
1148 #define CHIP_NUM_57712_MF 0x1663
1149 #define CHIP_NUM_57712_VF 0x166f
1150 #define CHIP_NUM_57800 0x168a
1151 #define CHIP_NUM_57800_MF 0x16a5
1152 #define CHIP_NUM_57800_VF 0x16a9
1153 #define CHIP_NUM_57810 0x168e
1154 #define CHIP_NUM_57810_MF 0x16ae
1155 #define CHIP_NUM_57810_VF 0x16af
1156 #define CHIP_NUM_57811 0x163d
1157 #define CHIP_NUM_57811_MF 0x163e
1158 #define CHIP_NUM_57811_VF 0x163f
1159 #define CHIP_NUM_57840_OBS 0x168d
1160 #define CHIP_NUM_57840_OBS_MF 0x16ab
1161 #define CHIP_NUM_57840_4_10 0x16a1
1162 #define CHIP_NUM_57840_2_20 0x16a2
1163 #define CHIP_NUM_57840_MF 0x16a4
1164 #define CHIP_NUM_57840_VF 0x16ad
1166 #define CHIP_REV_SHIFT 12
1167 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1168 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1170 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1171 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1172 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1174 #define CHIP_REV_IS_SLOW(sc) \
1175 (CHIP_REV(sc) > 0x00005000)
1176 #define CHIP_REV_IS_FPGA(sc) \
1177 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1178 #define CHIP_REV_IS_EMUL(sc) \
1179 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1180 #define CHIP_REV_IS_ASIC(sc) \
1181 (!CHIP_REV_IS_SLOW(sc))
1183 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1184 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1186 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1187 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1188 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1189 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1190 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1191 (CHIP_IS_57711E(sc)))
1192 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1195 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1196 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1197 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1198 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1199 CHIP_IS_57712_MF(sc))
1201 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1202 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1203 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1204 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1205 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1206 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1207 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1208 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1209 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1210 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1211 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1212 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1213 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1214 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1215 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1217 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1218 CHIP_IS_57800_MF(sc) || \
1219 CHIP_IS_57800_VF(sc) || \
1220 CHIP_IS_57810(sc) || \
1221 CHIP_IS_57810_MF(sc) || \
1222 CHIP_IS_57810_VF(sc) || \
1223 CHIP_IS_57811(sc) || \
1224 CHIP_IS_57811_MF(sc) || \
1225 CHIP_IS_57811_VF(sc) || \
1226 CHIP_IS_57840(sc) || \
1227 CHIP_IS_57840_MF(sc) || \
1228 CHIP_IS_57840_VF(sc))
1229 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1230 (CHIP_REV(sc) == CHIP_REV_Ax))
1231 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1232 (CHIP_REV(sc) == CHIP_REV_Bx))
1234 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1235 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1238 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1239 CHIP_IS_57712_MF(sc) || \
1242 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1243 CHIP_IS_57800_VF(sc) || \
1244 CHIP_IS_57810_VF(sc) || \
1245 CHIP_IS_57840_VF(sc))
1246 #define IS_PF(sc) (!IS_VF(sc))
1249 * This define is used in two main places:
1250 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
1251 * to nic-only mode or to offload mode. Offload mode is configured if either
1252 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
1253 * already registered for this port (which means that the user wants storage
1255 * 2. During cnic-related load, to know if offload mode is already configured
1256 * in the HW or needs to be configrued. Since the transition from nic-mode to
1257 * offload-mode in HW causes traffic coruption, nic-mode is configured only
1258 * in ports on which storage services where never requested.
1260 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1262 uint8_t chip_port_mode;
1263 #define CHIP_4_PORT_MODE 0x0
1264 #define CHIP_2_PORT_MODE 0x1
1265 #define CHIP_PORT_MODE_NONE 0x2
1266 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1267 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1270 #define INT_BLOCK_HC 0
1271 #define INT_BLOCK_IGU 1
1272 #define INT_BLOCK_MODE_NORMAL 0
1273 #define INT_BLOCK_MODE_BW_COMP 2
1274 #define CHIP_INT_MODE_IS_NBC(sc) \
1275 (!CHIP_IS_E1x(sc) && \
1276 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1277 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1279 uint32_t shmem_base;
1280 uint32_t shmem2_base;
1282 char bc_ver_str[32];
1283 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
1284 struct bxe_mf_info mf_info;
1287 #define NVRAM_1MB_SIZE 0x20000
1288 #define NVRAM_TIMEOUT_COUNT 30000
1289 #define NVRAM_PAGE_SIZE 256
1291 /* PCIe capability information */
1292 uint32_t pcie_cap_flags;
1293 #define BXE_PM_CAPABLE_FLAG 0x00000001
1294 #define BXE_PCIE_CAPABLE_FLAG 0x00000002
1295 #define BXE_MSI_CAPABLE_FLAG 0x00000004
1296 #define BXE_MSIX_CAPABLE_FLAG 0x00000008
1297 uint16_t pcie_pm_cap_reg;
1298 uint16_t pcie_pcie_cap_reg;
1299 //uint16_t pcie_devctl;
1300 uint16_t pcie_link_width;
1301 uint16_t pcie_link_speed;
1302 uint16_t pcie_msi_cap_reg;
1303 uint16_t pcie_msix_cap_reg;
1305 /* device configuration read from bootcode shared memory */
1307 uint32_t hw_config2;
1308 }; /* struct bxe_devinfo */
1310 struct bxe_sp_objs {
1311 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1312 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1313 }; /* struct bxe_sp_objs */
1316 * Data that will be used to create a link report message. We will keep the
1317 * data used for the last link report in order to prevent reporting the same
1318 * link parameters twice.
1320 struct bxe_link_report_data {
1321 uint16_t line_speed; /* Effective line speed */
1322 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */
1325 BXE_LINK_REPORT_FULL_DUPLEX,
1326 BXE_LINK_REPORT_LINK_DOWN,
1327 BXE_LINK_REPORT_RX_FC_ON,
1328 BXE_LINK_REPORT_TX_FC_ON
1331 /* Top level device private data structure. */
1334 * First entry must be a pointer to the BSD ifnet struct which
1335 * has a first element of 'void *if_softc' (which is us). XXX
1338 struct ifmedia ifmedia; /* network interface media structure */
1341 volatile int state; /* device state */
1342 #define BXE_STATE_CLOSED 0x0000
1343 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1344 #define BXE_STATE_OPENING_WAITING_PORT 0x2000
1345 #define BXE_STATE_OPEN 0x3000
1346 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1347 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1348 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1349 #define BXE_STATE_DISABLED 0xD000
1350 #define BXE_STATE_DIAG 0xE000
1351 #define BXE_STATE_ERROR 0xF000
1354 #define BXE_ONE_PORT_FLAG 0x00000001
1355 #define BXE_NO_ISCSI 0x00000002
1356 #define BXE_NO_FCOE 0x00000004
1357 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1358 //#define BXE_NO_WOL_FLAG 0x00000008
1359 //#define BXE_USING_DAC_FLAG 0x00000010
1360 //#define BXE_USING_MSIX_FLAG 0x00000020
1361 //#define BXE_USING_MSI_FLAG 0x00000040
1362 //#define BXE_DISABLE_MSI_FLAG 0x00000080
1363 #define BXE_NO_MCP_FLAG 0x00000200
1364 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1365 //#define BXE_SAFC_TX_FLAG 0x00000400
1366 #define BXE_MF_FUNC_DIS 0x00000800
1367 #define BXE_TX_SWITCHING 0x00001000
1368 #define BXE_NO_PULSE 0x00002000
1370 unsigned long debug; /* per-instance debug logging config */
1373 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1375 uint16_t doorbell_size;
1377 /* periodic timer callout */
1378 #define PERIODIC_STOP 0
1379 #define PERIODIC_GO 1
1380 volatile unsigned long periodic_flags;
1381 struct callout periodic_callout;
1383 /* chip start/stop/reset taskqueue */
1384 #define CHIP_TQ_NONE 0
1385 #define CHIP_TQ_START 1
1386 #define CHIP_TQ_STOP 2
1387 #define CHIP_TQ_REINIT 3
1388 volatile unsigned long chip_tq_flags;
1389 struct task chip_tq_task;
1390 struct taskqueue *chip_tq;
1391 char chip_tq_name[32];
1393 /* slowpath interrupt taskqueue */
1394 struct task sp_tq_task;
1395 struct taskqueue *sp_tq;
1396 char sp_tq_name[32];
1398 struct bxe_fastpath fp[MAX_RSS_CHAINS];
1399 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS];
1401 device_t dev; /* parent device handle */
1402 uint8_t unit; /* driver instance number */
1404 int pcie_bus; /* PCIe bus number */
1405 int pcie_device; /* PCIe device/slot number */
1406 int pcie_func; /* PCIe function number */
1408 uint8_t pfunc_rel; /* function relative */
1409 uint8_t pfunc_abs; /* function absolute */
1410 uint8_t path_id; /* function absolute */
1411 #define SC_PATH(sc) (sc->path_id)
1412 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1413 #define SC_FUNC(sc) (sc->pfunc_rel)
1414 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1415 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1416 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1417 #define PORT_ID(sc) SC_PORT(sc)
1418 #define PATH_ID(sc) SC_PATH(sc)
1419 #define VNIC_ID(sc) SC_VN(sc)
1420 #define FUNC_ID(sc) SC_FUNC(sc)
1421 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1422 #define SC_FW_MB_IDX_VN(sc, vn) \
1423 (SC_PORT(sc) + (vn) * \
1424 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1425 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1427 int if_capen; /* enabled interface capabilities */
1429 struct bxe_devinfo devinfo;
1430 char fw_ver_str[32];
1431 char mf_mode_str[32];
1432 char pci_link_str[32];
1434 const struct iro *iro_array;
1436 #ifdef BXE_CORE_LOCK_SX
1438 char core_sx_name[32];
1440 struct mtx core_mtx;
1441 char core_mtx_name[32];
1444 char sp_mtx_name[32];
1445 struct mtx dmae_mtx;
1446 char dmae_mtx_name[32];
1447 struct mtx fwmb_mtx;
1448 char fwmb_mtx_name[32];
1449 struct mtx print_mtx;
1450 char print_mtx_name[32];
1451 struct mtx stats_mtx;
1452 char stats_mtx_name[32];
1453 struct mtx mcast_mtx;
1454 char mcast_mtx_name[32];
1456 #ifdef BXE_CORE_LOCK_SX
1457 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1458 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1459 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1460 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1462 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1463 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1464 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1465 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1468 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1469 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1470 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1472 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1473 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1474 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1476 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1477 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1478 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1480 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1481 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1482 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1484 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1485 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1486 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1488 #if __FreeBSD_version < 800000
1489 #define BXE_MCAST_LOCK(sc) \
1491 mtx_lock(&sc->mcast_mtx); \
1492 IF_ADDR_LOCK(sc->ifp); \
1494 #define BXE_MCAST_UNLOCK(sc) \
1496 IF_ADDR_UNLOCK(sc->ifp); \
1497 mtx_unlock(&sc->mcast_mtx); \
1500 #define BXE_MCAST_LOCK(sc) \
1502 mtx_lock(&sc->mcast_mtx); \
1503 if_maddr_rlock(sc->ifp); \
1505 #define BXE_MCAST_UNLOCK(sc) \
1507 if_maddr_runlock(sc->ifp); \
1508 mtx_unlock(&sc->mcast_mtx); \
1511 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1514 #define DMAE_READY(sc) (sc->dmae_ready)
1516 struct ecore_credit_pool_obj vlans_pool;
1517 struct ecore_credit_pool_obj macs_pool;
1518 struct ecore_rx_mode_obj rx_mode_obj;
1519 struct ecore_mcast_obj mcast_obj;
1520 struct ecore_rss_config_obj rss_conf_obj;
1521 struct ecore_func_sp_obj func_obj;
1524 uint16_t fw_drv_pulse_wr_seq;
1527 struct elink_params link_params;
1528 struct elink_vars link_vars;
1530 struct bxe_link_report_data last_reported_link;
1531 char mac_addr_str[32];
1533 int last_reported_link_state;
1541 #define BXE_RECOVERY_DONE 1
1542 #define BXE_RECOVERY_INIT 2
1543 #define BXE_RECOVERY_WAIT 3
1544 #define BXE_RECOVERY_FAILED 4
1545 #define BXE_RECOVERY_NIC_LOADING 5
1548 #define BXE_RX_MODE_NONE 0
1549 #define BXE_RX_MODE_NORMAL 1
1550 #define BXE_RX_MODE_ALLMULTI 2
1551 #define BXE_RX_MODE_PROMISC 3
1552 #define BXE_MAX_MULTICAST 64
1554 struct bxe_port port;
1556 struct cmng_init cmng;
1564 int max_aggregation_size;
1567 #define AUTO_GREEN_HW_DEFAULT 0
1568 #define AUTO_GREEN_FORCE_ON 1
1569 #define AUTO_GREEN_FORCE_OFF 2
1571 #define INTR_MODE_INTX 0
1572 #define INTR_MODE_MSI 1
1573 #define INTR_MODE_MSIX 2
1576 /* interrupt allocations */
1577 struct bxe_intr intr[MAX_RSS_CHAINS+1];
1580 uint8_t igu_base_sb;
1582 //uint8_t min_msix_vec_cnt;
1583 uint32_t igu_base_addr;
1584 //bus_addr_t def_status_blk_mapping;
1585 uint8_t base_fw_ndsb;
1586 #define DEF_SB_IGU_ID 16
1587 #define DEF_SB_ID HC_SP_SB_ID
1589 /* parent bus DMA tag */
1590 bus_dma_tag_t parent_dma_tag;
1592 /* default status block */
1593 struct bxe_dma def_sb_dma;
1594 struct host_sp_status_block *def_sb;
1596 uint16_t def_att_idx;
1597 uint32_t attn_state;
1598 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1600 /* general SP events - stats query, cfc delete, etc */
1601 #define HC_SP_INDEX_ETH_DEF_CONS 3
1602 /* EQ completions */
1603 #define HC_SP_INDEX_EQ_CONS 7
1604 /* FCoE L2 connection completions */
1605 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1606 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1608 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1609 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1612 struct bxe_dma eq_dma;
1613 union event_ring_elem *eq;
1616 uint16_t *eq_cons_sb;
1617 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1618 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1619 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1620 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1621 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1622 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1623 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1624 #define NEXT_EQ_IDX(x) \
1625 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1626 ((x) + 2) : ((x) + 1))
1627 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1628 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1631 struct bxe_dma sp_dma;
1632 struct bxe_slowpath *sp;
1633 unsigned long sp_state;
1635 /* slow path queue */
1636 struct bxe_dma spq_dma;
1637 struct eth_spe *spq;
1638 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1639 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1640 #define MAX_SPQ_PENDING 8
1642 uint16_t spq_prod_idx;
1643 struct eth_spe *spq_prod_bd;
1644 struct eth_spe *spq_last_bd;
1645 uint16_t *dsb_sp_prod;
1646 //uint16_t *spq_hw_con;
1647 //uint16_t spq_left;
1649 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1650 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1652 /* fw decompression buffer */
1653 struct bxe_dma gz_buf_dma;
1657 #define GUNZIP_BUF(sc) (sc->gz_buf)
1658 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1659 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1660 #define FW_BUF_SIZE 0x40000
1662 const struct raw_op *init_ops;
1663 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1664 const uint32_t *init_data; /* data blob, 32 bit granularity */
1665 uint32_t init_mode_flags;
1666 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1667 /* PRAM blobs - raw data */
1668 const uint8_t *tsem_int_table_data;
1669 const uint8_t *tsem_pram_data;
1670 const uint8_t *usem_int_table_data;
1671 const uint8_t *usem_pram_data;
1672 const uint8_t *xsem_int_table_data;
1673 const uint8_t *xsem_pram_data;
1674 const uint8_t *csem_int_table_data;
1675 const uint8_t *csem_pram_data;
1676 #define INIT_OPS(sc) (sc->init_ops)
1677 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1678 #define INIT_DATA(sc) (sc->init_data)
1679 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1680 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1681 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1682 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1683 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1684 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1685 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1686 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1689 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1690 * context size we need 8 ILT entries.
1692 #define ILT_MAX_L2_LINES 8
1693 struct hw_context context[ILT_MAX_L2_LINES];
1694 struct ecore_ilt *ilt;
1695 #define ILT_MAX_LINES 256
1697 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1698 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1699 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1701 #define BXE_L2_MAX_CID(sc) \
1702 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1704 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \
1705 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1708 #define BXE_L2_CID_COUNT(sc) \
1709 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1711 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \
1712 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1714 #define L2_ILT_LINES(sc) \
1715 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1719 uint8_t dropless_fc;
1721 /* total number of FW statistics requests */
1722 uint8_t fw_stats_num;
1724 * This is a memory buffer that will contain both statistics ramrod
1727 struct bxe_dma fw_stats_dma;
1729 * FW statistics request shortcut (points at the beginning of fw_stats
1732 int fw_stats_req_size;
1733 struct bxe_fw_stats_req *fw_stats_req;
1734 bus_addr_t fw_stats_req_mapping;
1736 * FW statistics data shortcut (points at the beginning of fw_stats
1737 * buffer + fw_stats_req_size).
1739 int fw_stats_data_size;
1740 struct bxe_fw_stats_data *fw_stats_data;
1741 bus_addr_t fw_stats_data_mapping;
1743 /* tracking a pending STAT_QUERY ramrod */
1744 uint16_t stats_pending;
1745 /* number of completed statistics ramrods */
1746 uint16_t stats_comp;
1747 uint16_t stats_counter;
1751 struct bxe_eth_stats eth_stats;
1752 struct host_func_stats func_stats;
1753 struct bxe_eth_stats_old eth_stats_old;
1754 struct bxe_net_stats_old net_stats_old;
1755 struct bxe_fw_port_stats_old fw_stats_old;
1757 struct dmae_cmd stats_dmae; /* used by dmae command loader */
1763 struct bxe_config_lldp_params lldp_config_params;
1764 /* DCB support on/off */
1766 #define BXE_DCB_STATE_OFF 0
1767 #define BXE_DCB_STATE_ON 1
1768 /* DCBX engine mode */
1770 #define BXE_DCBX_ENABLED_OFF 0
1771 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1772 #define BXE_DCBX_ENABLED_ON_NEG_ON 2
1773 #define BXE_DCBX_ENABLED_INVALID -1
1774 uint8_t dcbx_mode_uset;
1775 struct bxe_config_dcbx_params dcbx_config_params;
1776 struct bxe_dcbx_port_params dcbx_port_params;
1779 uint8_t cnic_support;
1780 uint8_t cnic_enabled;
1781 uint8_t cnic_loaded;
1782 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1783 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1784 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1786 /* multiple tx classes of service */
1788 #define BXE_MAX_PRIORITY 8
1789 /* priority to cos mapping */
1790 uint8_t prio_to_cos[BXE_MAX_PRIORITY];
1794 struct cdev *ioctl_dev;
1797 unsigned int trigger_grcdump;
1798 unsigned int grcdump_done;
1799 unsigned int grcdump_started;
1800 int bxe_pause_param;
1802 }; /* struct bxe_softc */
1804 /* IOCTL sub-commands for edebug and firmware upgrade */
1805 #define BXE_IOC_RD_NVRAM 1
1806 #define BXE_IOC_WR_NVRAM 2
1807 #define BXE_IOC_STATS_SHOW_NUM 3
1808 #define BXE_IOC_STATS_SHOW_STR 4
1809 #define BXE_IOC_STATS_SHOW_CNT 5
1811 struct bxe_nvram_data {
1812 uint32_t op; /* ioctl sub-command */
1815 uint32_t value[1]; /* variable */
1818 union bxe_stats_show_data {
1819 uint32_t op; /* ioctl sub-command */
1822 uint32_t num; /* return number of stats */
1823 uint32_t len; /* length of each string item */
1826 /* variable length... */
1827 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1829 /* variable length... */
1830 uint64_t stats[1]; /* holds all stats */
1833 /* function init flags */
1834 #define FUNC_FLG_RSS 0x0001
1835 #define FUNC_FLG_STATS 0x0002
1836 /* FUNC_FLG_UNMATCHED 0x0004 */
1837 #define FUNC_FLG_TPA 0x0008
1838 #define FUNC_FLG_SPQ 0x0010
1839 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1841 struct bxe_func_init_params {
1842 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1843 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1845 uint16_t func_id; /* abs function id */
1847 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1850 /* memory resources reside at BARs 0, 2, 4 */
1851 /* Run `pciconf -lb` to see mappings */
1856 #ifdef BXE_REG_NO_INLINE
1858 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset);
1859 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset);
1860 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset);
1862 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val);
1863 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val);
1864 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
1866 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1867 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1868 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1870 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1871 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1872 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1874 #else /* not BXE_REG_NO_INLINE */
1876 #define REG_WR8(sc, offset, val) \
1877 bus_space_write_1(sc->bar[BAR0].tag, \
1878 sc->bar[BAR0].handle, \
1881 #define REG_WR16(sc, offset, val) \
1882 bus_space_write_2(sc->bar[BAR0].tag, \
1883 sc->bar[BAR0].handle, \
1886 #define REG_WR32(sc, offset, val) \
1887 bus_space_write_4(sc->bar[BAR0].tag, \
1888 sc->bar[BAR0].handle, \
1891 #define REG_RD8(sc, offset) \
1892 bus_space_read_1(sc->bar[BAR0].tag, \
1893 sc->bar[BAR0].handle, \
1896 #define REG_RD16(sc, offset) \
1897 bus_space_read_2(sc->bar[BAR0].tag, \
1898 sc->bar[BAR0].handle, \
1901 #define REG_RD32(sc, offset) \
1902 bus_space_read_4(sc->bar[BAR0].tag, \
1903 sc->bar[BAR0].handle, \
1906 #endif /* BXE_REG_NO_INLINE */
1908 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1909 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1911 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1912 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1914 #define BXE_SP(sc, var) (&(sc)->sp->var)
1915 #define BXE_SP_MAPPING(sc, var) \
1916 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1918 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1919 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1921 #define REG_RD_DMAE(sc, offset, valp, len32) \
1923 bxe_read_dmae(sc, offset, len32); \
1924 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1927 #define REG_WR_DMAE(sc, offset, valp, len32) \
1929 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1930 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1933 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1934 REG_WR_DMAE(sc, offset, valp, len32)
1936 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1937 REG_RD_DMAE(sc, offset, valp, len32)
1939 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1941 /* if (le32_swap) { */ \
1942 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \
1944 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1945 ecore_write_big_buf_wb(sc, addr, len32); \
1948 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */
1949 #define BXE_DB_SHIFT 7 /* 128 bytes */
1950 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1951 #error "Minimum DB doorbell stride is 8"
1953 #define DPM_TRIGGER_TYPE 0x40
1954 #define DOORBELL(sc, cid, val) \
1956 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
1957 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
1961 #define SHMEM_ADDR(sc, field) \
1962 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
1963 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
1964 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
1965 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
1967 #define SHMEM2_ADDR(sc, field) \
1968 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
1969 #define SHMEM2_HAS(sc, field) \
1970 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
1971 offsetof(struct shmem2_region, field)))
1972 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
1973 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
1975 #define MFCFG_ADDR(sc, field) \
1976 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
1977 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
1978 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
1979 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
1981 /* DMAE command defines */
1983 #define DMAE_TIMEOUT -1
1984 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1985 #define DMAE_NOT_RDY -3
1986 #define DMAE_PCI_ERR_FLAG 0x80000000
1988 #define DMAE_SRC_PCI 0
1989 #define DMAE_SRC_GRC 1
1991 #define DMAE_DST_NONE 0
1992 #define DMAE_DST_PCI 1
1993 #define DMAE_DST_GRC 2
1995 #define DMAE_COMP_PCI 0
1996 #define DMAE_COMP_GRC 1
1998 #define DMAE_COMP_REGULAR 0
1999 #define DMAE_COM_SET_ERR 1
2001 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT)
2002 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT)
2003 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT)
2004 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT)
2006 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT)
2007 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT)
2009 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT)
2010 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT)
2011 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT)
2012 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT)
2014 #define DMAE_CMD_PORT_0 0
2015 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT
2017 #define DMAE_SRC_PF 0
2018 #define DMAE_SRC_VF 1
2020 #define DMAE_DST_PF 0
2021 #define DMAE_DST_VF 1
2023 #define DMAE_C_SRC 0
2024 #define DMAE_C_DST 1
2026 #define DMAE_LEN32_RD_MAX 0x80
2027 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
2029 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
2031 #define MAX_DMAE_C_PER_PORT 8
2032 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
2033 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
2035 static const uint32_t dmae_reg_go_c[] = {
2036 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2037 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2038 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2039 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2042 #define ATTN_NIG_FOR_FUNC (1L << 8)
2043 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2044 #define GPIO_2_FUNC (1L << 10)
2045 #define GPIO_3_FUNC (1L << 11)
2046 #define GPIO_4_FUNC (1L << 12)
2047 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2048 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2049 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2050 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2051 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2052 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2053 #define ATTN_HARD_WIRED_MASK 0xff00
2054 #define ATTENTION_ID 4
2056 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2057 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2059 #define MAX_IGU_ATTN_ACK_TO 100
2061 #define STORM_ASSERT_ARRAY_SIZE 50
2063 #define BXE_PMF_LINK_ASSERT(sc) \
2064 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2066 #define BXE_MC_ASSERT_BITS \
2067 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2068 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2069 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2070 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2072 #define BXE_MCP_ASSERT \
2073 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2075 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2076 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2077 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2078 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2079 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2080 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2081 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2083 #define MULTI_MASK 0x7f
2085 #define PFS_PER_PORT(sc) \
2086 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2087 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2089 #define FIRST_ABS_FUNC_IN_PORT(sc) \
2090 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2091 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2093 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2094 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2095 (i) < MAX_FUNC_NUM; \
2096 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2098 #define BXE_SWCID_SHIFT 17
2099 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2101 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2102 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2104 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2105 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2106 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2107 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2108 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2110 /* must be used on a CID before placing it on a HW ring */
2111 #define HW_CID(sc, x) \
2112 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2115 #define SPEED_100 100
2116 #define SPEED_1000 1000
2117 #define SPEED_2500 2500
2118 #define SPEED_10000 10000
2121 #define PCI_PM_D3hot 2
2123 #ifndef DUPLEX_UNKNOWN
2124 #define DUPLEX_UNKNOWN (0xff)
2127 #ifndef SPEED_UNKNOWN
2128 #define SPEED_UNKNOWN (-1)
2131 /* Enable or disable autonegotiation. */
2132 #define AUTONEG_DISABLE 0x00
2133 #define AUTONEG_ENABLE 0x01
2135 /* Which connector port. */
2136 #define PORT_TP 0x00
2137 #define PORT_AUI 0x01
2138 #define PORT_MII 0x02
2139 #define PORT_FIBRE 0x03
2140 #define PORT_BNC 0x04
2141 #define PORT_DA 0x05
2142 #define PORT_NONE 0xef
2143 #define PORT_OTHER 0xff
2145 int bxe_test_bit(int nr, volatile unsigned long * addr);
2146 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr);
2147 void bxe_clear_bit(int nr, volatile unsigned long * addr);
2148 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr);
2149 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr);
2150 int bxe_cmpxchg(volatile int *addr, int old, int new);
2152 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr,
2154 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr);
2157 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size,
2158 struct bxe_dma *dma, const char *msg);
2159 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma);
2161 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2162 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode);
2163 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type,
2164 uint8_t dst_type, uint8_t with_comp,
2166 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx);
2167 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32);
2168 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr,
2169 uint32_t dst_addr, uint32_t len32);
2170 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
2171 uint32_t addr, uint32_t len);
2173 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt,
2175 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id,
2176 uint8_t sb_index, uint8_t disable,
2179 int bxe_sp_post(struct bxe_softc *sc, int command, int cid,
2180 uint32_t data_hi, uint32_t data_lo, int cmd_type);
2182 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
2183 uint8_t segment, uint16_t index, uint8_t op,
2186 void ecore_init_e1_firmware(struct bxe_softc *sc);
2187 void ecore_init_e1h_firmware(struct bxe_softc *sc);
2188 void ecore_init_e2_firmware(struct bxe_softc *sc);
2190 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr,
2191 size_t size, uint32_t *data);
2193 /*********************/
2194 /* LOGGING AND DEBUG */
2195 /*********************/
2197 /* debug logging codepaths */
2198 #define DBG_LOAD 0x00000001 /* load and unload */
2199 #define DBG_INTR 0x00000002 /* interrupt handling */
2200 #define DBG_SP 0x00000004 /* slowpath handling */
2201 #define DBG_STATS 0x00000008 /* stats updates */
2202 #define DBG_TX 0x00000010 /* packet transmit */
2203 #define DBG_RX 0x00000020 /* packet receive */
2204 #define DBG_PHY 0x00000040 /* phy/link handling */
2205 #define DBG_IOCTL 0x00000080 /* ioctl handling */
2206 #define DBG_MBUF 0x00000100 /* dumping mbuf info */
2207 #define DBG_REGS 0x00000200 /* register access */
2208 #define DBG_LRO 0x00000400 /* lro processing */
2209 #define DBG_ASSERT 0x80000000 /* debug assert */
2210 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */
2212 #define DBASSERT(sc, exp, msg) \
2214 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2215 if (__predict_false(!(exp))) { \
2221 /* log a debug message */
2222 #define BLOGD(sc, codepath, format, args...) \
2224 if (__predict_false(sc->debug & (codepath))) { \
2225 device_printf((sc)->dev, \
2226 "%s(%s:%d) " format, \
2234 /* log a info message */
2235 #define BLOGI(sc, format, args...) \
2237 if (__predict_false(sc->debug)) { \
2238 device_printf((sc)->dev, \
2239 "%s(%s:%d) " format, \
2245 device_printf((sc)->dev, \
2251 /* log a warning message */
2252 #define BLOGW(sc, format, args...) \
2254 if (__predict_false(sc->debug)) { \
2255 device_printf((sc)->dev, \
2256 "%s(%s:%d) WARNING: " format, \
2262 device_printf((sc)->dev, \
2263 "WARNING: " format, \
2268 /* log a error message */
2269 #define BLOGE(sc, format, args...) \
2271 if (__predict_false(sc->debug)) { \
2272 device_printf((sc)->dev, \
2273 "%s(%s:%d) ERROR: " format, \
2279 device_printf((sc)->dev, \
2285 #ifdef ECORE_STOP_ON_ERROR
2287 #define bxe_panic(sc, msg) \
2294 #define bxe_panic(sc, msg) \
2295 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
2299 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2300 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2302 void bxe_dump_mem(struct bxe_softc *sc, char *tag,
2303 uint8_t *mem, uint32_t len);
2304 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
2305 struct mbuf *m, uint8_t contents);
2307 #if __FreeBSD_version >= 800000
2308 #if (__FreeBSD_version >= 1001513 && __FreeBSD_version < 1100000) ||\
2309 __FreeBSD_version >= 1100048
2310 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE)
2311 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
2313 #define BXE_VALID_FLOWID(m) ((m->m_flags & M_FLOWID) != 0)
2314 #define BXE_SET_FLOWID(m) m->m_flags |= M_FLOWID
2316 #endif /* #if __FreeBSD_version >= 800000 */
2322 static inline uint32_t
2323 reg_poll(struct bxe_softc *sc,
2332 val = REG_RD(sc, reg);
2333 if (val == expected) {
2344 bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
2346 mb(); /* status block is written to by the chip */
2347 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
2351 bxe_igu_ack_sb_gen(struct bxe_softc *sc,
2359 struct igu_regular cmd_data = {0};
2361 cmd_data.sb_id_and_flags =
2362 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
2363 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2364 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2365 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
2367 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2368 cmd_data.sb_id_and_flags, igu_addr);
2369 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2371 /* Make sure that ACK is written */
2372 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2373 BUS_SPACE_BARRIER_WRITE);
2378 bxe_hc_ack_sb(struct bxe_softc *sc,
2385 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2386 COMMAND_REG_INT_ACK);
2387 struct igu_ack_register igu_ack;
2389 igu_ack.status_block_index = index;
2390 igu_ack.sb_id_and_flags =
2391 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2392 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2393 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2394 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2396 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2398 /* Make sure that ACK is written */
2399 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2400 BUS_SPACE_BARRIER_WRITE);
2405 bxe_ack_sb(struct bxe_softc *sc,
2412 if (sc->devinfo.int_block == INT_BLOCK_HC)
2413 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
2416 if (CHIP_INT_MODE_IS_BC(sc)) {
2418 } else if (igu_sb_id != sc->igu_dsb_id) {
2419 segment = IGU_SEG_ACCESS_DEF;
2420 } else if (storm == ATTENTION_ID) {
2421 segment = IGU_SEG_ACCESS_ATTN;
2423 segment = IGU_SEG_ACCESS_DEF;
2425 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
2429 static inline uint16_t
2430 bxe_hc_ack_int(struct bxe_softc *sc)
2432 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2433 COMMAND_REG_SIMD_MASK);
2434 uint32_t result = REG_RD(sc, hc_addr);
2440 static inline uint16_t
2441 bxe_igu_ack_int(struct bxe_softc *sc)
2443 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
2444 uint32_t result = REG_RD(sc, igu_addr);
2446 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n",
2453 static inline uint16_t
2454 bxe_ack_int(struct bxe_softc *sc)
2457 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2458 return (bxe_hc_ack_int(sc));
2460 return (bxe_igu_ack_int(sc));
2465 func_by_vn(struct bxe_softc *sc,
2468 return (2 * vn + SC_PORT(sc));
2472 * Statistics ID are global per chip/path, while Client IDs for E1x
2475 static inline uint8_t
2476 bxe_stats_id(struct bxe_fastpath *fp)
2478 struct bxe_softc *sc = fp->sc;
2480 if (!CHIP_IS_E1x(sc)) {
2484 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
2487 #endif /* __BXE_H__ */