2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "bxe_elink.h"
32 #include "ecore_mfw_req.h"
33 #include "ecore_fw_defs.h"
34 #include "ecore_hsi.h"
35 #include "ecore_reg.h"
38 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
39 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
40 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
41 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
42 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
44 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
45 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
46 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
47 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
48 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
49 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
50 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
51 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
52 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
53 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
54 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
55 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
56 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
57 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
58 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
59 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
60 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
62 #define MDIO_REG_BANK_RX0 0x80b0
63 #define MDIO_RX0_RX_STATUS 0x10
64 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
65 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
66 #define MDIO_RX0_RX_EQ_BOOST 0x1c
67 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
68 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
70 #define MDIO_REG_BANK_RX1 0x80c0
71 #define MDIO_RX1_RX_EQ_BOOST 0x1c
72 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
73 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
75 #define MDIO_REG_BANK_RX2 0x80d0
76 #define MDIO_RX2_RX_EQ_BOOST 0x1c
77 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
78 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
80 #define MDIO_REG_BANK_RX3 0x80e0
81 #define MDIO_RX3_RX_EQ_BOOST 0x1c
82 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
83 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
85 #define MDIO_REG_BANK_RX_ALL 0x80f0
86 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
87 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
88 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
90 #define MDIO_REG_BANK_TX0 0x8060
91 #define MDIO_TX0_TX_DRIVER 0x17
92 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
93 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
94 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
95 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
96 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
97 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
98 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
99 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
100 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
102 #define MDIO_REG_BANK_TX1 0x8070
103 #define MDIO_TX1_TX_DRIVER 0x17
104 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
105 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
106 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
107 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
108 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
109 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
110 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
111 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
112 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
114 #define MDIO_REG_BANK_TX2 0x8080
115 #define MDIO_TX2_TX_DRIVER 0x17
116 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
117 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
118 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
119 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
120 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
121 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
122 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
123 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
124 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
126 #define MDIO_REG_BANK_TX3 0x8090
127 #define MDIO_TX3_TX_DRIVER 0x17
128 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
129 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
130 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
131 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
132 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
133 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
134 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
135 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
136 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
138 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
139 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
141 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
142 #define MDIO_BLOCK1_LANE_CTRL0 0x15
143 #define MDIO_BLOCK1_LANE_CTRL1 0x16
144 #define MDIO_BLOCK1_LANE_CTRL2 0x17
145 #define MDIO_BLOCK1_LANE_PRBS 0x19
147 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
148 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
149 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
150 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
151 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
152 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
153 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
154 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
155 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
156 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
158 #define MDIO_REG_BANK_GP_STATUS 0x8120
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
191 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
192 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
193 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
194 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
195 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
196 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
197 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
199 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
203 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
204 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
205 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
206 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
215 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
216 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
222 #define MDIO_SERDES_DIGITAL_MISC1 0x18
223 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
224 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
226 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
227 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
228 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
234 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
235 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
242 #define MDIO_REG_BANK_OVER_1G 0x8320
243 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
244 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
245 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
246 #define MDIO_OVER_1G_UP1 0x19
247 #define MDIO_OVER_1G_UP1_2_5G 0x0001
248 #define MDIO_OVER_1G_UP1_5G 0x0002
249 #define MDIO_OVER_1G_UP1_6G 0x0004
250 #define MDIO_OVER_1G_UP1_10G 0x0010
251 #define MDIO_OVER_1G_UP1_10GH 0x0008
252 #define MDIO_OVER_1G_UP1_12G 0x0020
253 #define MDIO_OVER_1G_UP1_12_5G 0x0040
254 #define MDIO_OVER_1G_UP1_13G 0x0080
255 #define MDIO_OVER_1G_UP1_15G 0x0100
256 #define MDIO_OVER_1G_UP1_16G 0x0200
257 #define MDIO_OVER_1G_UP2 0x1A
258 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
259 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
260 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
261 #define MDIO_OVER_1G_UP3 0x1B
262 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
263 #define MDIO_OVER_1G_LP_UP1 0x1C
264 #define MDIO_OVER_1G_LP_UP2 0x1D
265 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
266 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
267 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
268 #define MDIO_OVER_1G_LP_UP3 0x1E
270 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
271 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
272 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
273 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
275 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
276 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
277 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
278 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
280 #define MDIO_REG_BANK_CL73_USERB0 0x8370
281 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
282 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
283 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
284 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
285 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
286 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
287 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
288 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
289 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
290 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
291 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
293 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
294 #define MDIO_AER_BLOCK_AER_REG 0x1E
296 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
297 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
298 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
299 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
300 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
301 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
302 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
303 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
304 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
305 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
306 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
307 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
308 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
309 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
320 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
322 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
327 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
328 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
329 Theotherbitsarereservedandshouldbezero*/
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
333 #define MDIO_PMA_DEVAD 0x1
335 #define MDIO_PMA_REG_CTRL 0x0
336 #define MDIO_PMA_REG_STATUS 0x1
337 #define MDIO_PMA_REG_10G_CTRL2 0x7
338 #define MDIO_PMA_REG_TX_DISABLE 0x0009
339 #define MDIO_PMA_REG_RX_SD 0xa
341 #define MDIO_PMA_REG_BCM_CTRL 0x0096
342 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
343 #define MDIO_PMA_LASI_RXCTRL 0x9000
344 #define MDIO_PMA_LASI_TXCTRL 0x9001
345 #define MDIO_PMA_LASI_CTRL 0x9002
346 #define MDIO_PMA_LASI_RXSTAT 0x9003
347 #define MDIO_PMA_LASI_TXSTAT 0x9004
348 #define MDIO_PMA_LASI_STAT 0x9005
349 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
350 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
351 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
352 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
353 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
354 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
355 #define MDIO_PMA_REG_GEN_CTRL 0xca10
356 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
357 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
358 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
359 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
360 #define MDIO_PMA_REG_ROM_VER1 0xca19
361 #define MDIO_PMA_REG_ROM_VER2 0xca1a
362 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
363 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
364 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
365 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
366 #define MDIO_PMA_REG_LRM_MODE 0xca3f
367 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
368 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
370 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
371 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
372 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
373 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
374 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
375 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
376 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
378 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
379 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
380 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
381 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
383 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
384 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
385 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
386 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
388 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
389 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
390 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
391 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
392 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
394 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
395 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
396 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
397 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
398 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
400 #define MDIO_PMA_REG_7101_RESET 0xc000
401 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
402 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
403 #define MDIO_PMA_REG_7101_VER1 0xc026
404 #define MDIO_PMA_REG_7101_VER2 0xc027
406 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
407 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
408 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
409 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
410 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
411 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
412 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
413 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
414 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
415 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
419 #define MDIO_WIS_DEVAD 0x2
421 #define MDIO_WIS_REG_LASI_CNTL 0x9002
422 #define MDIO_WIS_REG_LASI_STATUS 0x9005
424 #define MDIO_PCS_DEVAD 0x3
425 #define MDIO_PCS_REG_STATUS 0x0020
426 #define MDIO_PCS_REG_LASI_STATUS 0x9005
427 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
428 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
429 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
430 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
431 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
432 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
433 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
434 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
435 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
439 #define MDIO_XS_DEVAD 0x4
440 #define MDIO_XS_REG_STATUS 0x0001
441 #define MDIO_XS_PLL_SEQUENCER 0x8000
442 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
444 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
445 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
446 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
447 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
448 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
450 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
452 #define MDIO_AN_DEVAD 0x7
454 #define MDIO_AN_REG_CTRL 0x0000
455 #define MDIO_AN_REG_STATUS 0x0001
456 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
457 #define MDIO_AN_REG_ADV_PAUSE 0x0010
458 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
459 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
460 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
461 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
462 #define MDIO_AN_REG_ADV 0x0011
463 #define MDIO_AN_REG_ADV2 0x0012
464 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
465 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
466 #define MDIO_AN_REG_MASTER_STATUS 0x0021
467 #define MDIO_AN_REG_EEE_ADV 0x003c
468 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
470 #define MDIO_AN_REG_LINK_STATUS 0x8304
471 #define MDIO_AN_REG_CL37_CL73 0x8370
472 #define MDIO_AN_REG_CL37_AN 0xffe0
473 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
474 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
475 #define MDIO_AN_REG_1000T_STATUS 0xffea
477 #define MDIO_AN_REG_8073_2_5G 0x8329
478 #define MDIO_AN_REG_8073_BAM 0x8350
480 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
481 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
482 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
483 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
484 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
485 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
486 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
487 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
488 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
489 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
490 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
491 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
492 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
495 #define MDIO_CTL_DEVAD 0x1e
496 #define MDIO_CTL_REG_84823_MEDIA 0x401a
497 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
498 /* These pins configure the BCM84823 interface to MAC after reset. */
499 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
500 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
501 /* These pins configure the BCM84823 interface to Line after reset. */
502 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
503 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
504 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
505 /* When this pin is active high during reset, 10GBASE-T core is power
506 * down, When it is active low the 10GBASE-T is power up
508 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
509 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
510 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
511 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
512 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
513 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
514 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
515 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
516 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
517 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
518 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
519 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
522 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
523 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
524 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
525 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
526 #define MDIO_84833_SUPER_ISOLATE 0x8000
527 /* These are mailbox register set used by 84833. */
528 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005
529 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006
530 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007
531 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008
532 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009
533 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037
534 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038
535 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039
536 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a
537 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b
538 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c
539 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0
540 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26
541 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27
542 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28
543 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29
544 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30
545 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31
547 /* Mailbox command set used by 84833. */
548 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001
549 #define PHY84833_CMD_GET_EEE_MODE 0x8008
550 #define PHY84833_CMD_SET_EEE_MODE 0x8009
551 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031
552 /* Mailbox status set used by 84833. */
553 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
554 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
555 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
556 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
557 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
558 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
559 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
560 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
561 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
564 /* Warpcore clause 45 addressing */
565 #define MDIO_WC_DEVAD 0x3
566 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
567 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
568 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
569 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
570 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
571 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
572 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
573 #define MDIO_WC_REG_PCS_STATUS2 0x0021
574 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
575 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
576 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
577 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
578 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
579 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
580 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
581 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
582 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
583 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
584 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
585 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
586 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
587 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
588 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
589 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
590 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
591 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
592 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
593 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
594 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
595 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
596 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
597 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
598 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
599 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
600 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
601 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
602 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
603 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
604 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
605 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
606 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
607 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
608 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
609 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
610 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
611 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
612 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
613 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
614 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
615 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
616 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
617 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
618 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
619 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
620 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
621 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
622 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
623 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
624 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
625 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
626 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
627 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
628 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
629 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
630 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
631 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
632 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
633 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
634 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
635 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
636 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
637 #define MDIO_WC_REG_DSC_SMC 0x8213
638 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
639 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
640 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
641 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
642 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
643 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
644 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
645 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
646 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
647 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
648 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
649 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
650 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
651 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
652 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
653 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
654 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
655 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
656 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
657 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
658 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
659 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
660 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
661 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
662 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
663 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
664 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
665 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
666 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
667 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
668 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
669 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
670 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
671 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
672 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
673 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
674 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
675 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
676 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
677 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
678 #define MDIO_WC_REG_RX66_SCW0 0x83c2
679 #define MDIO_WC_REG_RX66_SCW1 0x83c3
680 #define MDIO_WC_REG_RX66_SCW2 0x83c4
681 #define MDIO_WC_REG_RX66_SCW3 0x83c5
682 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
683 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
684 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
685 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
686 #define MDIO_WC_REG_FX100_CTRL1 0x8400
687 #define MDIO_WC_REG_FX100_CTRL3 0x8402
688 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
689 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
690 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
691 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
692 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
693 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
694 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
695 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
696 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
697 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
698 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
699 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
700 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
701 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
703 #define MDIO_WC_REG_AERBLK_AER 0xffde
704 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
705 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
707 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
708 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
709 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
711 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
713 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
716 #define MDIO_REG_GPHY_MII_STATUS 0x1
717 #define MDIO_REG_GPHY_PHYID_LSB 0x3
718 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
719 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
720 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
721 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
722 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
723 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
724 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
725 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
726 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
727 #define MDIO_REG_GPHY_AUX_STATUS 0x19
728 #define MDIO_REG_INTR_STATUS 0x1a
729 #define MDIO_REG_INTR_MASK 0x1b
730 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
731 #define MDIO_REG_GPHY_SHADOW 0x1c
732 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
733 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
734 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
735 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
736 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
739 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
740 struct elink_params *params,
741 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
742 uint8_t *o_buf, uint8_t);
743 /********************************************************/
744 #define ELINK_ETH_HLEN 14
745 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
746 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
747 #define ELINK_ETH_MIN_PACKET_SIZE 60
748 #define ELINK_ETH_MAX_PACKET_SIZE 1500
749 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
750 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
751 #define WC_LANE_MAX 4
752 #define I2C_SWITCH_WIDTH 2
755 #define I2C_WA_RETRY_CNT 3
756 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
757 #define MCPR_IMC_COMMAND_READ_OP 1
758 #define MCPR_IMC_COMMAND_WRITE_OP 2
760 /* LED Blink rate that will achieve ~15.9Hz */
761 #define LED_BLINK_RATE_VAL_E3 354
762 #define LED_BLINK_RATE_VAL_E1X_E2 480
763 /***********************************************************/
764 /* Shortcut definitions */
765 /***********************************************************/
767 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
769 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
770 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
771 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
772 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
773 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
774 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
775 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
776 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
777 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
778 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
779 #define ELINK_NIG_MASK_MI_INT \
780 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
781 #define ELINK_NIG_MASK_XGXS0_LINK10G \
782 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
783 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
784 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
785 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
786 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
788 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
789 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
790 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
792 #define ELINK_XGXS_RESET_BITS \
793 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
794 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
795 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
796 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
797 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
799 #define ELINK_SERDES_RESET_BITS \
800 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
801 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
802 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
803 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
805 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
806 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
807 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
808 #define ELINK_AUTONEG_PARALLEL \
809 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
810 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
811 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
812 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
814 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
815 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
816 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
817 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
818 #define ELINK_GP_STATUS_SPEED_MASK \
819 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
820 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
821 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
822 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
823 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
824 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
825 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
826 #define ELINK_GP_STATUS_10G_HIG \
827 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
828 #define ELINK_GP_STATUS_10G_CX4 \
829 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
830 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
831 #define ELINK_GP_STATUS_10G_KX4 \
832 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
833 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
834 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
835 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
836 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
837 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
838 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
839 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
840 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
841 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
842 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
843 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
844 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
845 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
846 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
847 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
848 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
849 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
850 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
851 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
852 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
854 #define ELINK_LINK_UPDATE_MASK \
855 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
856 LINK_STATUS_LINK_UP | \
857 LINK_STATUS_PHYSICAL_LINK_FLAG | \
858 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
859 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
860 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
861 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
862 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
863 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
865 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
866 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
867 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
868 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
871 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3
872 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
873 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
874 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
876 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
877 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
878 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
880 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
881 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
882 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
884 #define ELINK_EDC_MODE_LINEAR 0x0022
885 #define ELINK_EDC_MODE_LIMITING 0x0044
886 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
887 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
890 #define DCBX_INVALID_COS (0xFF)
892 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
893 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
894 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
895 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
896 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
898 #define ELINK_MAX_PACKET_SIZE (9700)
899 #define MAX_KR_LINK_RETRY 4
901 /**********************************************************/
903 /**********************************************************/
905 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
906 elink_cl45_write(_sc, _phy, \
907 (_phy)->def_md_devad, \
908 (_bank + (_addr & 0xf)), \
911 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
912 elink_cl45_read(_sc, _phy, \
913 (_phy)->def_md_devad, \
914 (_bank + (_addr & 0xf)), \
917 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
919 uint32_t val = REG_RD(sc, reg);
922 REG_WR(sc, reg, val);
926 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
928 uint32_t val = REG_RD(sc, reg);
931 REG_WR(sc, reg, val);
936 * elink_check_lfa - This function checks if link reinitialization is required,
937 * or link flap can be avoided.
939 * @params: link parameters
940 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
943 static int elink_check_lfa(struct elink_params *params)
945 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
946 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
947 uint32_t saved_val, req_val, eee_status;
948 struct bxe_softc *sc = params->sc;
951 REG_RD(sc, params->lfa_base +
952 offsetof(struct shmem_lfa, additional_config));
954 /* NOTE: must be first condition checked -
955 * to verify DCC bit is cleared in any case!
957 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
958 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n");
959 REG_WR(sc, params->lfa_base +
960 offsetof(struct shmem_lfa, additional_config),
961 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
962 return LFA_DCC_LFA_DISABLED;
965 /* Verify that link is up */
966 link_status = REG_RD(sc, params->shmem_base +
967 offsetof(struct shmem_region,
968 port_mb[params->port].link_status));
969 if (!(link_status & LINK_STATUS_LINK_UP))
970 return LFA_LINK_DOWN;
972 /* if loaded after BOOT from SAN, don't flap the link in any case and
973 * rely on link set by preboot driver
975 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
978 /* Verify that loopback mode is not set */
979 if (params->loopback_mode)
980 return LFA_LOOPBACK_ENABLED;
982 /* Verify that MFW supports LFA */
983 if (!params->lfa_base)
984 return LFA_MFW_IS_TOO_OLD;
986 if (params->num_phys == 3) {
988 lfa_mask = 0xffffffff;
995 saved_val = REG_RD(sc, params->lfa_base +
996 offsetof(struct shmem_lfa, req_duplex));
997 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
998 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
999 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n",
1000 (saved_val & lfa_mask), (req_val & lfa_mask));
1001 return LFA_DUPLEX_MISMATCH;
1003 /* Compare Flow Control */
1004 saved_val = REG_RD(sc, params->lfa_base +
1005 offsetof(struct shmem_lfa, req_flow_ctrl));
1006 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1007 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1008 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n",
1009 (saved_val & lfa_mask), (req_val & lfa_mask));
1010 return LFA_FLOW_CTRL_MISMATCH;
1012 /* Compare Link Speed */
1013 saved_val = REG_RD(sc, params->lfa_base +
1014 offsetof(struct shmem_lfa, req_line_speed));
1015 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1016 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1017 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n",
1018 (saved_val & lfa_mask), (req_val & lfa_mask));
1019 return LFA_LINK_SPEED_MISMATCH;
1022 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1023 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1024 offsetof(struct shmem_lfa,
1025 speed_cap_mask[cfg_idx]));
1027 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1028 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n",
1030 params->speed_cap_mask[cfg_idx]);
1031 return LFA_SPEED_CAP_MISMATCH;
1035 cur_req_fc_auto_adv =
1036 REG_RD(sc, params->lfa_base +
1037 offsetof(struct shmem_lfa, additional_config)) &
1038 REQ_FC_AUTO_ADV_MASK;
1040 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1041 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n",
1042 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1043 return LFA_FLOW_CTRL_MISMATCH;
1046 eee_status = REG_RD(sc, params->shmem2_base +
1047 offsetof(struct shmem2_region,
1048 eee_status[params->port]));
1050 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1051 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1052 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1053 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1054 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode,
1056 return LFA_EEE_MISMATCH;
1059 /* LFA conditions are met */
1062 /******************************************************************/
1063 /* EPIO/GPIO section */
1064 /******************************************************************/
1065 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en)
1067 uint32_t epio_mask, gp_oenable;
1070 if (epio_pin > 31) {
1071 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin);
1075 epio_mask = 1 << epio_pin;
1076 /* Set this EPIO to output */
1077 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1078 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1080 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1082 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en)
1084 uint32_t epio_mask, gp_output, gp_oenable;
1087 if (epio_pin > 31) {
1088 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin);
1091 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en);
1092 epio_mask = 1 << epio_pin;
1093 /* Set this EPIO to output */
1094 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1096 gp_output |= epio_mask;
1098 gp_output &= ~epio_mask;
1100 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1102 /* Set the value for this EPIO */
1103 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1104 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1107 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val)
1109 if (pin_cfg == PIN_CFG_NA)
1111 if (pin_cfg >= PIN_CFG_EPIO0) {
1112 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1114 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1115 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1116 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
1120 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val)
1122 if (pin_cfg == PIN_CFG_NA)
1123 return ELINK_STATUS_ERROR;
1124 if (pin_cfg >= PIN_CFG_EPIO0) {
1125 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1127 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1128 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1129 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1131 return ELINK_STATUS_OK;
1134 /******************************************************************/
1136 /******************************************************************/
1137 static void elink_ets_e2e3a0_disabled(struct elink_params *params)
1139 /* ETS disabled configuration*/
1140 struct bxe_softc *sc = params->sc;
1142 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n");
1144 /* mapping between entry priority to client number (0,1,2 -debug and
1145 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1147 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1148 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
1151 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1152 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1153 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1154 * COS0 entry, 4 - COS1 entry.
1155 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1156 * bit4 bit3 bit2 bit1 bit0
1157 * MCP and debug are strict
1160 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1161 /* defines which entries (clients) are subjected to WFQ arbitration */
1162 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1163 /* For strict priority entries defines the number of consecutive
1164 * slots for the highest priority.
1166 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1167 /* mapping between the CREDIT_WEIGHT registers and actual client
1170 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1171 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1172 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1174 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1175 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1176 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1177 /* ETS mode disable */
1178 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1179 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
1180 * weight for COS0/COS1.
1182 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1183 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1184 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
1185 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1186 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1187 /* Defines the number of consecutive slots for the strict priority */
1188 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1190 /******************************************************************************
1192 * Getting min_w_val will be set according to line speed .
1194 ******************************************************************************/
1195 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
1197 uint32_t min_w_val = 0;
1198 /* Calculate min_w_val.*/
1199 if (vars->link_up) {
1200 if (vars->line_speed == ELINK_SPEED_20000)
1201 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1203 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
1205 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1206 /* If the link isn't up (static configuration for example ) The
1207 * link will be according to 20GBPS.
1211 /******************************************************************************
1213 * Getting credit upper bound form min_w_val.
1215 ******************************************************************************/
1216 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
1218 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val),
1219 ELINK_MAX_PACKET_SIZE);
1220 return credit_upper_bound;
1222 /******************************************************************************
1224 * Set credit upper bound for NIG.
1226 ******************************************************************************/
1227 static void elink_ets_e3b0_set_credit_upper_bound_nig(
1228 const struct elink_params *params,
1229 const uint32_t min_w_val)
1231 struct bxe_softc *sc = params->sc;
1232 const uint8_t port = params->port;
1233 const uint32_t credit_upper_bound =
1234 elink_ets_get_credit_upper_bound(min_w_val);
1236 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1237 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
1238 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1239 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
1240 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1241 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
1242 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1243 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
1244 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1245 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
1246 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1247 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
1250 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1251 credit_upper_bound);
1252 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1253 credit_upper_bound);
1254 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1255 credit_upper_bound);
1258 /******************************************************************************
1260 * Will return the NIG ETS registers to init values.Except
1261 * credit_upper_bound.
1262 * That isn't used in this configuration (No WFQ is enabled) and will be
1263 * configured acording to spec
1265 ******************************************************************************/
1266 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
1267 const struct elink_vars *vars)
1269 struct bxe_softc *sc = params->sc;
1270 const uint8_t port = params->port;
1271 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
1272 /* Mapping between entry priority to client number (0,1,2 -debug and
1273 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
1274 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
1275 * reset value or init tool
1278 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1279 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1281 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1282 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1284 /* For strict priority entries defines the number of consecutive
1285 * slots for the highest priority.
1287 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1288 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1289 /* Mapping between the CREDIT_WEIGHT registers and actual client
1293 /*Port 1 has 6 COS*/
1294 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1295 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1297 /*Port 0 has 9 COS*/
1298 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1300 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1303 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1304 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1305 * COS0 entry, 4 - COS1 entry.
1306 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1307 * bit4 bit3 bit2 bit1 bit0
1308 * MCP and debug are strict
1311 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1313 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1314 /* defines which entries (clients) are subjected to WFQ arbitration */
1315 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1316 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1318 /* Please notice the register address are note continuous and a
1319 * for here is note appropriate.In 2 port mode port0 only COS0-5
1320 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
1321 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1322 * are never used for WFQ
1324 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1325 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
1326 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1327 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
1328 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1329 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
1330 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1331 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
1332 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1333 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
1334 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1335 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
1337 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1338 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1339 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1342 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
1344 /******************************************************************************
1346 * Set credit upper bound for PBF.
1348 ******************************************************************************/
1349 static void elink_ets_e3b0_set_credit_upper_bound_pbf(
1350 const struct elink_params *params,
1351 const uint32_t min_w_val)
1353 struct bxe_softc *sc = params->sc;
1354 const uint32_t credit_upper_bound =
1355 elink_ets_get_credit_upper_bound(min_w_val);
1356 const uint8_t port = params->port;
1357 uint32_t base_upper_bound = 0;
1358 uint8_t max_cos = 0;
1360 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1361 * port mode port1 has COS0-2 that can be used for WFQ.
1364 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
1365 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1367 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
1368 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1371 for (i = 0; i < max_cos; i++)
1372 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1375 /******************************************************************************
1377 * Will return the PBF ETS registers to init values.Except
1378 * credit_upper_bound.
1379 * That isn't used in this configuration (No WFQ is enabled) and will be
1380 * configured acording to spec
1382 ******************************************************************************/
1383 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
1385 struct bxe_softc *sc = params->sc;
1386 const uint8_t port = params->port;
1387 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1389 uint32_t base_weight = 0;
1390 uint8_t max_cos = 0;
1392 /* Mapping between entry priority to client number 0 - COS0
1393 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
1394 * TODO_ETS - Should be done by reset value or init tool
1397 /* 0x688 (|011|0 10|00 1|000) */
1398 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1400 /* (10 1|100 |011|0 10|00 1|000) */
1401 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1403 /* TODO_ETS - Should be done by reset value or init tool */
1405 /* 0x688 (|011|0 10|00 1|000)*/
1406 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1408 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
1409 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1411 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1412 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
1415 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1416 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
1418 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1419 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
1420 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1421 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1424 base_weight = PBF_REG_COS0_WEIGHT_P0;
1425 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1427 base_weight = PBF_REG_COS0_WEIGHT_P1;
1428 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1431 for (i = 0; i < max_cos; i++)
1432 REG_WR(sc, base_weight + (0x4 * i), 0);
1434 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1436 /******************************************************************************
1438 * E3B0 disable will return basicly the values to init values.
1440 ******************************************************************************/
1441 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
1442 const struct elink_vars *vars)
1444 struct bxe_softc *sc = params->sc;
1446 if (!CHIP_IS_E3B0(sc)) {
1448 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1449 return ELINK_STATUS_ERROR;
1452 elink_ets_e3b0_nig_disabled(params, vars);
1454 elink_ets_e3b0_pbf_disabled(params);
1456 return ELINK_STATUS_OK;
1459 /******************************************************************************
1461 * Disable will return basicly the values to init values.
1463 ******************************************************************************/
1464 elink_status_t elink_ets_disabled(struct elink_params *params,
1465 struct elink_vars *vars)
1467 struct bxe_softc *sc = params->sc;
1468 elink_status_t elink_status = ELINK_STATUS_OK;
1470 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc)))
1471 elink_ets_e2e3a0_disabled(params);
1472 else if (CHIP_IS_E3B0(sc))
1473 elink_status = elink_ets_e3b0_disabled(params, vars);
1475 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n");
1476 return ELINK_STATUS_ERROR;
1479 return elink_status;
1482 /******************************************************************************
1484 * Set the COS mappimg to SP and BW until this point all the COS are not
1486 ******************************************************************************/
1487 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
1488 const struct elink_ets_params *ets_params,
1489 const uint8_t cos_sp_bitmap,
1490 const uint8_t cos_bw_bitmap)
1492 struct bxe_softc *sc = params->sc;
1493 const uint8_t port = params->port;
1494 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
1495 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
1496 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
1497 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
1499 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1500 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
1502 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1503 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
1505 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1506 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1507 nig_cli_subject2wfq_bitmap);
1509 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1510 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
1511 pbf_cli_subject2wfq_bitmap);
1513 return ELINK_STATUS_OK;
1516 /******************************************************************************
1518 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1519 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1520 ******************************************************************************/
1521 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc,
1522 const uint8_t cos_entry,
1523 const uint32_t min_w_val_nig,
1524 const uint32_t min_w_val_pbf,
1525 const uint16_t total_bw,
1529 uint32_t nig_reg_adress_crd_weight = 0;
1530 uint32_t pbf_reg_adress_crd_weight = 0;
1531 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
1532 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
1533 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
1535 switch (cos_entry) {
1537 nig_reg_adress_crd_weight =
1538 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1539 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
1540 pbf_reg_adress_crd_weight = (port) ?
1541 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
1544 nig_reg_adress_crd_weight = (port) ?
1545 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1546 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
1547 pbf_reg_adress_crd_weight = (port) ?
1548 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
1551 nig_reg_adress_crd_weight = (port) ?
1552 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1553 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
1555 pbf_reg_adress_crd_weight = (port) ?
1556 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
1560 return ELINK_STATUS_ERROR;
1561 nig_reg_adress_crd_weight =
1562 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
1563 pbf_reg_adress_crd_weight =
1564 PBF_REG_COS3_WEIGHT_P0;
1568 return ELINK_STATUS_ERROR;
1569 nig_reg_adress_crd_weight =
1570 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
1571 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
1575 return ELINK_STATUS_ERROR;
1576 nig_reg_adress_crd_weight =
1577 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
1578 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
1582 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1584 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1586 return ELINK_STATUS_OK;
1588 /******************************************************************************
1590 * Calculate the total BW.A value of 0 isn't legal.
1592 ******************************************************************************/
1593 static elink_status_t elink_ets_e3b0_get_total_bw(
1594 const struct elink_params *params,
1595 struct elink_ets_params *ets_params,
1598 struct bxe_softc *sc = params->sc;
1599 uint8_t cos_idx = 0;
1600 uint8_t is_bw_cos_exist = 0;
1603 /* Calculate total BW requested */
1604 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
1605 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
1606 is_bw_cos_exist = 1;
1607 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
1608 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
1610 /* This is to prevent a state when ramrods
1613 ets_params->cos[cos_idx].params.bw_params.bw
1617 ets_params->cos[cos_idx].params.bw_params.bw;
1621 /* Check total BW is valid */
1622 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
1623 if (*total_bw == 0) {
1625 "elink_ets_E3B0_config total BW shouldn't be 0\n");
1626 return ELINK_STATUS_ERROR;
1629 "elink_ets_E3B0_config total BW should be 100\n");
1630 /* We can handle a case whre the BW isn't 100 this can happen
1631 * if the TC are joined.
1634 return ELINK_STATUS_OK;
1637 /******************************************************************************
1639 * Invalidate all the sp_pri_to_cos.
1641 ******************************************************************************/
1642 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
1645 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
1646 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
1648 /******************************************************************************
1650 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1651 * according to sp_pri_to_cos.
1653 ******************************************************************************/
1654 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
1655 uint8_t *sp_pri_to_cos, const uint8_t pri,
1656 const uint8_t cos_entry)
1658 struct bxe_softc *sc = params->sc;
1659 const uint8_t port = params->port;
1660 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1661 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1663 if (pri >= max_num_of_cos) {
1664 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1665 "parameter Illegal strict priority\n");
1666 return ELINK_STATUS_ERROR;
1669 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
1670 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1671 "parameter There can't be two COS's with "
1672 "the same strict pri\n");
1673 return ELINK_STATUS_ERROR;
1676 sp_pri_to_cos[pri] = cos_entry;
1677 return ELINK_STATUS_OK;
1681 /******************************************************************************
1683 * Returns the correct value according to COS and priority in
1684 * the sp_pri_cli register.
1686 ******************************************************************************/
1687 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset,
1688 const uint8_t pri_set,
1689 const uint8_t pri_offset,
1690 const uint8_t entry_size)
1692 uint64_t pri_cli_nig = 0;
1693 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
1694 (pri_set + pri_offset));
1698 /******************************************************************************
1700 * Returns the correct value according to COS and priority in the
1701 * sp_pri_cli register for NIG.
1703 ******************************************************************************/
1704 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set)
1706 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1707 const uint8_t nig_cos_offset = 3;
1708 const uint8_t nig_pri_offset = 3;
1710 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1714 /******************************************************************************
1716 * Returns the correct value according to COS and priority in the
1717 * sp_pri_cli register for PBF.
1719 ******************************************************************************/
1720 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set)
1722 const uint8_t pbf_cos_offset = 0;
1723 const uint8_t pbf_pri_offset = 0;
1725 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1730 /******************************************************************************
1732 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1733 * according to sp_pri_to_cos.(which COS has higher priority)
1735 ******************************************************************************/
1736 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
1737 uint8_t *sp_pri_to_cos)
1739 struct bxe_softc *sc = params->sc;
1741 const uint8_t port = params->port;
1742 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1743 uint64_t pri_cli_nig = 0x210;
1744 uint32_t pri_cli_pbf = 0x0;
1745 uint8_t pri_set = 0;
1746 uint8_t pri_bitmask = 0;
1747 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1748 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1750 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
1752 /* Set all the strict priority first */
1753 for (i = 0; i < max_num_of_cos; i++) {
1754 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1755 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
1757 "elink_ets_e3b0_sp_set_pri_cli_reg "
1758 "invalid cos entry\n");
1759 return ELINK_STATUS_ERROR;
1762 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1763 sp_pri_to_cos[i], pri_set);
1765 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1766 sp_pri_to_cos[i], pri_set);
1767 pri_bitmask = 1 << sp_pri_to_cos[i];
1768 /* COS is used remove it from bitmap.*/
1769 if (!(pri_bitmask & cos_bit_to_set)) {
1771 "elink_ets_e3b0_sp_set_pri_cli_reg "
1772 "invalid There can't be two COS's with"
1773 " the same strict pri\n");
1774 return ELINK_STATUS_ERROR;
1776 cos_bit_to_set &= ~pri_bitmask;
1781 /* Set all the Non strict priority i= COS*/
1782 for (i = 0; i < max_num_of_cos; i++) {
1783 pri_bitmask = 1 << i;
1784 /* Check if COS was already used for SP */
1785 if (pri_bitmask & cos_bit_to_set) {
1786 /* COS wasn't used for SP */
1787 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1790 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1792 /* COS is used remove it from bitmap.*/
1793 cos_bit_to_set &= ~pri_bitmask;
1798 if (pri_set != max_num_of_cos) {
1799 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1800 "entries were set\n");
1801 return ELINK_STATUS_ERROR;
1805 /* Only 6 usable clients*/
1806 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1807 (uint32_t)pri_cli_nig);
1809 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1811 /* Only 9 usable clients*/
1812 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig);
1813 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);
1815 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1817 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1820 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1822 return ELINK_STATUS_OK;
1825 /******************************************************************************
1827 * Configure the COS to ETS according to BW and SP settings.
1828 ******************************************************************************/
1829 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
1830 const struct elink_vars *vars,
1831 struct elink_ets_params *ets_params)
1833 struct bxe_softc *sc = params->sc;
1834 elink_status_t elink_status = ELINK_STATUS_OK;
1835 const uint8_t port = params->port;
1836 uint16_t total_bw = 0;
1837 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
1838 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1839 uint8_t cos_bw_bitmap = 0;
1840 uint8_t cos_sp_bitmap = 0;
1841 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
1842 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1843 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1844 uint8_t cos_entry = 0;
1846 if (!CHIP_IS_E3B0(sc)) {
1848 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1849 return ELINK_STATUS_ERROR;
1852 if ((ets_params->num_of_cos > max_num_of_cos)) {
1853 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
1854 "isn't supported\n");
1855 return ELINK_STATUS_ERROR;
1858 /* Prepare sp strict priority parameters*/
1859 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1861 /* Prepare BW parameters*/
1862 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
1864 if (elink_status != ELINK_STATUS_OK) {
1866 "elink_ets_E3B0_config get_total_bw failed\n");
1867 return ELINK_STATUS_ERROR;
1870 /* Upper bound is set according to current link speed (min_w_val
1871 * should be the same for upper bound and COS credit val).
1873 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1874 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1877 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1878 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
1879 cos_bw_bitmap |= (1 << cos_entry);
1880 /* The function also sets the BW in HW(not the mappin
1883 elink_status = elink_ets_e3b0_set_cos_bw(
1884 sc, cos_entry, min_w_val_nig, min_w_val_pbf,
1886 ets_params->cos[cos_entry].params.bw_params.bw,
1888 } else if (elink_cos_state_strict ==
1889 ets_params->cos[cos_entry].state){
1890 cos_sp_bitmap |= (1 << cos_entry);
1892 elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
1895 ets_params->cos[cos_entry].params.sp_params.pri,
1900 "elink_ets_e3b0_config cos state not valid\n");
1901 return ELINK_STATUS_ERROR;
1903 if (elink_status != ELINK_STATUS_OK) {
1905 "elink_ets_e3b0_config set cos bw failed\n");
1906 return elink_status;
1910 /* Set SP register (which COS has higher priority) */
1911 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
1914 if (elink_status != ELINK_STATUS_OK) {
1916 "elink_ets_E3B0_config set_pri_cli_reg failed\n");
1917 return elink_status;
1920 /* Set client mapping of BW and strict */
1921 elink_status = elink_ets_e3b0_cli_map(params, ets_params,
1925 if (elink_status != ELINK_STATUS_OK) {
1926 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n");
1927 return elink_status;
1929 return ELINK_STATUS_OK;
1931 static void elink_ets_bw_limit_common(const struct elink_params *params)
1933 /* ETS disabled configuration */
1934 struct bxe_softc *sc = params->sc;
1935 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1936 /* Defines which entries (clients) are subjected to WFQ arbitration
1940 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1941 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1942 * client numbers (WEIGHT_0 does not actually have to represent
1944 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1945 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1947 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1949 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1950 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1951 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1952 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1954 /* ETS mode enabled*/
1955 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1957 /* Defines the number of consecutive slots for the strict priority */
1958 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1959 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1960 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1961 * entry, 4 - COS1 entry.
1962 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1963 * bit4 bit3 bit2 bit1 bit0
1964 * MCP and debug are strict
1966 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1968 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1969 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
1970 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1971 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
1972 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1975 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
1976 const uint32_t cos1_bw)
1978 /* ETS disabled configuration*/
1979 struct bxe_softc *sc = params->sc;
1980 const uint32_t total_bw = cos0_bw + cos1_bw;
1981 uint32_t cos0_credit_weight = 0;
1982 uint32_t cos1_credit_weight = 0;
1984 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1989 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n");
1993 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
1995 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
1998 elink_ets_bw_limit_common(params);
2000 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2001 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2003 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2004 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2007 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos)
2009 /* ETS disabled configuration*/
2010 struct bxe_softc *sc = params->sc;
2013 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n");
2014 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2015 * as strict. Bits 0,1,2 - debug and management entries,
2016 * 3 - COS0 entry, 4 - COS1 entry.
2017 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
2018 * bit4 bit3 bit2 bit1 bit0
2019 * MCP and debug are strict
2021 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2022 /* For strict priority entries defines the number of consecutive slots
2023 * for the highest priority.
2025 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2026 /* ETS mode disable */
2027 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2028 /* Defines the number of consecutive slots for the strict priority */
2029 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2031 /* Defines the number of consecutive slots for the strict priority */
2032 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2034 /* Mapping between entry priority to client number (0,1,2 -debug and
2035 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
2037 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
2038 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
2039 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
2041 val = (!strict_cos) ? 0x2318 : 0x22E0;
2042 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2044 return ELINK_STATUS_OK;
2047 /******************************************************************/
2049 /******************************************************************/
2050 static void elink_update_pfc_xmac(struct elink_params *params,
2051 struct elink_vars *vars,
2054 struct bxe_softc *sc = params->sc;
2056 uint32_t pause_val, pfc0_val, pfc1_val;
2058 /* XMAC base adrr */
2059 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2061 /* Initialize pause and pfc registers */
2062 pause_val = 0x18000;
2063 pfc0_val = 0xFFFF8000;
2066 /* No PFC support */
2067 if (!(params->feature_config_flags &
2068 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2070 /* RX flow control - Process pause frame in receive direction
2072 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2073 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
2075 /* TX flow control - Send pause packet when buffer is full */
2076 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2077 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
2078 } else {/* PFC support */
2079 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
2080 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
2081 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
2082 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
2083 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2084 /* Write pause and PFC registers */
2085 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2086 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2087 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2088 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2092 /* Write pause and PFC registers */
2093 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2094 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2095 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2098 /* Set MAC address for source TX Pause/PFC frames */
2099 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2100 ((params->mac_addr[2] << 24) |
2101 (params->mac_addr[3] << 16) |
2102 (params->mac_addr[4] << 8) |
2103 (params->mac_addr[5])));
2104 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2105 ((params->mac_addr[0] << 8) |
2106 (params->mac_addr[1])));
2112 static void elink_emac_get_pfc_stat(struct elink_params *params,
2113 uint32_t pfc_frames_sent[2],
2114 uint32_t pfc_frames_received[2])
2116 /* Read pfc statistic */
2117 struct bxe_softc *sc = params->sc;
2118 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2119 uint32_t val_xon = 0;
2120 uint32_t val_xoff = 0;
2122 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n");
2124 /* PFC received frames */
2125 val_xoff = REG_RD(sc, emac_base +
2126 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
2127 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
2128 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2129 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
2131 pfc_frames_received[0] = val_xon + val_xoff;
2133 /* PFC received sent */
2134 val_xoff = REG_RD(sc, emac_base +
2135 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
2136 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
2137 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2138 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
2140 pfc_frames_sent[0] = val_xon + val_xoff;
2143 /* Read pfc statistic*/
2144 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
2145 uint32_t pfc_frames_sent[2],
2146 uint32_t pfc_frames_received[2])
2148 /* Read pfc statistic */
2149 struct bxe_softc *sc = params->sc;
2151 ELINK_DEBUG_P0(sc, "pfc statistic\n");
2156 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
2157 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n");
2158 elink_emac_get_pfc_stat(params, pfc_frames_sent,
2159 pfc_frames_received);
2162 /******************************************************************/
2163 /* MAC/PBF section */
2164 /******************************************************************/
2165 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id,
2168 uint32_t new_mode, cur_mode;
2170 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
2171 * (a value of 49==0x31) and make sure that the AUTO poll is off
2173 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2175 if (USES_WARPCORE(sc))
2176 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2178 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2180 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
2181 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
2184 new_mode = cur_mode &
2185 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
2186 new_mode |= clc_cnt;
2187 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
2189 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",
2190 cur_mode, new_mode);
2191 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2195 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc,
2196 struct elink_params *params)
2199 /* Set mdio clock per phy */
2200 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
2202 elink_set_mdio_clk(sc, params->chip_id,
2203 params->phy[phy_index].mdio_ctrl);
2206 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc)
2208 uint32_t port4mode_ovwr_val;
2209 /* Check 4-port override enabled */
2210 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2211 if (port4mode_ovwr_val & (1<<0)) {
2212 /* Return 4-port mode override value */
2213 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
2215 /* Return 4-port mode from input pin */
2216 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2219 static void elink_emac_init(struct elink_params *params,
2220 struct elink_vars *vars)
2222 /* reset and unreset the emac core */
2223 struct bxe_softc *sc = params->sc;
2224 uint8_t port = params->port;
2225 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2229 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2230 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2232 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2233 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2235 /* init emac - use read-modify-write */
2236 /* self clear reset */
2237 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2238 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2242 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2243 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val);
2245 ELINK_DEBUG_P0(sc, "EMAC timeout!\n");
2249 } while (val & EMAC_MODE_RESET);
2251 elink_set_mdio_emac_per_phy(sc, params);
2252 /* Set mac address */
2253 val = ((params->mac_addr[0] << 8) |
2254 params->mac_addr[1]);
2255 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
2257 val = ((params->mac_addr[2] << 24) |
2258 (params->mac_addr[3] << 16) |
2259 (params->mac_addr[4] << 8) |
2260 params->mac_addr[5]);
2261 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
2264 static void elink_set_xumac_nig(struct elink_params *params,
2265 uint16_t tx_pause_en,
2268 struct bxe_softc *sc = params->sc;
2270 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2272 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2274 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2275 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
2278 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
2280 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2282 struct bxe_softc *sc = params->sc;
2283 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2284 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2286 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2288 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
2289 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2291 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
2292 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2293 /* Disable RX and TX */
2294 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2297 static void elink_umac_enable(struct elink_params *params,
2298 struct elink_vars *vars, uint8_t lb)
2301 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2302 struct bxe_softc *sc = params->sc;
2304 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2305 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2308 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2309 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2311 ELINK_DEBUG_P0(sc, "enabling UMAC\n");
2313 /* This register opens the gate for the UMAC despite its name */
2314 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2316 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
2317 UMAC_COMMAND_CONFIG_REG_PAD_EN |
2318 UMAC_COMMAND_CONFIG_REG_SW_RESET |
2319 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
2320 switch (vars->line_speed) {
2321 case ELINK_SPEED_10:
2324 case ELINK_SPEED_100:
2327 case ELINK_SPEED_1000:
2330 case ELINK_SPEED_2500:
2334 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n",
2338 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2339 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
2341 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2342 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
2344 if (vars->duplex == DUPLEX_HALF)
2345 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
2347 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2350 /* Configure UMAC for EEE */
2351 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2352 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n");
2353 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2354 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
2355 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2357 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2360 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
2361 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2362 ((params->mac_addr[2] << 24) |
2363 (params->mac_addr[3] << 16) |
2364 (params->mac_addr[4] << 8) |
2365 (params->mac_addr[5])));
2366 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2367 ((params->mac_addr[0] << 8) |
2368 (params->mac_addr[1])));
2370 /* Enable RX and TX */
2371 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
2372 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
2373 UMAC_COMMAND_CONFIG_REG_RX_ENA;
2374 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2377 /* Remove SW Reset */
2378 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
2380 /* Check loopback mode */
2382 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
2383 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2385 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
2386 * length used by the MAC receive logic to check frames.
2388 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2389 elink_set_xumac_nig(params,
2390 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2391 vars->mac_type = ELINK_MAC_TYPE_UMAC;
2395 /* Define the XMAC mode */
2396 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
2398 struct bxe_softc *sc = params->sc;
2399 uint32_t is_port4mode = elink_is_4_port_mode(sc);
2401 /* In 4-port mode, need to set the mode only once, so if XMAC is
2402 * already out of reset, it means the mode has already been set,
2403 * and it must not* reset the XMAC again, since it controls both
2407 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
2408 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
2409 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
2411 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2412 MISC_REGISTERS_RESET_REG_2_XMAC)) {
2414 "XMAC already out of reset in 4-port mode\n");
2419 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2420 MISC_REGISTERS_RESET_REG_2_XMAC);
2423 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2424 MISC_REGISTERS_RESET_REG_2_XMAC);
2426 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n");
2428 /* Set the number of ports on the system side to up to 2 */
2429 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2431 /* Set the number of ports on the Warp Core to 10G */
2432 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2434 /* Set the number of ports on the system side to 1 */
2435 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2436 if (max_speed == ELINK_SPEED_10000) {
2438 "Init XMAC to 10G x 1 port per path\n");
2439 /* Set the number of ports on the Warp Core to 10G */
2440 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2443 "Init XMAC to 20G x 2 ports per path\n");
2444 /* Set the number of ports on the Warp Core to 20G */
2445 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2449 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2450 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2454 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2458 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
2460 uint8_t port = params->port;
2461 struct bxe_softc *sc = params->sc;
2462 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2465 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2466 MISC_REGISTERS_RESET_REG_2_XMAC) {
2467 /* Send an indication to change the state in the NIG back to XON
2468 * Clearing this bit enables the next set of this bit to get
2471 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2472 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2473 (pfc_ctrl & ~(1<<1)));
2474 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2475 (pfc_ctrl | (1<<1)));
2476 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2477 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2479 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2481 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2482 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2486 static elink_status_t elink_xmac_enable(struct elink_params *params,
2487 struct elink_vars *vars, uint8_t lb)
2489 uint32_t val, xmac_base;
2490 struct bxe_softc *sc = params->sc;
2491 ELINK_DEBUG_P0(sc, "enabling XMAC\n");
2493 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2495 elink_xmac_init(params, vars->line_speed);
2497 /* This register determines on which events the MAC will assert
2498 * error on the i/f to the NIG along w/ EOP.
2501 /* This register tells the NIG whether to send traffic to UMAC
2504 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2506 /* When XMAC is in XLGMII mode, disable sending idles for fault
2509 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2510 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2511 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
2512 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
2513 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2514 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2515 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
2516 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
2518 /* Set Max packet size */
2519 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2521 /* CRC append for Tx packets */
2522 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2525 elink_update_pfc_xmac(params, vars, 0);
2527 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2528 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n");
2529 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2530 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2532 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2535 /* Enable TX and RX */
2536 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
2538 /* Set MAC in XLGMII mode for dual-mode */
2539 if ((vars->line_speed == ELINK_SPEED_20000) &&
2540 (params->phy[ELINK_INT_PHY].supported &
2541 ELINK_SUPPORTED_20000baseKR2_Full))
2542 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
2544 /* Check loopback mode */
2546 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
2547 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2548 elink_set_xumac_nig(params,
2549 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2551 vars->mac_type = ELINK_MAC_TYPE_XMAC;
2553 return ELINK_STATUS_OK;
2556 static elink_status_t elink_emac_enable(struct elink_params *params,
2557 struct elink_vars *vars, uint8_t lb)
2559 struct bxe_softc *sc = params->sc;
2560 uint8_t port = params->port;
2561 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2564 ELINK_DEBUG_P0(sc, "enabling EMAC\n");
2567 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2568 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2570 /* enable emac and not bmac */
2571 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2573 #ifdef ELINK_INCLUDE_EMUL
2575 if (CHIP_REV_IS_EMUL(sc)) {
2576 /* Use lane 1 (of lanes 0-3) */
2577 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2578 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2583 #ifdef ELINK_INCLUDE_FPGA
2584 if (CHIP_REV_IS_FPGA(sc)) {
2585 /* Use lane 1 (of lanes 0-3) */
2586 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n");
2588 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2589 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2593 if (vars->phy_flags & PHY_XGXS_FLAG) {
2594 uint32_t ser_lane = ((params->lane_config &
2595 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2596 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2598 ELINK_DEBUG_P0(sc, "XGXS\n");
2599 /* select the master lanes (out of 0-3) */
2600 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2602 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2604 } else { /* SerDes */
2605 ELINK_DEBUG_P0(sc, "SerDes\n");
2607 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2610 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2611 EMAC_RX_MODE_RESET);
2612 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2613 EMAC_TX_MODE_RESET);
2615 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2616 if (CHIP_REV_IS_SLOW(sc)) {
2617 /* config GMII mode */
2618 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2619 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2622 /* pause enable/disable */
2623 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2624 EMAC_RX_MODE_FLOW_EN);
2626 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2627 (EMAC_TX_MODE_EXT_PAUSE_EN |
2628 EMAC_TX_MODE_FLOW_EN));
2629 if (!(params->feature_config_flags &
2630 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2631 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2632 elink_bits_en(sc, emac_base +
2633 EMAC_REG_EMAC_RX_MODE,
2634 EMAC_RX_MODE_FLOW_EN);
2636 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2637 elink_bits_en(sc, emac_base +
2638 EMAC_REG_EMAC_TX_MODE,
2639 (EMAC_TX_MODE_EXT_PAUSE_EN |
2640 EMAC_TX_MODE_FLOW_EN));
2642 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2643 EMAC_TX_MODE_FLOW_EN);
2644 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2648 /* KEEP_VLAN_TAG, promiscuous */
2649 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2650 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2652 /* Setting this bit causes MAC control frames (except for pause
2653 * frames) to be passed on for processing. This setting has no
2654 * affect on the operation of the pause frames. This bit effects
2655 * all packets regardless of RX Parser packet sorting logic.
2656 * Turn the PFC off to make sure we are in Xon state before
2659 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
2660 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2661 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2662 /* Enable PFC again */
2663 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
2664 EMAC_REG_RX_PFC_MODE_RX_EN |
2665 EMAC_REG_RX_PFC_MODE_TX_EN |
2666 EMAC_REG_RX_PFC_MODE_PRIORITIES);
2668 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
2670 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
2672 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
2673 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
2675 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
2678 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2683 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
2686 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2688 /* Enable emac for jumbo packets */
2689 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
2690 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2691 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
2694 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2696 /* Disable the NIG in/out to the bmac */
2697 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2698 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2699 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2701 /* Enable the NIG in/out to the emac */
2702 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2704 if ((params->feature_config_flags &
2705 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2706 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2709 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2710 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2712 #ifdef ELINK_INCLUDE_EMUL
2713 if (CHIP_REV_IS_EMUL(sc)) {
2714 /* Take the BigMac out of reset */
2715 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2716 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2718 /* Enable access for bmac registers */
2719 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2722 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2724 vars->mac_type = ELINK_MAC_TYPE_EMAC;
2725 return ELINK_STATUS_OK;
2728 static void elink_update_pfc_bmac1(struct elink_params *params,
2729 struct elink_vars *vars)
2731 uint32_t wb_data[2];
2732 struct bxe_softc *sc = params->sc;
2733 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2734 NIG_REG_INGRESS_BMAC0_MEM;
2736 uint32_t val = 0x14;
2737 if ((!(params->feature_config_flags &
2738 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2739 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2740 /* Enable BigMAC to react on received Pause packets */
2744 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2748 if (!(params->feature_config_flags &
2749 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2750 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2754 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2757 static void elink_update_pfc_bmac2(struct elink_params *params,
2758 struct elink_vars *vars,
2761 /* Set rx control: Strip CRC and enable BigMAC to relay
2762 * control packets to the system as well
2764 uint32_t wb_data[2];
2765 struct bxe_softc *sc = params->sc;
2766 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2767 NIG_REG_INGRESS_BMAC0_MEM;
2768 uint32_t val = 0x14;
2770 if ((!(params->feature_config_flags &
2771 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2772 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2773 /* Enable BigMAC to react on received Pause packets */
2777 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2782 if (!(params->feature_config_flags &
2783 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2784 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2788 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2790 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2791 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2792 /* Enable PFC RX & TX & STATS and set 8 COS */
2794 wb_data[0] |= (1<<0); /* RX */
2795 wb_data[0] |= (1<<1); /* TX */
2796 wb_data[0] |= (1<<2); /* Force initial Xon */
2797 wb_data[0] |= (1<<3); /* 8 cos */
2798 wb_data[0] |= (1<<5); /* STATS */
2800 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2802 /* Clear the force Xon */
2803 wb_data[0] &= ~(1<<2);
2805 ELINK_DEBUG_P0(sc, "PFC is disabled\n");
2806 /* Disable PFC RX & TX & STATS and set 8 COS */
2811 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2813 /* Set Time (based unit is 512 bit time) between automatic
2814 * re-sending of PP packets amd enable automatic re-send of
2815 * Per-Priroity Packet as long as pp_gen is asserted and
2816 * pp_disable is low.
2819 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2820 val |= (1<<16); /* enable automatic re-send */
2824 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2828 val = 0x3; /* Enable RX and TX */
2830 val |= 0x4; /* Local loopback */
2831 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
2833 /* When PFC enabled, Pass pause frames towards the NIG. */
2834 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2835 val |= ((1<<6)|(1<<5));
2839 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2842 /******************************************************************************
2844 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2845 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2846 ******************************************************************************/
2847 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc,
2849 uint32_t priority_mask, uint8_t port)
2851 uint32_t nig_reg_rx_priority_mask_add = 0;
2853 switch (cos_entry) {
2855 nig_reg_rx_priority_mask_add = (port) ?
2856 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2857 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2860 nig_reg_rx_priority_mask_add = (port) ?
2861 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2862 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2865 nig_reg_rx_priority_mask_add = (port) ?
2866 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2867 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2871 return ELINK_STATUS_ERROR;
2872 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2876 return ELINK_STATUS_ERROR;
2877 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2881 return ELINK_STATUS_ERROR;
2882 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2886 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2888 return ELINK_STATUS_OK;
2890 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
2892 struct bxe_softc *sc = params->sc;
2894 REG_WR(sc, params->shmem_base +
2895 offsetof(struct shmem_region,
2896 port_mb[params->port].link_status), link_status);
2899 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr)
2901 struct bxe_softc *sc = params->sc;
2903 if (SHMEM2_HAS(sc, link_attr_sync))
2904 REG_WR(sc, params->shmem2_base +
2905 offsetof(struct shmem2_region,
2906 link_attr_sync[params->port]), link_attr);
2909 static void elink_update_pfc_nig(struct elink_params *params,
2910 struct elink_vars *vars,
2911 struct elink_nig_brb_pfc_port_params *nig_params)
2913 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2914 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2915 uint32_t pkt_priority_to_cos = 0;
2916 struct bxe_softc *sc = params->sc;
2917 uint8_t port = params->port;
2919 int set_pfc = params->feature_config_flags &
2920 ELINK_FEATURE_CONFIG_PFC_ENABLED;
2921 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n");
2923 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2924 * MAC control frames (that are not pause packets)
2925 * will be forwarded to the XCM.
2927 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2928 NIG_REG_LLH0_XCM_MASK);
2929 /* NIG params will override non PFC params, since it's possible to
2930 * do transition from PFC to SAFC
2940 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2941 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2946 llfc_out_en = nig_params->llfc_out_en;
2947 llfc_enable = nig_params->llfc_enable;
2948 pause_enable = nig_params->pause_enable;
2949 } else /* Default non PFC mode - PAUSE */
2952 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2953 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2958 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2959 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2960 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2961 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2962 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2963 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2964 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2965 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2967 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2968 NIG_REG_PPP_ENABLE_0, ppp_enable);
2970 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2971 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2973 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2974 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
2976 /* Output enable for RX_XCM # IF */
2977 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
2978 NIG_REG_XCM0_OUT_EN, xcm_out_en);
2980 /* HW PFC TX enable */
2981 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
2982 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
2986 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
2988 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
2989 elink_pfc_nig_rx_priority_mask(sc, i,
2990 nig_params->rx_cos_priority_mask[i], port);
2992 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
2993 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
2994 nig_params->llfc_high_priority_classes);
2996 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
2997 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
2998 nig_params->llfc_low_priority_classes);
3000 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3001 NIG_REG_P0_PKT_PRIORITY_TO_COS,
3002 pkt_priority_to_cos);
3005 elink_status_t elink_update_pfc(struct elink_params *params,
3006 struct elink_vars *vars,
3007 struct elink_nig_brb_pfc_port_params *pfc_params)
3009 /* The PFC and pause are orthogonal to one another, meaning when
3010 * PFC is enabled, the pause are disabled, and when PFC is
3011 * disabled, pause are set according to the pause result.
3014 struct bxe_softc *sc = params->sc;
3015 elink_status_t elink_status = ELINK_STATUS_OK;
3016 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
3018 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
3019 vars->link_status |= LINK_STATUS_PFC_ENABLED;
3021 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
3023 elink_update_mng(params, vars->link_status);
3025 /* Update NIG params */
3026 elink_update_pfc_nig(params, vars, pfc_params);
3029 return elink_status;
3031 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n");
3033 if (CHIP_IS_E3(sc)) {
3034 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
3035 elink_update_pfc_xmac(params, vars, 0);
3037 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3039 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3041 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n");
3042 elink_emac_enable(params, vars, 0);
3043 return elink_status;
3046 elink_update_pfc_bmac2(params, vars, bmac_loopback);
3048 elink_update_pfc_bmac1(params, vars);
3051 if ((params->feature_config_flags &
3052 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3053 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3055 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3057 return elink_status;
3060 static elink_status_t elink_bmac1_enable(struct elink_params *params,
3061 struct elink_vars *vars,
3064 struct bxe_softc *sc = params->sc;
3065 uint8_t port = params->port;
3066 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3067 NIG_REG_INGRESS_BMAC0_MEM;
3068 uint32_t wb_data[2];
3071 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n");
3076 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
3080 wb_data[0] = ((params->mac_addr[2] << 24) |
3081 (params->mac_addr[3] << 16) |
3082 (params->mac_addr[4] << 8) |
3083 params->mac_addr[5]);
3084 wb_data[1] = ((params->mac_addr[0] << 8) |
3085 params->mac_addr[1]);
3086 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3092 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
3096 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3099 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3101 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3103 elink_update_pfc_bmac1(params, vars);
3106 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3108 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3110 /* Set cnt max size */
3111 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3113 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3115 /* Configure SAFC */
3116 wb_data[0] = 0x1000200;
3118 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
3120 #ifdef ELINK_INCLUDE_EMUL
3121 /* Fix for emulation */
3122 if (CHIP_REV_IS_EMUL(sc)) {
3123 wb_data[0] = 0xf000;
3125 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
3130 return ELINK_STATUS_OK;
3133 static elink_status_t elink_bmac2_enable(struct elink_params *params,
3134 struct elink_vars *vars,
3137 struct bxe_softc *sc = params->sc;
3138 uint8_t port = params->port;
3139 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3140 NIG_REG_INGRESS_BMAC0_MEM;
3141 uint32_t wb_data[2];
3143 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n");
3147 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3150 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3153 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
3159 wb_data[0] = ((params->mac_addr[2] << 24) |
3160 (params->mac_addr[3] << 16) |
3161 (params->mac_addr[4] << 8) |
3162 params->mac_addr[5]);
3163 wb_data[1] = ((params->mac_addr[0] << 8) |
3164 params->mac_addr[1]);
3165 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
3170 /* Configure SAFC */
3171 wb_data[0] = 0x1000200;
3173 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
3178 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3180 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3184 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3186 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3188 /* Set cnt max size */
3189 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3191 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3193 elink_update_pfc_bmac2(params, vars, is_lb);
3195 return ELINK_STATUS_OK;
3198 static elink_status_t elink_bmac_enable(struct elink_params *params,
3199 struct elink_vars *vars,
3200 uint8_t is_lb, uint8_t reset_bmac)
3202 elink_status_t rc = ELINK_STATUS_OK;
3203 uint8_t port = params->port;
3204 struct bxe_softc *sc = params->sc;
3206 /* Reset and unreset the BigMac */
3208 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3209 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3213 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3214 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3216 /* Enable access for bmac registers */
3217 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3219 /* Enable BMAC according to BMAC type*/
3221 rc = elink_bmac2_enable(params, vars, is_lb);
3223 rc = elink_bmac1_enable(params, vars, is_lb);
3224 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3225 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3226 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3228 if ((params->feature_config_flags &
3229 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3230 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3232 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3233 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3234 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3235 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3236 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3237 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3239 vars->mac_type = ELINK_MAC_TYPE_BMAC;
3243 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3245 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3246 NIG_REG_INGRESS_BMAC0_MEM;
3247 uint32_t wb_data[2];
3248 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3251 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
3253 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
3254 /* Only if the bmac is out of reset */
3255 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3256 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3258 /* Clear Rx Enable bit in BMAC_CONTROL register */
3259 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3261 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3263 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3264 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
3269 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl,
3270 uint32_t line_speed)
3272 struct bxe_softc *sc = params->sc;
3273 uint8_t port = params->port;
3274 uint32_t init_crd, crd;
3275 uint32_t count = 1000;
3278 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3280 /* Wait for init credit */
3281 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3282 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3283 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
3285 while ((init_crd != crd) && count) {
3287 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3290 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3291 if (init_crd != crd) {
3292 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",
3294 return ELINK_STATUS_ERROR;
3297 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
3298 line_speed == ELINK_SPEED_10 ||
3299 line_speed == ELINK_SPEED_100 ||
3300 line_speed == ELINK_SPEED_1000 ||
3301 line_speed == ELINK_SPEED_2500) {
3302 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3303 /* Update threshold */
3304 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3305 /* Update init credit */
3306 init_crd = 778; /* (800-18-4) */
3309 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
3310 ELINK_ETH_OVREHEAD)/16;
3311 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3312 /* Update threshold */
3313 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3314 /* Update init credit */
3315 switch (line_speed) {
3316 case ELINK_SPEED_10000:
3317 init_crd = thresh + 553 - 22;
3320 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
3322 return ELINK_STATUS_ERROR;
3325 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3326 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n",
3327 line_speed, init_crd);
3329 /* Probe the credit changes */
3330 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3332 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3335 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3336 return ELINK_STATUS_OK;
3340 * elink_get_emac_base - retrive emac base address
3342 * @bp: driver handle
3343 * @mdc_mdio_access: access type
3346 * This function selects the MDC/MDIO access (through emac0 or
3347 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3348 * phy has a default access mode, which could also be overridden
3349 * by nvram configuration. This parameter, whether this is the
3350 * default phy configuration, or the nvram overrun
3351 * configuration, is passed here as mdc_mdio_access and selects
3352 * the emac_base for the CL45 read/writes operations
3354 static uint32_t elink_get_emac_base(struct bxe_softc *sc,
3355 uint32_t mdc_mdio_access, uint8_t port)
3357 uint32_t emac_base = 0;
3358 switch (mdc_mdio_access) {
3359 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3361 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3362 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3363 emac_base = GRCBASE_EMAC1;
3365 emac_base = GRCBASE_EMAC0;
3367 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3368 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3369 emac_base = GRCBASE_EMAC0;
3371 emac_base = GRCBASE_EMAC1;
3373 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3374 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3376 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3377 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3386 /******************************************************************/
3387 /* CL22 access functions */
3388 /******************************************************************/
3389 static elink_status_t elink_cl22_write(struct bxe_softc *sc,
3390 struct elink_phy *phy,
3391 uint16_t reg, uint16_t val)
3395 elink_status_t rc = ELINK_STATUS_OK;
3396 /* Switch to CL22 */
3397 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3398 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3399 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3402 tmp = ((phy->addr << 21) | (reg << 16) | val |
3403 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3404 EMAC_MDIO_COMM_START_BUSY);
3405 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3407 for (i = 0; i < 50; i++) {
3410 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3411 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3416 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3417 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3418 rc = ELINK_STATUS_TIMEOUT;
3420 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3424 static elink_status_t elink_cl22_read(struct bxe_softc *sc,
3425 struct elink_phy *phy,
3426 uint16_t reg, uint16_t *ret_val)
3430 elink_status_t rc = ELINK_STATUS_OK;
3432 /* Switch to CL22 */
3433 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3434 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3435 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3438 val = ((phy->addr << 21) | (reg << 16) |
3439 EMAC_MDIO_COMM_COMMAND_READ_22 |
3440 EMAC_MDIO_COMM_START_BUSY);
3441 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3443 for (i = 0; i < 50; i++) {
3446 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3447 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3448 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3453 if (val & EMAC_MDIO_COMM_START_BUSY) {
3454 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3457 rc = ELINK_STATUS_TIMEOUT;
3459 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3463 /******************************************************************/
3464 /* CL45 access functions */
3465 /******************************************************************/
3466 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3467 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3471 elink_status_t rc = ELINK_STATUS_OK;
3473 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3474 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3475 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3476 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3479 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3480 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3481 EMAC_MDIO_STATUS_10MB);
3483 val = ((phy->addr << 21) | (devad << 16) | reg |
3484 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3485 EMAC_MDIO_COMM_START_BUSY);
3486 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3488 for (i = 0; i < 50; i++) {
3491 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3492 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3497 if (val & EMAC_MDIO_COMM_START_BUSY) {
3498 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3499 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3502 rc = ELINK_STATUS_TIMEOUT;
3505 val = ((phy->addr << 21) | (devad << 16) |
3506 EMAC_MDIO_COMM_COMMAND_READ_45 |
3507 EMAC_MDIO_COMM_START_BUSY);
3508 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3510 for (i = 0; i < 50; i++) {
3513 val = REG_RD(sc, phy->mdio_ctrl +
3514 EMAC_REG_EMAC_MDIO_COMM);
3515 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3516 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3520 if (val & EMAC_MDIO_COMM_START_BUSY) {
3521 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3522 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3525 rc = ELINK_STATUS_TIMEOUT;
3528 /* Work around for E3 A0 */
3529 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3530 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3531 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3533 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3537 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3538 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3539 EMAC_MDIO_STATUS_10MB);
3543 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3544 uint8_t devad, uint16_t reg, uint16_t val)
3548 elink_status_t rc = ELINK_STATUS_OK;
3550 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3551 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3552 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3553 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3556 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3557 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3558 EMAC_MDIO_STATUS_10MB);
3561 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3562 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3563 EMAC_MDIO_COMM_START_BUSY);
3564 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3566 for (i = 0; i < 50; i++) {
3569 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3570 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3575 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3576 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3577 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3579 rc = ELINK_STATUS_TIMEOUT;
3582 tmp = ((phy->addr << 21) | (devad << 16) | val |
3583 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3584 EMAC_MDIO_COMM_START_BUSY);
3585 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3587 for (i = 0; i < 50; i++) {
3590 tmp = REG_RD(sc, phy->mdio_ctrl +
3591 EMAC_REG_EMAC_MDIO_COMM);
3592 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3597 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3598 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3599 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3601 rc = ELINK_STATUS_TIMEOUT;
3604 /* Work around for E3 A0 */
3605 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3606 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3607 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3609 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3612 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3613 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3614 EMAC_MDIO_STATUS_10MB);
3618 /******************************************************************/
3620 /******************************************************************/
3621 static uint8_t elink_eee_has_cap(struct elink_params *params)
3623 struct bxe_softc *sc = params->sc;
3625 if (REG_RD(sc, params->shmem2_base) <=
3626 offsetof(struct shmem2_region, eee_status[params->port]))
3632 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer)
3634 switch (nvram_mode) {
3635 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3636 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
3638 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3639 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3641 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3642 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
3649 return ELINK_STATUS_OK;
3652 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode)
3654 switch (idle_timer) {
3655 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
3656 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3658 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3659 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3661 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
3662 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3665 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3669 return ELINK_STATUS_OK;
3672 static uint32_t elink_eee_calc_timer(struct elink_params *params)
3674 uint32_t eee_mode, eee_idle;
3675 struct bxe_softc *sc = params->sc;
3677 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
3678 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3679 /* time value in eee_mode --> used directly*/
3680 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
3682 /* hsi value in eee_mode --> time */
3683 if (elink_eee_nvram_to_time(params->eee_mode &
3684 ELINK_EEE_MODE_NVRAM_MASK,
3689 /* hsi values in nvram --> time*/
3690 eee_mode = ((REG_RD(sc, params->shmem_base +
3691 offsetof(struct shmem_region, dev_info.
3692 port_feature_config[params->port].
3694 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3695 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3697 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
3704 static elink_status_t elink_eee_set_timers(struct elink_params *params,
3705 struct elink_vars *vars)
3707 uint32_t eee_idle = 0, eee_mode;
3708 struct bxe_softc *sc = params->sc;
3710 eee_idle = elink_eee_calc_timer(params);
3713 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3715 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
3716 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
3717 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
3718 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");
3719 return ELINK_STATUS_ERROR;
3722 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3723 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3724 /* eee_idle in 1u --> eee_status in 16u */
3726 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3727 SHMEM_EEE_TIME_OUTPUT_BIT;
3729 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
3730 return ELINK_STATUS_ERROR;
3731 vars->eee_status |= eee_mode;
3734 return ELINK_STATUS_OK;
3737 static elink_status_t elink_eee_initial_config(struct elink_params *params,
3738 struct elink_vars *vars, uint8_t mode)
3740 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3742 /* Propogate params' bits --> vars (for migration exposure) */
3743 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
3744 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3746 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3748 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
3749 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3751 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3753 return elink_eee_set_timers(params, vars);
3756 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3757 struct elink_params *params,
3758 struct elink_vars *vars)
3760 struct bxe_softc *sc = params->sc;
3762 /* Make Certain LPI is disabled */
3763 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3765 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3767 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3769 return ELINK_STATUS_OK;
3772 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3773 struct elink_params *params,
3774 struct elink_vars *vars, uint8_t modes)
3776 struct bxe_softc *sc = params->sc;
3779 /* Mask events preventing LPI generation */
3780 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3782 if (modes & SHMEM_EEE_10G_ADV) {
3783 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n");
3786 if (modes & SHMEM_EEE_1G_ADV) {
3787 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n");
3791 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3793 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3794 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3796 return ELINK_STATUS_OK;
3799 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status)
3801 struct bxe_softc *sc = params->sc;
3803 if (elink_eee_has_cap(params))
3804 REG_WR(sc, params->shmem2_base +
3805 offsetof(struct shmem2_region,
3806 eee_status[params->port]), eee_status);
3809 static void elink_eee_an_resolve(struct elink_phy *phy,
3810 struct elink_params *params,
3811 struct elink_vars *vars)
3813 struct bxe_softc *sc = params->sc;
3814 uint16_t adv = 0, lp = 0;
3815 uint32_t lp_adv = 0;
3818 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3819 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3822 lp_adv |= SHMEM_EEE_100M_ADV;
3824 if (vars->line_speed == ELINK_SPEED_100)
3826 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n");
3830 lp_adv |= SHMEM_EEE_1G_ADV;
3832 if (vars->line_speed == ELINK_SPEED_1000)
3834 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n");
3838 lp_adv |= SHMEM_EEE_10G_ADV;
3840 if (vars->line_speed == ELINK_SPEED_10000)
3842 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n");
3846 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3847 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3850 ELINK_DEBUG_P0(sc, "EEE is active\n");
3851 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3855 /******************************************************************/
3856 /* BSC access functions from E3 */
3857 /******************************************************************/
3858 static void elink_bsc_module_sel(struct elink_params *params)
3861 uint32_t board_cfg, sfp_ctrl;
3862 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3863 struct bxe_softc *sc = params->sc;
3864 uint8_t port = params->port;
3865 /* Read I2C output PINs */
3866 board_cfg = REG_RD(sc, params->shmem_base +
3867 offsetof(struct shmem_region,
3868 dev_info.shared_hw_config.board));
3869 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3870 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3871 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3873 /* Read I2C output value */
3874 sfp_ctrl = REG_RD(sc, params->shmem_base +
3875 offsetof(struct shmem_region,
3876 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3877 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3878 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3879 ELINK_DEBUG_P0(sc, "Setting BSC switch\n");
3880 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3881 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
3884 static elink_status_t elink_bsc_read(struct elink_params *params,
3885 struct bxe_softc *sc,
3890 uint32_t *data_array)
3893 elink_status_t rc = ELINK_STATUS_OK;
3895 if (xfer_cnt > 16) {
3896 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n",
3898 return ELINK_STATUS_ERROR;
3901 elink_bsc_module_sel(params);
3903 xfer_cnt = 16 - lc_addr;
3905 /* Enable the engine */
3906 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3907 val |= MCPR_IMC_COMMAND_ENABLE;
3908 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3910 /* Program slave device ID */
3911 val = (sl_devid << 16) | sl_addr;
3912 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3914 /* Start xfer with 0 byte to update the address pointer ???*/
3915 val = (MCPR_IMC_COMMAND_ENABLE) |
3916 (MCPR_IMC_COMMAND_WRITE_OP <<
3917 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3918 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3919 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3921 /* Poll for completion */
3923 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3924 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3926 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3928 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",
3930 rc = ELINK_STATUS_TIMEOUT;
3934 if (rc == ELINK_STATUS_TIMEOUT)
3937 /* Start xfer with read op */
3938 val = (MCPR_IMC_COMMAND_ENABLE) |
3939 (MCPR_IMC_COMMAND_READ_OP <<
3940 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3941 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3943 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3945 /* Poll for completion */
3947 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3948 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3950 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3952 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i);
3953 rc = ELINK_STATUS_TIMEOUT;
3957 if (rc == ELINK_STATUS_TIMEOUT)
3960 for (i = (lc_addr >> 2); i < 4; i++) {
3961 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3963 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3964 ((data_array[i] & 0x0000ff00) << 8) |
3965 ((data_array[i] & 0x00ff0000) >> 8) |
3966 ((data_array[i] & 0xff000000) >> 24);
3972 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3973 uint8_t devad, uint16_t reg, uint16_t or_val)
3976 elink_cl45_read(sc, phy, devad, reg, &val);
3977 elink_cl45_write(sc, phy, devad, reg, val | or_val);
3980 static void elink_cl45_read_and_write(struct bxe_softc *sc,
3981 struct elink_phy *phy,
3982 uint8_t devad, uint16_t reg, uint16_t and_val)
3985 elink_cl45_read(sc, phy, devad, reg, &val);
3986 elink_cl45_write(sc, phy, devad, reg, val & and_val);
3989 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
3990 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3993 /* Probe for the phy according to the given phy_addr, and execute
3994 * the read request on it
3996 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
3997 if (params->phy[phy_index].addr == phy_addr) {
3998 return elink_cl45_read(params->sc,
3999 ¶ms->phy[phy_index], devad,
4003 return ELINK_STATUS_ERROR;
4006 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
4007 uint8_t devad, uint16_t reg, uint16_t val)
4010 /* Probe for the phy according to the given phy_addr, and execute
4011 * the write request on it
4013 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4014 if (params->phy[phy_index].addr == phy_addr) {
4015 return elink_cl45_write(params->sc,
4016 ¶ms->phy[phy_index], devad,
4020 return ELINK_STATUS_ERROR;
4022 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4023 struct elink_params *params)
4026 struct bxe_softc *sc = params->sc;
4027 uint32_t path_swap, path_swap_ovr;
4031 port = params->port;
4033 if (elink_is_4_port_mode(sc)) {
4034 uint32_t port_swap, port_swap_ovr;
4036 /* Figure out path swap value */
4037 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4038 if (path_swap_ovr & 0x1)
4039 path_swap = (path_swap_ovr & 0x2);
4041 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4046 /* Figure out port swap value */
4047 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4048 if (port_swap_ovr & 0x1)
4049 port_swap = (port_swap_ovr & 0x2);
4051 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4056 lane = (port<<1) + path;
4057 } else { /* Two port mode - no port swap */
4059 /* Figure out path swap value */
4061 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4062 if (path_swap_ovr & 0x1) {
4063 path_swap = (path_swap_ovr & 0x2);
4066 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4076 static void elink_set_aer_mmd(struct elink_params *params,
4077 struct elink_phy *phy)
4080 uint16_t offset, aer_val;
4081 struct bxe_softc *sc = params->sc;
4082 ser_lane = ((params->lane_config &
4083 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4084 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4086 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4087 (phy->addr + ser_lane) : 0;
4089 if (USES_WARPCORE(sc)) {
4090 aer_val = elink_get_warpcore_lane(phy, params);
4091 /* In Dual-lane mode, two lanes are joined together,
4092 * so in order to configure them, the AER broadcast method is
4094 * 0x200 is the broadcast address for lanes 0,1
4095 * 0x201 is the broadcast address for lanes 2,3
4097 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4098 aer_val = (aer_val >> 1) | 0x200;
4099 } else if (CHIP_IS_E2(sc))
4100 aer_val = 0x3800 + offset - 1;
4102 aer_val = 0x3800 + offset;
4104 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4105 MDIO_AER_BLOCK_AER_REG, aer_val);
4109 /******************************************************************/
4110 /* Internal phy section */
4111 /******************************************************************/
4113 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4115 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4118 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4119 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4121 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4124 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4127 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4131 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n");
4133 val = ELINK_SERDES_RESET_BITS << (port*16);
4135 /* Reset and unreset the SerDes/XGXS */
4136 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4138 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4140 elink_set_serdes_access(sc, port);
4142 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4143 ELINK_DEFAULT_PHY_DEV_ADDR);
4146 static void elink_xgxs_specific_func(struct elink_phy *phy,
4147 struct elink_params *params,
4150 struct bxe_softc *sc = params->sc;
4152 case ELINK_PHY_INIT:
4153 /* Set correct devad */
4154 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4155 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4161 static void elink_xgxs_deassert(struct elink_params *params)
4163 struct bxe_softc *sc = params->sc;
4166 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n");
4167 port = params->port;
4169 val = ELINK_XGXS_RESET_BITS << (port*16);
4171 /* Reset and unreset the SerDes/XGXS */
4172 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4174 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4175 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4179 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4180 struct elink_params *params, uint16_t *ieee_fc)
4182 struct bxe_softc *sc = params->sc;
4183 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
4184 /* Resolve pause mode and advertisement Please refer to Table
4185 * 28B-3 of the 802.3ab-1999 spec
4188 switch (phy->req_flow_ctrl) {
4189 case ELINK_FLOW_CTRL_AUTO:
4190 switch (params->req_fc_auto_adv) {
4191 case ELINK_FLOW_CTRL_BOTH:
4192 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4194 case ELINK_FLOW_CTRL_RX:
4195 case ELINK_FLOW_CTRL_TX:
4197 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4203 case ELINK_FLOW_CTRL_TX:
4204 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4207 case ELINK_FLOW_CTRL_RX:
4208 case ELINK_FLOW_CTRL_BOTH:
4209 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4212 case ELINK_FLOW_CTRL_NONE:
4214 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
4217 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);
4220 static void set_phy_vars(struct elink_params *params,
4221 struct elink_vars *vars)
4223 struct bxe_softc *sc = params->sc;
4224 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
4225 uint8_t phy_config_swapped = params->multi_phy_config &
4226 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
4227 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
4229 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
4230 actual_phy_idx = phy_index;
4231 if (phy_config_swapped) {
4232 if (phy_index == ELINK_EXT_PHY1)
4233 actual_phy_idx = ELINK_EXT_PHY2;
4234 else if (phy_index == ELINK_EXT_PHY2)
4235 actual_phy_idx = ELINK_EXT_PHY1;
4237 params->phy[actual_phy_idx].req_flow_ctrl =
4238 params->req_flow_ctrl[link_cfg_idx];
4240 params->phy[actual_phy_idx].req_line_speed =
4241 params->req_line_speed[link_cfg_idx];
4243 params->phy[actual_phy_idx].speed_cap_mask =
4244 params->speed_cap_mask[link_cfg_idx];
4246 params->phy[actual_phy_idx].req_duplex =
4247 params->req_duplex[link_cfg_idx];
4249 if (params->req_line_speed[link_cfg_idx] ==
4250 ELINK_SPEED_AUTO_NEG)
4251 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
4253 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
4254 " speed_cap_mask %x\n",
4255 params->phy[actual_phy_idx].req_flow_ctrl,
4256 params->phy[actual_phy_idx].req_line_speed,
4257 params->phy[actual_phy_idx].speed_cap_mask);
4261 static void elink_ext_phy_set_pause(struct elink_params *params,
4262 struct elink_phy *phy,
4263 struct elink_vars *vars)
4266 struct bxe_softc *sc = params->sc;
4267 /* Read modify write pause advertizing */
4268 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4270 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
4272 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4273 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4274 if ((vars->ieee_fc &
4275 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4276 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4277 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
4279 if ((vars->ieee_fc &
4280 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4282 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
4284 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4285 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4288 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result)
4290 switch (pause_result) { /* ASYM P ASYM P */
4291 case 0xb: /* 1 0 1 1 */
4292 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
4295 case 0xe: /* 1 1 1 0 */
4296 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4299 case 0x5: /* 0 1 0 1 */
4300 case 0x7: /* 0 1 1 1 */
4301 case 0xd: /* 1 1 0 1 */
4302 case 0xf: /* 1 1 1 1 */
4303 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
4309 if (pause_result & (1<<0))
4310 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
4311 if (pause_result & (1<<1))
4312 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
4316 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4317 struct elink_params *params,
4318 struct elink_vars *vars)
4320 uint16_t ld_pause; /* local */
4321 uint16_t lp_pause; /* link partner */
4322 uint16_t pause_result;
4323 struct bxe_softc *sc = params->sc;
4324 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4325 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4326 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4327 } else if (CHIP_IS_E3(sc) &&
4328 ELINK_SINGLE_MEDIA_DIRECT(params)) {
4329 uint8_t lane = elink_get_warpcore_lane(phy, params);
4330 uint16_t gp_status, gp_mask;
4331 elink_cl45_read(sc, phy,
4332 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
4334 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
4335 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
4337 if ((gp_status & gp_mask) == gp_mask) {
4338 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4339 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4340 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4341 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4343 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4344 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4345 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4346 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4347 ld_pause = ((ld_pause &
4348 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4350 lp_pause = ((lp_pause &
4351 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4355 elink_cl45_read(sc, phy,
4357 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4358 elink_cl45_read(sc, phy,
4360 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4362 pause_result = (ld_pause &
4363 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
4364 pause_result |= (lp_pause &
4365 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
4366 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);
4367 elink_pause_resolve(vars, pause_result);
4371 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4372 struct elink_params *params,
4373 struct elink_vars *vars)
4376 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4377 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4378 /* Update the advertised flow-controled of LD/LP in AN */
4379 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4380 elink_ext_phy_update_adv_fc(phy, params, vars);
4381 /* But set the flow-control result as the requested one */
4382 vars->flow_ctrl = phy->req_flow_ctrl;
4383 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4384 vars->flow_ctrl = params->req_fc_auto_adv;
4385 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
4387 elink_ext_phy_update_adv_fc(phy, params, vars);
4391 /******************************************************************/
4392 /* Warpcore section */
4393 /******************************************************************/
4394 /* The init_internal_warpcore should mirror the xgxs,
4395 * i.e. reset the lane (if needed), set aer for the
4396 * init configuration, and set/clear SGMII flag. Internal
4397 * phy init is done purely in phy_init stage.
4399 #define WC_TX_DRIVER(post2, idriver, ipre) \
4400 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
4401 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
4402 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET))
4404 #define WC_TX_FIR(post, main, pre) \
4405 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
4406 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
4407 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
4409 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4410 struct elink_params *params,
4411 struct elink_vars *vars)
4413 struct bxe_softc *sc = params->sc;
4415 static struct elink_reg_set reg_set[] = {
4416 /* Step 1 - Program the TX/RX alignment markers */
4417 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
4418 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
4419 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
4420 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
4421 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
4422 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
4423 /* Step 2 - Configure the NP registers */
4424 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
4425 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
4426 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
4427 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
4428 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
4429 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
4430 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
4431 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
4432 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
4434 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n");
4436 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4437 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
4439 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4440 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4443 /* Start KR2 work-around timer which handles BCM8073 link-parner */
4444 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
4445 elink_update_link_attr(params, vars->link_attr_sync);
4448 static void elink_disable_kr2(struct elink_params *params,
4449 struct elink_vars *vars,
4450 struct elink_phy *phy)
4452 struct bxe_softc *sc = params->sc;
4454 static struct elink_reg_set reg_set[] = {
4455 /* Step 1 - Program the TX/RX alignment markers */
4456 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
4457 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
4458 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
4459 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
4460 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
4461 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
4462 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
4463 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
4464 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
4465 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
4466 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
4467 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
4468 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
4472 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n");
4474 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4475 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4477 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
4478 elink_update_link_attr(params, vars->link_attr_sync);
4480 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
4483 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4484 struct elink_params *params)
4486 struct bxe_softc *sc = params->sc;
4488 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n");
4489 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4490 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
4491 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4492 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4495 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4496 struct elink_params *params)
4498 /* Restart autoneg on the leading lane only */
4499 struct bxe_softc *sc = params->sc;
4500 uint16_t lane = elink_get_warpcore_lane(phy, params);
4501 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4502 MDIO_AER_BLOCK_AER_REG, lane);
4503 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4504 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4507 elink_set_aer_mmd(params, phy);
4510 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4511 struct elink_params *params,
4512 struct elink_vars *vars) {
4513 uint16_t lane, i, cl72_ctrl, an_adv = 0;
4514 struct bxe_softc *sc = params->sc;
4515 static struct elink_reg_set reg_set[] = {
4516 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4517 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
4518 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
4519 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
4520 /* Disable Autoneg: re-enable it after adv is done. */
4521 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
4522 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
4523 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
4525 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n");
4526 /* Set to default registers that may be overriden by 10G force */
4527 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4528 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4531 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4532 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4533 cl72_ctrl &= 0x08ff;
4534 cl72_ctrl |= 0x3800;
4535 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4536 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
4538 /* Check adding advertisement for 1G KX */
4539 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4540 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4541 (vars->line_speed == ELINK_SPEED_1000)) {
4542 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
4545 /* Enable CL37 1G Parallel Detect */
4546 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4547 ELINK_DEBUG_P0(sc, "Advertize 1G\n");
4549 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4550 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4551 (vars->line_speed == ELINK_SPEED_10000)) {
4552 /* Check adding advertisement for 10G KR */
4554 /* Enable 10G Parallel Detect */
4555 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4556 MDIO_AER_BLOCK_AER_REG, 0);
4558 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4559 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
4560 elink_set_aer_mmd(params, phy);
4561 ELINK_DEBUG_P0(sc, "Advertize 10G\n");
4564 /* Set Transmit PMD settings */
4565 lane = elink_get_warpcore_lane(phy, params);
4566 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4567 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4568 WC_TX_DRIVER(0x02, 0x06, 0x09));
4569 /* Configure the next lane if dual mode */
4570 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4571 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4572 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4573 WC_TX_DRIVER(0x02, 0x06, 0x09));
4574 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4575 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
4577 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4578 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
4581 /* Advertised speeds */
4582 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4583 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
4585 /* Advertised and set FEC (Forward Error Correction) */
4586 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4587 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
4588 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
4589 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
4591 /* Enable CL37 BAM */
4592 if (REG_RD(sc, params->shmem_base +
4593 offsetof(struct shmem_region, dev_info.
4594 port_hw_config[params->port].default_cfg)) &
4595 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4596 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4597 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
4599 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
4602 /* Advertise pause */
4603 elink_ext_phy_set_pause(params, phy, vars);
4604 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4605 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4606 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4608 /* Over 1G - AN local device user page 1 */
4609 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4610 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4612 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4613 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4614 (phy->req_line_speed == ELINK_SPEED_20000)) {
4616 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4617 MDIO_AER_BLOCK_AER_REG, lane);
4619 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4620 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4623 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4624 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4625 elink_set_aer_mmd(params, phy);
4627 elink_warpcore_enable_AN_KR2(phy, params, vars);
4629 /* Enable Auto-Detect to support 1G over CL37 as well */
4630 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4631 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
4633 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
4634 * parallel-detect loop when CL73 and CL37 are enabled.
4636 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4637 MDIO_AER_BLOCK_AER_REG, 0);
4638 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4639 MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI, 0x0800);
4640 elink_set_aer_mmd(params, phy);
4642 elink_disable_kr2(params, vars, phy);
4645 /* Enable Autoneg: only on the main lane */
4646 elink_warpcore_restart_AN_KR(phy, params);
4649 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4650 struct elink_params *params,
4651 struct elink_vars *vars)
4653 struct bxe_softc *sc = params->sc;
4654 uint16_t val16, i, lane;
4655 static struct elink_reg_set reg_set[] = {
4656 /* Disable Autoneg */
4657 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4658 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4660 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4661 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4662 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4663 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4664 /* Leave cl72 training enable, needed for KR */
4665 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
4668 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4669 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4672 lane = elink_get_warpcore_lane(phy, params);
4673 /* Global registers */
4674 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4675 MDIO_AER_BLOCK_AER_REG, 0);
4676 /* Disable CL36 PCS Tx */
4677 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4678 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4679 val16 &= ~(0x0011 << lane);
4680 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4681 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4683 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4684 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4685 val16 |= (0x0303 << (lane << 1));
4686 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4687 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4689 elink_set_aer_mmd(params, phy);
4690 /* Set speed via PMA/PMD register */
4691 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4692 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4694 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4695 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4697 /* Enable encoded forced speed */
4698 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4699 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4701 /* Turn TX scramble payload only the 64/66 scrambler */
4702 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4703 MDIO_WC_REG_TX66_CONTROL, 0x9);
4705 /* Turn RX scramble payload only the 64/66 scrambler */
4706 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4707 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4709 /* Set and clear loopback to cause a reset to 64/66 decoder */
4710 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4711 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4712 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4713 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4717 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4718 struct elink_params *params,
4721 struct bxe_softc *sc = params->sc;
4722 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4723 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
4725 /* Hold rxSeqStart */
4726 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4727 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4729 /* Hold tx_fifo_reset */
4730 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4731 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4733 /* Disable CL73 AN */
4734 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4736 /* Disable 100FX Enable and Auto-Detect */
4737 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4738 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
4740 /* Disable 100FX Idle detect */
4741 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4742 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4744 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4745 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4746 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
4748 /* Turn off auto-detect & fiber mode */
4749 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4750 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4753 /* Set filter_force_link, disable_false_link and parallel_detect */
4754 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4755 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4756 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4757 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4758 ((val | 0x0006) & 0xFFFE));
4761 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4762 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4764 misc1_val &= ~(0x1f);
4768 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4769 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03);
4771 cfg_tap_val = REG_RD(sc, params->shmem_base +
4772 offsetof(struct shmem_region, dev_info.
4773 port_hw_config[params->port].
4776 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4778 tx_drv_brdct = (cfg_tap_val &
4779 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4780 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4784 /* TAP values are controlled by nvram, if value there isn't 0 */
4786 tap_val = (uint16_t)tx_equal;
4788 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4791 tx_driver_val = WC_TX_DRIVER(0x03, (uint16_t)tx_drv_brdct,
4794 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06);
4796 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4797 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4799 /* Set Transmit PMD settings */
4800 lane = elink_get_warpcore_lane(phy, params);
4801 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4802 MDIO_WC_REG_TX_FIR_TAP,
4803 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4804 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4805 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4808 /* Enable fiber mode, enable and invert sig_det */
4809 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4810 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4812 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4813 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4814 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4816 elink_warpcore_set_lpi_passthrough(phy, params);
4818 /* 10G XFI Full Duplex */
4819 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4820 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4822 /* Release tx_fifo_reset */
4823 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4824 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4826 /* Release rxSeqStart */
4827 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4828 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4831 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4832 struct elink_params *params)
4835 struct bxe_softc *sc = params->sc;
4836 /* Set global registers, so set AER lane to 0 */
4837 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4838 MDIO_AER_BLOCK_AER_REG, 0);
4840 /* Disable sequencer */
4841 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4842 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4844 elink_set_aer_mmd(params, phy);
4846 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4847 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4848 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4849 MDIO_AN_REG_CTRL, 0);
4851 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4852 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4855 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4856 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4858 /* Set 20G KR2 force speed */
4859 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4860 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4862 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4863 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4865 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4866 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4869 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4870 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4871 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4872 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4874 /* Enable sequencer (over lane 0) */
4875 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4876 MDIO_AER_BLOCK_AER_REG, 0);
4878 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4879 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4881 elink_set_aer_mmd(params, phy);
4884 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc,
4885 struct elink_phy *phy,
4888 /* Rx0 anaRxControl1G */
4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4890 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4892 /* Rx2 anaRxControl1G */
4893 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4894 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4896 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4897 MDIO_WC_REG_RX66_SCW0, 0xE070);
4899 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4900 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4902 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4903 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4905 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4906 MDIO_WC_REG_RX66_SCW3, 0x8090);
4908 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4909 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4911 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4912 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4914 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4915 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
4917 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4918 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
4920 /* Serdes Digital Misc1 */
4921 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4922 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
4924 /* Serdes Digital4 Misc3 */
4925 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4926 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
4928 /* Set Transmit PMD settings */
4929 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4930 MDIO_WC_REG_TX_FIR_TAP,
4931 (WC_TX_FIR(0x12, 0x2d, 0x00) |
4932 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
4933 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4934 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4935 WC_TX_DRIVER(0x02, 0x02, 0x02));
4938 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
4939 struct elink_params *params,
4941 uint8_t always_autoneg)
4943 struct bxe_softc *sc = params->sc;
4944 uint16_t val16, digctrl_kx1, digctrl_kx2;
4946 /* Clear XFI clock comp in non-10G single lane mode. */
4947 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4948 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
4950 elink_warpcore_set_lpi_passthrough(phy, params);
4952 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
4954 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4955 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
4957 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
4959 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4960 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4962 switch (phy->req_line_speed) {
4963 case ELINK_SPEED_10:
4965 case ELINK_SPEED_100:
4968 case ELINK_SPEED_1000:
4973 "Speed not supported: 0x%x\n", phy->req_line_speed);
4977 if (phy->req_duplex == DUPLEX_FULL)
4980 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4981 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
4983 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n",
4984 phy->req_line_speed);
4985 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4986 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
4987 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16);
4990 /* SGMII Slave mode and disable signal detect */
4991 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
4996 digctrl_kx1 &= 0xff4a;
4998 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4999 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5002 /* Turn off parallel detect */
5003 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5004 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
5005 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5006 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5007 (digctrl_kx2 & ~(1<<2)));
5009 /* Re-enable parallel detect */
5010 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5011 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5012 (digctrl_kx2 | (1<<2)));
5014 /* Enable autodet */
5015 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5016 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5017 (digctrl_kx1 | 0x10));
5021 static void elink_warpcore_reset_lane(struct bxe_softc *sc,
5022 struct elink_phy *phy,
5026 /* Take lane out of reset after configuration is finished */
5027 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5028 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5033 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5034 MDIO_WC_REG_DIGITAL5_MISC6, val);
5035 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5036 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5039 /* Clear SFI/XFI link settings registers */
5040 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5041 struct elink_params *params,
5044 struct bxe_softc *sc = params->sc;
5046 static struct elink_reg_set wc_regs[] = {
5047 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
5048 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
5049 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
5050 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
5051 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5053 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5055 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
5057 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
5058 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
5059 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
5060 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
5062 /* Set XFI clock comp as default. */
5063 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5064 MDIO_WC_REG_RX66_CONTROL, (3<<13));
5066 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
5067 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5070 lane = elink_get_warpcore_lane(phy, params);
5071 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5072 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5076 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc,
5078 uint32_t shmem_base, uint8_t port,
5079 uint8_t *gpio_num, uint8_t *gpio_port)
5084 if (CHIP_IS_E3(sc)) {
5085 cfg_pin = (REG_RD(sc, shmem_base +
5086 offsetof(struct shmem_region,
5087 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5088 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
5089 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
5091 /* Should not happen. This function called upon interrupt
5092 * triggered by GPIO ( since EPIO can only generate interrupts
5094 * So if this function was called and none of the GPIOs was set,
5095 * it means the shit hit the fan.
5097 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
5098 (cfg_pin > PIN_CFG_GPIO3_P1)) {
5100 "No cfg pin %x for module detect indication\n",
5102 return ELINK_STATUS_ERROR;
5105 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
5106 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
5108 *gpio_num = MISC_REGISTERS_GPIO_3;
5112 return ELINK_STATUS_OK;
5115 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5116 struct elink_params *params)
5118 struct bxe_softc *sc = params->sc;
5119 uint8_t gpio_num, gpio_port;
5121 if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
5122 params->shmem_base, params->port,
5123 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
5125 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
5127 /* Call the handling function in case module is detected */
5133 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5134 struct elink_params *params)
5136 uint16_t gp2_status_reg0, lane;
5137 struct bxe_softc *sc = params->sc;
5139 lane = elink_get_warpcore_lane(phy, params);
5141 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5144 return (gp2_status_reg0 >> (8+lane)) & 0x1;
5147 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5148 struct elink_params *params,
5149 struct elink_vars *vars)
5151 struct bxe_softc *sc = params->sc;
5152 uint32_t serdes_net_if;
5153 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
5155 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
5157 if (!vars->turn_to_run_wc_rt)
5160 if (vars->rx_tx_asic_rst) {
5161 uint16_t lane = elink_get_warpcore_lane(phy, params);
5162 serdes_net_if = (REG_RD(sc, params->shmem_base +
5163 offsetof(struct shmem_region, dev_info.
5164 port_hw_config[params->port].default_cfg)) &
5165 PORT_HW_CFG_NET_SERDES_IF_MASK);
5167 switch (serdes_net_if) {
5168 case PORT_HW_CFG_NET_SERDES_IF_KR:
5169 /* Do we get link yet? */
5170 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5172 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5174 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5176 if (lnkup_kr || lnkup) {
5177 vars->rx_tx_asic_rst = 0;
5179 /* Reset the lane to see if link comes up.*/
5180 elink_warpcore_reset_lane(sc, phy, 1);
5181 elink_warpcore_reset_lane(sc, phy, 0);
5183 /* Restart Autoneg */
5184 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5185 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
5187 vars->rx_tx_asic_rst--;
5188 ELINK_DEBUG_P1(sc, "0x%x retry left\n",
5189 vars->rx_tx_asic_rst);
5197 } /*params->rx_tx_asic_rst*/
5200 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5201 struct elink_params *params)
5203 uint16_t lane = elink_get_warpcore_lane(phy, params);
5204 struct bxe_softc *sc = params->sc;
5205 elink_warpcore_clear_regs(phy, params, lane);
5206 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
5207 ELINK_SPEED_10000) &&
5208 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5209 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n");
5210 elink_warpcore_set_10G_XFI(phy, params, 0);
5212 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n");
5213 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5217 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
5218 struct elink_phy *phy,
5221 struct bxe_softc *sc = params->sc;
5223 uint8_t port = params->port;
5225 cfg_pin = REG_RD(sc, params->shmem_base +
5226 offsetof(struct shmem_region,
5227 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5228 PORT_HW_CFG_E3_TX_LASER_MASK;
5229 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
5230 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en);
5232 /* For 20G, the expected pin to be used is 3 pins after the current */
5233 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
5234 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5235 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
5238 static void elink_warpcore_config_init(struct elink_phy *phy,
5239 struct elink_params *params,
5240 struct elink_vars *vars)
5242 struct bxe_softc *sc = params->sc;
5243 uint32_t serdes_net_if;
5245 uint16_t lane = elink_get_warpcore_lane(phy, params);
5246 serdes_net_if = (REG_RD(sc, params->shmem_base +
5247 offsetof(struct shmem_region, dev_info.
5248 port_hw_config[params->port].default_cfg)) &
5249 PORT_HW_CFG_NET_SERDES_IF_MASK);
5250 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
5251 "serdes_net_if = 0x%x\n",
5252 vars->line_speed, serdes_net_if);
5253 elink_set_aer_mmd(params, phy);
5254 elink_warpcore_reset_lane(sc, phy, 1);
5255 vars->phy_flags |= PHY_XGXS_FLAG;
5256 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
5257 (phy->req_line_speed &&
5258 ((phy->req_line_speed == ELINK_SPEED_100) ||
5259 (phy->req_line_speed == ELINK_SPEED_10)))) {
5260 vars->phy_flags |= PHY_SGMII_FLAG;
5261 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n");
5262 elink_warpcore_clear_regs(phy, params, lane);
5263 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5265 switch (serdes_net_if) {
5266 case PORT_HW_CFG_NET_SERDES_IF_KR:
5267 /* Enable KR Auto Neg */
5268 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
5269 elink_warpcore_enable_AN_KR(phy, params, vars);
5271 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n");
5272 elink_warpcore_set_10G_KR(phy, params, vars);
5276 case PORT_HW_CFG_NET_SERDES_IF_XFI:
5277 elink_warpcore_clear_regs(phy, params, lane);
5278 if (vars->line_speed == ELINK_SPEED_10000) {
5279 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n");
5280 elink_warpcore_set_10G_XFI(phy, params, 1);
5282 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5283 ELINK_DEBUG_P0(sc, "1G Fiber\n");
5286 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n");
5289 elink_warpcore_set_sgmii_speed(phy,
5297 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5298 /* Issue Module detection if module is plugged, or
5299 * enabled transmitter to avoid current leakage in case
5300 * no module is connected
5302 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
5303 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5304 if (elink_is_sfp_module_plugged(phy, params))
5305 elink_sfp_module_detection(phy, params);
5307 elink_sfp_e3_set_transmitter(params,
5311 elink_warpcore_config_sfi(phy, params);
5314 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
5315 if (vars->line_speed != ELINK_SPEED_20000) {
5316 ELINK_DEBUG_P0(sc, "Speed not supported yet\n");
5319 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n");
5320 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5321 /* Issue Module detection */
5323 elink_sfp_module_detection(phy, params);
5325 case PORT_HW_CFG_NET_SERDES_IF_KR2:
5326 if (!params->loopback_mode) {
5327 elink_warpcore_enable_AN_KR(phy, params, vars);
5329 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n");
5330 elink_warpcore_set_20G_force_KR2(phy, params);
5335 "Unsupported Serdes Net Interface 0x%x\n",
5341 /* Take lane out of reset after configuration is finished */
5342 elink_warpcore_reset_lane(sc, phy, 0);
5343 ELINK_DEBUG_P0(sc, "Exit config init\n");
5346 static void elink_warpcore_link_reset(struct elink_phy *phy,
5347 struct elink_params *params)
5349 struct bxe_softc *sc = params->sc;
5350 uint16_t val16, lane;
5351 elink_sfp_e3_set_transmitter(params, phy, 0);
5352 elink_set_mdio_emac_per_phy(sc, params);
5353 elink_set_aer_mmd(params, phy);
5354 /* Global register */
5355 elink_warpcore_reset_lane(sc, phy, 1);
5357 /* Clear loopback settings (if any) */
5359 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5360 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
5362 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5363 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
5365 /* Update those 1-copy registers */
5366 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5367 MDIO_AER_BLOCK_AER_REG, 0);
5368 /* Enable 1G MDIO (1-copy) */
5369 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5370 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5373 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5374 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
5375 lane = elink_get_warpcore_lane(phy, params);
5376 /* Disable CL36 PCS Tx */
5377 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5378 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
5379 val16 |= (0x11 << lane);
5380 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5381 val16 |= (0x22 << lane);
5382 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5383 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
5385 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5386 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
5387 val16 &= ~(0x0303 << (lane << 1));
5388 val16 |= (0x0101 << (lane << 1));
5389 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5390 val16 &= ~(0x0c0c << (lane << 1));
5391 val16 |= (0x0404 << (lane << 1));
5394 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5395 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
5397 elink_set_aer_mmd(params, phy);
5401 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5402 struct elink_params *params)
5404 struct bxe_softc *sc = params->sc;
5407 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n",
5408 params->loopback_mode, phy->req_line_speed);
5410 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5411 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5412 /* 10/100/1000/20G-KR2 */
5414 /* Update those 1-copy registers */
5415 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5416 MDIO_AER_BLOCK_AER_REG, 0);
5417 /* Enable 1G MDIO (1-copy) */
5418 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5419 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5421 /* Set 1G loopback based on lane (1-copy) */
5422 lane = elink_get_warpcore_lane(phy, params);
5423 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5424 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
5426 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5428 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5429 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
5432 /* Switch back to 4-copy registers */
5433 elink_set_aer_mmd(params, phy);
5435 /* 10G / 20G-DXGXS */
5436 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5437 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5439 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5440 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
5446 static void elink_sync_link(struct elink_params *params,
5447 struct elink_vars *vars)
5449 struct bxe_softc *sc = params->sc;
5450 uint8_t link_10g_plus;
5451 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5452 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
5453 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
5454 if (vars->link_up) {
5455 ELINK_DEBUG_P0(sc, "phy link up\n");
5457 vars->phy_link_up = 1;
5458 vars->duplex = DUPLEX_FULL;
5459 switch (vars->link_status &
5460 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
5461 case ELINK_LINK_10THD:
5462 vars->duplex = DUPLEX_HALF;
5464 case ELINK_LINK_10TFD:
5465 vars->line_speed = ELINK_SPEED_10;
5468 case ELINK_LINK_100TXHD:
5469 vars->duplex = DUPLEX_HALF;
5471 case ELINK_LINK_100T4:
5472 case ELINK_LINK_100TXFD:
5473 vars->line_speed = ELINK_SPEED_100;
5476 case ELINK_LINK_1000THD:
5477 vars->duplex = DUPLEX_HALF;
5479 case ELINK_LINK_1000TFD:
5480 vars->line_speed = ELINK_SPEED_1000;
5483 case ELINK_LINK_2500THD:
5484 vars->duplex = DUPLEX_HALF;
5486 case ELINK_LINK_2500TFD:
5487 vars->line_speed = ELINK_SPEED_2500;
5490 case ELINK_LINK_10GTFD:
5491 vars->line_speed = ELINK_SPEED_10000;
5493 case ELINK_LINK_20GTFD:
5494 vars->line_speed = ELINK_SPEED_20000;
5499 vars->flow_ctrl = 0;
5500 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
5501 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
5503 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
5504 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
5506 if (!vars->flow_ctrl)
5507 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5509 if (vars->line_speed &&
5510 ((vars->line_speed == ELINK_SPEED_10) ||
5511 (vars->line_speed == ELINK_SPEED_100))) {
5512 vars->phy_flags |= PHY_SGMII_FLAG;
5514 vars->phy_flags &= ~PHY_SGMII_FLAG;
5516 if (vars->line_speed &&
5517 USES_WARPCORE(sc) &&
5518 (vars->line_speed == ELINK_SPEED_1000))
5519 vars->phy_flags |= PHY_SGMII_FLAG;
5520 /* Anything 10 and over uses the bmac */
5521 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
5523 if (link_10g_plus) {
5524 if (USES_WARPCORE(sc))
5525 vars->mac_type = ELINK_MAC_TYPE_XMAC;
5527 vars->mac_type = ELINK_MAC_TYPE_BMAC;
5529 if (USES_WARPCORE(sc))
5530 vars->mac_type = ELINK_MAC_TYPE_UMAC;
5532 vars->mac_type = ELINK_MAC_TYPE_EMAC;
5534 } else { /* Link down */
5535 ELINK_DEBUG_P0(sc, "phy link down\n");
5537 vars->phy_link_up = 0;
5539 vars->line_speed = 0;
5540 vars->duplex = DUPLEX_FULL;
5541 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5543 /* Indicate no mac active */
5544 vars->mac_type = ELINK_MAC_TYPE_NONE;
5545 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5546 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
5547 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
5548 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
5552 void elink_link_status_update(struct elink_params *params,
5553 struct elink_vars *vars)
5555 struct bxe_softc *sc = params->sc;
5556 uint8_t port = params->port;
5557 uint32_t sync_offset, media_types;
5558 /* Update PHY configuration */
5559 set_phy_vars(params, vars);
5561 vars->link_status = REG_RD(sc, params->shmem_base +
5562 offsetof(struct shmem_region,
5563 port_mb[port].link_status));
5565 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
5566 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
5567 params->loopback_mode != ELINK_LOOPBACK_EXT)
5568 vars->link_status |= LINK_STATUS_LINK_UP;
5570 if (elink_eee_has_cap(params))
5571 vars->eee_status = REG_RD(sc, params->shmem2_base +
5572 offsetof(struct shmem2_region,
5573 eee_status[params->port]));
5575 vars->phy_flags = PHY_XGXS_FLAG;
5576 elink_sync_link(params, vars);
5577 /* Sync media type */
5578 sync_offset = params->shmem_base +
5579 offsetof(struct shmem_region,
5580 dev_info.port_hw_config[port].media_type);
5581 media_types = REG_RD(sc, sync_offset);
5583 params->phy[ELINK_INT_PHY].media_type =
5584 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
5585 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
5586 params->phy[ELINK_EXT_PHY1].media_type =
5587 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
5588 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
5589 params->phy[ELINK_EXT_PHY2].media_type =
5590 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
5591 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
5592 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);
5594 /* Sync AEU offset */
5595 sync_offset = params->shmem_base +
5596 offsetof(struct shmem_region,
5597 dev_info.port_hw_config[port].aeu_int_mask);
5599 vars->aeu_int_mask = REG_RD(sc, sync_offset);
5601 /* Sync PFC status */
5602 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
5603 params->feature_config_flags |=
5604 ELINK_FEATURE_CONFIG_PFC_ENABLED;
5606 params->feature_config_flags &=
5607 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
5609 if (SHMEM2_HAS(sc, link_attr_sync))
5610 vars->link_attr_sync = SHMEM2_RD(sc,
5611 link_attr_sync[params->port]);
5613 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5614 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
5615 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5616 vars->line_speed, vars->duplex, vars->flow_ctrl);
5619 static void elink_set_master_ln(struct elink_params *params,
5620 struct elink_phy *phy)
5622 struct bxe_softc *sc = params->sc;
5623 uint16_t new_master_ln, ser_lane;
5624 ser_lane = ((params->lane_config &
5625 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5626 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5628 /* Set the master_ln for AN */
5629 CL22_RD_OVER_CL45(sc, phy,
5630 MDIO_REG_BANK_XGXS_BLOCK2,
5631 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5634 CL22_WR_OVER_CL45(sc, phy,
5635 MDIO_REG_BANK_XGXS_BLOCK2 ,
5636 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5637 (new_master_ln | ser_lane));
5640 static elink_status_t elink_reset_unicore(struct elink_params *params,
5641 struct elink_phy *phy,
5644 struct bxe_softc *sc = params->sc;
5645 uint16_t mii_control;
5647 CL22_RD_OVER_CL45(sc, phy,
5648 MDIO_REG_BANK_COMBO_IEEE0,
5649 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
5651 /* Reset the unicore */
5652 CL22_WR_OVER_CL45(sc, phy,
5653 MDIO_REG_BANK_COMBO_IEEE0,
5654 MDIO_COMBO_IEEE0_MII_CONTROL,
5656 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
5658 elink_set_serdes_access(sc, params->port);
5660 /* Wait for the reset to self clear */
5661 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
5664 /* The reset erased the previous bank value */
5665 CL22_RD_OVER_CL45(sc, phy,
5666 MDIO_REG_BANK_COMBO_IEEE0,
5667 MDIO_COMBO_IEEE0_MII_CONTROL,
5670 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
5672 return ELINK_STATUS_OK;
5676 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5679 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n");
5680 return ELINK_STATUS_ERROR;
5684 static void elink_set_swap_lanes(struct elink_params *params,
5685 struct elink_phy *phy)
5687 struct bxe_softc *sc = params->sc;
5688 /* Each two bits represents a lane number:
5689 * No swap is 0123 => 0x1b no need to enable the swap
5691 uint16_t rx_lane_swap, tx_lane_swap;
5693 rx_lane_swap = ((params->lane_config &
5694 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
5695 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
5696 tx_lane_swap = ((params->lane_config &
5697 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
5698 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
5700 if (rx_lane_swap != 0x1b) {
5701 CL22_WR_OVER_CL45(sc, phy,
5702 MDIO_REG_BANK_XGXS_BLOCK2,
5703 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
5705 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5706 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5708 CL22_WR_OVER_CL45(sc, phy,
5709 MDIO_REG_BANK_XGXS_BLOCK2,
5710 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5713 if (tx_lane_swap != 0x1b) {
5714 CL22_WR_OVER_CL45(sc, phy,
5715 MDIO_REG_BANK_XGXS_BLOCK2,
5716 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5718 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5720 CL22_WR_OVER_CL45(sc, phy,
5721 MDIO_REG_BANK_XGXS_BLOCK2,
5722 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5726 static void elink_set_parallel_detection(struct elink_phy *phy,
5727 struct elink_params *params)
5729 struct bxe_softc *sc = params->sc;
5731 CL22_RD_OVER_CL45(sc, phy,
5732 MDIO_REG_BANK_SERDES_DIGITAL,
5733 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5735 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5736 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5738 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5739 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5740 phy->speed_cap_mask, control2);
5741 CL22_WR_OVER_CL45(sc, phy,
5742 MDIO_REG_BANK_SERDES_DIGITAL,
5743 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5746 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5747 (phy->speed_cap_mask &
5748 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5749 ELINK_DEBUG_P0(sc, "XGXS\n");
5751 CL22_WR_OVER_CL45(sc, phy,
5752 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5753 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5754 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5756 CL22_RD_OVER_CL45(sc, phy,
5757 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5758 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5763 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5765 CL22_WR_OVER_CL45(sc, phy,
5766 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5767 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5770 /* Disable parallel detection of HiG */
5771 CL22_WR_OVER_CL45(sc, phy,
5772 MDIO_REG_BANK_XGXS_BLOCK2,
5773 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5774 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5775 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5779 static void elink_set_autoneg(struct elink_phy *phy,
5780 struct elink_params *params,
5781 struct elink_vars *vars,
5782 uint8_t enable_cl73)
5784 struct bxe_softc *sc = params->sc;
5788 CL22_RD_OVER_CL45(sc, phy,
5789 MDIO_REG_BANK_COMBO_IEEE0,
5790 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5792 /* CL37 Autoneg Enabled */
5793 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5794 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5795 else /* CL37 Autoneg Disabled */
5796 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5797 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5799 CL22_WR_OVER_CL45(sc, phy,
5800 MDIO_REG_BANK_COMBO_IEEE0,
5801 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5803 /* Enable/Disable Autodetection */
5805 CL22_RD_OVER_CL45(sc, phy,
5806 MDIO_REG_BANK_SERDES_DIGITAL,
5807 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5808 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5809 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5810 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5811 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5812 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5814 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5816 CL22_WR_OVER_CL45(sc, phy,
5817 MDIO_REG_BANK_SERDES_DIGITAL,
5818 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5820 /* Enable TetonII and BAM autoneg */
5821 CL22_RD_OVER_CL45(sc, phy,
5822 MDIO_REG_BANK_BAM_NEXT_PAGE,
5823 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5825 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
5826 /* Enable BAM aneg Mode and TetonII aneg Mode */
5827 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5828 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5830 /* TetonII and BAM Autoneg Disabled */
5831 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5832 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5834 CL22_WR_OVER_CL45(sc, phy,
5835 MDIO_REG_BANK_BAM_NEXT_PAGE,
5836 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5840 /* Enable Cl73 FSM status bits */
5841 CL22_WR_OVER_CL45(sc, phy,
5842 MDIO_REG_BANK_CL73_USERB0,
5843 MDIO_CL73_USERB0_CL73_UCTRL,
5846 /* Enable BAM Station Manager*/
5847 CL22_WR_OVER_CL45(sc, phy,
5848 MDIO_REG_BANK_CL73_USERB0,
5849 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5850 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5851 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5852 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5854 /* Advertise CL73 link speeds */
5855 CL22_RD_OVER_CL45(sc, phy,
5856 MDIO_REG_BANK_CL73_IEEEB1,
5857 MDIO_CL73_IEEEB1_AN_ADV2,
5859 if (phy->speed_cap_mask &
5860 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5861 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5862 if (phy->speed_cap_mask &
5863 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5864 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5866 CL22_WR_OVER_CL45(sc, phy,
5867 MDIO_REG_BANK_CL73_IEEEB1,
5868 MDIO_CL73_IEEEB1_AN_ADV2,
5871 /* CL73 Autoneg Enabled */
5872 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5874 } else /* CL73 Autoneg Disabled */
5877 CL22_WR_OVER_CL45(sc, phy,
5878 MDIO_REG_BANK_CL73_IEEEB0,
5879 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5882 /* Program SerDes, forced speed */
5883 static void elink_program_serdes(struct elink_phy *phy,
5884 struct elink_params *params,
5885 struct elink_vars *vars)
5887 struct bxe_softc *sc = params->sc;
5890 /* Program duplex, disable autoneg and sgmii*/
5891 CL22_RD_OVER_CL45(sc, phy,
5892 MDIO_REG_BANK_COMBO_IEEE0,
5893 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5894 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5895 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5896 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5897 if (phy->req_duplex == DUPLEX_FULL)
5898 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5899 CL22_WR_OVER_CL45(sc, phy,
5900 MDIO_REG_BANK_COMBO_IEEE0,
5901 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5904 * - needed only if the speed is greater than 1G (2.5G or 10G)
5906 CL22_RD_OVER_CL45(sc, phy,
5907 MDIO_REG_BANK_SERDES_DIGITAL,
5908 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5909 /* Clearing the speed value before setting the right speed */
5910 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5912 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5913 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5915 if (!((vars->line_speed == ELINK_SPEED_1000) ||
5916 (vars->line_speed == ELINK_SPEED_100) ||
5917 (vars->line_speed == ELINK_SPEED_10))) {
5919 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
5920 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
5921 if (vars->line_speed == ELINK_SPEED_10000)
5923 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
5926 CL22_WR_OVER_CL45(sc, phy,
5927 MDIO_REG_BANK_SERDES_DIGITAL,
5928 MDIO_SERDES_DIGITAL_MISC1, reg_val);
5932 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
5933 struct elink_params *params)
5935 struct bxe_softc *sc = params->sc;
5938 /* Set extended capabilities */
5939 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
5940 val |= MDIO_OVER_1G_UP1_2_5G;
5941 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5942 val |= MDIO_OVER_1G_UP1_10G;
5943 CL22_WR_OVER_CL45(sc, phy,
5944 MDIO_REG_BANK_OVER_1G,
5945 MDIO_OVER_1G_UP1, val);
5947 CL22_WR_OVER_CL45(sc, phy,
5948 MDIO_REG_BANK_OVER_1G,
5949 MDIO_OVER_1G_UP3, 0x400);
5952 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
5953 struct elink_params *params,
5956 struct bxe_softc *sc = params->sc;
5958 /* For AN, we are always publishing full duplex */
5960 CL22_WR_OVER_CL45(sc, phy,
5961 MDIO_REG_BANK_COMBO_IEEE0,
5962 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
5963 CL22_RD_OVER_CL45(sc, phy,
5964 MDIO_REG_BANK_CL73_IEEEB1,
5965 MDIO_CL73_IEEEB1_AN_ADV1, &val);
5966 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
5967 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
5968 CL22_WR_OVER_CL45(sc, phy,
5969 MDIO_REG_BANK_CL73_IEEEB1,
5970 MDIO_CL73_IEEEB1_AN_ADV1, val);
5973 static void elink_restart_autoneg(struct elink_phy *phy,
5974 struct elink_params *params,
5975 uint8_t enable_cl73)
5977 struct bxe_softc *sc = params->sc;
5978 uint16_t mii_control;
5980 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n");
5981 /* Enable and restart BAM/CL37 aneg */
5984 CL22_RD_OVER_CL45(sc, phy,
5985 MDIO_REG_BANK_CL73_IEEEB0,
5986 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5989 CL22_WR_OVER_CL45(sc, phy,
5990 MDIO_REG_BANK_CL73_IEEEB0,
5991 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
5993 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
5994 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
5997 CL22_RD_OVER_CL45(sc, phy,
5998 MDIO_REG_BANK_COMBO_IEEE0,
5999 MDIO_COMBO_IEEE0_MII_CONTROL,
6002 "elink_restart_autoneg mii_control before = 0x%x\n",
6004 CL22_WR_OVER_CL45(sc, phy,
6005 MDIO_REG_BANK_COMBO_IEEE0,
6006 MDIO_COMBO_IEEE0_MII_CONTROL,
6008 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6009 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
6013 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6014 struct elink_params *params,
6015 struct elink_vars *vars)
6017 struct bxe_softc *sc = params->sc;
6020 /* In SGMII mode, the unicore is always slave */
6022 CL22_RD_OVER_CL45(sc, phy,
6023 MDIO_REG_BANK_SERDES_DIGITAL,
6024 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6026 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
6027 /* Set sgmii mode (and not fiber) */
6028 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
6029 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
6030 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
6031 CL22_WR_OVER_CL45(sc, phy,
6032 MDIO_REG_BANK_SERDES_DIGITAL,
6033 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6036 /* If forced speed */
6037 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
6038 /* Set speed, disable autoneg */
6039 uint16_t mii_control;
6041 CL22_RD_OVER_CL45(sc, phy,
6042 MDIO_REG_BANK_COMBO_IEEE0,
6043 MDIO_COMBO_IEEE0_MII_CONTROL,
6045 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6046 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
6047 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
6049 switch (vars->line_speed) {
6050 case ELINK_SPEED_100:
6052 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
6054 case ELINK_SPEED_1000:
6056 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
6058 case ELINK_SPEED_10:
6059 /* There is nothing to set for 10M */
6062 /* Invalid speed for SGMII */
6063 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6068 /* Setting the full duplex */
6069 if (phy->req_duplex == DUPLEX_FULL)
6071 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
6072 CL22_WR_OVER_CL45(sc, phy,
6073 MDIO_REG_BANK_COMBO_IEEE0,
6074 MDIO_COMBO_IEEE0_MII_CONTROL,
6077 } else { /* AN mode */
6078 /* Enable and restart AN */
6079 elink_restart_autoneg(phy, params, 0);
6085 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6086 struct elink_params *params)
6088 struct bxe_softc *sc = params->sc;
6089 uint16_t pd_10g, status2_1000x;
6090 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6091 return ELINK_STATUS_OK;
6092 CL22_RD_OVER_CL45(sc, phy,
6093 MDIO_REG_BANK_SERDES_DIGITAL,
6094 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6096 CL22_RD_OVER_CL45(sc, phy,
6097 MDIO_REG_BANK_SERDES_DIGITAL,
6098 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6100 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
6101 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6106 CL22_RD_OVER_CL45(sc, phy,
6107 MDIO_REG_BANK_10G_PARALLEL_DETECT,
6108 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
6111 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
6112 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6116 return ELINK_STATUS_OK;
6119 static void elink_update_adv_fc(struct elink_phy *phy,
6120 struct elink_params *params,
6121 struct elink_vars *vars,
6124 uint16_t ld_pause; /* local driver */
6125 uint16_t lp_pause; /* link partner */
6126 uint16_t pause_result;
6127 struct bxe_softc *sc = params->sc;
6129 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6130 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
6131 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6132 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
6134 CL22_RD_OVER_CL45(sc, phy,
6135 MDIO_REG_BANK_CL73_IEEEB1,
6136 MDIO_CL73_IEEEB1_AN_ADV1,
6138 CL22_RD_OVER_CL45(sc, phy,
6139 MDIO_REG_BANK_CL73_IEEEB1,
6140 MDIO_CL73_IEEEB1_AN_LP_ADV1,
6142 pause_result = (ld_pause &
6143 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
6144 pause_result |= (lp_pause &
6145 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
6146 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);
6148 CL22_RD_OVER_CL45(sc, phy,
6149 MDIO_REG_BANK_COMBO_IEEE0,
6150 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
6152 CL22_RD_OVER_CL45(sc, phy,
6153 MDIO_REG_BANK_COMBO_IEEE0,
6154 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
6156 pause_result = (ld_pause &
6157 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
6158 pause_result |= (lp_pause &
6159 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
6160 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);
6162 elink_pause_resolve(vars, pause_result);
6166 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6167 struct elink_params *params,
6168 struct elink_vars *vars,
6171 struct bxe_softc *sc = params->sc;
6172 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6174 /* Resolve from gp_status in case of AN complete and not sgmii */
6175 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6176 /* Update the advertised flow-controled of LD/LP in AN */
6177 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6178 elink_update_adv_fc(phy, params, vars, gp_status);
6179 /* But set the flow-control result as the requested one */
6180 vars->flow_ctrl = phy->req_flow_ctrl;
6181 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6182 vars->flow_ctrl = params->req_fc_auto_adv;
6183 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
6184 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
6185 if (elink_direct_parallel_detect_used(phy, params)) {
6186 vars->flow_ctrl = params->req_fc_auto_adv;
6189 elink_update_adv_fc(phy, params, vars, gp_status);
6191 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6194 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6195 struct elink_params *params)
6197 struct bxe_softc *sc = params->sc;
6198 uint16_t rx_status, ustat_val, cl37_fsm_received;
6199 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n");
6200 /* Step 1: Make sure signal is detected */
6201 CL22_RD_OVER_CL45(sc, phy,
6205 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
6206 (MDIO_RX0_RX_STATUS_SIGDET)) {
6207 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
6208 "rx_status(0x80b0) = 0x%x\n", rx_status);
6209 CL22_WR_OVER_CL45(sc, phy,
6210 MDIO_REG_BANK_CL73_IEEEB0,
6211 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6212 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
6215 /* Step 2: Check CL73 state machine */
6216 CL22_RD_OVER_CL45(sc, phy,
6217 MDIO_REG_BANK_CL73_USERB0,
6218 MDIO_CL73_USERB0_CL73_USTAT1,
6221 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6222 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
6223 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6224 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
6225 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
6226 "ustat_val(0x8371) = 0x%x\n", ustat_val);
6229 /* Step 3: Check CL37 Message Pages received to indicate LP
6230 * supports only CL37
6232 CL22_RD_OVER_CL45(sc, phy,
6233 MDIO_REG_BANK_REMOTE_PHY,
6234 MDIO_REMOTE_PHY_MISC_RX_STATUS,
6235 &cl37_fsm_received);
6236 if ((cl37_fsm_received &
6237 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6238 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
6239 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6240 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
6241 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
6242 "misc_rx_status(0x8330) = 0x%x\n",
6246 /* The combined cl37/cl73 fsm state information indicating that
6247 * we are connected to a device which does not support cl73, but
6248 * does support cl37 BAM. In this case we disable cl73 and
6249 * restart cl37 auto-neg
6253 CL22_WR_OVER_CL45(sc, phy,
6254 MDIO_REG_BANK_CL73_IEEEB0,
6255 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6257 /* Restart CL37 autoneg */
6258 elink_restart_autoneg(phy, params, 0);
6259 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n");
6262 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6263 struct elink_params *params,
6264 struct elink_vars *vars,
6267 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
6268 vars->link_status |=
6269 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6271 if (elink_direct_parallel_detect_used(phy, params))
6272 vars->link_status |=
6273 LINK_STATUS_PARALLEL_DETECTION_USED;
6275 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6276 struct elink_params *params,
6277 struct elink_vars *vars,
6278 uint16_t is_link_up,
6279 uint16_t speed_mask,
6282 struct bxe_softc *sc = params->sc;
6283 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6284 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
6286 ELINK_DEBUG_P0(sc, "phy link up\n");
6288 vars->phy_link_up = 1;
6289 vars->link_status |= LINK_STATUS_LINK_UP;
6291 switch (speed_mask) {
6292 case ELINK_GP_STATUS_10M:
6293 vars->line_speed = ELINK_SPEED_10;
6294 if (is_duplex == DUPLEX_FULL)
6295 vars->link_status |= ELINK_LINK_10TFD;
6297 vars->link_status |= ELINK_LINK_10THD;
6300 case ELINK_GP_STATUS_100M:
6301 vars->line_speed = ELINK_SPEED_100;
6302 if (is_duplex == DUPLEX_FULL)
6303 vars->link_status |= ELINK_LINK_100TXFD;
6305 vars->link_status |= ELINK_LINK_100TXHD;
6308 case ELINK_GP_STATUS_1G:
6309 case ELINK_GP_STATUS_1G_KX:
6310 vars->line_speed = ELINK_SPEED_1000;
6311 if (is_duplex == DUPLEX_FULL)
6312 vars->link_status |= ELINK_LINK_1000TFD;
6314 vars->link_status |= ELINK_LINK_1000THD;
6317 case ELINK_GP_STATUS_2_5G:
6318 vars->line_speed = ELINK_SPEED_2500;
6319 if (is_duplex == DUPLEX_FULL)
6320 vars->link_status |= ELINK_LINK_2500TFD;
6322 vars->link_status |= ELINK_LINK_2500THD;
6325 case ELINK_GP_STATUS_5G:
6326 case ELINK_GP_STATUS_6G:
6328 "link speed unsupported gp_status 0x%x\n",
6330 return ELINK_STATUS_ERROR;
6332 case ELINK_GP_STATUS_10G_KX4:
6333 case ELINK_GP_STATUS_10G_HIG:
6334 case ELINK_GP_STATUS_10G_CX4:
6335 case ELINK_GP_STATUS_10G_KR:
6336 case ELINK_GP_STATUS_10G_SFI:
6337 case ELINK_GP_STATUS_10G_XFI:
6338 vars->line_speed = ELINK_SPEED_10000;
6339 vars->link_status |= ELINK_LINK_10GTFD;
6341 case ELINK_GP_STATUS_20G_DXGXS:
6342 case ELINK_GP_STATUS_20G_KR2:
6343 vars->line_speed = ELINK_SPEED_20000;
6344 vars->link_status |= ELINK_LINK_20GTFD;
6348 "link speed unsupported gp_status 0x%x\n",
6350 return ELINK_STATUS_ERROR;
6352 } else { /* link_down */
6353 ELINK_DEBUG_P0(sc, "phy link down\n");
6355 vars->phy_link_up = 0;
6357 vars->duplex = DUPLEX_FULL;
6358 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6359 vars->mac_type = ELINK_MAC_TYPE_NONE;
6361 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n",
6362 vars->phy_link_up, vars->line_speed);
6363 return ELINK_STATUS_OK;
6366 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6367 struct elink_params *params,
6368 struct elink_vars *vars)
6370 struct bxe_softc *sc = params->sc;
6372 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
6373 elink_status_t rc = ELINK_STATUS_OK;
6375 /* Read gp_status */
6376 CL22_RD_OVER_CL45(sc, phy,
6377 MDIO_REG_BANK_GP_STATUS,
6378 MDIO_GP_STATUS_TOP_AN_STATUS1,
6380 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
6381 duplex = DUPLEX_FULL;
6382 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
6384 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
6385 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6386 gp_status, link_up, speed_mask);
6387 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6389 if (rc == ELINK_STATUS_ERROR)
6392 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
6393 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6394 vars->duplex = duplex;
6395 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6396 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6397 elink_xgxs_an_resolve(phy, params, vars,
6400 } else { /* Link_down */
6401 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6402 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6403 /* Check signal is detected */
6404 elink_check_fallback_to_cl37(phy, params);
6408 /* Read LP advertised speeds*/
6409 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6410 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
6413 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6414 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
6416 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6417 vars->link_status |=
6418 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6419 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6420 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6421 vars->link_status |=
6422 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6424 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6425 MDIO_OVER_1G_LP_UP1, &val);
6427 if (val & MDIO_OVER_1G_UP1_2_5G)
6428 vars->link_status |=
6429 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6430 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6431 vars->link_status |=
6432 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6435 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6436 vars->duplex, vars->flow_ctrl, vars->link_status);
6440 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6441 struct elink_params *params,
6442 struct elink_vars *vars)
6444 struct bxe_softc *sc = params->sc;
6446 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
6447 elink_status_t rc = ELINK_STATUS_OK;
6448 lane = elink_get_warpcore_lane(phy, params);
6449 /* Read gp_status */
6450 if ((params->loopback_mode) &&
6451 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6452 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6453 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6454 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6455 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6457 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6458 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6459 uint16_t temp_link_up;
6460 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6462 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6464 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",
6465 temp_link_up, link_up);
6468 elink_ext_phy_resolve_fc(phy, params, vars);
6470 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6471 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6473 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);
6474 /* Check for either KR, 1G, or AN up. */
6475 link_up = ((gp_status1 >> 8) |
6476 (gp_status1 >> 12) |
6479 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6481 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6482 MDIO_AN_REG_STATUS, &an_link);
6483 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6484 MDIO_AN_REG_STATUS, &an_link);
6485 link_up |= (an_link & (1<<2));
6487 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
6488 uint16_t pd, gp_status4;
6489 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6490 /* Check Autoneg complete */
6491 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6492 MDIO_WC_REG_GP2_STATUS_GP_2_4,
6494 if (gp_status4 & ((1<<12)<<lane))
6495 vars->link_status |=
6496 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6498 /* Check parallel detect used */
6499 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6500 MDIO_WC_REG_PAR_DET_10G_STATUS,
6503 vars->link_status |=
6504 LINK_STATUS_PARALLEL_DETECTION_USED;
6506 elink_ext_phy_resolve_fc(phy, params, vars);
6507 vars->duplex = duplex;
6511 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
6512 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6515 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6516 MDIO_AN_REG_LP_AUTO_NEG2, &val);
6518 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6519 vars->link_status |=
6520 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6521 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6522 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6523 vars->link_status |=
6524 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6526 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6527 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
6529 if (val & MDIO_OVER_1G_UP1_2_5G)
6530 vars->link_status |=
6531 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6532 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6533 vars->link_status |=
6534 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6540 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6541 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
6543 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6544 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
6546 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6548 if ((lane & 1) == 0)
6551 link_up = !!link_up;
6553 /* Reset the TX FIFO to fix SGMII issue */
6554 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6557 /* In case of KR link down, start up the recovering procedure */
6558 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6559 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6560 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
6562 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6563 vars->duplex, vars->flow_ctrl, vars->link_status);
6566 static void elink_set_gmii_tx_driver(struct elink_params *params)
6568 struct bxe_softc *sc = params->sc;
6569 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6575 CL22_RD_OVER_CL45(sc, phy,
6576 MDIO_REG_BANK_OVER_1G,
6577 MDIO_OVER_1G_LP_UP2, &lp_up2);
6579 /* Bits [10:7] at lp_up2, positioned at [15:12] */
6580 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
6581 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
6582 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
6587 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
6588 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
6589 CL22_RD_OVER_CL45(sc, phy,
6591 MDIO_TX0_TX_DRIVER, &tx_driver);
6593 /* Replace tx_driver bits [15:12] */
6595 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
6596 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
6597 tx_driver |= lp_up2;
6598 CL22_WR_OVER_CL45(sc, phy,
6600 MDIO_TX0_TX_DRIVER, tx_driver);
6605 static elink_status_t elink_emac_program(struct elink_params *params,
6606 struct elink_vars *vars)
6608 struct bxe_softc *sc = params->sc;
6609 uint8_t port = params->port;
6612 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n");
6613 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6615 (EMAC_MODE_25G_MODE |
6616 EMAC_MODE_PORT_MII_10M |
6617 EMAC_MODE_HALF_DUPLEX));
6618 switch (vars->line_speed) {
6619 case ELINK_SPEED_10:
6620 mode |= EMAC_MODE_PORT_MII_10M;
6623 case ELINK_SPEED_100:
6624 mode |= EMAC_MODE_PORT_MII;
6627 case ELINK_SPEED_1000:
6628 mode |= EMAC_MODE_PORT_GMII;
6631 case ELINK_SPEED_2500:
6632 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
6636 /* 10G not valid for EMAC */
6637 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6639 return ELINK_STATUS_ERROR;
6642 if (vars->duplex == DUPLEX_HALF)
6643 mode |= EMAC_MODE_HALF_DUPLEX;
6645 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6648 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
6649 return ELINK_STATUS_OK;
6652 static void elink_set_preemphasis(struct elink_phy *phy,
6653 struct elink_params *params)
6656 uint16_t bank, i = 0;
6657 struct bxe_softc *sc = params->sc;
6659 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
6660 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
6661 CL22_WR_OVER_CL45(sc, phy,
6663 MDIO_RX0_RX_EQ_BOOST,
6664 phy->rx_preemphasis[i]);
6667 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
6668 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
6669 CL22_WR_OVER_CL45(sc, phy,
6672 phy->tx_preemphasis[i]);
6676 static void elink_xgxs_config_init(struct elink_phy *phy,
6677 struct elink_params *params,
6678 struct elink_vars *vars)
6680 struct bxe_softc *sc = params->sc;
6681 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6682 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6683 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
6684 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6685 (params->feature_config_flags &
6686 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
6687 elink_set_preemphasis(phy, params);
6689 /* Forced speed requested? */
6690 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
6691 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6692 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
6693 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n");
6695 /* Disable autoneg */
6696 elink_set_autoneg(phy, params, vars, 0);
6698 /* Program speed and duplex */
6699 elink_program_serdes(phy, params, vars);
6701 } else { /* AN_mode */
6702 ELINK_DEBUG_P0(sc, "not SGMII, AN\n");
6705 elink_set_brcm_cl37_advertisement(phy, params);
6707 /* Program duplex & pause advertisement (for aneg) */
6708 elink_set_ieee_aneg_advertisement(phy, params,
6711 /* Enable autoneg */
6712 elink_set_autoneg(phy, params, vars, enable_cl73);
6714 /* Enable and restart AN */
6715 elink_restart_autoneg(phy, params, enable_cl73);
6718 } else { /* SGMII mode */
6719 ELINK_DEBUG_P0(sc, "SGMII\n");
6721 elink_initialize_sgmii_process(phy, params, vars);
6725 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6726 struct elink_params *params,
6727 struct elink_vars *vars)
6730 vars->phy_flags |= PHY_XGXS_FLAG;
6731 if ((phy->req_line_speed &&
6732 ((phy->req_line_speed == ELINK_SPEED_100) ||
6733 (phy->req_line_speed == ELINK_SPEED_10))) ||
6734 (!phy->req_line_speed &&
6735 (phy->speed_cap_mask >=
6736 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6737 (phy->speed_cap_mask <
6738 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6739 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6740 vars->phy_flags |= PHY_SGMII_FLAG;
6742 vars->phy_flags &= ~PHY_SGMII_FLAG;
6744 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6745 elink_set_aer_mmd(params, phy);
6746 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6747 elink_set_master_ln(params, phy);
6749 rc = elink_reset_unicore(params, phy, 0);
6750 /* Reset the SerDes and wait for reset bit return low */
6751 if (rc != ELINK_STATUS_OK)
6754 elink_set_aer_mmd(params, phy);
6755 /* Setting the masterLn_def again after the reset */
6756 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6757 elink_set_master_ln(params, phy);
6758 elink_set_swap_lanes(params, phy);
6764 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc,
6765 struct elink_phy *phy,
6766 struct elink_params *params)
6769 /* Wait for soft reset to get cleared up to 1 sec */
6770 for (cnt = 0; cnt < 1000; cnt++) {
6771 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6772 elink_cl22_read(sc, phy,
6773 MDIO_PMA_REG_CTRL, &ctrl);
6775 elink_cl45_read(sc, phy,
6777 MDIO_PMA_REG_CTRL, &ctrl);
6778 if (!(ctrl & (1<<15)))
6784 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6787 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6791 static void elink_link_int_enable(struct elink_params *params)
6793 uint8_t port = params->port;
6795 struct bxe_softc *sc = params->sc;
6797 /* Setting the status to report on link up for either XGXS or SerDes */
6798 if (CHIP_IS_E3(sc)) {
6799 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
6800 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
6801 mask |= ELINK_NIG_MASK_MI_INT;
6802 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6803 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
6804 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
6805 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n");
6806 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6807 params->phy[ELINK_INT_PHY].type !=
6808 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6809 mask |= ELINK_NIG_MASK_MI_INT;
6810 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6813 } else { /* SerDes */
6814 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
6815 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n");
6816 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6817 params->phy[ELINK_INT_PHY].type !=
6818 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6819 mask |= ELINK_NIG_MASK_MI_INT;
6820 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6824 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6827 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6828 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
6829 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6830 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6831 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6832 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6833 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6834 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
6835 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6836 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6839 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6842 uint32_t latch_status = 0;
6844 /* Disable the MI INT ( external phy int ) by writing 1 to the
6845 * status register. Link down indication is high-active-signal,
6846 * so in this case we need to write the status to clear the XOR
6848 /* Read Latched signals */
6849 latch_status = REG_RD(sc,
6850 NIG_REG_LATCH_STATUS_0 + port*8);
6851 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);
6852 /* Handle only those with latched-signal=up.*/
6855 NIG_REG_STATUS_INTERRUPT_PORT0
6857 ELINK_NIG_STATUS_EMAC0_MI_INT);
6860 NIG_REG_STATUS_INTERRUPT_PORT0
6862 ELINK_NIG_STATUS_EMAC0_MI_INT);
6864 if (latch_status & 1) {
6866 /* For all latched-signal=up : Re-Arm Latch signals */
6867 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6868 (latch_status & 0xfffe) | (latch_status & 1));
6870 /* For all latched-signal=up,Write original_signal to status */
6873 static void elink_link_int_ack(struct elink_params *params,
6874 struct elink_vars *vars, uint8_t is_10g_plus)
6876 struct bxe_softc *sc = params->sc;
6877 uint8_t port = params->port;
6879 /* First reset all status we assume only one line will be
6882 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6883 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6884 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6885 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
6886 if (vars->phy_link_up) {
6887 if (USES_WARPCORE(sc))
6888 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
6891 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
6892 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6893 /* Disable the link interrupt by writing 1 to
6894 * the relevant lane in the status register
6897 ((params->lane_config &
6898 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6899 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6900 mask = ((1 << ser_lane) <<
6901 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6903 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
6905 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",
6908 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6913 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len)
6915 uint8_t *str_ptr = str;
6916 uint32_t mask = 0xf0000000;
6917 uint8_t shift = 8*4;
6919 uint8_t remove_leading_zeros = 1;
6921 /* Need more than 10chars for this format */
6924 return ELINK_STATUS_ERROR;
6929 digit = ((num & mask) >> shift);
6930 if (digit == 0 && remove_leading_zeros) {
6933 } else if (digit < 0xa)
6934 *str_ptr = digit + '0';
6936 *str_ptr = digit - 0xa + 'a';
6937 remove_leading_zeros = 0;
6945 remove_leading_zeros = 1;
6948 return ELINK_STATUS_OK;
6952 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
6956 return ELINK_STATUS_OK;
6959 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
6962 struct bxe_softc *sc;
6963 uint32_t spirom_ver = 0;
6964 elink_status_t status = ELINK_STATUS_OK;
6965 uint8_t *ver_p = version;
6966 uint16_t remain_len = len;
6967 if (version == NULL || params == NULL)
6968 return ELINK_STATUS_ERROR;
6971 /* Extract first external phy*/
6973 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
6975 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
6976 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
6979 ver_p += (len - remain_len);
6981 if ((params->num_phys == ELINK_MAX_PHYS) &&
6982 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
6983 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
6984 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
6988 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
6992 ver_p = version + (len - remain_len);
6999 static void elink_set_xgxs_loopback(struct elink_phy *phy,
7000 struct elink_params *params)
7002 uint8_t port = params->port;
7003 struct bxe_softc *sc = params->sc;
7005 if (phy->req_line_speed != ELINK_SPEED_1000) {
7006 uint32_t md_devad = 0;
7008 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n");
7010 if (!CHIP_IS_E3(sc)) {
7011 /* Change the uni_phy_addr in the nig */
7012 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7015 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7019 elink_cl45_write(sc, phy,
7021 (MDIO_REG_BANK_AER_BLOCK +
7022 (MDIO_AER_BLOCK_AER_REG & 0xf)),
7025 elink_cl45_write(sc, phy,
7027 (MDIO_REG_BANK_CL73_IEEEB0 +
7028 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
7031 /* Set aer mmd back */
7032 elink_set_aer_mmd(params, phy);
7034 if (!CHIP_IS_E3(sc)) {
7036 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7041 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n");
7042 elink_cl45_read(sc, phy, 5,
7043 (MDIO_REG_BANK_COMBO_IEEE0 +
7044 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7046 elink_cl45_write(sc, phy, 5,
7047 (MDIO_REG_BANK_COMBO_IEEE0 +
7048 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7050 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
7054 elink_status_t elink_set_led(struct elink_params *params,
7055 struct elink_vars *vars, uint8_t mode, uint32_t speed)
7057 uint8_t port = params->port;
7058 uint16_t hw_led_mode = params->hw_led_mode;
7059 elink_status_t rc = ELINK_STATUS_OK;
7062 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7063 struct bxe_softc *sc = params->sc;
7064 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7065 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",
7066 speed, hw_led_mode);
7068 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7069 if (params->phy[phy_idx].set_link_led) {
7070 params->phy[phy_idx].set_link_led(
7071 ¶ms->phy[phy_idx], params, mode);
7074 #ifdef ELINK_INCLUDE_EMUL
7075 if (params->feature_config_flags &
7076 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
7081 case ELINK_LED_MODE_FRONT_PANEL_OFF:
7082 case ELINK_LED_MODE_OFF:
7083 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7084 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7085 SHARED_HW_CFG_LED_MAC1);
7087 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7088 if (params->phy[ELINK_EXT_PHY1].type ==
7089 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
7090 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
7091 EMAC_LED_100MB_OVERRIDE |
7092 EMAC_LED_10MB_OVERRIDE);
7094 tmp |= EMAC_LED_OVERRIDE;
7096 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
7099 case ELINK_LED_MODE_OPER:
7100 /* For all other phys, OPER mode is same as ON, so in case
7101 * link is down, do nothing
7105 case ELINK_LED_MODE_ON:
7106 if (((params->phy[ELINK_EXT_PHY1].type ==
7107 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
7108 (params->phy[ELINK_EXT_PHY1].type ==
7109 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
7110 CHIP_IS_E2(sc) && params->num_phys == 2) {
7111 /* This is a work-around for E2+8727 Configurations */
7112 if (mode == ELINK_LED_MODE_ON ||
7113 speed == ELINK_SPEED_10000){
7114 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7115 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7117 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7118 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7119 (tmp | EMAC_LED_OVERRIDE));
7120 /* Return here without enabling traffic
7121 * LED blink and setting rate in ON mode.
7122 * In oper mode, enabling LED blink
7123 * and setting rate is needed.
7125 if (mode == ELINK_LED_MODE_ON)
7128 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
7129 /* This is a work-around for HW issue found when link
7132 if ((!CHIP_IS_E3(sc)) ||
7134 mode == ELINK_LED_MODE_ON))
7135 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7137 if (CHIP_IS_E1x(sc) ||
7139 (mode == ELINK_LED_MODE_ON))
7140 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7142 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7144 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7145 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
7146 (mode == ELINK_LED_MODE_ON)) {
7147 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7148 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7149 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp |
7150 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
7151 /* Break here; otherwise, it'll disable the
7152 * intended override.
7156 uint32_t nig_led_mode = ((params->hw_led_mode <<
7157 SHARED_HW_CFG_LED_MODE_SHIFT) ==
7158 SHARED_HW_CFG_LED_EXTPHY2) ?
7159 (SHARED_HW_CFG_LED_PHY1 >>
7160 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
7161 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7165 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7166 /* Set blinking rate to ~15.9Hz */
7168 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7169 LED_BLINK_RATE_VAL_E3);
7171 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7172 LED_BLINK_RATE_VAL_E1X_E2);
7173 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7175 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7176 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7177 (tmp & (~EMAC_LED_OVERRIDE)));
7179 if (CHIP_IS_E1(sc) &&
7180 ((speed == ELINK_SPEED_2500) ||
7181 (speed == ELINK_SPEED_1000) ||
7182 (speed == ELINK_SPEED_100) ||
7183 (speed == ELINK_SPEED_10))) {
7184 /* For speeds less than 10G LED scheme is different */
7185 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7187 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7189 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7195 rc = ELINK_STATUS_ERROR;
7196 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n",
7204 /* This function comes to reflect the actual link state read DIRECTLY from the
7207 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
7210 struct bxe_softc *sc = params->sc;
7211 uint16_t gp_status = 0, phy_index = 0;
7212 uint8_t ext_phy_link_up = 0, serdes_phy_type;
7213 struct elink_vars temp_vars;
7214 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7215 #ifdef ELINK_INCLUDE_FPGA
7216 if (CHIP_REV_IS_FPGA(sc))
7217 return ELINK_STATUS_OK;
7219 #ifdef ELINK_INCLUDE_EMUL
7220 if (CHIP_REV_IS_EMUL(sc))
7221 return ELINK_STATUS_OK;
7224 if (CHIP_IS_E3(sc)) {
7226 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
7227 > ELINK_SPEED_10000) {
7228 /* Check 20G link */
7229 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7231 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7235 /* Check 10G link and below*/
7236 uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7237 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7238 MDIO_WC_REG_GP2_STATUS_GP_2_1,
7240 gp_status = ((gp_status >> 8) & 0xf) |
7241 ((gp_status >> 12) & 0xf);
7242 link_up = gp_status & (1 << lane);
7245 return ELINK_STATUS_NO_LINK;
7247 CL22_RD_OVER_CL45(sc, int_phy,
7248 MDIO_REG_BANK_GP_STATUS,
7249 MDIO_GP_STATUS_TOP_AN_STATUS1,
7251 /* Link is up only if both local phy and external phy are up */
7252 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
7253 return ELINK_STATUS_NO_LINK;
7255 /* In XGXS loopback mode, do not check external PHY */
7256 if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
7257 return ELINK_STATUS_OK;
7259 switch (params->num_phys) {
7261 /* No external PHY */
7262 return ELINK_STATUS_OK;
7264 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7265 ¶ms->phy[ELINK_EXT_PHY1],
7266 params, &temp_vars);
7268 case 3: /* Dual Media */
7269 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7271 serdes_phy_type = ((params->phy[phy_index].media_type ==
7272 ELINK_ETH_PHY_SFPP_10G_FIBER) ||
7273 (params->phy[phy_index].media_type ==
7274 ELINK_ETH_PHY_SFP_1G_FIBER) ||
7275 (params->phy[phy_index].media_type ==
7276 ELINK_ETH_PHY_XFP_FIBER) ||
7277 (params->phy[phy_index].media_type ==
7278 ELINK_ETH_PHY_DA_TWINAX));
7280 if (is_serdes != serdes_phy_type)
7282 if (params->phy[phy_index].read_status) {
7284 params->phy[phy_index].read_status(
7285 ¶ms->phy[phy_index],
7286 params, &temp_vars);
7291 if (ext_phy_link_up)
7292 return ELINK_STATUS_OK;
7293 return ELINK_STATUS_NO_LINK;
7296 static elink_status_t elink_link_initialize(struct elink_params *params,
7297 struct elink_vars *vars)
7299 elink_status_t rc = ELINK_STATUS_OK;
7300 uint8_t phy_index, non_ext_phy;
7301 struct bxe_softc *sc = params->sc;
7302 /* In case of external phy existence, the line speed would be the
7303 * line speed linked up by the external phy. In case it is direct
7304 * only, then the line_speed during initialization will be
7305 * equal to the req_line_speed
7307 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7309 /* Initialize the internal phy in case this is a direct board
7310 * (no external phys), or this board has external phy which requires
7313 if (!USES_WARPCORE(sc))
7314 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7315 /* init ext phy and enable link state int */
7316 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
7317 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
7320 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7321 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7322 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7323 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7326 elink_set_parallel_detection(phy, params);
7327 if (params->phy[ELINK_INT_PHY].config_init)
7328 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7331 /* Re-read this value in case it was changed inside config_init due to
7332 * limitations of optic module
7334 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7336 /* Init external phy*/
7338 if (params->phy[ELINK_INT_PHY].supported &
7339 ELINK_SUPPORTED_FIBRE)
7340 vars->link_status |= LINK_STATUS_SERDES_LINK;
7342 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7344 /* No need to initialize second phy in case of first
7345 * phy only selection. In case of second phy, we do
7346 * need to initialize the first phy, since they are
7349 if (params->phy[phy_index].supported &
7350 ELINK_SUPPORTED_FIBRE)
7351 vars->link_status |= LINK_STATUS_SERDES_LINK;
7353 if (phy_index == ELINK_EXT_PHY2 &&
7354 (elink_phy_selection(params) ==
7355 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
7357 "Not initializing second phy\n");
7360 params->phy[phy_index].config_init(
7361 ¶ms->phy[phy_index],
7365 /* Reset the interrupt indication after phy was initialized */
7366 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
7368 (ELINK_NIG_STATUS_XGXS0_LINK10G |
7369 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
7370 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
7371 ELINK_NIG_MASK_MI_INT));
7375 static void elink_int_link_reset(struct elink_phy *phy,
7376 struct elink_params *params)
7378 /* Reset the SerDes/XGXS */
7379 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7380 (0x1ff << (params->port*16)));
7383 static void elink_common_ext_link_reset(struct elink_phy *phy,
7384 struct elink_params *params)
7386 struct bxe_softc *sc = params->sc;
7390 gpio_port = SC_PATH(sc);
7392 gpio_port = params->port;
7393 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7394 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7396 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7397 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7399 ELINK_DEBUG_P0(sc, "reset external PHY\n");
7402 static elink_status_t elink_update_link_down(struct elink_params *params,
7403 struct elink_vars *vars)
7405 struct bxe_softc *sc = params->sc;
7406 uint8_t port = params->port;
7408 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7409 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
7410 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
7411 /* Indicate no mac active */
7412 vars->mac_type = ELINK_MAC_TYPE_NONE;
7414 /* Update shared memory */
7415 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7416 vars->line_speed = 0;
7417 elink_update_mng(params, vars->link_status);
7419 /* Activate nig drain */
7420 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7423 if (!CHIP_IS_E3(sc))
7424 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7427 /* Reset BigMac/Xmac */
7428 if (CHIP_IS_E1x(sc) ||
7430 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7432 if (CHIP_IS_E3(sc)) {
7433 /* Prevent LPI Generation by chip */
7434 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7436 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7438 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
7439 SHMEM_EEE_ACTIVE_BIT);
7441 elink_update_mng_eee(params, vars->eee_status);
7442 elink_set_xmac_rxtx(params, 0);
7443 elink_set_umac_rxtx(params, 0);
7446 return ELINK_STATUS_OK;
7449 static elink_status_t elink_update_link_up(struct elink_params *params,
7450 struct elink_vars *vars,
7453 struct bxe_softc *sc = params->sc;
7454 uint8_t phy_idx, port = params->port;
7455 elink_status_t rc = ELINK_STATUS_OK;
7457 vars->link_status |= (LINK_STATUS_LINK_UP |
7458 LINK_STATUS_PHYSICAL_LINK_FLAG);
7459 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7461 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
7462 vars->link_status |=
7463 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
7465 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
7466 vars->link_status |=
7467 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7468 if (USES_WARPCORE(sc)) {
7470 if (elink_xmac_enable(params, vars, 0) ==
7471 ELINK_STATUS_NO_LINK) {
7472 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n");
7474 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7475 vars->link_status &= ~LINK_STATUS_LINK_UP;
7478 elink_umac_enable(params, vars, 0);
7479 elink_set_led(params, vars,
7480 ELINK_LED_MODE_OPER, vars->line_speed);
7482 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
7483 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
7484 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n");
7485 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7486 (params->port << 2), 1);
7487 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7488 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7489 (params->port << 2), 0xfc20);
7492 if ((CHIP_IS_E1x(sc) ||
7495 if (elink_bmac_enable(params, vars, 0, 1) ==
7496 ELINK_STATUS_NO_LINK) {
7497 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n");
7499 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7500 vars->link_status &= ~LINK_STATUS_LINK_UP;
7503 elink_set_led(params, vars,
7504 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
7506 rc = elink_emac_program(params, vars);
7507 elink_emac_enable(params, vars, 0);
7510 if ((vars->link_status &
7511 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
7512 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
7513 ELINK_SINGLE_MEDIA_DIRECT(params))
7514 elink_set_gmii_tx_driver(params);
7519 if (CHIP_IS_E1x(sc))
7520 rc |= elink_pbf_update(params, vars->flow_ctrl,
7524 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7526 /* Update shared memory */
7527 elink_update_mng(params, vars->link_status);
7528 elink_update_mng_eee(params, vars->eee_status);
7529 /* Check remote fault */
7530 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7531 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7532 elink_check_half_open_conn(params, vars, 0);
7539 /* The elink_link_update function should be called upon link
7541 * Link is considered up as follows:
7542 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7544 * - SINGLE_MEDIA - The link between the 577xx and the external
7545 * phy (XGXS) need to up as well as the external link of the
7547 * - DUAL_MEDIA - The link between the 577xx and the first
7548 * external phy needs to be up, and at least one of the 2
7549 * external phy link must be up.
7551 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
7553 struct bxe_softc *sc = params->sc;
7554 struct elink_vars phy_vars[ELINK_MAX_PHYS];
7555 uint8_t port = params->port;
7556 uint8_t link_10g_plus, phy_index;
7557 uint8_t ext_phy_link_up = 0, cur_link_up;
7558 elink_status_t rc = ELINK_STATUS_OK;
7559 uint8_t is_mi_int = 0;
7560 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
7561 uint8_t active_external_phy = ELINK_INT_PHY;
7562 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
7563 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7564 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
7566 phy_vars[phy_index].flow_ctrl = 0;
7567 phy_vars[phy_index].link_status = 0;
7568 phy_vars[phy_index].line_speed = 0;
7569 phy_vars[phy_index].duplex = DUPLEX_FULL;
7570 phy_vars[phy_index].phy_link_up = 0;
7571 phy_vars[phy_index].link_up = 0;
7572 phy_vars[phy_index].fault_detected = 0;
7573 /* different consideration, since vars holds inner state */
7574 phy_vars[phy_index].eee_status = vars->eee_status;
7577 if (USES_WARPCORE(sc))
7578 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7580 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7581 port, (vars->phy_flags & PHY_XGXS_FLAG),
7582 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7584 is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT +
7586 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7587 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7589 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7591 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
7592 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7593 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7596 if (!CHIP_IS_E3(sc))
7597 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7600 * Check external link change only for external phys, and apply
7601 * priority selection between them in case the link on both phys
7602 * is up. Note that instead of the common vars, a temporary
7603 * vars argument is used since each phy may have different link/
7604 * speed/duplex result
7606 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7608 struct elink_phy *phy = ¶ms->phy[phy_index];
7609 if (!phy->read_status)
7611 /* Read link status and params of this ext phy */
7612 cur_link_up = phy->read_status(phy, params,
7613 &phy_vars[phy_index]);
7615 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7618 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7623 if (!ext_phy_link_up) {
7624 ext_phy_link_up = 1;
7625 active_external_phy = phy_index;
7627 switch (elink_phy_selection(params)) {
7628 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7629 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7630 /* In this option, the first PHY makes sure to pass the
7631 * traffic through itself only.
7632 * Its not clear how to reset the link on the second phy
7634 active_external_phy = ELINK_EXT_PHY1;
7636 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7637 /* In this option, the first PHY makes sure to pass the
7638 * traffic through the second PHY.
7640 active_external_phy = ELINK_EXT_PHY2;
7643 /* Link indication on both PHYs with the following cases
7645 * - FIRST_PHY means that second phy wasn't initialized,
7646 * hence its link is expected to be down
7647 * - SECOND_PHY means that first phy should not be able
7648 * to link up by itself (using configuration)
7649 * - DEFAULT should be overriden during initialiazation
7651 ELINK_DEBUG_P1(sc, "Invalid link indication"
7652 "mpc=0x%x. DISABLING LINK !!!\n",
7653 params->multi_phy_config);
7654 ext_phy_link_up = 0;
7659 prev_line_speed = vars->line_speed;
7661 * Read the status of the internal phy. In case of
7662 * DIRECT_SINGLE_MEDIA board, this link is the external link,
7663 * otherwise this is the link between the 577xx and the first
7666 if (params->phy[ELINK_INT_PHY].read_status)
7667 params->phy[ELINK_INT_PHY].read_status(
7668 ¶ms->phy[ELINK_INT_PHY],
7670 /* The INT_PHY flow control reside in the vars. This include the
7671 * case where the speed or flow control are not set to AUTO.
7672 * Otherwise, the active external phy flow control result is set
7673 * to the vars. The ext_phy_line_speed is needed to check if the
7674 * speed is different between the internal phy and external phy.
7675 * This case may be result of intermediate link speed change.
7677 if (active_external_phy > ELINK_INT_PHY) {
7678 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
7679 /* Link speed is taken from the XGXS. AN and FC result from
7682 vars->link_status |= phy_vars[active_external_phy].link_status;
7684 /* if active_external_phy is first PHY and link is up - disable
7685 * disable TX on second external PHY
7687 if (active_external_phy == ELINK_EXT_PHY1) {
7688 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7690 "Disabling TX on EXT_PHY2\n");
7691 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7692 ¶ms->phy[ELINK_EXT_PHY2],
7693 params, ELINK_DISABLE_TX);
7697 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7698 vars->duplex = phy_vars[active_external_phy].duplex;
7699 if (params->phy[active_external_phy].supported &
7700 ELINK_SUPPORTED_FIBRE)
7701 vars->link_status |= LINK_STATUS_SERDES_LINK;
7703 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7705 vars->eee_status = phy_vars[active_external_phy].eee_status;
7707 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7708 active_external_phy);
7711 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7713 if (params->phy[phy_index].flags &
7714 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
7715 elink_rearm_latch_signal(sc, port,
7717 active_external_phy);
7721 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7722 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7723 vars->link_status, ext_phy_line_speed);
7724 /* Upon link speed change set the NIG into drain mode. Comes to
7725 * deals with possible FIFO glitch due to clk change when speed
7726 * is decreased without link down indicator
7729 if (vars->phy_link_up) {
7730 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7731 (ext_phy_line_speed != vars->line_speed)) {
7732 ELINK_DEBUG_P2(sc, "Internal link speed %d is"
7733 " different than the external"
7734 " link speed %d\n", vars->line_speed,
7735 ext_phy_line_speed);
7736 vars->phy_link_up = 0;
7737 } else if (prev_line_speed != vars->line_speed) {
7738 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7744 /* Anything 10 and over uses the bmac */
7745 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
7747 elink_link_int_ack(params, vars, link_10g_plus);
7749 /* In case external phy link is up, and internal link is down
7750 * (not initialized yet probably after link initialization, it
7751 * needs to be initialized.
7752 * Note that after link down-up as result of cable plug, the xgxs
7753 * link would probably become up again without the need
7756 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
7757 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
7758 " init_preceding = %d\n", ext_phy_link_up,
7760 params->phy[ELINK_EXT_PHY1].flags &
7761 ELINK_FLAGS_INIT_XGXS_FIRST);
7762 if (!(params->phy[ELINK_EXT_PHY1].flags &
7763 ELINK_FLAGS_INIT_XGXS_FIRST)
7764 && ext_phy_link_up && !vars->phy_link_up) {
7765 vars->line_speed = ext_phy_line_speed;
7766 if (vars->line_speed < ELINK_SPEED_1000)
7767 vars->phy_flags |= PHY_SGMII_FLAG;
7769 vars->phy_flags &= ~PHY_SGMII_FLAG;
7771 if (params->phy[ELINK_INT_PHY].config_init)
7772 params->phy[ELINK_INT_PHY].config_init(
7773 ¶ms->phy[ELINK_INT_PHY], params,
7777 /* Link is up only if both local phy and external phy (in case of
7778 * non-direct board) are up and no fault detected on active PHY.
7780 vars->link_up = (vars->phy_link_up &&
7782 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
7783 (phy_vars[active_external_phy].fault_detected == 0));
7785 /* Update the PFC configuration in case it was changed */
7786 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
7787 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7789 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7792 rc = elink_update_link_up(params, vars, link_10g_plus);
7794 rc = elink_update_link_down(params, vars);
7796 /* Update MCP link status was changed */
7797 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7798 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7803 /*****************************************************************************/
7804 /* External Phy section */
7805 /*****************************************************************************/
7806 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7808 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7809 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7811 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7812 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7815 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7816 uint32_t spirom_ver, uint32_t ver_addr)
7818 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7819 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7822 REG_WR(sc, ver_addr, spirom_ver);
7825 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc,
7826 struct elink_phy *phy,
7829 uint16_t fw_ver1, fw_ver2;
7831 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7832 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7833 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7834 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7835 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7839 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc,
7840 struct elink_phy *phy,
7841 struct elink_vars *vars)
7844 elink_cl45_read(sc, phy,
7846 MDIO_AN_REG_STATUS, &val);
7847 elink_cl45_read(sc, phy,
7849 MDIO_AN_REG_STATUS, &val);
7851 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7852 if ((val & (1<<0)) == 0)
7853 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7856 /******************************************************************/
7857 /* common BCM8073/BCM8727 PHY SECTION */
7858 /******************************************************************/
7859 static void elink_8073_resolve_fc(struct elink_phy *phy,
7860 struct elink_params *params,
7861 struct elink_vars *vars)
7863 struct bxe_softc *sc = params->sc;
7864 if (phy->req_line_speed == ELINK_SPEED_10 ||
7865 phy->req_line_speed == ELINK_SPEED_100) {
7866 vars->flow_ctrl = phy->req_flow_ctrl;
7870 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
7871 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
7872 uint16_t pause_result;
7873 uint16_t ld_pause; /* local */
7874 uint16_t lp_pause; /* link partner */
7875 elink_cl45_read(sc, phy,
7877 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7879 elink_cl45_read(sc, phy,
7881 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7882 pause_result = (ld_pause &
7883 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7884 pause_result |= (lp_pause &
7885 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7887 elink_pause_resolve(vars, pause_result);
7888 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",
7892 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc,
7893 struct elink_phy *phy,
7897 uint16_t fw_ver1, fw_msgout;
7898 elink_status_t rc = ELINK_STATUS_OK;
7900 /* Boot port from external ROM */
7902 elink_cl45_write(sc, phy,
7904 MDIO_PMA_REG_GEN_CTRL,
7907 /* Ucode reboot and rst */
7908 elink_cl45_write(sc, phy,
7910 MDIO_PMA_REG_GEN_CTRL,
7913 elink_cl45_write(sc, phy,
7915 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
7917 /* Reset internal microprocessor */
7918 elink_cl45_write(sc, phy,
7920 MDIO_PMA_REG_GEN_CTRL,
7921 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
7923 /* Release srst bit */
7924 elink_cl45_write(sc, phy,
7926 MDIO_PMA_REG_GEN_CTRL,
7927 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
7929 /* Delay 100ms per the PHY specifications */
7932 /* 8073 sometimes taking longer to download */
7937 "elink_8073_8727_external_rom_boot port %x:"
7938 "Download failed. fw version = 0x%x\n",
7940 rc = ELINK_STATUS_ERROR;
7944 elink_cl45_read(sc, phy,
7946 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7947 elink_cl45_read(sc, phy,
7949 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
7952 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
7953 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
7954 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
7956 /* Clear ser_boot_ctl bit */
7957 elink_cl45_write(sc, phy,
7959 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
7960 elink_save_bcm_spirom_ver(sc, phy, port);
7963 "elink_8073_8727_external_rom_boot port %x:"
7964 "Download complete. fw version = 0x%x\n",
7970 /******************************************************************/
7971 /* BCM8073 PHY SECTION */
7972 /******************************************************************/
7973 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
7975 /* This is only required for 8073A1, version 102 only */
7978 /* Read 8073 HW revision*/
7979 elink_cl45_read(sc, phy,
7981 MDIO_PMA_REG_8073_CHIP_REV, &val);
7984 /* No need to workaround in 8073 A1 */
7985 return ELINK_STATUS_OK;
7988 elink_cl45_read(sc, phy,
7990 MDIO_PMA_REG_ROM_VER2, &val);
7992 /* SNR should be applied only for version 0x102 */
7994 return ELINK_STATUS_OK;
7999 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
8001 uint16_t val, cnt, cnt1 ;
8003 elink_cl45_read(sc, phy,
8005 MDIO_PMA_REG_8073_CHIP_REV, &val);
8008 /* No need to workaround in 8073 A1 */
8009 return ELINK_STATUS_OK;
8011 /* XAUI workaround in 8073 A0: */
8013 /* After loading the boot ROM and restarting Autoneg, poll
8017 for (cnt = 0; cnt < 1000; cnt++) {
8018 elink_cl45_read(sc, phy,
8020 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8022 /* If bit [14] = 0 or bit [13] = 0, continue on with
8023 * system initialization (XAUI work-around not required, as
8024 * these bits indicate 2.5G or 1G link up).
8026 if (!(val & (1<<14)) || !(val & (1<<13))) {
8027 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n");
8028 return ELINK_STATUS_OK;
8029 } else if (!(val & (1<<15))) {
8030 ELINK_DEBUG_P0(sc, "bit 15 went off\n");
8031 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
8032 * MSB (bit15) goes to 1 (indicating that the XAUI
8033 * workaround has completed), then continue on with
8034 * system initialization.
8036 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
8037 elink_cl45_read(sc, phy,
8039 MDIO_PMA_REG_8073_XAUI_WA, &val);
8040 if (val & (1<<15)) {
8042 "XAUI workaround has completed\n");
8043 return ELINK_STATUS_OK;
8051 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n");
8052 return ELINK_STATUS_ERROR;
8055 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8057 /* Force KR or KX */
8058 elink_cl45_write(sc, phy,
8059 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8060 elink_cl45_write(sc, phy,
8061 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
8062 elink_cl45_write(sc, phy,
8063 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
8064 elink_cl45_write(sc, phy,
8065 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
8068 static void elink_8073_set_pause_cl37(struct elink_params *params,
8069 struct elink_phy *phy,
8070 struct elink_vars *vars)
8073 struct bxe_softc *sc = params->sc;
8074 elink_cl45_read(sc, phy,
8075 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
8077 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8078 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
8079 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8080 if ((vars->ieee_fc &
8081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
8082 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
8083 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
8085 if ((vars->ieee_fc &
8086 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
8087 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
8088 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
8090 if ((vars->ieee_fc &
8091 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
8092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
8093 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8096 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8098 elink_cl45_write(sc, phy,
8099 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
8103 static void elink_8073_specific_func(struct elink_phy *phy,
8104 struct elink_params *params,
8107 struct bxe_softc *sc = params->sc;
8109 case ELINK_PHY_INIT:
8111 elink_cl45_write(sc, phy,
8112 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
8113 elink_cl45_write(sc, phy,
8114 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8119 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8120 struct elink_params *params,
8121 struct elink_vars *vars)
8123 struct bxe_softc *sc = params->sc;
8124 uint16_t val = 0, tmp1;
8126 ELINK_DEBUG_P0(sc, "Init 8073\n");
8129 gpio_port = SC_PATH(sc);
8131 gpio_port = params->port;
8132 /* Restore normal power mode*/
8133 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8134 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8136 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8137 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8139 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8140 elink_8073_set_pause_cl37(params, phy, vars);
8142 elink_cl45_read(sc, phy,
8143 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8145 elink_cl45_read(sc, phy,
8146 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8148 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8150 /* Swap polarity if required - Must be done only in non-1G mode */
8151 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8152 /* Configure the 8073 to swap _P and _N of the KR lines */
8153 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n");
8154 /* 10G Rx/Tx and 1G Tx signal polarity swap */
8155 elink_cl45_read(sc, phy,
8157 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
8158 elink_cl45_write(sc, phy,
8160 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
8165 /* Enable CL37 BAM */
8166 if (REG_RD(sc, params->shmem_base +
8167 offsetof(struct shmem_region, dev_info.
8168 port_hw_config[params->port].default_cfg)) &
8169 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
8171 elink_cl45_read(sc, phy,
8173 MDIO_AN_REG_8073_BAM, &val);
8174 elink_cl45_write(sc, phy,
8176 MDIO_AN_REG_8073_BAM, val | 1);
8177 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
8179 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
8180 elink_807x_force_10G(sc, phy);
8181 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n");
8182 return ELINK_STATUS_OK;
8184 elink_cl45_write(sc, phy,
8185 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
8187 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8188 if (phy->req_line_speed == ELINK_SPEED_10000) {
8190 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8192 /* Note that 2.5G works only when used with 1G
8199 if (phy->speed_cap_mask &
8200 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
8203 /* Note that 2.5G works only when used with 1G advertisement */
8204 if (phy->speed_cap_mask &
8205 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
8206 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8208 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);
8211 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8212 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8214 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8215 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8216 (phy->req_line_speed == ELINK_SPEED_2500)) {
8218 /* Allow 2.5G for A1 and above */
8219 elink_cl45_read(sc, phy,
8220 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
8222 ELINK_DEBUG_P0(sc, "Add 2.5G\n");
8228 ELINK_DEBUG_P0(sc, "Disable 2.5G\n");
8232 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8233 /* Add support for CL37 (passive mode) II */
8235 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8236 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8237 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8240 /* Add support for CL37 (passive mode) III */
8241 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8243 /* The SNR will improve about 2db by changing BW and FEE main
8244 * tap. Rest commands are executed after link is up
8245 * Change FFE main cursor to 5 in EDC register
8247 if (elink_8073_is_snr_needed(sc, phy))
8248 elink_cl45_write(sc, phy,
8249 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
8252 /* Enable FEC (Forware Error Correction) Request in the AN */
8253 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8255 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8257 elink_ext_phy_set_pause(params, phy, vars);
8259 /* Restart autoneg */
8261 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8262 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8263 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
8264 return ELINK_STATUS_OK;
8267 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8268 struct elink_params *params,
8269 struct elink_vars *vars)
8271 struct bxe_softc *sc = params->sc;
8272 uint8_t link_up = 0;
8273 uint16_t val1, val2;
8274 uint16_t link_status = 0;
8275 uint16_t an1000_status = 0;
8277 elink_cl45_read(sc, phy,
8278 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8280 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);
8282 /* Clear the interrupt LASI status register */
8283 elink_cl45_read(sc, phy,
8284 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8285 elink_cl45_read(sc, phy,
8286 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
8287 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);
8289 elink_cl45_read(sc, phy,
8290 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8292 /* Check the LASI */
8293 elink_cl45_read(sc, phy,
8294 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8296 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);
8298 /* Check the link status */
8299 elink_cl45_read(sc, phy,
8300 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8301 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);
8303 elink_cl45_read(sc, phy,
8304 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8305 elink_cl45_read(sc, phy,
8306 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8307 link_up = ((val1 & 4) == 4);
8308 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);
8311 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8312 if (elink_8073_xaui_wa(sc, phy) != 0)
8315 elink_cl45_read(sc, phy,
8316 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8317 elink_cl45_read(sc, phy,
8318 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8320 /* Check the link status on 1.1.2 */
8321 elink_cl45_read(sc, phy,
8322 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8323 elink_cl45_read(sc, phy,
8324 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8325 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
8326 "an_link_status=0x%x\n", val2, val1, an1000_status);
8328 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
8329 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8330 /* The SNR will improve about 2dbby changing the BW and FEE main
8331 * tap. The 1st write to change FFE main tap is set before
8332 * restart AN. Change PLL Bandwidth in EDC register
8334 elink_cl45_write(sc, phy,
8335 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
8338 /* Change CDR Bandwidth in EDC register */
8339 elink_cl45_write(sc, phy,
8340 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
8343 elink_cl45_read(sc, phy,
8344 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8347 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
8348 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8350 vars->line_speed = ELINK_SPEED_10000;
8351 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8353 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
8355 vars->line_speed = ELINK_SPEED_2500;
8356 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8358 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8360 vars->line_speed = ELINK_SPEED_1000;
8361 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8365 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8370 /* Swap polarity if required */
8371 if (params->lane_config &
8372 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8373 /* Configure the 8073 to swap P and N of the KR lines */
8374 elink_cl45_read(sc, phy,
8376 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8377 /* Set bit 3 to invert Rx in 1G mode and clear this bit
8378 * when it`s in 10G mode.
8380 if (vars->line_speed == ELINK_SPEED_1000) {
8381 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
8387 elink_cl45_write(sc, phy,
8389 MDIO_XS_REG_8073_RX_CTRL_PCIE,
8392 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8393 elink_8073_resolve_fc(phy, params, vars);
8394 vars->duplex = DUPLEX_FULL;
8397 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8398 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8399 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
8402 vars->link_status |=
8403 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
8405 vars->link_status |=
8406 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
8412 static void elink_8073_link_reset(struct elink_phy *phy,
8413 struct elink_params *params)
8415 struct bxe_softc *sc = params->sc;
8418 gpio_port = SC_PATH(sc);
8420 gpio_port = params->port;
8421 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8423 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8424 MISC_REGISTERS_GPIO_OUTPUT_LOW,
8428 /******************************************************************/
8429 /* BCM8705 PHY SECTION */
8430 /******************************************************************/
8431 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8432 struct elink_params *params,
8433 struct elink_vars *vars)
8435 struct bxe_softc *sc = params->sc;
8436 ELINK_DEBUG_P0(sc, "init 8705\n");
8437 /* Restore normal power mode*/
8438 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8439 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8441 elink_ext_phy_hw_reset(sc, params->port);
8442 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8443 elink_wait_reset_complete(sc, phy, params);
8445 elink_cl45_write(sc, phy,
8446 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
8447 elink_cl45_write(sc, phy,
8448 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
8449 elink_cl45_write(sc, phy,
8450 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
8451 elink_cl45_write(sc, phy,
8452 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
8453 /* BCM8705 doesn't have microcode, hence the 0 */
8454 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8455 return ELINK_STATUS_OK;
8458 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8459 struct elink_params *params,
8460 struct elink_vars *vars)
8462 uint8_t link_up = 0;
8463 uint16_t val1, rx_sd;
8464 struct bxe_softc *sc = params->sc;
8465 ELINK_DEBUG_P0(sc, "read status 8705\n");
8466 elink_cl45_read(sc, phy,
8467 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8468 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8470 elink_cl45_read(sc, phy,
8471 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8472 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8474 elink_cl45_read(sc, phy,
8475 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8477 elink_cl45_read(sc, phy,
8478 MDIO_PMA_DEVAD, 0xc809, &val1);
8479 elink_cl45_read(sc, phy,
8480 MDIO_PMA_DEVAD, 0xc809, &val1);
8482 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);
8483 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
8485 vars->line_speed = ELINK_SPEED_10000;
8486 elink_ext_phy_resolve_fc(phy, params, vars);
8491 /******************************************************************/
8492 /* SFP+ module Section */
8493 /******************************************************************/
8494 static void elink_set_disable_pmd_transmit(struct elink_params *params,
8495 struct elink_phy *phy,
8498 struct bxe_softc *sc = params->sc;
8499 /* Disable transmitter only for bootcodes which can enable it afterwards
8503 if (params->feature_config_flags &
8504 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
8505 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n");
8507 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n");
8511 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n");
8512 elink_cl45_write(sc, phy,
8514 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
8517 static uint8_t elink_get_gpio_port(struct elink_params *params)
8520 uint32_t swap_val, swap_override;
8521 struct bxe_softc *sc = params->sc;
8523 gpio_port = SC_PATH(sc);
8525 gpio_port = params->port;
8526 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8527 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8528 return gpio_port ^ (swap_val && swap_override);
8531 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
8532 struct elink_phy *phy,
8536 uint8_t port = params->port;
8537 struct bxe_softc *sc = params->sc;
8538 uint32_t tx_en_mode;
8540 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
8541 tx_en_mode = REG_RD(sc, params->shmem_base +
8542 offsetof(struct shmem_region,
8543 dev_info.port_hw_config[port].sfp_ctrl)) &
8544 PORT_HW_CFG_TX_LASER_MASK;
8545 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8546 "mode = %x\n", tx_en, port, tx_en_mode);
8547 switch (tx_en_mode) {
8548 case PORT_HW_CFG_TX_LASER_MDIO:
8550 elink_cl45_read(sc, phy,
8552 MDIO_PMA_REG_PHY_IDENTIFIER,
8560 elink_cl45_write(sc, phy,
8562 MDIO_PMA_REG_PHY_IDENTIFIER,
8565 case PORT_HW_CFG_TX_LASER_GPIO0:
8566 case PORT_HW_CFG_TX_LASER_GPIO1:
8567 case PORT_HW_CFG_TX_LASER_GPIO2:
8568 case PORT_HW_CFG_TX_LASER_GPIO3:
8571 uint8_t gpio_port, gpio_mode;
8573 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
8575 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
8577 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
8578 gpio_port = elink_get_gpio_port(params);
8579 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8583 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8588 static void elink_sfp_set_transmitter(struct elink_params *params,
8589 struct elink_phy *phy,
8592 struct bxe_softc *sc = params->sc;
8593 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en);
8595 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8597 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8600 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8601 struct elink_params *params,
8602 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8603 uint8_t *o_buf, uint8_t is_init)
8605 struct bxe_softc *sc = params->sc;
8608 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8610 "Reading from eeprom is limited to 0xf\n");
8611 return ELINK_STATUS_ERROR;
8613 /* Set the read command byte count */
8614 elink_cl45_write(sc, phy,
8615 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8616 (byte_cnt | (dev_addr << 8)));
8618 /* Set the read command address */
8619 elink_cl45_write(sc, phy,
8620 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8623 /* Activate read command */
8624 elink_cl45_write(sc, phy,
8625 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8628 /* Wait up to 500us for command complete status */
8629 for (i = 0; i < 100; i++) {
8630 elink_cl45_read(sc, phy,
8632 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8633 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8634 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8639 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8640 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8642 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8643 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8644 return ELINK_STATUS_ERROR;
8647 /* Read the buffer */
8648 for (i = 0; i < byte_cnt; i++) {
8649 elink_cl45_read(sc, phy,
8651 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
8652 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
8655 for (i = 0; i < 100; i++) {
8656 elink_cl45_read(sc, phy,
8658 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8659 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8660 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8661 return ELINK_STATUS_OK;
8664 return ELINK_STATUS_ERROR;
8667 static void elink_warpcore_power_module(struct elink_params *params,
8671 struct bxe_softc *sc = params->sc;
8673 pin_cfg = (REG_RD(sc, params->shmem_base +
8674 offsetof(struct shmem_region,
8675 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8676 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8677 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8679 if (pin_cfg == PIN_CFG_NA)
8681 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n",
8683 /* Low ==> corresponding SFP+ module is powered
8684 * high ==> the SFP+ module is powered down
8686 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
8688 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8689 struct elink_params *params,
8691 uint16_t addr, uint8_t byte_cnt,
8692 uint8_t *o_buf, uint8_t is_init)
8694 elink_status_t rc = ELINK_STATUS_OK;
8695 uint8_t i, j = 0, cnt = 0;
8696 uint32_t data_array[4];
8698 struct bxe_softc *sc = params->sc;
8700 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8702 "Reading from eeprom is limited to 16 bytes\n");
8703 return ELINK_STATUS_ERROR;
8706 /* 4 byte aligned address */
8707 addr32 = addr & (~0x3);
8709 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8710 elink_warpcore_power_module(params, 0);
8711 /* Note that 100us are not enough here */
8713 elink_warpcore_power_module(params, 1);
8715 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt,
8717 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
8719 if (rc == ELINK_STATUS_OK) {
8720 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8721 o_buf[j] = *((uint8_t *)data_array + i);
8729 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8730 struct elink_params *params,
8731 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8732 uint8_t *o_buf, uint8_t is_init)
8734 struct bxe_softc *sc = params->sc;
8737 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8739 "Reading from eeprom is limited to 0xf\n");
8740 return ELINK_STATUS_ERROR;
8743 /* Set 2-wire transfer rate of SFP+ module EEPROM
8744 * to 100Khz since some DACs(direct attached cables) do
8745 * not work at 400Khz.
8747 elink_cl45_write(sc, phy,
8749 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8750 ((dev_addr << 8) | 1));
8752 /* Need to read from 1.8000 to clear it */
8753 elink_cl45_read(sc, phy,
8755 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8758 /* Set the read command byte count */
8759 elink_cl45_write(sc, phy,
8761 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8762 ((byte_cnt < 2) ? 2 : byte_cnt));
8764 /* Set the read command address */
8765 elink_cl45_write(sc, phy,
8767 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8769 /* Set the destination address */
8770 elink_cl45_write(sc, phy,
8773 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8775 /* Activate read command */
8776 elink_cl45_write(sc, phy,
8778 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8780 /* Wait appropriate time for two-wire command to finish before
8781 * polling the status register
8785 /* Wait up to 500us for command complete status */
8786 for (i = 0; i < 100; i++) {
8787 elink_cl45_read(sc, phy,
8789 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8790 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8791 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8796 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8797 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8799 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8800 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8801 return ELINK_STATUS_TIMEOUT;
8804 /* Read the buffer */
8805 for (i = 0; i < byte_cnt; i++) {
8806 elink_cl45_read(sc, phy,
8808 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8809 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8812 for (i = 0; i < 100; i++) {
8813 elink_cl45_read(sc, phy,
8815 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8816 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8817 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8818 return ELINK_STATUS_OK;
8822 return ELINK_STATUS_ERROR;
8824 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8825 struct elink_params *params, uint8_t dev_addr,
8826 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf)
8828 elink_status_t rc = 0;
8829 struct bxe_softc *sc = params->sc;
8831 uint8_t *user_data = o_buf;
8832 read_sfp_module_eeprom_func_p read_func;
8833 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8834 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);
8835 return ELINK_STATUS_ERROR;
8838 switch (phy->type) {
8839 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8840 read_func = elink_8726_read_sfp_module_eeprom;
8842 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8843 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8844 read_func = elink_8727_read_sfp_module_eeprom;
8846 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8847 read_func = elink_warpcore_read_sfp_module_eeprom;
8850 return ELINK_OP_NOT_SUPPORTED;
8853 while (!rc && (byte_cnt > 0)) {
8854 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
8855 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
8856 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8858 byte_cnt -= xfer_size;
8859 user_data += xfer_size;
8865 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
8866 struct elink_params *params,
8869 struct bxe_softc *sc = params->sc;
8870 uint32_t sync_offset = 0, phy_idx, media_types;
8871 uint8_t gport, val[2], check_limiting_mode = 0;
8872 *edc_mode = ELINK_EDC_MODE_LIMITING;
8873 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
8874 /* First check for copper cable */
8875 if (elink_read_sfp_module_eeprom(phy,
8877 ELINK_I2C_DEV_ADDR_A0,
8878 ELINK_SFP_EEPROM_CON_TYPE_ADDR,
8880 (uint8_t *)val) != 0) {
8881 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n");
8882 return ELINK_STATUS_ERROR;
8886 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
8888 uint8_t copper_module_type;
8889 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
8890 /* Check if its active cable (includes SFP+ module)
8893 if (elink_read_sfp_module_eeprom(phy,
8895 ELINK_I2C_DEV_ADDR_A0,
8896 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR,
8898 &copper_module_type) != 0) {
8900 "Failed to read copper-cable-type"
8901 " from SFP+ EEPROM\n");
8902 return ELINK_STATUS_ERROR;
8905 if (copper_module_type &
8906 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
8907 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
8908 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
8909 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
8911 check_limiting_mode = 1;
8913 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
8914 /* Even in case PASSIVE_DAC indication is not set,
8915 * treat it as a passive DAC cable, since some cables
8916 * don't have this indication.
8918 if (copper_module_type &
8919 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
8921 "Passive Copper cable detected\n");
8924 "Unknown copper-cable-type\n");
8929 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
8930 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
8931 check_limiting_mode = 1;
8932 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK |
8933 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK |
8934 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) {
8935 ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
8936 gport = params->port;
8937 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
8938 if (phy->req_line_speed != ELINK_SPEED_1000) {
8939 phy->req_line_speed = ELINK_SPEED_1000;
8940 if (!CHIP_IS_E1x(sc)) {
8941 gport = SC_PATH(sc) +
8942 (params->port << 1);
8944 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
8945 // " Current SFP module in port %d is not"
8946 // " compliant with 10G Ethernet\n",
8950 int idx, cfg_idx = 0;
8951 ELINK_DEBUG_P0(sc, "10G Optic module detected\n");
8952 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
8953 if (params->phy[idx].type == phy->type) {
8954 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
8958 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
8959 phy->req_line_speed = params->req_line_speed[cfg_idx];
8963 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",
8965 return ELINK_STATUS_ERROR;
8967 sync_offset = params->shmem_base +
8968 offsetof(struct shmem_region,
8969 dev_info.port_hw_config[params->port].media_type);
8970 media_types = REG_RD(sc, sync_offset);
8971 /* Update media type for non-PMF sync */
8972 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
8973 if (&(params->phy[phy_idx]) == phy) {
8974 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
8975 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8976 media_types |= ((phy->media_type &
8977 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
8978 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
8982 REG_WR(sc, sync_offset, media_types);
8983 if (check_limiting_mode) {
8984 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
8985 if (elink_read_sfp_module_eeprom(phy,
8987 ELINK_I2C_DEV_ADDR_A0,
8988 ELINK_SFP_EEPROM_OPTIONS_ADDR,
8989 ELINK_SFP_EEPROM_OPTIONS_SIZE,
8992 "Failed to read Option field from module EEPROM\n");
8993 return ELINK_STATUS_ERROR;
8995 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
8996 *edc_mode = ELINK_EDC_MODE_LINEAR;
8998 *edc_mode = ELINK_EDC_MODE_LIMITING;
9000 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);
9001 return ELINK_STATUS_OK;
9003 /* This function read the relevant field from the module (SFP+), and verify it
9004 * is compliant with this board
9006 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
9007 struct elink_params *params)
9009 struct bxe_softc *sc = params->sc;
9011 uint32_t fw_resp, fw_cmd_param;
9012 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
9013 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
9014 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9015 val = REG_RD(sc, params->shmem_base +
9016 offsetof(struct shmem_region, dev_info.
9017 port_feature_config[params->port].config));
9018 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9019 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
9020 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n");
9021 return ELINK_STATUS_OK;
9024 if (params->feature_config_flags &
9025 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
9026 /* Use specific phy request */
9027 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
9028 } else if (params->feature_config_flags &
9029 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
9030 /* Use first phy request only in case of non-dual media*/
9031 if (ELINK_DUAL_MEDIA(params)) {
9033 "FW does not support OPT MDL verification\n");
9034 return ELINK_STATUS_ERROR;
9036 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
9038 /* No support in OPT MDL detection */
9040 "FW does not support OPT MDL verification\n");
9041 return ELINK_STATUS_ERROR;
9044 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9045 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
9046 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
9047 ELINK_DEBUG_P0(sc, "Approved module\n");
9048 return ELINK_STATUS_OK;
9051 /* Format the warning message */
9052 if (elink_read_sfp_module_eeprom(phy,
9054 ELINK_I2C_DEV_ADDR_A0,
9055 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
9056 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
9057 (uint8_t *)vendor_name))
9058 vendor_name[0] = '\0';
9060 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
9061 if (elink_read_sfp_module_eeprom(phy,
9063 ELINK_I2C_DEV_ADDR_A0,
9064 ELINK_SFP_EEPROM_PART_NO_ADDR,
9065 ELINK_SFP_EEPROM_PART_NO_SIZE,
9066 (uint8_t *)vendor_pn))
9067 vendor_pn[0] = '\0';
9069 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
9071 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9072 // " Port %d from %s part number %s\n",
9074 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
9075 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
9076 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9077 return ELINK_STATUS_ERROR;
9080 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9081 struct elink_params *params)
9086 struct bxe_softc *sc = params->sc;
9088 /* Initialization time after hot-plug may take up to 300ms for
9089 * some phys type ( e.g. JDSU )
9092 for (timeout = 0; timeout < 60; timeout++) {
9093 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9094 rc = elink_warpcore_read_sfp_module_eeprom(
9095 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9098 rc = elink_read_sfp_module_eeprom(phy, params,
9099 ELINK_I2C_DEV_ADDR_A0,
9103 "SFP+ module initialization took %d ms\n",
9105 return ELINK_STATUS_OK;
9109 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9114 static void elink_8727_power_module(struct bxe_softc *sc,
9115 struct elink_phy *phy,
9116 uint8_t is_power_up) {
9117 /* Make sure GPIOs are not using for LED mode */
9119 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
9120 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
9122 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
9123 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
9124 * where the 1st bit is the over-current(only input), and 2nd bit is
9125 * for power( only output )
9127 * In case of NOC feature is disabled and power is up, set GPIO control
9128 * as input to enable listening of over-current indication
9130 if (phy->flags & ELINK_FLAGS_NOC)
9135 /* Set GPIO control to OUTPUT, and set the power bit
9136 * to according to the is_power_up
9140 elink_cl45_write(sc, phy,
9142 MDIO_PMA_REG_8727_GPIO_CTRL,
9146 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc,
9147 struct elink_phy *phy,
9150 uint16_t cur_limiting_mode;
9152 elink_cl45_read(sc, phy,
9154 MDIO_PMA_REG_ROM_VER2,
9155 &cur_limiting_mode);
9156 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",
9159 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
9160 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n");
9161 elink_cl45_write(sc, phy,
9163 MDIO_PMA_REG_ROM_VER2,
9164 ELINK_EDC_MODE_LIMITING);
9165 } else { /* LRM mode ( default )*/
9167 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n");
9169 /* Changing to LRM mode takes quite few seconds. So do it only
9170 * if current mode is limiting (default is LRM)
9172 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
9173 return ELINK_STATUS_OK;
9175 elink_cl45_write(sc, phy,
9177 MDIO_PMA_REG_LRM_MODE,
9179 elink_cl45_write(sc, phy,
9181 MDIO_PMA_REG_ROM_VER2,
9183 elink_cl45_write(sc, phy,
9185 MDIO_PMA_REG_MISC_CTRL0,
9187 elink_cl45_write(sc, phy,
9189 MDIO_PMA_REG_LRM_MODE,
9192 return ELINK_STATUS_OK;
9195 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc,
9196 struct elink_phy *phy,
9199 uint16_t phy_identifier;
9200 uint16_t rom_ver2_val;
9201 elink_cl45_read(sc, phy,
9203 MDIO_PMA_REG_PHY_IDENTIFIER,
9206 elink_cl45_write(sc, phy,
9208 MDIO_PMA_REG_PHY_IDENTIFIER,
9209 (phy_identifier & ~(1<<9)));
9211 elink_cl45_read(sc, phy,
9213 MDIO_PMA_REG_ROM_VER2,
9215 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
9216 elink_cl45_write(sc, phy,
9218 MDIO_PMA_REG_ROM_VER2,
9219 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
9221 elink_cl45_write(sc, phy,
9223 MDIO_PMA_REG_PHY_IDENTIFIER,
9224 (phy_identifier | (1<<9)));
9226 return ELINK_STATUS_OK;
9229 static void elink_8727_specific_func(struct elink_phy *phy,
9230 struct elink_params *params,
9233 struct bxe_softc *sc = params->sc;
9236 case ELINK_DISABLE_TX:
9237 elink_sfp_set_transmitter(params, phy, 0);
9239 case ELINK_ENABLE_TX:
9240 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9241 elink_sfp_set_transmitter(params, phy, 1);
9243 case ELINK_PHY_INIT:
9244 elink_cl45_write(sc, phy,
9245 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9247 elink_cl45_write(sc, phy,
9248 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9250 elink_cl45_write(sc, phy,
9251 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
9252 /* Make MOD_ABS give interrupt on change */
9253 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9254 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9257 if (phy->flags & ELINK_FLAGS_NOC)
9259 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9260 * status which reflect SFP+ module over-current
9262 if (!(phy->flags & ELINK_FLAGS_NOC))
9263 val &= 0xff8f; /* Reset bits 4-6 */
9264 elink_cl45_write(sc, phy,
9265 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9269 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",
9275 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
9278 struct bxe_softc *sc = params->sc;
9280 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9281 offsetof(struct shmem_region,
9282 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9283 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
9284 switch (fault_led_gpio) {
9285 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
9287 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
9288 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
9289 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
9290 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
9292 uint8_t gpio_port = elink_get_gpio_port(params);
9293 uint16_t gpio_pin = fault_led_gpio -
9294 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
9295 ELINK_DEBUG_P3(sc, "Set fault module-detected led "
9296 "pin %x port %x mode %x\n",
9297 gpio_pin, gpio_port, gpio_mode);
9298 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
9302 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",
9307 static void elink_set_e3_module_fault_led(struct elink_params *params,
9311 uint8_t port = params->port;
9312 struct bxe_softc *sc = params->sc;
9313 pin_cfg = (REG_RD(sc, params->shmem_base +
9314 offsetof(struct shmem_region,
9315 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9316 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
9317 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
9318 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n",
9319 gpio_mode, pin_cfg);
9320 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
9323 static void elink_set_sfp_module_fault_led(struct elink_params *params,
9326 struct bxe_softc *sc = params->sc;
9327 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9328 if (CHIP_IS_E3(sc)) {
9329 /* Low ==> if SFP+ module is supported otherwise
9330 * High ==> if SFP+ module is not on the approved vendor list
9332 elink_set_e3_module_fault_led(params, gpio_mode);
9334 elink_set_e1e2_module_fault_led(params, gpio_mode);
9337 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9338 struct elink_params *params)
9340 struct bxe_softc *sc = params->sc;
9341 elink_warpcore_power_module(params, 0);
9342 /* Put Warpcore in low power mode */
9343 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9345 /* Put LCPLL in low power mode */
9346 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9347 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9348 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9351 static void elink_power_sfp_module(struct elink_params *params,
9352 struct elink_phy *phy,
9355 struct bxe_softc *sc = params->sc;
9356 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power);
9358 switch (phy->type) {
9359 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9360 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9361 elink_8727_power_module(params->sc, phy, power);
9363 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9364 elink_warpcore_power_module(params, power);
9370 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
9371 struct elink_phy *phy,
9375 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9376 struct bxe_softc *sc = params->sc;
9378 uint8_t lane = elink_get_warpcore_lane(phy, params);
9379 /* This is a global register which controls all lanes */
9380 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9381 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9382 val &= ~(0xf << (lane << 2));
9385 case ELINK_EDC_MODE_LINEAR:
9386 case ELINK_EDC_MODE_LIMITING:
9387 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9389 case ELINK_EDC_MODE_PASSIVE_DAC:
9390 case ELINK_EDC_MODE_ACTIVE_DAC:
9391 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
9397 val |= (mode << (lane << 2));
9398 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9399 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
9401 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9402 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9404 /* Restart microcode to re-read the new mode */
9405 elink_warpcore_reset_lane(sc, phy, 1);
9406 elink_warpcore_reset_lane(sc, phy, 0);
9410 static void elink_set_limiting_mode(struct elink_params *params,
9411 struct elink_phy *phy,
9414 switch (phy->type) {
9415 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9416 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9418 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9419 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9420 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9422 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9423 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9428 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9429 struct elink_params *params)
9431 struct bxe_softc *sc = params->sc;
9433 elink_status_t rc = ELINK_STATUS_OK;
9435 uint32_t val = REG_RD(sc, params->shmem_base +
9436 offsetof(struct shmem_region, dev_info.
9437 port_feature_config[params->port].config));
9438 /* Enabled transmitter by default */
9439 elink_sfp_set_transmitter(params, phy, 1);
9440 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9442 /* Power up module */
9443 elink_power_sfp_module(params, phy, 1);
9444 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9445 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n");
9446 return ELINK_STATUS_ERROR;
9447 } else if (elink_verify_sfp_module(phy, params) != 0) {
9448 /* Check SFP+ module compatibility */
9449 ELINK_DEBUG_P0(sc, "Module verification failed!!\n");
9450 rc = ELINK_STATUS_ERROR;
9451 /* Turn on fault module-detected led */
9452 elink_set_sfp_module_fault_led(params,
9453 MISC_REGISTERS_GPIO_HIGH);
9455 /* Check if need to power down the SFP+ module */
9456 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9457 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
9458 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n");
9459 elink_power_sfp_module(params, phy, 0);
9463 /* Turn off fault module-detected led */
9464 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
9467 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
9468 * is done automatically
9470 elink_set_limiting_mode(params, phy, edc_mode);
9472 /* Disable transmit for this module if the module is not approved, and
9473 * laser needs to be disabled.
9476 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9477 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
9478 elink_sfp_set_transmitter(params, phy, 0);
9483 void elink_handle_module_detect_int(struct elink_params *params)
9485 struct bxe_softc *sc = params->sc;
9486 struct elink_phy *phy;
9488 uint8_t gpio_num, gpio_port;
9489 if (CHIP_IS_E3(sc)) {
9490 phy = ¶ms->phy[ELINK_INT_PHY];
9491 /* Always enable TX laser,will be disabled in case of fault */
9492 elink_sfp_set_transmitter(params, phy, 1);
9494 phy = ¶ms->phy[ELINK_EXT_PHY1];
9496 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
9497 params->port, &gpio_num, &gpio_port) ==
9498 ELINK_STATUS_ERROR) {
9499 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n");
9503 /* Set valid module led off */
9504 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
9506 /* Get current gpio val reflecting module plugged in / out*/
9507 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
9509 /* Call the handling function in case module is detected */
9510 if (gpio_val == 0) {
9511 elink_set_mdio_emac_per_phy(sc, params);
9512 elink_set_aer_mmd(params, phy);
9514 elink_power_sfp_module(params, phy, 1);
9515 elink_cb_gpio_int_write(sc, gpio_num,
9516 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
9518 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9519 elink_sfp_module_detection(phy, params);
9520 if (CHIP_IS_E3(sc)) {
9521 uint16_t rx_tx_in_reset;
9522 /* In case WC is out of reset, reconfigure the
9523 * link speed while taking into account 1G
9524 * module limitation.
9526 elink_cl45_read(sc, phy,
9528 MDIO_WC_REG_DIGITAL5_MISC6,
9530 if ((!rx_tx_in_reset) &&
9531 (params->link_flags &
9532 ELINK_PHY_INITIALIZED)) {
9533 elink_warpcore_reset_lane(sc, phy, 1);
9534 elink_warpcore_config_sfi(phy, params);
9535 elink_warpcore_reset_lane(sc, phy, 0);
9539 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
9542 elink_cb_gpio_int_write(sc, gpio_num,
9543 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
9545 /* Module was plugged out.
9546 * Disable transmit for this module
9548 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9552 /******************************************************************/
9553 /* Used by 8706 and 8727 */
9554 /******************************************************************/
9555 static void elink_sfp_mask_fault(struct bxe_softc *sc,
9556 struct elink_phy *phy,
9557 uint16_t alarm_status_offset,
9558 uint16_t alarm_ctrl_offset)
9560 uint16_t alarm_status, val;
9561 elink_cl45_read(sc, phy,
9562 MDIO_PMA_DEVAD, alarm_status_offset,
9564 elink_cl45_read(sc, phy,
9565 MDIO_PMA_DEVAD, alarm_status_offset,
9567 /* Mask or enable the fault event. */
9568 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9569 if (alarm_status & (1<<0))
9573 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9575 /******************************************************************/
9576 /* common BCM8706/BCM8726 PHY SECTION */
9577 /******************************************************************/
9578 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9579 struct elink_params *params,
9580 struct elink_vars *vars)
9582 uint8_t link_up = 0;
9583 uint16_t val1, val2, rx_sd, pcs_status;
9584 struct bxe_softc *sc = params->sc;
9585 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n");
9587 elink_cl45_read(sc, phy,
9588 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
9590 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9591 MDIO_PMA_LASI_TXCTRL);
9593 /* Clear LASI indication*/
9594 elink_cl45_read(sc, phy,
9595 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9596 elink_cl45_read(sc, phy,
9597 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
9598 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9600 elink_cl45_read(sc, phy,
9601 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
9602 elink_cl45_read(sc, phy,
9603 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
9604 elink_cl45_read(sc, phy,
9605 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9606 elink_cl45_read(sc, phy,
9607 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9609 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9610 " link_status 0x%x\n", rx_sd, pcs_status, val2);
9611 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
9612 * are set, or if the autoneg bit 1 is set
9614 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
9617 vars->line_speed = ELINK_SPEED_1000;
9619 vars->line_speed = ELINK_SPEED_10000;
9620 elink_ext_phy_resolve_fc(phy, params, vars);
9621 vars->duplex = DUPLEX_FULL;
9624 /* Capture 10G link fault. Read twice to clear stale value. */
9625 if (vars->line_speed == ELINK_SPEED_10000) {
9626 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9627 MDIO_PMA_LASI_TXSTAT, &val1);
9628 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9629 MDIO_PMA_LASI_TXSTAT, &val1);
9631 vars->fault_detected = 1;
9637 /******************************************************************/
9638 /* BCM8706 PHY SECTION */
9639 /******************************************************************/
9640 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9641 struct elink_params *params,
9642 struct elink_vars *vars)
9644 uint32_t tx_en_mode;
9645 uint16_t cnt, val, tmp1;
9646 struct bxe_softc *sc = params->sc;
9648 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9649 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9651 elink_ext_phy_hw_reset(sc, params->port);
9652 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9653 elink_wait_reset_complete(sc, phy, params);
9655 /* Wait until fw is loaded */
9656 for (cnt = 0; cnt < 100; cnt++) {
9657 elink_cl45_read(sc, phy,
9658 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
9663 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt);
9664 if ((params->feature_config_flags &
9665 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9668 for (i = 0; i < 4; i++) {
9669 reg = MDIO_XS_8706_REG_BANK_RX0 +
9670 i*(MDIO_XS_8706_REG_BANK_RX1 -
9671 MDIO_XS_8706_REG_BANK_RX0);
9672 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9673 /* Clear first 3 bits of the control */
9675 /* Set control bits according to configuration */
9676 val |= (phy->rx_preemphasis[i] & 0x7);
9677 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706"
9678 " reg 0x%x <-- val 0x%x\n", reg, val);
9679 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9683 if (phy->req_line_speed == ELINK_SPEED_10000) {
9684 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n");
9686 elink_cl45_write(sc, phy,
9688 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9689 elink_cl45_write(sc, phy,
9690 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9692 /* Arm LASI for link and Tx fault. */
9693 elink_cl45_write(sc, phy,
9694 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9696 /* Force 1Gbps using autoneg with 1G advertisement */
9698 /* Allow CL37 through CL73 */
9699 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n");
9700 elink_cl45_write(sc, phy,
9701 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9703 /* Enable Full-Duplex advertisement on CL37 */
9704 elink_cl45_write(sc, phy,
9705 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9706 /* Enable CL37 AN */
9707 elink_cl45_write(sc, phy,
9708 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9710 elink_cl45_write(sc, phy,
9711 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9713 /* Enable clause 73 AN */
9714 elink_cl45_write(sc, phy,
9715 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9716 elink_cl45_write(sc, phy,
9717 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9719 elink_cl45_write(sc, phy,
9720 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9723 elink_save_bcm_spirom_ver(sc, phy, params->port);
9725 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9726 * power mode, if TX Laser is disabled
9729 tx_en_mode = REG_RD(sc, params->shmem_base +
9730 offsetof(struct shmem_region,
9731 dev_info.port_hw_config[params->port].sfp_ctrl))
9732 & PORT_HW_CFG_TX_LASER_MASK;
9734 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9735 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
9736 elink_cl45_read(sc, phy,
9737 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9739 elink_cl45_write(sc, phy,
9740 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9743 return ELINK_STATUS_OK;
9746 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9747 struct elink_params *params,
9748 struct elink_vars *vars)
9750 return elink_8706_8726_read_status(phy, params, vars);
9753 /******************************************************************/
9754 /* BCM8726 PHY SECTION */
9755 /******************************************************************/
9756 static void elink_8726_config_loopback(struct elink_phy *phy,
9757 struct elink_params *params)
9759 struct bxe_softc *sc = params->sc;
9760 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n");
9761 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9764 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9765 struct elink_params *params)
9767 struct bxe_softc *sc = params->sc;
9768 /* Need to wait 100ms after reset */
9771 /* Micro controller re-boot */
9772 elink_cl45_write(sc, phy,
9773 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9775 /* Set soft reset */
9776 elink_cl45_write(sc, phy,
9778 MDIO_PMA_REG_GEN_CTRL,
9779 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9781 elink_cl45_write(sc, phy,
9783 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9785 elink_cl45_write(sc, phy,
9787 MDIO_PMA_REG_GEN_CTRL,
9788 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9790 /* Wait for 150ms for microcode load */
9793 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9794 elink_cl45_write(sc, phy,
9796 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9799 elink_save_bcm_spirom_ver(sc, phy, params->port);
9802 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9803 struct elink_params *params,
9804 struct elink_vars *vars)
9806 struct bxe_softc *sc = params->sc;
9808 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9810 elink_cl45_read(sc, phy,
9811 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9813 if (val1 & (1<<15)) {
9814 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
9816 vars->line_speed = 0;
9823 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9824 struct elink_params *params,
9825 struct elink_vars *vars)
9827 struct bxe_softc *sc = params->sc;
9828 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n");
9830 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9831 elink_wait_reset_complete(sc, phy, params);
9833 elink_8726_external_rom_boot(phy, params);
9835 /* Need to call module detected on initialization since the module
9836 * detection triggered by actual module insertion might occur before
9837 * driver is loaded, and when driver is loaded, it reset all
9838 * registers, including the transmitter
9840 elink_sfp_module_detection(phy, params);
9842 if (phy->req_line_speed == ELINK_SPEED_1000) {
9843 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9844 elink_cl45_write(sc, phy,
9845 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9846 elink_cl45_write(sc, phy,
9847 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9848 elink_cl45_write(sc, phy,
9849 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9850 elink_cl45_write(sc, phy,
9851 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9853 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9854 (phy->speed_cap_mask &
9855 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9856 ((phy->speed_cap_mask &
9857 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9858 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9859 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
9860 /* Set Flow control */
9861 elink_ext_phy_set_pause(params, phy, vars);
9862 elink_cl45_write(sc, phy,
9863 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9864 elink_cl45_write(sc, phy,
9865 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9866 elink_cl45_write(sc, phy,
9867 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9868 elink_cl45_write(sc, phy,
9869 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9870 elink_cl45_write(sc, phy,
9871 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9872 /* Enable RX-ALARM control to receive interrupt for 1G speed
9875 elink_cl45_write(sc, phy,
9876 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9877 elink_cl45_write(sc, phy,
9878 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9881 } else { /* Default 10G. Set only LASI control */
9882 elink_cl45_write(sc, phy,
9883 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
9886 /* Set TX PreEmphasis if needed */
9887 if ((params->feature_config_flags &
9888 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9890 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9891 phy->tx_preemphasis[0],
9892 phy->tx_preemphasis[1]);
9893 elink_cl45_write(sc, phy,
9895 MDIO_PMA_REG_8726_TX_CTRL1,
9896 phy->tx_preemphasis[0]);
9898 elink_cl45_write(sc, phy,
9900 MDIO_PMA_REG_8726_TX_CTRL2,
9901 phy->tx_preemphasis[1]);
9904 return ELINK_STATUS_OK;
9908 static void elink_8726_link_reset(struct elink_phy *phy,
9909 struct elink_params *params)
9911 struct bxe_softc *sc = params->sc;
9912 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
9913 /* Set serial boot control for external load */
9914 elink_cl45_write(sc, phy,
9916 MDIO_PMA_REG_GEN_CTRL, 0x0001);
9919 /******************************************************************/
9920 /* BCM8727 PHY SECTION */
9921 /******************************************************************/
9923 static void elink_8727_set_link_led(struct elink_phy *phy,
9924 struct elink_params *params, uint8_t mode)
9926 struct bxe_softc *sc = params->sc;
9927 uint16_t led_mode_bitmask = 0;
9928 uint16_t gpio_pins_bitmask = 0;
9930 /* Only NOC flavor requires to set the LED specifically */
9931 if (!(phy->flags & ELINK_FLAGS_NOC))
9934 case ELINK_LED_MODE_FRONT_PANEL_OFF:
9935 case ELINK_LED_MODE_OFF:
9936 led_mode_bitmask = 0;
9937 gpio_pins_bitmask = 0x03;
9939 case ELINK_LED_MODE_ON:
9940 led_mode_bitmask = 0;
9941 gpio_pins_bitmask = 0x02;
9943 case ELINK_LED_MODE_OPER:
9944 led_mode_bitmask = 0x60;
9945 gpio_pins_bitmask = 0x11;
9948 elink_cl45_read(sc, phy,
9950 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9953 val |= led_mode_bitmask;
9954 elink_cl45_write(sc, phy,
9956 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9958 elink_cl45_read(sc, phy,
9960 MDIO_PMA_REG_8727_GPIO_CTRL,
9963 val |= gpio_pins_bitmask;
9964 elink_cl45_write(sc, phy,
9966 MDIO_PMA_REG_8727_GPIO_CTRL,
9969 static void elink_8727_hw_reset(struct elink_phy *phy,
9970 struct elink_params *params) {
9971 uint32_t swap_val, swap_override;
9973 /* The PHY reset is controlled by GPIO 1. Fake the port number
9974 * to cancel the swap done in set_gpio()
9976 struct bxe_softc *sc = params->sc;
9977 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
9978 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
9979 port = (swap_val && swap_override) ^ 1;
9980 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
9981 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
9984 static void elink_8727_config_speed(struct elink_phy *phy,
9985 struct elink_params *params)
9987 struct bxe_softc *sc = params->sc;
9989 /* Set option 1G speed */
9990 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
9991 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
9992 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9993 elink_cl45_write(sc, phy,
9994 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9995 elink_cl45_write(sc, phy,
9996 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9997 elink_cl45_read(sc, phy,
9998 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
9999 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
10000 /* Power down the XAUI until link is up in case of dual-media
10003 if (ELINK_DUAL_MEDIA(params)) {
10004 elink_cl45_read(sc, phy,
10006 MDIO_PMA_REG_8727_PCS_GP, &val);
10008 elink_cl45_write(sc, phy,
10010 MDIO_PMA_REG_8727_PCS_GP, val);
10012 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10013 ((phy->speed_cap_mask &
10014 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
10015 ((phy->speed_cap_mask &
10016 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10017 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10019 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10020 elink_cl45_write(sc, phy,
10021 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
10022 elink_cl45_write(sc, phy,
10023 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
10025 /* Since the 8727 has only single reset pin, need to set the 10G
10026 * registers although it is default
10028 elink_cl45_write(sc, phy,
10029 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
10031 elink_cl45_write(sc, phy,
10032 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
10033 elink_cl45_write(sc, phy,
10034 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
10035 elink_cl45_write(sc, phy,
10036 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
10041 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10042 struct elink_params *params,
10043 struct elink_vars *vars)
10045 uint32_t tx_en_mode;
10046 uint16_t tmp1, mod_abs, tmp2;
10047 struct bxe_softc *sc = params->sc;
10048 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
10050 elink_wait_reset_complete(sc, phy, params);
10052 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n");
10054 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10055 /* Initially configure MOD_ABS to interrupt when module is
10058 elink_cl45_read(sc, phy,
10059 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10060 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
10061 * When the EDC is off it locks onto a reference clock and avoids
10064 mod_abs &= ~(1<<8);
10065 if (!(phy->flags & ELINK_FLAGS_NOC))
10066 mod_abs &= ~(1<<9);
10067 elink_cl45_write(sc, phy,
10068 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10070 /* Enable/Disable PHY transmitter output */
10071 elink_set_disable_pmd_transmit(params, phy, 0);
10073 elink_8727_power_module(sc, phy, 1);
10075 elink_cl45_read(sc, phy,
10076 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
10078 elink_cl45_read(sc, phy,
10079 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
10081 elink_8727_config_speed(phy, params);
10084 /* Set TX PreEmphasis if needed */
10085 if ((params->feature_config_flags &
10086 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10087 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10088 phy->tx_preemphasis[0],
10089 phy->tx_preemphasis[1]);
10090 elink_cl45_write(sc, phy,
10091 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
10092 phy->tx_preemphasis[0]);
10094 elink_cl45_write(sc, phy,
10095 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
10096 phy->tx_preemphasis[1]);
10099 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
10100 * power mode, if TX Laser is disabled
10102 tx_en_mode = REG_RD(sc, params->shmem_base +
10103 offsetof(struct shmem_region,
10104 dev_info.port_hw_config[params->port].sfp_ctrl))
10105 & PORT_HW_CFG_TX_LASER_MASK;
10107 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
10109 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
10110 elink_cl45_read(sc, phy,
10111 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
10114 elink_cl45_write(sc, phy,
10115 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
10116 elink_cl45_read(sc, phy,
10117 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10119 elink_cl45_write(sc, phy,
10120 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10124 return ELINK_STATUS_OK;
10127 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10128 struct elink_params *params)
10130 struct bxe_softc *sc = params->sc;
10131 uint16_t mod_abs, rx_alarm_status;
10132 uint32_t val = REG_RD(sc, params->shmem_base +
10133 offsetof(struct shmem_region, dev_info.
10134 port_feature_config[params->port].
10136 elink_cl45_read(sc, phy,
10138 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10139 if (mod_abs & (1<<8)) {
10141 /* Module is absent */
10143 "MOD_ABS indication show module is absent\n");
10144 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10145 /* 1. Set mod_abs to detect next module
10147 * 2. Set EDC off by setting OPTXLOS signal input to low
10149 * When the EDC is off it locks onto a reference clock and
10150 * avoids becoming 'lost'.
10152 mod_abs &= ~(1<<8);
10153 if (!(phy->flags & ELINK_FLAGS_NOC))
10154 mod_abs &= ~(1<<9);
10155 elink_cl45_write(sc, phy,
10157 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10159 /* Clear RX alarm since it stays up as long as
10160 * the mod_abs wasn't changed
10162 elink_cl45_read(sc, phy,
10164 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10167 /* Module is present */
10169 "MOD_ABS indication show module is present\n");
10170 /* First disable transmitter, and if the module is ok, the
10171 * module_detection will enable it
10172 * 1. Set mod_abs to detect next module absent event ( bit 8)
10173 * 2. Restore the default polarity of the OPRXLOS signal and
10174 * this signal will then correctly indicate the presence or
10175 * absence of the Rx signal. (bit 9)
10178 if (!(phy->flags & ELINK_FLAGS_NOC))
10180 elink_cl45_write(sc, phy,
10182 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10184 /* Clear RX alarm since it stays up as long as the mod_abs
10185 * wasn't changed. This is need to be done before calling the
10186 * module detection, otherwise it will clear* the link update
10189 elink_cl45_read(sc, phy,
10191 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10194 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
10195 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
10196 elink_sfp_set_transmitter(params, phy, 0);
10198 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10199 elink_sfp_module_detection(phy, params);
10201 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
10203 /* Reconfigure link speed based on module type limitations */
10204 elink_8727_config_speed(phy, params);
10207 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",
10209 /* No need to check link status in case of module plugged in/out */
10212 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10213 struct elink_params *params,
10214 struct elink_vars *vars)
10217 struct bxe_softc *sc = params->sc;
10218 uint8_t link_up = 0, oc_port = params->port;
10219 uint16_t link_status = 0;
10220 uint16_t rx_alarm_status, lasi_ctrl, val1;
10222 /* If PHY is not initialized, do not check link status */
10223 elink_cl45_read(sc, phy,
10224 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
10229 /* Check the LASI on Rx */
10230 elink_cl45_read(sc, phy,
10231 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
10233 vars->line_speed = 0;
10234 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10236 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10237 MDIO_PMA_LASI_TXCTRL);
10239 elink_cl45_read(sc, phy,
10240 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10242 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);
10244 /* Clear MSG-OUT */
10245 elink_cl45_read(sc, phy,
10246 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
10248 /* If a module is present and there is need to check
10251 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10252 /* Check over-current using 8727 GPIO0 input*/
10253 elink_cl45_read(sc, phy,
10254 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
10257 if ((val1 & (1<<8)) == 0) {
10258 if (!CHIP_IS_E1x(sc))
10259 oc_port = SC_PATH(sc) + (params->port << 1);
10261 "8727 Power fault has been detected on port %d\n",
10263 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10264 // "been detected and the power to "
10265 // "that SFP+ module has been removed "
10266 // "to prevent failure of the card. "
10267 // "Please remove the SFP+ module and "
10268 // "restart the system to clear this "
10270 /* Disable all RX_ALARMs except for mod_abs */
10271 elink_cl45_write(sc, phy,
10273 MDIO_PMA_LASI_RXCTRL, (1<<5));
10275 elink_cl45_read(sc, phy,
10277 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
10278 /* Wait for module_absent_event */
10280 elink_cl45_write(sc, phy,
10282 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
10283 /* Clear RX alarm */
10284 elink_cl45_read(sc, phy,
10286 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10287 elink_8727_power_module(params->sc, phy, 0);
10290 } /* Over current check */
10292 /* When module absent bit is set, check module */
10293 if (rx_alarm_status & (1<<5)) {
10294 elink_8727_handle_mod_abs(phy, params);
10295 /* Enable all mod_abs and link detection bits */
10296 elink_cl45_write(sc, phy,
10297 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10298 ((1<<5) | (1<<2)));
10301 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10302 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n");
10303 elink_sfp_set_transmitter(params, phy, 1);
10305 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
10309 elink_cl45_read(sc, phy,
10311 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
10313 /* Bits 0..2 --> speed detected,
10314 * Bits 13..15--> link is down
10316 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
10318 vars->line_speed = ELINK_SPEED_10000;
10319 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10321 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
10323 vars->line_speed = ELINK_SPEED_1000;
10324 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10328 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10332 /* Capture 10G link fault. */
10333 if (vars->line_speed == ELINK_SPEED_10000) {
10334 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10335 MDIO_PMA_LASI_TXSTAT, &val1);
10337 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10338 MDIO_PMA_LASI_TXSTAT, &val1);
10340 if (val1 & (1<<0)) {
10341 vars->fault_detected = 1;
10346 elink_ext_phy_resolve_fc(phy, params, vars);
10347 vars->duplex = DUPLEX_FULL;
10348 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);
10351 if ((ELINK_DUAL_MEDIA(params)) &&
10352 (phy->req_line_speed == ELINK_SPEED_1000)) {
10353 elink_cl45_read(sc, phy,
10355 MDIO_PMA_REG_8727_PCS_GP, &val1);
10356 /* In case of dual-media board and 1G, power up the XAUI side,
10357 * otherwise power it down. For 10G it is done automatically
10363 elink_cl45_write(sc, phy,
10365 MDIO_PMA_REG_8727_PCS_GP, val1);
10370 static void elink_8727_link_reset(struct elink_phy *phy,
10371 struct elink_params *params)
10373 struct bxe_softc *sc = params->sc;
10375 /* Enable/Disable PHY transmitter output */
10376 elink_set_disable_pmd_transmit(params, phy, 1);
10378 /* Disable Transmitter */
10379 elink_sfp_set_transmitter(params, phy, 0);
10381 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10385 /******************************************************************/
10386 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
10387 /******************************************************************/
10388 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10389 struct bxe_softc *sc,
10392 uint16_t val, fw_ver2, cnt, i;
10393 static struct elink_reg_set reg_set[] = {
10394 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
10395 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
10396 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
10397 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
10398 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
10402 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10403 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10404 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10405 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10408 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
10409 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
10410 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10411 elink_cl45_write(sc, phy, reg_set[i].devad,
10412 reg_set[i].reg, reg_set[i].val);
10414 for (cnt = 0; cnt < 100; cnt++) {
10415 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10421 ELINK_DEBUG_P0(sc, "Unable to read 848xx "
10422 "phy fw version(1)\n");
10423 elink_save_spirom_version(sc, port, 0,
10429 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
10430 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10431 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10432 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10433 for (cnt = 0; cnt < 100; cnt++) {
10434 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10440 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10442 elink_save_spirom_version(sc, port, 0,
10447 /* lower 16 bits of the register SPI_FW_STATUS */
10448 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10449 /* upper 16 bits of register SPI_FW_STATUS */
10450 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10452 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10457 static void elink_848xx_set_led(struct bxe_softc *sc,
10458 struct elink_phy *phy)
10460 uint16_t val, offset, i;
10461 static struct elink_reg_set reg_set[] = {
10462 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
10463 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
10464 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
10465 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
10466 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
10467 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
10468 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
10470 /* PHYC_CTL_LED_CTL */
10471 elink_cl45_read(sc, phy,
10473 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10477 elink_cl45_write(sc, phy,
10479 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10481 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10482 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10485 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10486 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
10487 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
10489 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
10491 /* stretch_en for LED3*/
10492 elink_cl45_read_or_write(sc, phy,
10493 MDIO_PMA_DEVAD, offset,
10494 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
10497 static void elink_848xx_specific_func(struct elink_phy *phy,
10498 struct elink_params *params,
10501 struct bxe_softc *sc = params->sc;
10503 case ELINK_PHY_INIT:
10504 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10505 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10506 /* Save spirom version */
10507 elink_save_848xx_spirom_version(phy, sc, params->port);
10509 /* This phy uses the NIG latch mechanism since link indication
10510 * arrives through its LED4 and not via its LASI signal, so we
10511 * get steady signal instead of clear on read
10513 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10514 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
10516 elink_848xx_set_led(sc, phy);
10521 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10522 struct elink_params *params,
10523 struct elink_vars *vars)
10525 struct bxe_softc *sc = params->sc;
10526 uint16_t autoneg_val, an_1000_val, an_10_100_val;
10528 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10529 elink_cl45_write(sc, phy,
10530 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
10532 /* set 1000 speed advertisement */
10533 elink_cl45_read(sc, phy,
10534 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10537 elink_ext_phy_set_pause(params, phy, vars);
10538 elink_cl45_read(sc, phy,
10540 MDIO_AN_REG_8481_LEGACY_AN_ADV,
10542 elink_cl45_read(sc, phy,
10543 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10545 /* Disable forced speed */
10546 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10547 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
10549 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10550 (phy->speed_cap_mask &
10551 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10552 (phy->req_line_speed == ELINK_SPEED_1000)) {
10553 an_1000_val |= (1<<8);
10554 autoneg_val |= (1<<9 | 1<<12);
10555 if (phy->req_duplex == DUPLEX_FULL)
10556 an_1000_val |= (1<<9);
10557 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
10559 an_1000_val &= ~((1<<8) | (1<<9));
10561 elink_cl45_write(sc, phy,
10562 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10565 /* Set 10/100 speed advertisement */
10566 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10567 if (phy->speed_cap_mask &
10568 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10569 /* Enable autoneg and restart autoneg for legacy speeds
10571 autoneg_val |= (1<<9 | 1<<12);
10572 an_10_100_val |= (1<<8);
10573 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
10576 if (phy->speed_cap_mask &
10577 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10578 /* Enable autoneg and restart autoneg for legacy speeds
10580 autoneg_val |= (1<<9 | 1<<12);
10581 an_10_100_val |= (1<<7);
10582 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
10585 if ((phy->speed_cap_mask &
10586 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
10587 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10588 an_10_100_val |= (1<<6);
10589 autoneg_val |= (1<<9 | 1<<12);
10590 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
10593 if ((phy->speed_cap_mask &
10594 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
10595 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10596 an_10_100_val |= (1<<5);
10597 autoneg_val |= (1<<9 | 1<<12);
10598 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
10602 /* Only 10/100 are allowed to work in FORCE mode */
10603 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10605 (ELINK_SUPPORTED_100baseT_Half |
10606 ELINK_SUPPORTED_100baseT_Full))) {
10607 autoneg_val |= (1<<13);
10608 /* Enabled AUTO-MDIX when autoneg is disabled */
10609 elink_cl45_write(sc, phy,
10610 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10611 (1<<15 | 1<<9 | 7<<0));
10612 /* The PHY needs this set even for forced link. */
10613 an_10_100_val |= (1<<8) | (1<<7);
10614 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
10616 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10618 (ELINK_SUPPORTED_10baseT_Half |
10619 ELINK_SUPPORTED_10baseT_Full))) {
10620 /* Enabled AUTO-MDIX when autoneg is disabled */
10621 elink_cl45_write(sc, phy,
10622 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10623 (1<<15 | 1<<9 | 7<<0));
10624 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
10627 elink_cl45_write(sc, phy,
10628 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
10631 if (phy->req_duplex == DUPLEX_FULL)
10632 autoneg_val |= (1<<8);
10634 /* Always write this if this is not 84833/4.
10635 * For 84833/4, write it only when it's a forced speed.
10637 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10638 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) ||
10639 ((autoneg_val & (1<<12)) == 0))
10640 elink_cl45_write(sc, phy,
10642 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
10644 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10645 (phy->speed_cap_mask &
10646 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10647 (phy->req_line_speed == ELINK_SPEED_10000)) {
10648 ELINK_DEBUG_P0(sc, "Advertising 10G\n");
10649 /* Restart autoneg for 10G*/
10651 elink_cl45_read_or_write(
10654 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10656 elink_cl45_write(sc, phy,
10657 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10660 elink_cl45_write(sc, phy,
10662 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10665 return ELINK_STATUS_OK;
10668 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10669 struct elink_params *params,
10670 struct elink_vars *vars)
10672 struct bxe_softc *sc = params->sc;
10673 /* Restore normal power mode*/
10674 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10675 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10678 elink_ext_phy_hw_reset(sc, params->port);
10679 elink_wait_reset_complete(sc, phy, params);
10681 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10682 return elink_848xx_cmn_config_init(phy, params, vars);
10685 #define PHY84833_CMDHDLR_WAIT 300
10686 #define PHY84833_CMDHDLR_MAX_ARGS 5
10687 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10688 struct elink_params *params, uint16_t fw_cmd,
10689 uint16_t cmd_args[], int argc)
10693 struct bxe_softc *sc = params->sc;
10694 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10695 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10696 MDIO_84833_CMD_HDLR_STATUS,
10697 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10698 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10699 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10700 MDIO_84833_CMD_HDLR_STATUS, &val);
10701 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10705 if (idx >= PHY84833_CMDHDLR_WAIT) {
10706 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10707 return ELINK_STATUS_ERROR;
10710 /* Prepare argument(s) and issue command */
10711 for (idx = 0; idx < argc; idx++) {
10712 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10713 MDIO_84833_CMD_HDLR_DATA1 + idx,
10716 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10717 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd);
10718 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) {
10719 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10720 MDIO_84833_CMD_HDLR_STATUS, &val);
10721 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10722 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10726 if ((idx >= PHY84833_CMDHDLR_WAIT) ||
10727 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10728 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10729 return ELINK_STATUS_ERROR;
10731 /* Gather returning data */
10732 for (idx = 0; idx < argc; idx++) {
10733 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10734 MDIO_84833_CMD_HDLR_DATA1 + idx,
10737 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10738 MDIO_84833_CMD_HDLR_STATUS,
10739 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10740 return ELINK_STATUS_OK;
10743 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy,
10744 struct elink_params *params,
10745 struct elink_vars *vars)
10747 uint32_t pair_swap;
10748 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS];
10749 elink_status_t status;
10750 struct bxe_softc *sc = params->sc;
10752 /* Check for configuration. */
10753 pair_swap = REG_RD(sc, params->shmem_base +
10754 offsetof(struct shmem_region,
10755 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10756 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10758 if (pair_swap == 0)
10759 return ELINK_STATUS_OK;
10761 /* Only the second argument is used for this command */
10762 data[1] = (uint16_t)pair_swap;
10764 status = elink_84833_cmd_hdlr(phy, params,
10765 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS);
10766 if (status == ELINK_STATUS_OK)
10767 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);
10772 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc,
10773 uint32_t shmem_base_path[],
10776 uint32_t reset_pin[2];
10778 uint8_t reset_gpios;
10779 if (CHIP_IS_E3(sc)) {
10780 /* Assume that these will be GPIOs, not EPIOs. */
10781 for (idx = 0; idx < 2; idx++) {
10782 /* Map config param to register bit. */
10783 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10784 offsetof(struct shmem_region,
10785 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
10786 reset_pin[idx] = (reset_pin[idx] &
10787 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
10788 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
10789 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
10790 reset_pin[idx] = (1 << reset_pin[idx]);
10792 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10794 /* E2, look from diff place of shmem. */
10795 for (idx = 0; idx < 2; idx++) {
10796 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
10797 offsetof(struct shmem_region,
10798 dev_info.port_hw_config[0].default_cfg));
10799 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
10800 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
10801 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
10802 reset_pin[idx] = (1 << reset_pin[idx]);
10804 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
10807 return reset_gpios;
10810 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
10811 struct elink_params *params)
10813 struct bxe_softc *sc = params->sc;
10814 uint8_t reset_gpios;
10815 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
10816 offsetof(struct shmem2_region,
10817 other_shmem_base_addr));
10819 uint32_t shmem_base_path[2];
10821 /* Work around for 84833 LED failure inside RESET status */
10822 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10823 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10824 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
10825 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
10826 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
10827 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
10829 shmem_base_path[0] = params->shmem_base;
10830 shmem_base_path[1] = other_shmem_base_addr;
10832 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
10835 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
10837 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",
10840 return ELINK_STATUS_OK;
10843 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
10844 struct elink_params *params,
10845 struct elink_vars *vars)
10848 struct bxe_softc *sc = params->sc;
10849 uint16_t cmd_args = 0;
10851 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n");
10853 /* Prevent Phy from working in EEE and advertising it */
10854 rc = elink_84833_cmd_hdlr(phy, params,
10855 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10856 if (rc != ELINK_STATUS_OK) {
10857 ELINK_DEBUG_P0(sc, "EEE disable failed.\n");
10861 return elink_eee_disable(phy, params, vars);
10864 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
10865 struct elink_params *params,
10866 struct elink_vars *vars)
10869 struct bxe_softc *sc = params->sc;
10870 uint16_t cmd_args = 1;
10872 rc = elink_84833_cmd_hdlr(phy, params,
10873 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1);
10874 if (rc != ELINK_STATUS_OK) {
10875 ELINK_DEBUG_P0(sc, "EEE enable failed.\n");
10879 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
10882 #define PHY84833_CONSTANT_LATENCY 1193
10883 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
10884 struct elink_params *params,
10885 struct elink_vars *vars)
10887 struct bxe_softc *sc = params->sc;
10888 uint8_t port, initialize = 1;
10890 uint32_t actual_phy_selection;
10891 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS];
10892 elink_status_t rc = ELINK_STATUS_OK;
10896 if (!(CHIP_IS_E1x(sc)))
10897 port = SC_PATH(sc);
10899 port = params->port;
10901 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10902 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
10903 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
10907 elink_cl45_write(sc, phy,
10909 MDIO_PMA_REG_CTRL, 0x8000);
10912 elink_wait_reset_complete(sc, phy, params);
10914 /* Wait for GPHY to come out of reset */
10916 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) &&
10917 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10918 /* BCM84823 requires that XGXS links up first @ 10G for normal
10922 temp = vars->line_speed;
10923 vars->line_speed = ELINK_SPEED_10000;
10924 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
10925 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
10926 vars->line_speed = temp;
10929 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10930 MDIO_CTL_REG_84823_MEDIA, &val);
10931 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10932 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
10933 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
10934 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
10935 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
10937 if (CHIP_IS_E3(sc)) {
10938 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
10939 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
10941 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
10942 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
10945 actual_phy_selection = elink_phy_selection(params);
10947 switch (actual_phy_selection) {
10948 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
10949 /* Do nothing. Essentially this is like the priority copper */
10951 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
10952 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
10954 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
10955 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
10957 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
10958 /* Do nothing here. The first PHY won't be initialized at all */
10960 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
10961 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
10965 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
10966 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
10968 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10969 MDIO_CTL_REG_84823_MEDIA, val);
10970 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10971 params->multi_phy_config, val);
10973 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10974 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
10975 elink_84833_pair_swap_cfg(phy, params, vars);
10977 /* Keep AutogrEEEn disabled. */
10980 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
10981 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
10982 rc = elink_84833_cmd_hdlr(phy, params,
10983 PHY84833_CMD_SET_EEE_MODE, cmd_args,
10984 PHY84833_CMDHDLR_MAX_ARGS);
10985 if (rc != ELINK_STATUS_OK)
10986 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n");
10989 rc = elink_848xx_cmn_config_init(phy, params, vars);
10991 elink_save_848xx_spirom_version(phy, sc, params->port);
10992 /* 84833 PHY has a better feature and doesn't need to support this. */
10993 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
10994 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
10995 offsetof(struct shmem_region,
10996 dev_info.port_hw_config[params->port].default_cfg)) &
10997 PORT_HW_CFG_ENABLE_CMS_MASK;
10999 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11000 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
11002 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
11004 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
11005 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11006 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
11009 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11010 MDIO_84833_TOP_CFG_FW_REV, &val);
11012 /* Configure EEE support */
11013 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
11014 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
11015 elink_eee_has_cap(params)) {
11016 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
11017 if (rc != ELINK_STATUS_OK) {
11018 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11019 elink_8483x_disable_eee(phy, params, vars);
11023 if ((phy->req_duplex == DUPLEX_FULL) &&
11024 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11025 (elink_eee_calc_timer(params) ||
11026 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
11027 rc = elink_8483x_enable_eee(phy, params, vars);
11029 rc = elink_8483x_disable_eee(phy, params, vars);
11030 if (rc != ELINK_STATUS_OK) {
11031 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n");
11035 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
11038 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11039 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) {
11040 /* Bring PHY out of super isolate mode as the final step. */
11041 elink_cl45_read_and_write(sc, phy,
11043 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
11044 (uint16_t)~MDIO_84833_SUPER_ISOLATE);
11049 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11050 struct elink_params *params,
11051 struct elink_vars *vars)
11053 struct bxe_softc *sc = params->sc;
11054 uint16_t val, val1, val2;
11055 uint8_t link_up = 0;
11058 /* Check 10G-BaseT link status */
11059 /* Check PMD signal ok */
11060 elink_cl45_read(sc, phy,
11061 MDIO_AN_DEVAD, 0xFFFA, &val1);
11062 elink_cl45_read(sc, phy,
11063 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
11065 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11067 /* Check link 10G */
11068 if (val2 & (1<<11)) {
11069 vars->line_speed = ELINK_SPEED_10000;
11070 vars->duplex = DUPLEX_FULL;
11072 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11073 } else { /* Check Legacy speed link */
11074 uint16_t legacy_status, legacy_speed, mii_ctrl;
11076 /* Enable expansion register 0x42 (Operation mode status) */
11077 elink_cl45_write(sc, phy,
11079 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
11081 /* Get legacy speed operation status */
11082 elink_cl45_read(sc, phy,
11084 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
11087 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",
11089 link_up = ((legacy_status & (1<<11)) == (1<<11));
11090 legacy_speed = (legacy_status & (3<<9));
11091 if (legacy_speed == (0<<9))
11092 vars->line_speed = ELINK_SPEED_10;
11093 else if (legacy_speed == (1<<9))
11094 vars->line_speed = ELINK_SPEED_100;
11095 else if (legacy_speed == (2<<9))
11096 vars->line_speed = ELINK_SPEED_1000;
11097 else { /* Should not happen: Treat as link down */
11098 vars->line_speed = 0;
11102 if (params->feature_config_flags &
11103 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
11104 elink_cl45_read(sc, phy,
11106 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11108 /* For IEEE testing, check for a fake link. */
11109 link_up |= ((mii_ctrl & 0x3040) == 0x40);
11113 if (legacy_status & (1<<8))
11114 vars->duplex = DUPLEX_FULL;
11116 vars->duplex = DUPLEX_HALF;
11119 "Link is up in %dMbps, is_duplex_full= %d\n",
11121 (vars->duplex == DUPLEX_FULL));
11122 /* Check legacy speed AN resolution */
11123 elink_cl45_read(sc, phy,
11125 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
11128 vars->link_status |=
11129 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11130 elink_cl45_read(sc, phy,
11132 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
11134 if ((val & (1<<0)) == 0)
11135 vars->link_status |=
11136 LINK_STATUS_PARALLEL_DETECTION_USED;
11140 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n",
11142 elink_ext_phy_resolve_fc(phy, params, vars);
11144 /* Read LP advertised speeds */
11145 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11146 MDIO_AN_REG_CL37_FC_LP, &val);
11148 vars->link_status |=
11149 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11151 vars->link_status |=
11152 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11154 vars->link_status |=
11155 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11157 vars->link_status |=
11158 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11160 vars->link_status |=
11161 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11163 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11164 MDIO_AN_REG_1000T_STATUS, &val);
11167 vars->link_status |=
11168 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11170 vars->link_status |=
11171 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11173 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11174 MDIO_AN_REG_MASTER_STATUS, &val);
11177 vars->link_status |=
11178 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11180 /* Determine if EEE was negotiated */
11181 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
11182 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834))
11183 elink_eee_an_resolve(phy, params, vars);
11189 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len)
11191 elink_status_t status = ELINK_STATUS_OK;
11192 uint32_t spirom_ver;
11193 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
11194 status = elink_format_ver(spirom_ver, str, len);
11198 static void elink_8481_hw_reset(struct elink_phy *phy,
11199 struct elink_params *params)
11201 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11202 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
11203 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11204 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
11207 static void elink_8481_link_reset(struct elink_phy *phy,
11208 struct elink_params *params)
11210 elink_cl45_write(params->sc, phy,
11211 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
11212 elink_cl45_write(params->sc, phy,
11213 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
11216 static void elink_848x3_link_reset(struct elink_phy *phy,
11217 struct elink_params *params)
11219 struct bxe_softc *sc = params->sc;
11223 if (!(CHIP_IS_E1x(sc)))
11224 port = SC_PATH(sc);
11226 port = params->port;
11228 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11229 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11230 MISC_REGISTERS_GPIO_OUTPUT_LOW,
11233 elink_cl45_read(sc, phy,
11235 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
11236 val16 |= MDIO_84833_SUPER_ISOLATE;
11237 elink_cl45_write(sc, phy,
11239 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
11243 static void elink_848xx_set_link_led(struct elink_phy *phy,
11244 struct elink_params *params, uint8_t mode)
11246 struct bxe_softc *sc = params->sc;
11250 if (!(CHIP_IS_E1x(sc)))
11251 port = SC_PATH(sc);
11253 port = params->port;
11256 case ELINK_LED_MODE_OFF:
11258 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11260 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11261 SHARED_HW_CFG_LED_EXTPHY1) {
11263 /* Set LED masks */
11264 elink_cl45_write(sc, phy,
11266 MDIO_PMA_REG_8481_LED1_MASK,
11269 elink_cl45_write(sc, phy,
11271 MDIO_PMA_REG_8481_LED2_MASK,
11274 elink_cl45_write(sc, phy,
11276 MDIO_PMA_REG_8481_LED3_MASK,
11279 elink_cl45_write(sc, phy,
11281 MDIO_PMA_REG_8481_LED5_MASK,
11285 elink_cl45_write(sc, phy,
11287 MDIO_PMA_REG_8481_LED1_MASK,
11291 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11293 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11296 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11297 SHARED_HW_CFG_LED_EXTPHY1) {
11299 /* Set LED masks */
11300 elink_cl45_write(sc, phy,
11302 MDIO_PMA_REG_8481_LED1_MASK,
11305 elink_cl45_write(sc, phy,
11307 MDIO_PMA_REG_8481_LED2_MASK,
11310 elink_cl45_write(sc, phy,
11312 MDIO_PMA_REG_8481_LED3_MASK,
11315 elink_cl45_write(sc, phy,
11317 MDIO_PMA_REG_8481_LED5_MASK,
11321 elink_cl45_write(sc, phy,
11323 MDIO_PMA_REG_8481_LED1_MASK,
11326 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11327 /* Disable MI_INT interrupt before setting LED4
11328 * source to constant off.
11330 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11332 ELINK_NIG_MASK_MI_INT) {
11333 params->link_flags |=
11334 ELINK_LINK_FLAGS_INT_DISABLED;
11338 NIG_REG_MASK_INTERRUPT_PORT0 +
11340 ELINK_NIG_MASK_MI_INT);
11342 elink_cl45_write(sc, phy,
11344 MDIO_PMA_REG_8481_SIGNAL_MASK,
11349 case ELINK_LED_MODE_ON:
11351 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11353 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11354 SHARED_HW_CFG_LED_EXTPHY1) {
11355 /* Set control reg */
11356 elink_cl45_read(sc, phy,
11358 MDIO_PMA_REG_8481_LINK_SIGNAL,
11363 elink_cl45_write(sc, phy,
11365 MDIO_PMA_REG_8481_LINK_SIGNAL,
11368 /* Set LED masks */
11369 elink_cl45_write(sc, phy,
11371 MDIO_PMA_REG_8481_LED1_MASK,
11374 elink_cl45_write(sc, phy,
11376 MDIO_PMA_REG_8481_LED2_MASK,
11379 elink_cl45_write(sc, phy,
11381 MDIO_PMA_REG_8481_LED3_MASK,
11384 elink_cl45_write(sc, phy,
11386 MDIO_PMA_REG_8481_LED5_MASK,
11389 elink_cl45_write(sc, phy,
11391 MDIO_PMA_REG_8481_LED1_MASK,
11394 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11395 /* Disable MI_INT interrupt before setting LED4
11396 * source to constant on.
11398 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11400 ELINK_NIG_MASK_MI_INT) {
11401 params->link_flags |=
11402 ELINK_LINK_FLAGS_INT_DISABLED;
11406 NIG_REG_MASK_INTERRUPT_PORT0 +
11408 ELINK_NIG_MASK_MI_INT);
11410 elink_cl45_write(sc, phy,
11412 MDIO_PMA_REG_8481_SIGNAL_MASK,
11418 case ELINK_LED_MODE_OPER:
11420 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11422 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11423 SHARED_HW_CFG_LED_EXTPHY1) {
11425 /* Set control reg */
11426 elink_cl45_read(sc, phy,
11428 MDIO_PMA_REG_8481_LINK_SIGNAL,
11432 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
11433 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
11434 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n");
11435 elink_cl45_write(sc, phy,
11437 MDIO_PMA_REG_8481_LINK_SIGNAL,
11441 /* Set LED masks */
11442 elink_cl45_write(sc, phy,
11444 MDIO_PMA_REG_8481_LED1_MASK,
11447 elink_cl45_write(sc, phy,
11449 MDIO_PMA_REG_8481_LED2_MASK,
11452 elink_cl45_write(sc, phy,
11454 MDIO_PMA_REG_8481_LED3_MASK,
11457 elink_cl45_write(sc, phy,
11459 MDIO_PMA_REG_8481_LED5_MASK,
11463 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11464 * sources are all wired through LED1, rather than only
11465 * 10G in other modes.
11467 val = ((params->hw_led_mode <<
11468 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11469 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11471 elink_cl45_write(sc, phy,
11473 MDIO_PMA_REG_8481_LED1_MASK,
11476 /* Tell LED3 to blink on source */
11477 elink_cl45_read(sc, phy,
11479 MDIO_PMA_REG_8481_LINK_SIGNAL,
11482 val |= (1<<6); /* A83B[8:6]= 1 */
11483 elink_cl45_write(sc, phy,
11485 MDIO_PMA_REG_8481_LINK_SIGNAL,
11488 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11489 /* Restore LED4 source to external link,
11490 * and re-enable interrupts.
11492 elink_cl45_write(sc, phy,
11494 MDIO_PMA_REG_8481_SIGNAL_MASK,
11496 if (params->link_flags &
11497 ELINK_LINK_FLAGS_INT_DISABLED) {
11498 elink_link_int_enable(params);
11499 params->link_flags &=
11500 ~ELINK_LINK_FLAGS_INT_DISABLED;
11507 /* This is a workaround for E3+84833 until autoneg
11508 * restart is fixed in f/w
11510 if (CHIP_IS_E3(sc)) {
11511 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11512 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11516 /******************************************************************/
11517 /* 54618SE PHY SECTION */
11518 /******************************************************************/
11519 static void elink_54618se_specific_func(struct elink_phy *phy,
11520 struct elink_params *params,
11523 struct bxe_softc *sc = params->sc;
11526 case ELINK_PHY_INIT:
11527 /* Configure LED4: set to INTR (0x6). */
11528 /* Accessing shadow register 0xe. */
11529 elink_cl22_write(sc, phy,
11530 MDIO_REG_GPHY_SHADOW,
11531 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11532 elink_cl22_read(sc, phy,
11533 MDIO_REG_GPHY_SHADOW,
11535 temp &= ~(0xf << 4);
11536 temp |= (0x6 << 4);
11537 elink_cl22_write(sc, phy,
11538 MDIO_REG_GPHY_SHADOW,
11539 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11540 /* Configure INTR based on link status change. */
11541 elink_cl22_write(sc, phy,
11542 MDIO_REG_INTR_MASK,
11543 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11548 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11549 struct elink_params *params,
11550 struct elink_vars *vars)
11552 struct bxe_softc *sc = params->sc;
11554 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11557 ELINK_DEBUG_P0(sc, "54618SE cfg init\n");
11560 /* This works with E3 only, no need to check the chip
11561 * before determining the port.
11563 port = params->port;
11565 cfg_pin = (REG_RD(sc, params->shmem_base +
11566 offsetof(struct shmem_region,
11567 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11568 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11569 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11571 /* Drive pin high to bring the GPHY out of reset. */
11572 elink_set_cfg_pin(sc, cfg_pin, 1);
11574 /* wait for GPHY to reset */
11578 elink_cl22_write(sc, phy,
11579 MDIO_PMA_REG_CTRL, 0x8000);
11580 elink_wait_reset_complete(sc, phy, params);
11582 /* Wait for GPHY to reset */
11586 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11587 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11588 elink_cl22_write(sc, phy,
11589 MDIO_REG_GPHY_SHADOW,
11590 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11591 elink_cl22_read(sc, phy,
11592 MDIO_REG_GPHY_SHADOW,
11594 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11595 elink_cl22_write(sc, phy,
11596 MDIO_REG_GPHY_SHADOW,
11597 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11600 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11601 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11603 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11604 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11605 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11607 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11608 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11609 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11611 /* Read all advertisement */
11612 elink_cl22_read(sc, phy,
11616 elink_cl22_read(sc, phy,
11620 elink_cl22_read(sc, phy,
11624 /* Disable forced speed */
11625 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11626 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11629 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11630 (phy->speed_cap_mask &
11631 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11632 (phy->req_line_speed == ELINK_SPEED_1000)) {
11633 an_1000_val |= (1<<8);
11634 autoneg_val |= (1<<9 | 1<<12);
11635 if (phy->req_duplex == DUPLEX_FULL)
11636 an_1000_val |= (1<<9);
11637 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
11639 an_1000_val &= ~((1<<8) | (1<<9));
11641 elink_cl22_write(sc, phy,
11644 elink_cl22_read(sc, phy,
11648 /* Advertise 10/100 link speed */
11649 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11650 if (phy->speed_cap_mask &
11651 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11652 an_10_100_val |= (1<<5);
11653 autoneg_val |= (1<<9 | 1<<12);
11654 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
11656 if (phy->speed_cap_mask &
11657 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11658 an_10_100_val |= (1<<6);
11659 autoneg_val |= (1<<9 | 1<<12);
11660 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
11662 if (phy->speed_cap_mask &
11663 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11664 an_10_100_val |= (1<<7);
11665 autoneg_val |= (1<<9 | 1<<12);
11666 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
11668 if (phy->speed_cap_mask &
11669 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11670 an_10_100_val |= (1<<8);
11671 autoneg_val |= (1<<9 | 1<<12);
11672 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
11676 /* Only 10/100 are allowed to work in FORCE mode */
11677 if (phy->req_line_speed == ELINK_SPEED_100) {
11678 autoneg_val |= (1<<13);
11679 /* Enabled AUTO-MDIX when autoneg is disabled */
11680 elink_cl22_write(sc, phy,
11682 (1<<15 | 1<<9 | 7<<0));
11683 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
11685 if (phy->req_line_speed == ELINK_SPEED_10) {
11686 /* Enabled AUTO-MDIX when autoneg is disabled */
11687 elink_cl22_write(sc, phy,
11689 (1<<15 | 1<<9 | 7<<0));
11690 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
11693 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11696 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11697 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11698 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11699 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11701 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11703 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11704 if (rc != ELINK_STATUS_OK) {
11705 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11706 elink_eee_disable(phy, params, vars);
11707 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11708 (phy->req_duplex == DUPLEX_FULL) &&
11709 (elink_eee_calc_timer(params) ||
11710 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
11711 /* Need to advertise EEE only when requested,
11712 * and either no LPI assertion was requested,
11713 * or it was requested and a valid timer was set.
11714 * Also notice full duplex is required for EEE.
11716 elink_eee_advertise(phy, params, vars,
11719 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n");
11720 elink_eee_disable(phy, params, vars);
11723 vars->eee_status &= ~SHMEM_EEE_1G_ADV <<
11724 SHMEM_EEE_SUPPORTED_SHIFT;
11726 if (phy->flags & ELINK_FLAGS_EEE) {
11727 /* Handle legacy auto-grEEEn */
11728 if (params->feature_config_flags &
11729 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11731 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n");
11734 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n");
11736 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11737 MDIO_AN_REG_EEE_ADV, temp);
11741 elink_cl22_write(sc, phy,
11743 an_10_100_val | fc_val);
11745 if (phy->req_duplex == DUPLEX_FULL)
11746 autoneg_val |= (1<<8);
11748 elink_cl22_write(sc, phy,
11749 MDIO_PMA_REG_CTRL, autoneg_val);
11751 return ELINK_STATUS_OK;
11755 static void elink_5461x_set_link_led(struct elink_phy *phy,
11756 struct elink_params *params, uint8_t mode)
11758 struct bxe_softc *sc = params->sc;
11761 elink_cl22_write(sc, phy,
11762 MDIO_REG_GPHY_SHADOW,
11763 MDIO_REG_GPHY_SHADOW_LED_SEL1);
11764 elink_cl22_read(sc, phy,
11765 MDIO_REG_GPHY_SHADOW,
11769 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode);
11771 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11772 case ELINK_LED_MODE_OFF:
11775 case ELINK_LED_MODE_OPER:
11778 case ELINK_LED_MODE_ON:
11784 elink_cl22_write(sc, phy,
11785 MDIO_REG_GPHY_SHADOW,
11786 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11791 static void elink_54618se_link_reset(struct elink_phy *phy,
11792 struct elink_params *params)
11794 struct bxe_softc *sc = params->sc;
11798 /* In case of no EPIO routed to reset the GPHY, put it
11799 * in low power mode.
11801 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
11802 /* This works with E3 only, no need to check the chip
11803 * before determining the port.
11805 port = params->port;
11806 cfg_pin = (REG_RD(sc, params->shmem_base +
11807 offsetof(struct shmem_region,
11808 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11809 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11810 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11812 /* Drive pin low to put GPHY in reset. */
11813 elink_set_cfg_pin(sc, cfg_pin, 0);
11816 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
11817 struct elink_params *params,
11818 struct elink_vars *vars)
11820 struct bxe_softc *sc = params->sc;
11822 uint8_t link_up = 0;
11823 uint16_t legacy_status, legacy_speed;
11825 /* Get speed operation status */
11826 elink_cl22_read(sc, phy,
11827 MDIO_REG_GPHY_AUX_STATUS,
11829 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);
11831 /* Read status to clear the PHY interrupt. */
11832 elink_cl22_read(sc, phy,
11833 MDIO_REG_INTR_STATUS,
11836 link_up = ((legacy_status & (1<<2)) == (1<<2));
11839 legacy_speed = (legacy_status & (7<<8));
11840 if (legacy_speed == (7<<8)) {
11841 vars->line_speed = ELINK_SPEED_1000;
11842 vars->duplex = DUPLEX_FULL;
11843 } else if (legacy_speed == (6<<8)) {
11844 vars->line_speed = ELINK_SPEED_1000;
11845 vars->duplex = DUPLEX_HALF;
11846 } else if (legacy_speed == (5<<8)) {
11847 vars->line_speed = ELINK_SPEED_100;
11848 vars->duplex = DUPLEX_FULL;
11850 /* Omitting 100Base-T4 for now */
11851 else if (legacy_speed == (3<<8)) {
11852 vars->line_speed = ELINK_SPEED_100;
11853 vars->duplex = DUPLEX_HALF;
11854 } else if (legacy_speed == (2<<8)) {
11855 vars->line_speed = ELINK_SPEED_10;
11856 vars->duplex = DUPLEX_FULL;
11857 } else if (legacy_speed == (1<<8)) {
11858 vars->line_speed = ELINK_SPEED_10;
11859 vars->duplex = DUPLEX_HALF;
11860 } else /* Should not happen */
11861 vars->line_speed = 0;
11864 "Link is up in %dMbps, is_duplex_full= %d\n",
11866 (vars->duplex == DUPLEX_FULL));
11868 /* Check legacy speed AN resolution */
11869 elink_cl22_read(sc, phy,
11873 vars->link_status |=
11874 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11875 elink_cl22_read(sc, phy,
11878 if ((val & (1<<0)) == 0)
11879 vars->link_status |=
11880 LINK_STATUS_PARALLEL_DETECTION_USED;
11882 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n",
11885 elink_ext_phy_resolve_fc(phy, params, vars);
11887 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
11888 /* Report LP advertised speeds */
11889 elink_cl22_read(sc, phy, 0x5, &val);
11892 vars->link_status |=
11893 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11895 vars->link_status |=
11896 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11898 vars->link_status |=
11899 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11901 vars->link_status |=
11902 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11904 vars->link_status |=
11905 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11907 elink_cl22_read(sc, phy, 0xa, &val);
11909 vars->link_status |=
11910 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11912 vars->link_status |=
11913 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11915 if ((phy->flags & ELINK_FLAGS_EEE) &&
11916 elink_eee_has_cap(params))
11917 elink_eee_an_resolve(phy, params, vars);
11923 static void elink_54618se_config_loopback(struct elink_phy *phy,
11924 struct elink_params *params)
11926 struct bxe_softc *sc = params->sc;
11928 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
11930 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n");
11932 /* Enable master/slave manual mmode and set to master */
11933 /* mii write 9 [bits set 11 12] */
11934 elink_cl22_write(sc, phy, 0x09, 3<<11);
11936 /* forced 1G and disable autoneg */
11937 /* set val [mii read 0] */
11938 /* set val [expr $val & [bits clear 6 12 13]] */
11939 /* set val [expr $val | [bits set 6 8]] */
11940 /* mii write 0 $val */
11941 elink_cl22_read(sc, phy, 0x00, &val);
11942 val &= ~((1<<6) | (1<<12) | (1<<13));
11943 val |= (1<<6) | (1<<8);
11944 elink_cl22_write(sc, phy, 0x00, val);
11946 /* Set external loopback and Tx using 6dB coding */
11947 /* mii write 0x18 7 */
11948 /* set val [mii read 0x18] */
11949 /* mii write 0x18 [expr $val | [bits set 10 15]] */
11950 elink_cl22_write(sc, phy, 0x18, 7);
11951 elink_cl22_read(sc, phy, 0x18, &val);
11952 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
11954 /* This register opens the gate for the UMAC despite its name */
11955 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
11957 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
11958 * length used by the MAC receive logic to check frames.
11960 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
11963 /******************************************************************/
11964 /* SFX7101 PHY SECTION */
11965 /******************************************************************/
11966 static void elink_7101_config_loopback(struct elink_phy *phy,
11967 struct elink_params *params)
11969 struct bxe_softc *sc = params->sc;
11970 /* SFX7101_XGXS_TEST1 */
11971 elink_cl45_write(sc, phy,
11972 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
11975 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
11976 struct elink_params *params,
11977 struct elink_vars *vars)
11979 uint16_t fw_ver1, fw_ver2, val;
11980 struct bxe_softc *sc = params->sc;
11981 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n");
11983 /* Restore normal power mode*/
11984 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
11985 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
11987 elink_ext_phy_hw_reset(sc, params->port);
11988 elink_wait_reset_complete(sc, phy, params);
11990 elink_cl45_write(sc, phy,
11991 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
11992 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n");
11993 elink_cl45_write(sc, phy,
11994 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
11996 elink_ext_phy_set_pause(params, phy, vars);
11997 /* Restart autoneg */
11998 elink_cl45_read(sc, phy,
11999 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
12001 elink_cl45_write(sc, phy,
12002 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
12004 /* Save spirom version */
12005 elink_cl45_read(sc, phy,
12006 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
12008 elink_cl45_read(sc, phy,
12009 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
12010 elink_save_spirom_version(sc, params->port,
12011 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12012 return ELINK_STATUS_OK;
12015 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12016 struct elink_params *params,
12017 struct elink_vars *vars)
12019 struct bxe_softc *sc = params->sc;
12021 uint16_t val1, val2;
12022 elink_cl45_read(sc, phy,
12023 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
12024 elink_cl45_read(sc, phy,
12025 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
12026 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",
12028 elink_cl45_read(sc, phy,
12029 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
12030 elink_cl45_read(sc, phy,
12031 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
12032 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",
12034 link_up = ((val1 & 4) == 4);
12035 /* If link is up print the AN outcome of the SFX7101 PHY */
12037 elink_cl45_read(sc, phy,
12038 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
12040 vars->line_speed = ELINK_SPEED_10000;
12041 vars->duplex = DUPLEX_FULL;
12042 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",
12043 val2, (val2 & (1<<14)));
12044 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12045 elink_ext_phy_resolve_fc(phy, params, vars);
12047 /* Read LP advertised speeds */
12048 if (val2 & (1<<11))
12049 vars->link_status |=
12050 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
12055 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
12058 return ELINK_STATUS_ERROR;
12059 str[0] = (spirom_ver & 0xFF);
12060 str[1] = (spirom_ver & 0xFF00) >> 8;
12061 str[2] = (spirom_ver & 0xFF0000) >> 16;
12062 str[3] = (spirom_ver & 0xFF000000) >> 24;
12065 return ELINK_STATUS_OK;
12068 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12072 elink_cl45_read(sc, phy,
12074 MDIO_PMA_REG_7101_RESET, &val);
12076 for (cnt = 0; cnt < 10; cnt++) {
12078 /* Writes a self-clearing reset */
12079 elink_cl45_write(sc, phy,
12081 MDIO_PMA_REG_7101_RESET,
12083 /* Wait for clear */
12084 elink_cl45_read(sc, phy,
12086 MDIO_PMA_REG_7101_RESET, &val);
12088 if ((val & (1<<15)) == 0)
12093 static void elink_7101_hw_reset(struct elink_phy *phy,
12094 struct elink_params *params) {
12095 /* Low power mode is controlled by GPIO 2 */
12096 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
12097 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12098 /* The PHY reset is controlled by GPIO 1 */
12099 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
12100 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12103 static void elink_7101_set_link_led(struct elink_phy *phy,
12104 struct elink_params *params, uint8_t mode)
12107 struct bxe_softc *sc = params->sc;
12109 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12110 case ELINK_LED_MODE_OFF:
12113 case ELINK_LED_MODE_ON:
12116 case ELINK_LED_MODE_OPER:
12120 elink_cl45_write(sc, phy,
12122 MDIO_PMA_REG_7107_LINK_LED_CNTL,
12126 /******************************************************************/
12127 /* STATIC PHY DECLARATION */
12128 /******************************************************************/
12130 static const struct elink_phy phy_null = {
12131 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
12134 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12135 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12136 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12139 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12141 .req_flow_ctrl = 0,
12142 .req_line_speed = 0,
12143 .speed_cap_mask = 0,
12146 .config_init = (config_init_t)NULL,
12147 .read_status = (read_status_t)NULL,
12148 .link_reset = (link_reset_t)NULL,
12149 .config_loopback = (config_loopback_t)NULL,
12150 .format_fw_ver = (format_fw_ver_t)NULL,
12151 .hw_reset = (hw_reset_t)NULL,
12152 .set_link_led = (set_link_led_t)NULL,
12153 .phy_specific_func = (phy_specific_func_t)NULL
12156 static const struct elink_phy phy_serdes = {
12157 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
12161 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12162 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12164 .supported = (ELINK_SUPPORTED_10baseT_Half |
12165 ELINK_SUPPORTED_10baseT_Full |
12166 ELINK_SUPPORTED_100baseT_Half |
12167 ELINK_SUPPORTED_100baseT_Full |
12168 ELINK_SUPPORTED_1000baseT_Full |
12169 ELINK_SUPPORTED_2500baseX_Full |
12170 ELINK_SUPPORTED_TP |
12171 ELINK_SUPPORTED_Autoneg |
12172 ELINK_SUPPORTED_Pause |
12173 ELINK_SUPPORTED_Asym_Pause),
12174 .media_type = ELINK_ETH_PHY_BASE_T,
12176 .req_flow_ctrl = 0,
12177 .req_line_speed = 0,
12178 .speed_cap_mask = 0,
12181 .config_init = (config_init_t)elink_xgxs_config_init,
12182 .read_status = (read_status_t)elink_link_settings_status,
12183 .link_reset = (link_reset_t)elink_int_link_reset,
12184 .config_loopback = (config_loopback_t)NULL,
12185 .format_fw_ver = (format_fw_ver_t)NULL,
12186 .hw_reset = (hw_reset_t)NULL,
12187 .set_link_led = (set_link_led_t)NULL,
12188 .phy_specific_func = (phy_specific_func_t)NULL
12191 static const struct elink_phy phy_xgxs = {
12192 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12196 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12197 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12199 .supported = (ELINK_SUPPORTED_10baseT_Half |
12200 ELINK_SUPPORTED_10baseT_Full |
12201 ELINK_SUPPORTED_100baseT_Half |
12202 ELINK_SUPPORTED_100baseT_Full |
12203 ELINK_SUPPORTED_1000baseT_Full |
12204 ELINK_SUPPORTED_2500baseX_Full |
12205 ELINK_SUPPORTED_10000baseT_Full |
12206 ELINK_SUPPORTED_FIBRE |
12207 ELINK_SUPPORTED_Autoneg |
12208 ELINK_SUPPORTED_Pause |
12209 ELINK_SUPPORTED_Asym_Pause),
12210 .media_type = ELINK_ETH_PHY_CX4,
12212 .req_flow_ctrl = 0,
12213 .req_line_speed = 0,
12214 .speed_cap_mask = 0,
12217 .config_init = (config_init_t)elink_xgxs_config_init,
12218 .read_status = (read_status_t)elink_link_settings_status,
12219 .link_reset = (link_reset_t)elink_int_link_reset,
12220 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
12221 .format_fw_ver = (format_fw_ver_t)NULL,
12222 .hw_reset = (hw_reset_t)NULL,
12223 .set_link_led = (set_link_led_t)NULL,
12224 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
12226 static const struct elink_phy phy_warpcore = {
12227 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12230 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
12231 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12232 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12234 .supported = (ELINK_SUPPORTED_10baseT_Half |
12235 ELINK_SUPPORTED_10baseT_Full |
12236 ELINK_SUPPORTED_100baseT_Half |
12237 ELINK_SUPPORTED_100baseT_Full |
12238 ELINK_SUPPORTED_1000baseT_Full |
12239 ELINK_SUPPORTED_10000baseT_Full |
12240 ELINK_SUPPORTED_20000baseKR2_Full |
12241 ELINK_SUPPORTED_20000baseMLD2_Full |
12242 ELINK_SUPPORTED_FIBRE |
12243 ELINK_SUPPORTED_Autoneg |
12244 ELINK_SUPPORTED_Pause |
12245 ELINK_SUPPORTED_Asym_Pause),
12246 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
12248 .req_flow_ctrl = 0,
12249 .req_line_speed = 0,
12250 .speed_cap_mask = 0,
12251 /* req_duplex = */0,
12253 .config_init = (config_init_t)elink_warpcore_config_init,
12254 .read_status = (read_status_t)elink_warpcore_read_status,
12255 .link_reset = (link_reset_t)elink_warpcore_link_reset,
12256 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
12257 .format_fw_ver = (format_fw_ver_t)NULL,
12258 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
12259 .set_link_led = (set_link_led_t)NULL,
12260 .phy_specific_func = (phy_specific_func_t)NULL
12264 static const struct elink_phy phy_7101 = {
12265 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
12268 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
12269 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12270 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12272 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12273 ELINK_SUPPORTED_TP |
12274 ELINK_SUPPORTED_Autoneg |
12275 ELINK_SUPPORTED_Pause |
12276 ELINK_SUPPORTED_Asym_Pause),
12277 .media_type = ELINK_ETH_PHY_BASE_T,
12279 .req_flow_ctrl = 0,
12280 .req_line_speed = 0,
12281 .speed_cap_mask = 0,
12284 .config_init = (config_init_t)elink_7101_config_init,
12285 .read_status = (read_status_t)elink_7101_read_status,
12286 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12287 .config_loopback = (config_loopback_t)elink_7101_config_loopback,
12288 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
12289 .hw_reset = (hw_reset_t)elink_7101_hw_reset,
12290 .set_link_led = (set_link_led_t)elink_7101_set_link_led,
12291 .phy_specific_func = (phy_specific_func_t)NULL
12293 static const struct elink_phy phy_8073 = {
12294 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
12298 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12299 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12301 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12302 ELINK_SUPPORTED_2500baseX_Full |
12303 ELINK_SUPPORTED_1000baseT_Full |
12304 ELINK_SUPPORTED_FIBRE |
12305 ELINK_SUPPORTED_Autoneg |
12306 ELINK_SUPPORTED_Pause |
12307 ELINK_SUPPORTED_Asym_Pause),
12308 .media_type = ELINK_ETH_PHY_KR,
12310 .req_flow_ctrl = 0,
12311 .req_line_speed = 0,
12312 .speed_cap_mask = 0,
12315 .config_init = (config_init_t)elink_8073_config_init,
12316 .read_status = (read_status_t)elink_8073_read_status,
12317 .link_reset = (link_reset_t)elink_8073_link_reset,
12318 .config_loopback = (config_loopback_t)NULL,
12319 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12320 .hw_reset = (hw_reset_t)NULL,
12321 .set_link_led = (set_link_led_t)NULL,
12322 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
12324 static const struct elink_phy phy_8705 = {
12325 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
12328 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12329 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12330 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12332 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12333 ELINK_SUPPORTED_FIBRE |
12334 ELINK_SUPPORTED_Pause |
12335 ELINK_SUPPORTED_Asym_Pause),
12336 .media_type = ELINK_ETH_PHY_XFP_FIBER,
12338 .req_flow_ctrl = 0,
12339 .req_line_speed = 0,
12340 .speed_cap_mask = 0,
12343 .config_init = (config_init_t)elink_8705_config_init,
12344 .read_status = (read_status_t)elink_8705_read_status,
12345 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12346 .config_loopback = (config_loopback_t)NULL,
12347 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
12348 .hw_reset = (hw_reset_t)NULL,
12349 .set_link_led = (set_link_led_t)NULL,
12350 .phy_specific_func = (phy_specific_func_t)NULL
12352 static const struct elink_phy phy_8706 = {
12353 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
12356 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12357 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12358 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12360 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12361 ELINK_SUPPORTED_1000baseT_Full |
12362 ELINK_SUPPORTED_FIBRE |
12363 ELINK_SUPPORTED_Pause |
12364 ELINK_SUPPORTED_Asym_Pause),
12365 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
12367 .req_flow_ctrl = 0,
12368 .req_line_speed = 0,
12369 .speed_cap_mask = 0,
12372 .config_init = (config_init_t)elink_8706_config_init,
12373 .read_status = (read_status_t)elink_8706_read_status,
12374 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12375 .config_loopback = (config_loopback_t)NULL,
12376 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12377 .hw_reset = (hw_reset_t)NULL,
12378 .set_link_led = (set_link_led_t)NULL,
12379 .phy_specific_func = (phy_specific_func_t)NULL
12382 static const struct elink_phy phy_8726 = {
12383 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
12386 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
12387 ELINK_FLAGS_TX_ERROR_CHECK),
12388 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12389 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12391 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12392 ELINK_SUPPORTED_1000baseT_Full |
12393 ELINK_SUPPORTED_Autoneg |
12394 ELINK_SUPPORTED_FIBRE |
12395 ELINK_SUPPORTED_Pause |
12396 ELINK_SUPPORTED_Asym_Pause),
12397 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12399 .req_flow_ctrl = 0,
12400 .req_line_speed = 0,
12401 .speed_cap_mask = 0,
12404 .config_init = (config_init_t)elink_8726_config_init,
12405 .read_status = (read_status_t)elink_8726_read_status,
12406 .link_reset = (link_reset_t)elink_8726_link_reset,
12407 .config_loopback = (config_loopback_t)elink_8726_config_loopback,
12408 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12409 .hw_reset = (hw_reset_t)NULL,
12410 .set_link_led = (set_link_led_t)NULL,
12411 .phy_specific_func = (phy_specific_func_t)NULL
12414 static const struct elink_phy phy_8727 = {
12415 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
12418 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12419 ELINK_FLAGS_TX_ERROR_CHECK),
12420 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12421 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12423 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12424 ELINK_SUPPORTED_1000baseT_Full |
12425 ELINK_SUPPORTED_FIBRE |
12426 ELINK_SUPPORTED_Pause |
12427 ELINK_SUPPORTED_Asym_Pause),
12428 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12430 .req_flow_ctrl = 0,
12431 .req_line_speed = 0,
12432 .speed_cap_mask = 0,
12435 .config_init = (config_init_t)elink_8727_config_init,
12436 .read_status = (read_status_t)elink_8727_read_status,
12437 .link_reset = (link_reset_t)elink_8727_link_reset,
12438 .config_loopback = (config_loopback_t)NULL,
12439 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12440 .hw_reset = (hw_reset_t)elink_8727_hw_reset,
12441 .set_link_led = (set_link_led_t)elink_8727_set_link_led,
12442 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
12444 static const struct elink_phy phy_8481 = {
12445 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12448 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12449 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12450 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12451 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12453 .supported = (ELINK_SUPPORTED_10baseT_Half |
12454 ELINK_SUPPORTED_10baseT_Full |
12455 ELINK_SUPPORTED_100baseT_Half |
12456 ELINK_SUPPORTED_100baseT_Full |
12457 ELINK_SUPPORTED_1000baseT_Full |
12458 ELINK_SUPPORTED_10000baseT_Full |
12459 ELINK_SUPPORTED_TP |
12460 ELINK_SUPPORTED_Autoneg |
12461 ELINK_SUPPORTED_Pause |
12462 ELINK_SUPPORTED_Asym_Pause),
12463 .media_type = ELINK_ETH_PHY_BASE_T,
12465 .req_flow_ctrl = 0,
12466 .req_line_speed = 0,
12467 .speed_cap_mask = 0,
12470 .config_init = (config_init_t)elink_8481_config_init,
12471 .read_status = (read_status_t)elink_848xx_read_status,
12472 .link_reset = (link_reset_t)elink_8481_link_reset,
12473 .config_loopback = (config_loopback_t)NULL,
12474 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12475 .hw_reset = (hw_reset_t)elink_8481_hw_reset,
12476 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12477 .phy_specific_func = (phy_specific_func_t)NULL
12480 static const struct elink_phy phy_84823 = {
12481 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12484 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12485 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12486 ELINK_FLAGS_TX_ERROR_CHECK),
12487 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12488 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12490 .supported = (ELINK_SUPPORTED_10baseT_Half |
12491 ELINK_SUPPORTED_10baseT_Full |
12492 ELINK_SUPPORTED_100baseT_Half |
12493 ELINK_SUPPORTED_100baseT_Full |
12494 ELINK_SUPPORTED_1000baseT_Full |
12495 ELINK_SUPPORTED_10000baseT_Full |
12496 ELINK_SUPPORTED_TP |
12497 ELINK_SUPPORTED_Autoneg |
12498 ELINK_SUPPORTED_Pause |
12499 ELINK_SUPPORTED_Asym_Pause),
12500 .media_type = ELINK_ETH_PHY_BASE_T,
12502 .req_flow_ctrl = 0,
12503 .req_line_speed = 0,
12504 .speed_cap_mask = 0,
12507 .config_init = (config_init_t)elink_848x3_config_init,
12508 .read_status = (read_status_t)elink_848xx_read_status,
12509 .link_reset = (link_reset_t)elink_848x3_link_reset,
12510 .config_loopback = (config_loopback_t)NULL,
12511 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12512 .hw_reset = (hw_reset_t)NULL,
12513 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12514 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12517 static const struct elink_phy phy_84833 = {
12518 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12521 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12522 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12523 ELINK_FLAGS_TX_ERROR_CHECK |
12524 ELINK_FLAGS_TEMPERATURE),
12525 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12526 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12528 .supported = (ELINK_SUPPORTED_100baseT_Half |
12529 ELINK_SUPPORTED_100baseT_Full |
12530 ELINK_SUPPORTED_1000baseT_Full |
12531 ELINK_SUPPORTED_10000baseT_Full |
12532 ELINK_SUPPORTED_TP |
12533 ELINK_SUPPORTED_Autoneg |
12534 ELINK_SUPPORTED_Pause |
12535 ELINK_SUPPORTED_Asym_Pause),
12536 .media_type = ELINK_ETH_PHY_BASE_T,
12538 .req_flow_ctrl = 0,
12539 .req_line_speed = 0,
12540 .speed_cap_mask = 0,
12543 .config_init = (config_init_t)elink_848x3_config_init,
12544 .read_status = (read_status_t)elink_848xx_read_status,
12545 .link_reset = (link_reset_t)elink_848x3_link_reset,
12546 .config_loopback = (config_loopback_t)NULL,
12547 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12548 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12549 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12550 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12553 static const struct elink_phy phy_84834 = {
12554 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12557 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12558 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12559 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12560 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12562 .supported = (ELINK_SUPPORTED_100baseT_Half |
12563 ELINK_SUPPORTED_100baseT_Full |
12564 ELINK_SUPPORTED_1000baseT_Full |
12565 ELINK_SUPPORTED_10000baseT_Full |
12566 ELINK_SUPPORTED_TP |
12567 ELINK_SUPPORTED_Autoneg |
12568 ELINK_SUPPORTED_Pause |
12569 ELINK_SUPPORTED_Asym_Pause),
12570 .media_type = ELINK_ETH_PHY_BASE_T,
12572 .req_flow_ctrl = 0,
12573 .req_line_speed = 0,
12574 .speed_cap_mask = 0,
12577 .config_init = (config_init_t)elink_848x3_config_init,
12578 .read_status = (read_status_t)elink_848xx_read_status,
12579 .link_reset = (link_reset_t)elink_848x3_link_reset,
12580 .config_loopback = (config_loopback_t)NULL,
12581 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12582 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12583 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12584 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12587 static const struct elink_phy phy_54618se = {
12588 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12591 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12592 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12593 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12595 .supported = (ELINK_SUPPORTED_10baseT_Half |
12596 ELINK_SUPPORTED_10baseT_Full |
12597 ELINK_SUPPORTED_100baseT_Half |
12598 ELINK_SUPPORTED_100baseT_Full |
12599 ELINK_SUPPORTED_1000baseT_Full |
12600 ELINK_SUPPORTED_TP |
12601 ELINK_SUPPORTED_Autoneg |
12602 ELINK_SUPPORTED_Pause |
12603 ELINK_SUPPORTED_Asym_Pause),
12604 .media_type = ELINK_ETH_PHY_BASE_T,
12606 .req_flow_ctrl = 0,
12607 .req_line_speed = 0,
12608 .speed_cap_mask = 0,
12609 /* req_duplex = */0,
12611 .config_init = (config_init_t)elink_54618se_config_init,
12612 .read_status = (read_status_t)elink_54618se_read_status,
12613 .link_reset = (link_reset_t)elink_54618se_link_reset,
12614 .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
12615 .format_fw_ver = (format_fw_ver_t)NULL,
12616 .hw_reset = (hw_reset_t)NULL,
12617 .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
12618 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
12620 /*****************************************************************/
12622 /* Populate the phy according. Main function: elink_populate_phy */
12624 /*****************************************************************/
12626 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base,
12627 struct elink_phy *phy, uint8_t port,
12630 /* Get the 4 lanes xgxs config rx and tx */
12631 uint32_t rx = 0, tx = 0, i;
12632 for (i = 0; i < 2; i++) {
12633 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
12634 * the shmem. When num_phys is greater than 1, than this value
12635 * applies only to ELINK_EXT_PHY1
12637 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
12638 rx = REG_RD(sc, shmem_base +
12639 offsetof(struct shmem_region,
12640 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12642 tx = REG_RD(sc, shmem_base +
12643 offsetof(struct shmem_region,
12644 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12646 rx = REG_RD(sc, shmem_base +
12647 offsetof(struct shmem_region,
12648 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12650 tx = REG_RD(sc, shmem_base +
12651 offsetof(struct shmem_region,
12652 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12655 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12656 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12658 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12659 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12663 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base,
12664 uint8_t phy_index, uint8_t port)
12666 uint32_t ext_phy_config = 0;
12667 switch (phy_index) {
12668 case ELINK_EXT_PHY1:
12669 ext_phy_config = REG_RD(sc, shmem_base +
12670 offsetof(struct shmem_region,
12671 dev_info.port_hw_config[port].external_phy_config));
12673 case ELINK_EXT_PHY2:
12674 ext_phy_config = REG_RD(sc, shmem_base +
12675 offsetof(struct shmem_region,
12676 dev_info.port_hw_config[port].external_phy_config2));
12679 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index);
12680 return ELINK_STATUS_ERROR;
12683 return ext_phy_config;
12685 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
12686 struct elink_phy *phy)
12690 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
12691 offsetof(struct shmem_region,
12692 dev_info.port_feature_config[port].link_config)) &
12693 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12694 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
12695 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
12697 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);
12698 if (USES_WARPCORE(sc)) {
12699 uint32_t serdes_net_if;
12700 phy_addr = REG_RD(sc,
12701 MISC_REG_WC0_CTRL_PHY_ADDR);
12702 *phy = phy_warpcore;
12703 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12704 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
12706 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
12707 /* Check Dual mode */
12708 serdes_net_if = (REG_RD(sc, shmem_base +
12709 offsetof(struct shmem_region, dev_info.
12710 port_hw_config[port].default_cfg)) &
12711 PORT_HW_CFG_NET_SERDES_IF_MASK);
12712 /* Set the appropriate supported and flags indications per
12713 * interface type of the chip
12715 switch (serdes_net_if) {
12716 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
12717 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
12718 ELINK_SUPPORTED_10baseT_Full |
12719 ELINK_SUPPORTED_100baseT_Half |
12720 ELINK_SUPPORTED_100baseT_Full |
12721 ELINK_SUPPORTED_1000baseT_Full |
12722 ELINK_SUPPORTED_FIBRE |
12723 ELINK_SUPPORTED_Autoneg |
12724 ELINK_SUPPORTED_Pause |
12725 ELINK_SUPPORTED_Asym_Pause);
12726 phy->media_type = ELINK_ETH_PHY_BASE_T;
12728 case PORT_HW_CFG_NET_SERDES_IF_XFI:
12729 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12730 ELINK_SUPPORTED_10000baseT_Full |
12731 ELINK_SUPPORTED_FIBRE |
12732 ELINK_SUPPORTED_Pause |
12733 ELINK_SUPPORTED_Asym_Pause);
12734 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
12736 case PORT_HW_CFG_NET_SERDES_IF_SFI:
12737 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12738 ELINK_SUPPORTED_10000baseT_Full |
12739 ELINK_SUPPORTED_FIBRE |
12740 ELINK_SUPPORTED_Pause |
12741 ELINK_SUPPORTED_Asym_Pause);
12742 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
12744 case PORT_HW_CFG_NET_SERDES_IF_KR:
12745 phy->media_type = ELINK_ETH_PHY_KR;
12746 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
12747 ELINK_SUPPORTED_10000baseT_Full |
12748 ELINK_SUPPORTED_FIBRE |
12749 ELINK_SUPPORTED_Autoneg |
12750 ELINK_SUPPORTED_Pause |
12751 ELINK_SUPPORTED_Asym_Pause);
12753 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
12754 phy->media_type = ELINK_ETH_PHY_KR;
12755 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12756 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
12757 ELINK_SUPPORTED_FIBRE |
12758 ELINK_SUPPORTED_Pause |
12759 ELINK_SUPPORTED_Asym_Pause);
12761 case PORT_HW_CFG_NET_SERDES_IF_KR2:
12762 phy->media_type = ELINK_ETH_PHY_KR;
12763 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
12764 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
12765 ELINK_SUPPORTED_10000baseT_Full |
12766 ELINK_SUPPORTED_1000baseT_Full |
12767 ELINK_SUPPORTED_Autoneg |
12768 ELINK_SUPPORTED_FIBRE |
12769 ELINK_SUPPORTED_Pause |
12770 ELINK_SUPPORTED_Asym_Pause);
12771 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
12774 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",
12779 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
12780 * was not set as expected. For B0, ECO will be enabled so there
12781 * won't be an issue there
12783 if (CHIP_REV(sc) == CHIP_REV_Ax)
12784 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
12786 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
12789 switch (switch_cfg) {
12790 case ELINK_SWITCH_CFG_1G:
12791 phy_addr = REG_RD(sc,
12792 NIG_REG_SERDES0_CTRL_PHY_ADDR +
12796 case ELINK_SWITCH_CFG_10G:
12797 phy_addr = REG_RD(sc,
12798 NIG_REG_XGXS0_CTRL_PHY_ADDR +
12803 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n");
12804 return ELINK_STATUS_ERROR;
12807 phy->addr = (uint8_t)phy_addr;
12808 phy->mdio_ctrl = elink_get_emac_base(sc,
12809 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
12811 if (CHIP_IS_E2(sc))
12812 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
12814 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
12816 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
12817 port, phy->addr, phy->mdio_ctrl);
12819 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
12820 return ELINK_STATUS_OK;
12823 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc,
12825 uint32_t shmem_base,
12826 uint32_t shmem2_base,
12828 struct elink_phy *phy)
12830 uint32_t ext_phy_config, phy_type, config2;
12831 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
12832 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
12834 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
12835 /* Select the phy type */
12836 switch (phy_type) {
12837 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12838 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
12841 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
12844 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
12847 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12848 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12851 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
12852 /* BCM8727_NOC => BCM8727 no over current */
12853 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12855 phy->flags |= ELINK_FLAGS_NOC;
12857 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
12858 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12859 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
12862 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
12865 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
12868 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
12871 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
12874 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
12875 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
12876 *phy = phy_54618se;
12877 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
12878 phy->flags |= ELINK_FLAGS_EEE;
12880 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
12883 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
12885 return ELINK_STATUS_ERROR;
12888 /* In case external PHY wasn't found */
12889 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
12890 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
12891 return ELINK_STATUS_ERROR;
12892 return ELINK_STATUS_OK;
12895 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
12896 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
12898 /* The shmem address of the phy version is located on different
12899 * structures. In case this structure is too old, do not set
12902 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
12903 dev_info.shared_hw_config.config2));
12904 if (phy_index == ELINK_EXT_PHY1) {
12905 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
12906 port_mb[port].ext_phy_fw_version);
12908 /* Check specific mdc mdio settings */
12909 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
12910 mdc_mdio_access = config2 &
12911 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
12913 uint32_t size = REG_RD(sc, shmem2_base);
12916 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
12917 phy->ver_addr = shmem2_base +
12918 offsetof(struct shmem2_region,
12919 ext_phy_fw_version2[port]);
12921 /* Check specific mdc mdio settings */
12922 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
12923 mdc_mdio_access = (config2 &
12924 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
12925 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
12926 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
12928 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
12930 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
12931 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) &&
12933 /* Remove 100Mb link supported for BCM84833/4 when phy fw
12934 * version lower than or equal to 1.39
12936 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
12937 if (((raw_ver & 0x7F) <= 39) &&
12938 (((raw_ver & 0xF80) >> 7) <= 1))
12939 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
12940 ELINK_SUPPORTED_100baseT_Full);
12943 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
12944 phy_type, port, phy_index);
12945 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n",
12946 phy->addr, phy->mdio_ctrl);
12947 return ELINK_STATUS_OK;
12950 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base,
12951 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
12953 elink_status_t status = ELINK_STATUS_OK;
12954 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
12955 if (phy_index == ELINK_INT_PHY)
12956 return elink_populate_int_phy(sc, shmem_base, port, phy);
12957 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
12962 static void elink_phy_def_cfg(struct elink_params *params,
12963 struct elink_phy *phy,
12966 struct bxe_softc *sc = params->sc;
12967 uint32_t link_config;
12968 /* Populate the default phy configuration for MF mode */
12969 if (phy_index == ELINK_EXT_PHY2) {
12970 link_config = REG_RD(sc, params->shmem_base +
12971 offsetof(struct shmem_region, dev_info.
12972 port_feature_config[params->port].link_config2));
12973 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12974 offsetof(struct shmem_region,
12976 port_hw_config[params->port].speed_capability_mask2));
12978 link_config = REG_RD(sc, params->shmem_base +
12979 offsetof(struct shmem_region, dev_info.
12980 port_feature_config[params->port].link_config));
12981 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
12982 offsetof(struct shmem_region,
12984 port_hw_config[params->port].speed_capability_mask));
12987 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
12988 phy_index, link_config, phy->speed_cap_mask);
12990 phy->req_duplex = DUPLEX_FULL;
12991 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
12992 case PORT_FEATURE_LINK_SPEED_10M_HALF:
12993 phy->req_duplex = DUPLEX_HALF;
12994 case PORT_FEATURE_LINK_SPEED_10M_FULL:
12995 phy->req_line_speed = ELINK_SPEED_10;
12997 case PORT_FEATURE_LINK_SPEED_100M_HALF:
12998 phy->req_duplex = DUPLEX_HALF;
12999 case PORT_FEATURE_LINK_SPEED_100M_FULL:
13000 phy->req_line_speed = ELINK_SPEED_100;
13002 case PORT_FEATURE_LINK_SPEED_1G:
13003 phy->req_line_speed = ELINK_SPEED_1000;
13005 case PORT_FEATURE_LINK_SPEED_2_5G:
13006 phy->req_line_speed = ELINK_SPEED_2500;
13008 case PORT_FEATURE_LINK_SPEED_10G_CX4:
13009 phy->req_line_speed = ELINK_SPEED_10000;
13012 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13016 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
13017 case PORT_FEATURE_FLOW_CONTROL_AUTO:
13018 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13020 case PORT_FEATURE_FLOW_CONTROL_TX:
13021 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13023 case PORT_FEATURE_FLOW_CONTROL_RX:
13024 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13026 case PORT_FEATURE_FLOW_CONTROL_BOTH:
13027 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13030 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13035 uint32_t elink_phy_selection(struct elink_params *params)
13037 uint32_t phy_config_swapped, prio_cfg;
13038 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
13040 phy_config_swapped = params->multi_phy_config &
13041 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13043 prio_cfg = params->multi_phy_config &
13044 PORT_HW_CFG_PHY_SELECTION_MASK;
13046 if (phy_config_swapped) {
13047 switch (prio_cfg) {
13048 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
13049 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
13051 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
13052 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
13054 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
13055 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
13057 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
13058 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
13062 return_cfg = prio_cfg;
13067 elink_status_t elink_phy_probe(struct elink_params *params)
13069 uint8_t phy_index, actual_phy_idx;
13070 uint32_t phy_config_swapped, sync_offset, media_types;
13071 struct bxe_softc *sc = params->sc;
13072 struct elink_phy *phy;
13073 params->num_phys = 0;
13074 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13075 #ifdef ELINK_INCLUDE_EMUL
13076 if (CHIP_REV_IS_EMUL(sc))
13077 return ELINK_STATUS_OK;
13079 phy_config_swapped = params->multi_phy_config &
13080 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13082 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
13084 actual_phy_idx = phy_index;
13085 if (phy_config_swapped) {
13086 if (phy_index == ELINK_EXT_PHY1)
13087 actual_phy_idx = ELINK_EXT_PHY2;
13088 else if (phy_index == ELINK_EXT_PHY2)
13089 actual_phy_idx = ELINK_EXT_PHY1;
13091 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
13092 " actual_phy_idx %x\n", phy_config_swapped,
13093 phy_index, actual_phy_idx);
13094 phy = ¶ms->phy[actual_phy_idx];
13095 if (elink_populate_phy(sc, phy_index, params->shmem_base,
13096 params->shmem2_base, params->port,
13097 phy) != ELINK_STATUS_OK) {
13098 params->num_phys = 0;
13099 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13101 for (phy_index = ELINK_INT_PHY;
13102 phy_index < ELINK_MAX_PHYS;
13105 return ELINK_STATUS_ERROR;
13107 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13110 if (params->feature_config_flags &
13111 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
13112 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13114 if (!(params->feature_config_flags &
13115 ELINK_FEATURE_CONFIG_MT_SUPPORT))
13116 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13118 sync_offset = params->shmem_base +
13119 offsetof(struct shmem_region,
13120 dev_info.port_hw_config[params->port].media_type);
13121 media_types = REG_RD(sc, sync_offset);
13123 /* Update media type for non-PMF sync only for the first time
13124 * In case the media type changes afterwards, it will be updated
13125 * using the update_status function
13127 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
13128 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13129 actual_phy_idx))) == 0) {
13130 media_types |= ((phy->media_type &
13131 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
13132 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13135 REG_WR(sc, sync_offset, media_types);
13137 elink_phy_def_cfg(params, phy, phy_index);
13138 params->num_phys++;
13141 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13142 return ELINK_STATUS_OK;
13145 #ifdef ELINK_INCLUDE_EMUL
13146 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
13147 struct elink_vars *vars)
13149 struct bxe_softc *sc = params->sc;
13150 vars->line_speed = params->req_line_speed[0];
13151 /* In case link speed is auto, set speed the highest as possible */
13152 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
13153 if (params->feature_config_flags &
13154 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
13155 vars->line_speed = ELINK_SPEED_2500;
13156 else if (elink_is_4_port_mode(sc))
13157 vars->line_speed = ELINK_SPEED_10000;
13159 vars->line_speed = ELINK_SPEED_20000;
13161 if (vars->line_speed < ELINK_SPEED_10000) {
13162 if ((params->feature_config_flags &
13163 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
13164 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
13165 " disabled!\n", params->req_line_speed[0]);
13166 return ELINK_STATUS_ERROR;
13168 switch (vars->line_speed) {
13169 case ELINK_SPEED_10:
13170 vars->link_status = ELINK_LINK_10TFD;
13172 case ELINK_SPEED_100:
13173 vars->link_status = ELINK_LINK_100TXFD;
13175 case ELINK_SPEED_1000:
13176 vars->link_status = ELINK_LINK_1000TFD;
13178 case ELINK_SPEED_2500:
13179 vars->link_status = ELINK_LINK_2500TFD;
13182 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n",
13184 return ELINK_STATUS_ERROR;
13186 vars->link_status |= LINK_STATUS_LINK_UP;
13188 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13189 elink_umac_enable(params, vars, 1);
13191 elink_umac_enable(params, vars, 0);
13193 /* Link speed >= 10000 requires XMAC enabled */
13194 if (params->feature_config_flags &
13195 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
13196 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
13197 " disabled!\n", params->req_line_speed[0]);
13198 return ELINK_STATUS_ERROR;
13200 /* Check link speed */
13201 switch (vars->line_speed) {
13202 case ELINK_SPEED_10000:
13203 vars->link_status = ELINK_LINK_10GTFD;
13205 case ELINK_SPEED_20000:
13206 vars->link_status = ELINK_LINK_20GTFD;
13209 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n",
13211 return ELINK_STATUS_ERROR;
13213 vars->link_status |= LINK_STATUS_LINK_UP;
13214 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
13215 elink_xmac_enable(params, vars, 1);
13217 elink_xmac_enable(params, vars, 0);
13219 return ELINK_STATUS_OK;
13222 static elink_status_t elink_init_emul(struct elink_params *params,
13223 struct elink_vars *vars)
13225 struct bxe_softc *sc = params->sc;
13226 if (CHIP_IS_E3(sc)) {
13227 if (elink_init_e3_emul_mac(params, vars) !=
13229 return ELINK_STATUS_ERROR;
13231 if (params->feature_config_flags &
13232 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
13233 vars->line_speed = ELINK_SPEED_1000;
13234 vars->link_status = (LINK_STATUS_LINK_UP |
13235 ELINK_LINK_1000XFD);
13236 if (params->loopback_mode ==
13237 ELINK_LOOPBACK_EMAC)
13238 elink_emac_enable(params, vars, 1);
13240 elink_emac_enable(params, vars, 0);
13242 vars->line_speed = ELINK_SPEED_10000;
13243 vars->link_status = (LINK_STATUS_LINK_UP |
13244 ELINK_LINK_10GTFD);
13245 if (params->loopback_mode ==
13246 ELINK_LOOPBACK_BMAC)
13247 elink_bmac_enable(params, vars, 1, 1);
13249 elink_bmac_enable(params, vars, 0, 1);
13253 vars->duplex = DUPLEX_FULL;
13254 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13256 if (CHIP_IS_E1x(sc))
13257 elink_pbf_update(params, vars->flow_ctrl,
13259 /* Disable drain */
13260 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13262 /* update shared memory */
13263 elink_update_mng(params, vars->link_status);
13264 return ELINK_STATUS_OK;
13267 #ifdef ELINK_INCLUDE_FPGA
13268 static elink_status_t elink_init_fpga(struct elink_params *params,
13269 struct elink_vars *vars)
13271 /* Enable on E1.5 FPGA */
13272 struct bxe_softc *sc = params->sc;
13273 vars->duplex = DUPLEX_FULL;
13274 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13275 if (!(CHIP_IS_E1(sc))) {
13276 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
13277 ELINK_FLOW_CTRL_RX);
13278 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
13279 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
13281 if (CHIP_IS_E3(sc)) {
13282 vars->line_speed = params->req_line_speed[0];
13283 switch (vars->line_speed) {
13284 case ELINK_SPEED_AUTO_NEG:
13285 vars->line_speed = ELINK_SPEED_2500;
13286 case ELINK_SPEED_2500:
13287 vars->link_status = ELINK_LINK_2500TFD;
13289 case ELINK_SPEED_1000:
13290 vars->link_status = ELINK_LINK_1000XFD;
13292 case ELINK_SPEED_100:
13293 vars->link_status = ELINK_LINK_100TXFD;
13295 case ELINK_SPEED_10:
13296 vars->link_status = ELINK_LINK_10TFD;
13299 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n",
13300 params->req_line_speed[0]);
13301 return ELINK_STATUS_ERROR;
13303 vars->link_status |= LINK_STATUS_LINK_UP;
13304 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13305 elink_umac_enable(params, vars, 1);
13307 elink_umac_enable(params, vars, 0);
13309 vars->line_speed = ELINK_SPEED_10000;
13310 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
13311 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
13312 elink_emac_enable(params, vars, 1);
13314 elink_emac_enable(params, vars, 0);
13318 if (CHIP_IS_E1x(sc))
13319 elink_pbf_update(params, vars->flow_ctrl,
13321 /* Disable drain */
13322 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13324 /* Update shared memory */
13325 elink_update_mng(params, vars->link_status);
13326 return ELINK_STATUS_OK;
13329 static void elink_init_bmac_loopback(struct elink_params *params,
13330 struct elink_vars *vars)
13332 struct bxe_softc *sc = params->sc;
13334 vars->line_speed = ELINK_SPEED_10000;
13335 vars->duplex = DUPLEX_FULL;
13336 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13337 vars->mac_type = ELINK_MAC_TYPE_BMAC;
13339 vars->phy_flags = PHY_XGXS_FLAG;
13341 elink_xgxs_deassert(params);
13343 /* Set bmac loopback */
13344 elink_bmac_enable(params, vars, 1, 1);
13346 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13349 static void elink_init_emac_loopback(struct elink_params *params,
13350 struct elink_vars *vars)
13352 struct bxe_softc *sc = params->sc;
13354 vars->line_speed = ELINK_SPEED_1000;
13355 vars->duplex = DUPLEX_FULL;
13356 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13357 vars->mac_type = ELINK_MAC_TYPE_EMAC;
13359 vars->phy_flags = PHY_XGXS_FLAG;
13361 elink_xgxs_deassert(params);
13362 /* Set bmac loopback */
13363 elink_emac_enable(params, vars, 1);
13364 elink_emac_program(params, vars);
13365 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13368 static void elink_init_xmac_loopback(struct elink_params *params,
13369 struct elink_vars *vars)
13371 struct bxe_softc *sc = params->sc;
13373 if (!params->req_line_speed[0])
13374 vars->line_speed = ELINK_SPEED_10000;
13376 vars->line_speed = params->req_line_speed[0];
13377 vars->duplex = DUPLEX_FULL;
13378 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13379 vars->mac_type = ELINK_MAC_TYPE_XMAC;
13380 vars->phy_flags = PHY_XGXS_FLAG;
13381 /* Set WC to loopback mode since link is required to provide clock
13382 * to the XMAC in 20G mode
13384 elink_set_aer_mmd(params, ¶ms->phy[0]);
13385 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13386 params->phy[ELINK_INT_PHY].config_loopback(
13387 ¶ms->phy[ELINK_INT_PHY],
13390 elink_xmac_enable(params, vars, 1);
13391 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13394 static void elink_init_umac_loopback(struct elink_params *params,
13395 struct elink_vars *vars)
13397 struct bxe_softc *sc = params->sc;
13399 vars->line_speed = ELINK_SPEED_1000;
13400 vars->duplex = DUPLEX_FULL;
13401 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13402 vars->mac_type = ELINK_MAC_TYPE_UMAC;
13403 vars->phy_flags = PHY_XGXS_FLAG;
13404 elink_umac_enable(params, vars, 1);
13406 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13409 static void elink_init_xgxs_loopback(struct elink_params *params,
13410 struct elink_vars *vars)
13412 struct bxe_softc *sc = params->sc;
13413 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13415 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13416 vars->duplex = DUPLEX_FULL;
13417 if (params->req_line_speed[0] == ELINK_SPEED_1000)
13418 vars->line_speed = ELINK_SPEED_1000;
13419 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
13420 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
13421 vars->line_speed = ELINK_SPEED_20000;
13423 vars->line_speed = ELINK_SPEED_10000;
13425 if (!USES_WARPCORE(sc))
13426 elink_xgxs_deassert(params);
13427 elink_link_initialize(params, vars);
13429 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
13430 if (USES_WARPCORE(sc))
13431 elink_umac_enable(params, vars, 0);
13433 elink_emac_program(params, vars);
13434 elink_emac_enable(params, vars, 0);
13437 if (USES_WARPCORE(sc))
13438 elink_xmac_enable(params, vars, 0);
13440 elink_bmac_enable(params, vars, 0, 1);
13443 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
13444 /* Set 10G XGXS loopback */
13445 int_phy->config_loopback(int_phy, params);
13447 /* Set external phy loopback */
13449 for (phy_index = ELINK_EXT_PHY1;
13450 phy_index < params->num_phys; phy_index++)
13451 if (params->phy[phy_index].config_loopback)
13452 params->phy[phy_index].config_loopback(
13453 ¶ms->phy[phy_index],
13456 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13458 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
13461 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
13463 struct bxe_softc *sc = params->sc;
13464 uint8_t val = en * 0x1F;
13466 /* Open / close the gate between the NIG and the BRB */
13467 if (!CHIP_IS_E1x(sc))
13469 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13471 if (!CHIP_IS_E1(sc)) {
13472 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13476 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13477 NIG_REG_LLH0_BRB1_NOT_MCP), en);
13479 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
13480 struct elink_vars *vars)
13483 uint32_t dont_clear_stat, lfa_sts;
13484 struct bxe_softc *sc = params->sc;
13486 /* Sync the link parameters */
13487 elink_link_status_update(params, vars);
13490 * The module verification was already done by previous link owner,
13491 * so this call is meant only to get warning message
13494 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
13495 struct elink_phy *phy = ¶ms->phy[phy_idx];
13496 if (phy->phy_specific_func) {
13497 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n");
13498 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13500 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13501 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13502 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13503 elink_verify_sfp_module(phy, params);
13505 lfa_sts = REG_RD(sc, params->lfa_base +
13506 offsetof(struct shmem_lfa,
13509 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
13511 /* Re-enable the NIG/MAC */
13512 if (CHIP_IS_E3(sc)) {
13513 if (!dont_clear_stat) {
13514 REG_WR(sc, GRCBASE_MISC +
13515 MISC_REGISTERS_RESET_REG_2_CLEAR,
13516 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13518 REG_WR(sc, GRCBASE_MISC +
13519 MISC_REGISTERS_RESET_REG_2_SET,
13520 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13523 if (vars->line_speed < ELINK_SPEED_10000)
13524 elink_umac_enable(params, vars, 0);
13526 elink_xmac_enable(params, vars, 0);
13528 if (vars->line_speed < ELINK_SPEED_10000)
13529 elink_emac_enable(params, vars, 0);
13531 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
13534 /* Increment LFA count */
13535 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
13536 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
13537 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
13538 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
13539 /* Clear link flap reason */
13540 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13542 REG_WR(sc, params->lfa_base +
13543 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13545 /* Disable NIG DRAIN */
13546 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13548 /* Enable interrupts */
13549 elink_link_int_enable(params);
13550 return ELINK_STATUS_OK;
13553 static void elink_cannot_avoid_link_flap(struct elink_params *params,
13554 struct elink_vars *vars,
13557 uint32_t lfa_sts, cfg_idx, tmp_val;
13558 struct bxe_softc *sc = params->sc;
13560 elink_link_reset(params, vars, 1);
13562 if (!params->lfa_base)
13564 /* Store the new link parameters */
13565 REG_WR(sc, params->lfa_base +
13566 offsetof(struct shmem_lfa, req_duplex),
13567 params->req_duplex[0] | (params->req_duplex[1] << 16));
13569 REG_WR(sc, params->lfa_base +
13570 offsetof(struct shmem_lfa, req_flow_ctrl),
13571 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
13573 REG_WR(sc, params->lfa_base +
13574 offsetof(struct shmem_lfa, req_line_speed),
13575 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
13577 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
13578 REG_WR(sc, params->lfa_base +
13579 offsetof(struct shmem_lfa,
13580 speed_cap_mask[cfg_idx]),
13581 params->speed_cap_mask[cfg_idx]);
13584 tmp_val = REG_RD(sc, params->lfa_base +
13585 offsetof(struct shmem_lfa, additional_config));
13586 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13587 tmp_val |= params->req_fc_auto_adv;
13589 REG_WR(sc, params->lfa_base +
13590 offsetof(struct shmem_lfa, additional_config), tmp_val);
13592 lfa_sts = REG_RD(sc, params->lfa_base +
13593 offsetof(struct shmem_lfa, lfa_sts));
13595 /* Clear the "Don't Clear Statistics" bit, and set reason */
13596 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13598 /* Set link flap reason */
13599 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13600 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13601 LFA_LINK_FLAP_REASON_OFFSET);
13603 /* Increment link flap counter */
13604 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13605 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13606 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13607 << LINK_FLAP_COUNT_OFFSET));
13608 REG_WR(sc, params->lfa_base +
13609 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13610 /* Proceed with regular link initialization */
13613 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
13616 struct bxe_softc *sc = params->sc;
13617 ELINK_DEBUG_P0(sc, "Phy Initialization started\n");
13618 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n",
13619 params->req_line_speed[0], params->req_flow_ctrl[0]);
13620 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n",
13621 params->req_line_speed[1], params->req_flow_ctrl[1]);
13622 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13623 vars->link_status = 0;
13624 vars->phy_link_up = 0;
13626 vars->line_speed = 0;
13627 vars->duplex = DUPLEX_FULL;
13628 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13629 vars->mac_type = ELINK_MAC_TYPE_NONE;
13630 vars->phy_flags = 0;
13631 vars->check_kr2_recovery_cnt = 0;
13632 params->link_flags = ELINK_PHY_INITIALIZED;
13633 /* Driver opens NIG-BRB filters */
13634 elink_set_rx_filter(params, 1);
13635 /* Check if link flap can be avoided */
13636 lfa_status = elink_check_lfa(params);
13638 if (lfa_status == 0) {
13639 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n");
13640 return elink_avoid_link_flap(params, vars);
13643 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",
13645 elink_cannot_avoid_link_flap(params, vars, lfa_status);
13647 /* Disable attentions */
13648 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13649 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13650 ELINK_NIG_MASK_XGXS0_LINK10G |
13651 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13652 ELINK_NIG_MASK_MI_INT));
13653 #ifdef ELINK_INCLUDE_EMUL
13654 if (!(params->feature_config_flags &
13655 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
13658 elink_emac_init(params, vars);
13660 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
13661 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13663 if ((params->num_phys == 0) &&
13664 !CHIP_REV_IS_SLOW(sc)) {
13665 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
13666 return ELINK_STATUS_ERROR;
13668 set_phy_vars(params, vars);
13670 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys);
13671 #ifdef ELINK_INCLUDE_FPGA
13672 if (CHIP_REV_IS_FPGA(sc)) {
13673 return elink_init_fpga(params, vars);
13676 #ifdef ELINK_INCLUDE_EMUL
13677 if (CHIP_REV_IS_EMUL(sc)) {
13678 return elink_init_emul(params, vars);
13681 switch (params->loopback_mode) {
13682 case ELINK_LOOPBACK_BMAC:
13683 elink_init_bmac_loopback(params, vars);
13685 case ELINK_LOOPBACK_EMAC:
13686 elink_init_emac_loopback(params, vars);
13688 case ELINK_LOOPBACK_XMAC:
13689 elink_init_xmac_loopback(params, vars);
13691 case ELINK_LOOPBACK_UMAC:
13692 elink_init_umac_loopback(params, vars);
13694 case ELINK_LOOPBACK_XGXS:
13695 case ELINK_LOOPBACK_EXT_PHY:
13696 elink_init_xgxs_loopback(params, vars);
13699 if (!CHIP_IS_E3(sc)) {
13700 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
13701 elink_xgxs_deassert(params);
13703 elink_serdes_deassert(sc, params->port);
13705 elink_link_initialize(params, vars);
13707 elink_link_int_enable(params);
13710 elink_update_mng(params, vars->link_status);
13712 elink_update_mng_eee(params, vars->eee_status);
13713 return ELINK_STATUS_OK;
13716 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
13717 uint8_t reset_ext_phy)
13719 struct bxe_softc *sc = params->sc;
13720 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
13721 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
13722 /* Disable attentions */
13723 vars->link_status = 0;
13724 elink_update_mng(params, vars->link_status);
13725 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
13726 SHMEM_EEE_ACTIVE_BIT);
13727 elink_update_mng_eee(params, vars->eee_status);
13728 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
13729 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13730 ELINK_NIG_MASK_XGXS0_LINK10G |
13731 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13732 ELINK_NIG_MASK_MI_INT));
13734 /* Activate nig drain */
13735 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
13737 /* Disable nig egress interface */
13738 if (!CHIP_IS_E3(sc)) {
13739 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
13740 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
13743 #ifdef ELINK_INCLUDE_EMUL
13744 /* Stop BigMac rx */
13745 if (!(params->feature_config_flags &
13746 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
13748 if (!CHIP_IS_E3(sc))
13749 elink_set_bmac_rx(sc, params->chip_id, port, 0);
13750 #ifdef ELINK_INCLUDE_EMUL
13751 /* Stop XMAC/UMAC rx */
13752 if (!(params->feature_config_flags &
13753 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
13755 if (CHIP_IS_E3(sc) &&
13756 !CHIP_REV_IS_FPGA(sc)) {
13757 elink_set_xmac_rxtx(params, 0);
13758 elink_set_umac_rxtx(params, 0);
13761 if (!CHIP_IS_E3(sc))
13762 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
13765 /* The PHY reset is controlled by GPIO 1
13766 * Hold it as vars low
13768 /* Clear link led */
13769 elink_set_mdio_emac_per_phy(sc, params);
13770 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
13772 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
13773 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
13775 if (params->phy[phy_index].link_reset) {
13776 elink_set_aer_mmd(params,
13777 ¶ms->phy[phy_index]);
13778 params->phy[phy_index].link_reset(
13779 ¶ms->phy[phy_index],
13782 if (params->phy[phy_index].flags &
13783 ELINK_FLAGS_REARM_LATCH_SIGNAL)
13784 clear_latch_ind = 1;
13788 if (clear_latch_ind) {
13789 /* Clear latching indication */
13790 elink_rearm_latch_signal(sc, port, 0);
13791 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
13792 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
13794 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
13795 if (!CHIP_REV_IS_SLOW(sc))
13797 if (params->phy[ELINK_INT_PHY].link_reset)
13798 params->phy[ELINK_INT_PHY].link_reset(
13799 ¶ms->phy[ELINK_INT_PHY], params);
13801 /* Disable nig ingress interface */
13802 if (!CHIP_IS_E3(sc)) {
13804 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
13805 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
13806 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
13807 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
13809 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
13810 elink_set_xumac_nig(params, 0, 0);
13811 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
13812 MISC_REGISTERS_RESET_REG_2_XMAC)
13813 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
13814 XMAC_CTRL_REG_SOFT_RESET);
13817 vars->phy_flags = 0;
13818 return ELINK_STATUS_OK;
13820 elink_status_t elink_lfa_reset(struct elink_params *params,
13821 struct elink_vars *vars)
13823 struct bxe_softc *sc = params->sc;
13825 vars->phy_flags = 0;
13826 params->link_flags &= ~ELINK_PHY_INITIALIZED;
13827 if (!params->lfa_base)
13828 return elink_link_reset(params, vars, 1);
13830 * Activate NIG drain so that during this time the device won't send
13831 * anything while it is unable to response.
13833 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
13836 * Close gracefully the gate from BMAC to NIG such that no half packets
13839 if (!CHIP_IS_E3(sc))
13840 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
13842 if (CHIP_IS_E3(sc)) {
13843 elink_set_xmac_rxtx(params, 0);
13844 elink_set_umac_rxtx(params, 0);
13846 /* Wait 10ms for the pipe to clean up*/
13849 /* Clean the NIG-BRB using the network filters in a way that will
13850 * not cut a packet in the middle.
13852 elink_set_rx_filter(params, 0);
13855 * Re-open the gate between the BMAC and the NIG, after verifying the
13856 * gate to the BRB is closed, otherwise packets may arrive to the
13857 * firmware before driver had initialized it. The target is to achieve
13858 * minimum management protocol down time.
13860 if (!CHIP_IS_E3(sc))
13861 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
13863 if (CHIP_IS_E3(sc)) {
13864 elink_set_xmac_rxtx(params, 1);
13865 elink_set_umac_rxtx(params, 1);
13867 /* Disable NIG drain */
13868 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13869 return ELINK_STATUS_OK;
13872 /****************************************************************************/
13873 /* Common function */
13874 /****************************************************************************/
13875 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc,
13876 uint32_t shmem_base_path[],
13877 uint32_t shmem2_base_path[], uint8_t phy_index,
13880 struct elink_phy phy[PORT_MAX];
13881 struct elink_phy *phy_blk[PORT_MAX];
13884 int8_t port_of_path = 0;
13885 uint32_t swap_val, swap_override;
13886 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
13887 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
13888 port ^= (swap_val && swap_override);
13889 elink_ext_phy_hw_reset(sc, port);
13890 /* PART1 - Reset both phys */
13891 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13892 uint32_t shmem_base, shmem2_base;
13893 /* In E2, same phy is using for port0 of the two paths */
13894 if (CHIP_IS_E1x(sc)) {
13895 shmem_base = shmem_base_path[0];
13896 shmem2_base = shmem2_base_path[0];
13897 port_of_path = port;
13899 shmem_base = shmem_base_path[port];
13900 shmem2_base = shmem2_base_path[port];
13904 /* Extract the ext phy address for the port */
13905 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
13906 port_of_path, &phy[port]) !=
13908 ELINK_DEBUG_P0(sc, "populate_phy failed\n");
13909 return ELINK_STATUS_ERROR;
13911 /* Disable attentions */
13912 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
13914 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13915 ELINK_NIG_MASK_XGXS0_LINK10G |
13916 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13917 ELINK_NIG_MASK_MI_INT));
13919 /* Need to take the phy out of low power mode in order
13920 * to write to access its registers
13922 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
13923 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
13926 /* Reset the phy */
13927 elink_cl45_write(sc, &phy[port],
13933 /* Add delay of 150ms after reset */
13936 if (phy[PORT_0].addr & 0x1) {
13937 phy_blk[PORT_0] = &(phy[PORT_1]);
13938 phy_blk[PORT_1] = &(phy[PORT_0]);
13940 phy_blk[PORT_0] = &(phy[PORT_0]);
13941 phy_blk[PORT_1] = &(phy[PORT_1]);
13944 /* PART2 - Download firmware to both phys */
13945 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13946 if (CHIP_IS_E1x(sc))
13947 port_of_path = port;
13951 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
13952 phy_blk[port]->addr);
13953 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
13955 return ELINK_STATUS_ERROR;
13957 /* Only set bit 10 = 1 (Tx power down) */
13958 elink_cl45_read(sc, phy_blk[port],
13960 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13962 /* Phase1 of TX_POWER_DOWN reset */
13963 elink_cl45_write(sc, phy_blk[port],
13965 MDIO_PMA_REG_TX_POWER_DOWN,
13969 /* Toggle Transmitter: Power down and then up with 600ms delay
13974 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
13975 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
13976 /* Phase2 of POWER_DOWN_RESET */
13977 /* Release bit 10 (Release Tx power down) */
13978 elink_cl45_read(sc, phy_blk[port],
13980 MDIO_PMA_REG_TX_POWER_DOWN, &val);
13982 elink_cl45_write(sc, phy_blk[port],
13984 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
13987 /* Read modify write the SPI-ROM version select register */
13988 elink_cl45_read(sc, phy_blk[port],
13990 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
13991 elink_cl45_write(sc, phy_blk[port],
13993 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
13995 /* set GPIO2 back to LOW */
13996 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
13997 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
13999 return ELINK_STATUS_OK;
14001 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc,
14002 uint32_t shmem_base_path[],
14003 uint32_t shmem2_base_path[], uint8_t phy_index,
14008 struct elink_phy phy;
14009 /* Use port1 because of the static port-swap */
14010 /* Enable the module detection interrupt */
14011 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14012 val |= ((1<<MISC_REGISTERS_GPIO_3)|
14013 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
14014 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14016 elink_ext_phy_hw_reset(sc, 0);
14018 for (port = 0; port < PORT_MAX; port++) {
14019 uint32_t shmem_base, shmem2_base;
14021 /* In E2, same phy is using for port0 of the two paths */
14022 if (CHIP_IS_E1x(sc)) {
14023 shmem_base = shmem_base_path[0];
14024 shmem2_base = shmem2_base_path[0];
14026 shmem_base = shmem_base_path[port];
14027 shmem2_base = shmem2_base_path[port];
14029 /* Extract the ext phy address for the port */
14030 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14033 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14034 return ELINK_STATUS_ERROR;
14038 elink_cl45_write(sc, &phy,
14039 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
14042 /* Set fault module detected LED on */
14043 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
14044 MISC_REGISTERS_GPIO_HIGH,
14048 return ELINK_STATUS_OK;
14050 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base,
14051 uint8_t *io_gpio, uint8_t *io_port)
14054 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14055 offsetof(struct shmem_region,
14056 dev_info.port_hw_config[PORT_0].default_cfg));
14057 switch (phy_gpio_reset) {
14058 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
14062 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
14066 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
14070 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
14074 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
14078 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
14082 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
14086 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
14091 /* Don't override the io_gpio and io_port */
14096 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc,
14097 uint32_t shmem_base_path[],
14098 uint32_t shmem2_base_path[], uint8_t phy_index,
14101 int8_t port, reset_gpio;
14102 uint32_t swap_val, swap_override;
14103 struct elink_phy phy[PORT_MAX];
14104 struct elink_phy *phy_blk[PORT_MAX];
14105 int8_t port_of_path;
14106 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14107 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14109 reset_gpio = MISC_REGISTERS_GPIO_1;
14112 /* Retrieve the reset gpio/port which control the reset.
14113 * Default is GPIO1, PORT1
14115 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
14116 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14118 /* Calculate the port based on port swap */
14119 port ^= (swap_val && swap_override);
14121 /* Initiate PHY reset*/
14122 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14125 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14130 /* PART1 - Reset both phys */
14131 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14132 uint32_t shmem_base, shmem2_base;
14134 /* In E2, same phy is using for port0 of the two paths */
14135 if (CHIP_IS_E1x(sc)) {
14136 shmem_base = shmem_base_path[0];
14137 shmem2_base = shmem2_base_path[0];
14138 port_of_path = port;
14140 shmem_base = shmem_base_path[port];
14141 shmem2_base = shmem2_base_path[port];
14145 /* Extract the ext phy address for the port */
14146 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14147 port_of_path, &phy[port]) !=
14149 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14150 return ELINK_STATUS_ERROR;
14152 /* disable attentions */
14153 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14155 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14156 ELINK_NIG_MASK_XGXS0_LINK10G |
14157 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14158 ELINK_NIG_MASK_MI_INT));
14161 /* Reset the phy */
14162 elink_cl45_write(sc, &phy[port],
14163 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
14166 /* Add delay of 150ms after reset */
14168 if (phy[PORT_0].addr & 0x1) {
14169 phy_blk[PORT_0] = &(phy[PORT_1]);
14170 phy_blk[PORT_1] = &(phy[PORT_0]);
14172 phy_blk[PORT_0] = &(phy[PORT_0]);
14173 phy_blk[PORT_1] = &(phy[PORT_1]);
14175 /* PART2 - Download firmware to both phys */
14176 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14177 if (CHIP_IS_E1x(sc))
14178 port_of_path = port;
14181 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14182 phy_blk[port]->addr);
14183 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14185 return ELINK_STATUS_ERROR;
14186 /* Disable PHY transmitter output */
14187 elink_cl45_write(sc, phy_blk[port],
14189 MDIO_PMA_REG_TX_DISABLE, 1);
14192 return ELINK_STATUS_OK;
14195 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc,
14196 uint32_t shmem_base_path[],
14197 uint32_t shmem2_base_path[],
14201 uint8_t reset_gpios;
14202 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
14203 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14205 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14206 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",
14208 return ELINK_STATUS_OK;
14210 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[],
14211 uint32_t shmem2_base_path[], uint8_t phy_index,
14212 uint32_t ext_phy_type, uint32_t chip_id)
14214 elink_status_t rc = ELINK_STATUS_OK;
14216 switch (ext_phy_type) {
14217 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
14218 rc = elink_8073_common_init_phy(sc, shmem_base_path,
14220 phy_index, chip_id);
14222 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
14223 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
14224 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
14225 rc = elink_8727_common_init_phy(sc, shmem_base_path,
14227 phy_index, chip_id);
14230 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
14231 /* GPIO1 affects both ports, so there's need to pull
14232 * it for single port alone
14234 rc = elink_8726_common_init_phy(sc, shmem_base_path,
14236 phy_index, chip_id);
14238 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
14239 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
14240 /* GPIO3's are linked, and so both need to be toggled
14241 * to obtain required 2us pulse.
14243 rc = elink_84833_common_init_phy(sc, shmem_base_path,
14245 phy_index, chip_id);
14247 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
14248 rc = ELINK_STATUS_ERROR;
14252 "ext_phy 0x%x common init not required\n",
14257 if (rc != ELINK_STATUS_OK)
14258 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14264 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
14265 uint32_t shmem2_base_path[], uint32_t chip_id,
14266 uint8_t one_port_enabled)
14268 elink_status_t rc = ELINK_STATUS_OK;
14269 uint32_t phy_ver, val;
14270 uint8_t phy_index = 0;
14271 uint32_t ext_phy_type, ext_phy_config;
14272 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14273 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
14274 return ELINK_STATUS_OK;
14277 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
14278 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
14279 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14280 if (CHIP_IS_E3(sc)) {
14282 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14283 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14285 /* Check if common init was already done */
14286 phy_ver = REG_RD(sc, shmem_base_path[0] +
14287 offsetof(struct shmem_region,
14288 port_mb[PORT_0].ext_phy_fw_version));
14290 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14292 return ELINK_STATUS_OK;
14295 /* Read the ext_phy_type for arbitrary port(0) */
14296 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14298 ext_phy_config = elink_get_ext_phy_config(sc,
14299 shmem_base_path[0],
14301 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
14302 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
14304 phy_index, ext_phy_type,
14310 static void elink_check_over_curr(struct elink_params *params,
14311 struct elink_vars *vars)
14313 struct bxe_softc *sc = params->sc;
14315 uint8_t port = params->port;
14318 cfg_pin = (REG_RD(sc, params->shmem_base +
14319 offsetof(struct shmem_region,
14320 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14321 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
14322 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
14324 /* Ignore check if no external input PIN available */
14325 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14329 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
14330 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14331 // " been detected and the power to "
14332 // "that SFP+ module has been removed"
14333 // " to prevent failure of the card."
14334 // " Please remove the SFP+ module and"
14335 // " restart the system to clear this"
14337 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
14338 elink_warpcore_power_module(params, 0);
14341 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
14344 /* Returns 0 if no change occured since last check; 1 otherwise. */
14345 static uint8_t elink_analyze_link_error(struct elink_params *params,
14346 struct elink_vars *vars, uint32_t status,
14347 uint32_t phy_flag, uint32_t link_flag, uint8_t notify)
14349 struct bxe_softc *sc = params->sc;
14350 /* Compare new value with previous value */
14352 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
14354 if ((status ^ old_status) == 0)
14357 /* If values differ */
14358 switch (phy_flag) {
14359 case PHY_HALF_OPEN_CONN_FLAG:
14360 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n");
14362 case PHY_SFP_TX_FAULT_FLAG:
14363 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14366 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14368 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14369 old_status, status);
14371 /* Do not touch the link in case physical link down */
14372 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
14375 /* a. Update shmem->link_status accordingly
14376 * b. Update elink_vars->link_up
14379 vars->link_status &= ~LINK_STATUS_LINK_UP;
14380 vars->link_status |= link_flag;
14382 vars->phy_flags |= phy_flag;
14384 /* activate nig drain */
14385 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14386 /* Set LED mode to off since the PHY doesn't know about these
14389 led_mode = ELINK_LED_MODE_OFF;
14391 vars->link_status |= LINK_STATUS_LINK_UP;
14392 vars->link_status &= ~link_flag;
14394 vars->phy_flags &= ~phy_flag;
14395 led_mode = ELINK_LED_MODE_OPER;
14397 /* Clear nig drain */
14398 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14400 elink_sync_link(params, vars);
14401 /* Update the LED according to the link state */
14402 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
14404 /* Update link status in the shared memory */
14405 elink_update_mng(params, vars->link_status);
14407 /* C. Trigger General Attention */
14408 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
14410 elink_cb_notify_link_changed(sc);
14415 /******************************************************************************
14417 * This function checks for half opened connection change indication.
14418 * When such change occurs, it calls the elink_analyze_link_error
14419 * to check if Remote Fault is set or cleared. Reception of remote fault
14420 * status message in the MAC indicates that the peer's MAC has detected
14421 * a fault, for example, due to break in the TX side of fiber.
14423 ******************************************************************************/
14424 elink_status_t elink_check_half_open_conn(struct elink_params *params,
14425 struct elink_vars *vars,
14428 struct bxe_softc *sc = params->sc;
14429 uint32_t lss_status = 0;
14431 /* In case link status is physically up @ 10G do */
14432 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
14433 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14434 return ELINK_STATUS_OK;
14436 if (CHIP_IS_E3(sc) &&
14437 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14438 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
14439 /* Check E3 XMAC */
14440 /* Note that link speed cannot be queried here, since it may be
14441 * zero while link is down. In case UMAC is active, LSS will
14442 * simply not be set
14444 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14446 /* Clear stick bits (Requires rising edge) */
14447 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14448 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
14449 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
14450 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
14451 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14454 elink_analyze_link_error(params, vars, lss_status,
14455 PHY_HALF_OPEN_CONN_FLAG,
14456 LINK_STATUS_NONE, notify);
14457 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14458 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14459 /* Check E1X / E2 BMAC */
14460 uint32_t lss_status_reg;
14461 uint32_t wb_data[2];
14462 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14463 NIG_REG_INGRESS_BMAC0_MEM;
14464 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
14465 if (CHIP_IS_E2(sc))
14466 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
14468 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
14470 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14471 lss_status = (wb_data[0] > 0);
14473 elink_analyze_link_error(params, vars, lss_status,
14474 PHY_HALF_OPEN_CONN_FLAG,
14475 LINK_STATUS_NONE, notify);
14477 return ELINK_STATUS_OK;
14479 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14480 struct elink_params *params,
14481 struct elink_vars *vars)
14483 struct bxe_softc *sc = params->sc;
14484 uint32_t cfg_pin, value = 0;
14485 uint8_t led_change, port = params->port;
14487 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
14488 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14489 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14490 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
14491 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
14493 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
14494 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);
14498 led_change = elink_analyze_link_error(params, vars, value,
14499 PHY_SFP_TX_FAULT_FLAG,
14500 LINK_STATUS_SFP_TX_FAULT, 1);
14503 /* Change TX_Fault led, set link status for further syncs */
14506 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
14507 led_mode = MISC_REGISTERS_GPIO_HIGH;
14508 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
14510 led_mode = MISC_REGISTERS_GPIO_LOW;
14511 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14514 /* If module is unapproved, led should be on regardless */
14515 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14516 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n",
14518 elink_set_e3_module_fault_led(params, led_mode);
14522 static void elink_kr2_recovery(struct elink_params *params,
14523 struct elink_vars *vars,
14524 struct elink_phy *phy)
14526 struct bxe_softc *sc = params->sc;
14527 ELINK_DEBUG_P0(sc, "KR2 recovery\n");
14528 elink_warpcore_enable_AN_KR2(phy, params, vars);
14529 elink_warpcore_restart_AN_KR(phy, params);
14532 static void elink_check_kr2_wa(struct elink_params *params,
14533 struct elink_vars *vars,
14534 struct elink_phy *phy)
14536 struct bxe_softc *sc = params->sc;
14537 uint16_t base_page, next_page, not_kr2_device, lane;
14540 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
14541 * Since some switches tend to reinit the AN process and clear the
14542 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
14543 * and recovered many times
14545 if (vars->check_kr2_recovery_cnt > 0) {
14546 vars->check_kr2_recovery_cnt--;
14550 sigdet = elink_warpcore_get_sigdet(phy, params);
14552 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14553 elink_kr2_recovery(params, vars, phy);
14554 ELINK_DEBUG_P0(sc, "No sigdet\n");
14559 lane = elink_get_warpcore_lane(phy, params);
14560 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14561 MDIO_AER_BLOCK_AER_REG, lane);
14562 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14563 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
14564 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14565 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
14566 elink_set_aer_mmd(params, phy);
14568 /* CL73 has not begun yet */
14569 if (base_page == 0) {
14570 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14571 elink_kr2_recovery(params, vars, phy);
14572 ELINK_DEBUG_P0(sc, "No BP\n");
14577 /* In case NP bit is not set in the BasePage, or it is set,
14578 * but only KX is advertised, declare this link partner as non-KR2
14581 not_kr2_device = (((base_page & 0x8000) == 0) ||
14582 (((base_page & 0x8000) &&
14583 ((next_page & 0xe0) == 0x2))));
14585 /* In case KR2 is already disabled, check if we need to re-enable it */
14586 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14587 if (!not_kr2_device) {
14588 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,
14590 elink_kr2_recovery(params, vars, phy);
14594 /* KR2 is enabled, but not KR2 device */
14595 if (not_kr2_device) {
14596 /* Disable KR2 on both lanes */
14597 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);
14598 elink_disable_kr2(params, vars, phy);
14599 /* Restart AN on leading lane */
14600 elink_warpcore_restart_AN_KR(phy, params);
14605 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
14608 struct bxe_softc *sc = params->sc;
14609 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
14610 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14611 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14612 if (elink_check_half_open_conn(params, vars, 1) !=
14614 ELINK_DEBUG_P0(sc, "Fault detection failed\n");
14619 if (CHIP_IS_E3(sc)) {
14620 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14621 elink_set_aer_mmd(params, phy);
14622 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) &&
14623 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
14624 elink_check_kr2_wa(params, vars, phy);
14625 elink_check_over_curr(params, vars);
14626 if (vars->rx_tx_asic_rst)
14627 elink_warpcore_config_runtime(phy, params, vars);
14629 if ((REG_RD(sc, params->shmem_base +
14630 offsetof(struct shmem_region, dev_info.
14631 port_hw_config[params->port].default_cfg))
14632 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14633 PORT_HW_CFG_NET_SERDES_IF_SFI) {
14634 if (elink_is_sfp_module_plugged(phy, params)) {
14635 elink_sfp_tx_fault_detection(phy, params, vars);
14636 } else if (vars->link_status &
14637 LINK_STATUS_SFP_TX_FAULT) {
14638 /* Clean trail, interrupt corrects the leds */
14639 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14640 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
14641 /* Update link status in the shared memory */
14642 elink_update_mng(params, vars->link_status);
14648 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc,
14649 uint32_t shmem_base,
14650 uint32_t shmem2_base,
14653 uint8_t phy_index, fan_failure_det_req = 0;
14654 struct elink_phy phy;
14655 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14657 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14659 != ELINK_STATUS_OK) {
14660 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14663 fan_failure_det_req |= (phy.flags &
14664 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
14666 return fan_failure_det_req;
14669 void elink_hw_reset_phy(struct elink_params *params)
14672 struct bxe_softc *sc = params->sc;
14673 elink_update_mng(params, 0);
14674 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14675 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14676 ELINK_NIG_MASK_XGXS0_LINK10G |
14677 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14678 ELINK_NIG_MASK_MI_INT));
14680 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
14682 if (params->phy[phy_index].hw_reset) {
14683 params->phy[phy_index].hw_reset(
14684 ¶ms->phy[phy_index],
14686 params->phy[phy_index] = phy_null;
14691 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
14692 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
14695 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
14697 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
14698 if (CHIP_IS_E3(sc)) {
14699 if (elink_get_mod_abs_int_cfg(sc, chip_id,
14703 &gpio_port) != ELINK_STATUS_OK)
14706 struct elink_phy phy;
14707 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14709 if (elink_populate_phy(sc, phy_index, shmem_base,
14710 shmem2_base, port, &phy)
14711 != ELINK_STATUS_OK) {
14712 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14715 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
14716 gpio_num = MISC_REGISTERS_GPIO_3;
14723 if (gpio_num == 0xff)
14726 /* Set GPIO3 to trigger SFP+ module insertion/removal */
14727 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
14729 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14730 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14731 gpio_port ^= (swap_val && swap_override);
14733 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
14734 (gpio_num + (gpio_port << 2));
14736 sync_offset = shmem_base +
14737 offsetof(struct shmem_region,
14738 dev_info.port_hw_config[port].aeu_int_mask);
14739 REG_WR(sc, sync_offset, vars->aeu_int_mask);
14741 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
14742 gpio_num, gpio_port, vars->aeu_int_mask);
14745 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
14747 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
14749 /* Open appropriate AEU for interrupts */
14750 aeu_mask = REG_RD(sc, offset);
14751 aeu_mask |= vars->aeu_int_mask;
14752 REG_WR(sc, offset, aeu_mask);
14754 /* Enable the GPIO to trigger interrupt */
14755 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14756 val |= 1 << (gpio_num + (gpio_port << 2));
14757 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);