2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
47 /***********************************************************/
48 /* CLC Call backs functions */
49 /***********************************************************/
50 /* CLC device structure */
53 extern uint32_t elink_cb_reg_read(struct bxe_softc *sc, uint32_t reg_addr);
54 extern void elink_cb_reg_write(struct bxe_softc *sc, uint32_t reg_addr, uint32_t val);
55 /* wb_write - pointer to 2 32 bits vars to be passed to the DMAE*/
56 extern void elink_cb_reg_wb_write(struct bxe_softc *sc, uint32_t offset,
57 uint32_t *wb_write, uint16_t len);
58 extern void elink_cb_reg_wb_read(struct bxe_softc *sc, uint32_t offset,
59 uint32_t *wb_write, uint16_t len);
61 /* mode - 0( LOW ) /1(HIGH)*/
62 extern uint8_t elink_cb_gpio_write(struct bxe_softc *sc,
64 uint8_t mode, uint8_t port);
65 extern uint8_t elink_cb_gpio_mult_write(struct bxe_softc *sc,
69 extern uint32_t elink_cb_gpio_read(struct bxe_softc *sc, uint16_t gpio_num, uint8_t port);
70 extern uint8_t elink_cb_gpio_int_write(struct bxe_softc *sc,
72 uint8_t mode, uint8_t port);
74 extern uint32_t elink_cb_fw_command(struct bxe_softc *sc, uint32_t command, uint32_t param);
77 extern void elink_cb_udelay(struct bxe_softc *sc, uint32_t microsecond);
79 /* This function is called every 1024 bytes downloading of phy firmware.
80 Driver can use it to print to screen indication for download progress */
81 extern void elink_cb_download_progress(struct bxe_softc *sc, uint32_t cur, uint32_t total);
83 /* Each log type has its own parameters */
84 typedef enum elink_log_id {
85 ELINK_LOG_ID_UNQUAL_IO_MODULE = 0, /* uint8_t port, const char* vendor_name, const char* vendor_pn */
86 ELINK_LOG_ID_OVER_CURRENT = 1, /* uint8_t port */
87 ELINK_LOG_ID_PHY_UNINITIALIZED = 2, /* uint8_t port */
88 ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT= 3, /* No params */
89 ELINK_LOG_ID_NON_10G_MODULE = 4, /* uint8_t port */
92 typedef enum elink_status {
97 ELINK_STATUS_INVALID_IMAGE,
98 ELINK_OP_NOT_SUPPORTED = 122
100 extern void elink_cb_event_log(struct bxe_softc *sc, const elink_log_id_t log_id, ...);
101 extern void elink_cb_load_warpcore_microcode(void);
103 extern uint8_t elink_cb_path_id(struct bxe_softc *sc);
105 extern void elink_cb_notify_link_changed(struct bxe_softc *sc);
107 #define ELINK_EVENT_LOG_LEVEL_ERROR 1
108 #define ELINK_EVENT_LOG_LEVEL_WARNING 2
109 #define ELINK_EVENT_ID_SFP_UNQUALIFIED_MODULE 1
110 #define ELINK_EVENT_ID_SFP_POWER_FAULT 2
112 #define ARRAY_SIZE(x) (sizeof(x)/sizeof(x[0]))
116 extern void elink_cb_dbg(struct bxe_softc *sc, char *fmt);
117 extern void elink_cb_dbg1(struct bxe_softc *sc, char *fmt, uint32_t arg1);
118 extern void elink_cb_dbg2(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2);
119 extern void elink_cb_dbg3(struct bxe_softc *sc, char *fmt, uint32_t arg1, uint32_t arg2,
122 #define ELINK_DEBUG_P0(sc, fmt) elink_cb_dbg(sc, fmt)
123 #define ELINK_DEBUG_P1(sc, fmt, arg1) elink_cb_dbg1(sc, fmt, arg1)
124 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2) elink_cb_dbg2(sc, fmt, arg1, arg2)
125 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3) \
126 elink_cb_dbg3(sc, fmt, arg1, arg2, arg3)
128 #define ELINK_DEBUG_P0(sc, fmt)
129 #define ELINK_DEBUG_P1(sc, fmt, arg1)
130 #define ELINK_DEBUG_P2(sc, fmt, arg1, arg2)
131 #define ELINK_DEBUG_P3(sc, fmt, arg1, arg2, arg3)
134 /***********************************************************/
136 /***********************************************************/
137 #define ELINK_DEFAULT_PHY_DEV_ADDR 3
138 #define ELINK_E2_DEFAULT_PHY_DEV_ADDR 5
141 #define DUPLEX_FULL 1
142 #define DUPLEX_HALF 2
144 #define ELINK_FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
145 #define ELINK_FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
146 #define ELINK_FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
147 #define ELINK_FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
148 #define ELINK_FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
150 #define ELINK_NET_SERDES_IF_XFI 1
151 #define ELINK_NET_SERDES_IF_SFI 2
152 #define ELINK_NET_SERDES_IF_KR 3
153 #define ELINK_NET_SERDES_IF_DXGXS 4
155 #define ELINK_SPEED_AUTO_NEG 0
156 #define ELINK_SPEED_10 10
157 #define ELINK_SPEED_100 100
158 #define ELINK_SPEED_1000 1000
159 #define ELINK_SPEED_2500 2500
160 #define ELINK_SPEED_10000 10000
161 #define ELINK_SPEED_20000 20000
163 #define ELINK_I2C_DEV_ADDR_A0 0xa0
164 #define ELINK_I2C_DEV_ADDR_A2 0xa2
166 #define ELINK_SFP_EEPROM_PAGE_SIZE 16
167 #define ELINK_SFP_EEPROM_VENDOR_NAME_ADDR 0x14
168 #define ELINK_SFP_EEPROM_VENDOR_NAME_SIZE 16
169 #define ELINK_SFP_EEPROM_VENDOR_OUI_ADDR 0x25
170 #define ELINK_SFP_EEPROM_VENDOR_OUI_SIZE 3
171 #define ELINK_SFP_EEPROM_PART_NO_ADDR 0x28
172 #define ELINK_SFP_EEPROM_PART_NO_SIZE 16
173 #define ELINK_SFP_EEPROM_REVISION_ADDR 0x38
174 #define ELINK_SFP_EEPROM_REVISION_SIZE 4
175 #define ELINK_SFP_EEPROM_SERIAL_ADDR 0x44
176 #define ELINK_SFP_EEPROM_SERIAL_SIZE 16
177 #define ELINK_SFP_EEPROM_DATE_ADDR 0x54 /* ASCII YYMMDD */
178 #define ELINK_SFP_EEPROM_DATE_SIZE 6
179 #define ELINK_SFP_EEPROM_DIAG_TYPE_ADDR 0x5c
180 #define ELINK_SFP_EEPROM_DIAG_TYPE_SIZE 1
181 #define ELINK_SFP_EEPROM_DIAG_ADDR_CHANGE_REQ (1<<2)
182 #define ELINK_SFP_EEPROM_SFF_8472_COMP_ADDR 0x5e
183 #define ELINK_SFP_EEPROM_SFF_8472_COMP_SIZE 1
185 #define ELINK_SFP_EEPROM_A2_CHECKSUM_RANGE 0x5e
186 #define ELINK_SFP_EEPROM_A2_CC_DMI_ADDR 0x5f
188 #define ELINK_PWR_FLT_ERR_MSG_LEN 250
190 #define ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config) \
191 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
192 #define ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config) \
193 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
194 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
195 #define ELINK_SERDES_EXT_PHY_TYPE(ext_phy_config) \
196 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
198 /* Single Media Direct board is the plain 577xx board with CX4/RJ45 jacks */
199 #define ELINK_SINGLE_MEDIA_DIRECT(params) (params->num_phys == 1)
200 /* Single Media board contains single external phy */
201 #define ELINK_SINGLE_MEDIA(params) (params->num_phys == 2)
202 /* Dual Media board contains two external phy with different media */
203 #define ELINK_DUAL_MEDIA(params) (params->num_phys == 3)
205 #define ELINK_FW_PARAM_PHY_ADDR_MASK 0x000000FF
206 #define ELINK_FW_PARAM_PHY_TYPE_MASK 0x0000FF00
207 #define ELINK_FW_PARAM_MDIO_CTRL_MASK 0xFFFF0000
208 #define ELINK_FW_PARAM_MDIO_CTRL_OFFSET 16
209 #define ELINK_FW_PARAM_PHY_ADDR(fw_param) (fw_param & \
210 ELINK_FW_PARAM_PHY_ADDR_MASK)
211 #define ELINK_FW_PARAM_PHY_TYPE(fw_param) (fw_param & \
212 ELINK_FW_PARAM_PHY_TYPE_MASK)
213 #define ELINK_FW_PARAM_MDIO_CTRL(fw_param) ((fw_param & \
214 ELINK_FW_PARAM_MDIO_CTRL_MASK) >> \
215 ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
216 #define ELINK_FW_PARAM_SET(phy_addr, phy_type, mdio_access) \
217 (phy_addr | phy_type | mdio_access << ELINK_FW_PARAM_MDIO_CTRL_OFFSET)
220 #define ELINK_PFC_BRB_FULL_LB_XOFF_THRESHOLD 170
221 #define ELINK_PFC_BRB_FULL_LB_XON_THRESHOLD 250
223 #define ELINK_MAXVAL(a, b) (((a) > (b)) ? (a) : (b))
225 #define ELINK_BMAC_CONTROL_RX_ENABLE 2
226 /***********************************************************/
228 /***********************************************************/
229 #define ELINK_INT_PHY 0
230 #define ELINK_EXT_PHY1 1
231 #define ELINK_EXT_PHY2 2
232 #define ELINK_MAX_PHYS 3
234 /* Same configuration is shared between the XGXS and the first external phy */
235 #define ELINK_LINK_CONFIG_SIZE (ELINK_MAX_PHYS - 1)
236 #define ELINK_LINK_CONFIG_IDX(_phy_idx) ((_phy_idx == ELINK_INT_PHY) ? \
238 /***********************************************************/
239 /* elink_phy struct */
240 /* Defines the required arguments and function per phy */
241 /***********************************************************/
246 typedef uint8_t (*config_init_t)(struct elink_phy *phy, struct elink_params *params,
247 struct elink_vars *vars);
248 typedef uint8_t (*read_status_t)(struct elink_phy *phy, struct elink_params *params,
249 struct elink_vars *vars);
250 typedef void (*link_reset_t)(struct elink_phy *phy,
251 struct elink_params *params);
252 typedef void (*config_loopback_t)(struct elink_phy *phy,
253 struct elink_params *params);
254 typedef uint8_t (*format_fw_ver_t)(uint32_t raw, uint8_t *str, uint16_t *len);
255 typedef void (*hw_reset_t)(struct elink_phy *phy, struct elink_params *params);
256 typedef void (*set_link_led_t)(struct elink_phy *phy,
257 struct elink_params *params, uint8_t mode);
258 typedef void (*phy_specific_func_t)(struct elink_phy *phy,
259 struct elink_params *params, uint32_t action);
260 struct elink_reg_set {
269 /* Loaded during init */
271 uint8_t def_md_devad;
273 /* No Over-Current detection */
274 #define ELINK_FLAGS_NOC (1<<1)
275 /* Fan failure detection required */
276 #define ELINK_FLAGS_FAN_FAILURE_DET_REQ (1<<2)
277 /* Initialize first the XGXS and only then the phy itself */
278 #define ELINK_FLAGS_INIT_XGXS_FIRST (1<<3)
279 #define ELINK_FLAGS_WC_DUAL_MODE (1<<4)
280 #define ELINK_FLAGS_4_PORT_MODE (1<<5)
281 #define ELINK_FLAGS_REARM_LATCH_SIGNAL (1<<6)
282 #define ELINK_FLAGS_SFP_NOT_APPROVED (1<<7)
283 #define ELINK_FLAGS_MDC_MDIO_WA (1<<8)
284 #define ELINK_FLAGS_DUMMY_READ (1<<9)
285 #define ELINK_FLAGS_MDC_MDIO_WA_B0 (1<<10)
286 #define ELINK_FLAGS_SFP_MODULE_PLUGGED_IN_WC (1<<11)
287 #define ELINK_FLAGS_TX_ERROR_CHECK (1<<12)
288 #define ELINK_FLAGS_EEE (1<<13)
289 #define ELINK_FLAGS_TEMPERATURE (1<<14)
290 #define ELINK_FLAGS_MDC_MDIO_WA_G (1<<15)
292 /* preemphasis values for the rx side */
293 uint16_t rx_preemphasis[4];
295 /* preemphasis values for the tx side */
296 uint16_t tx_preemphasis[4];
298 /* EMAC address for access MDIO */
302 #define ELINK_SUPPORTED_10baseT_Half (1<<0)
303 #define ELINK_SUPPORTED_10baseT_Full (1<<1)
304 #define ELINK_SUPPORTED_100baseT_Half (1<<2)
305 #define ELINK_SUPPORTED_100baseT_Full (1<<3)
306 #define ELINK_SUPPORTED_1000baseT_Full (1<<4)
307 #define ELINK_SUPPORTED_2500baseX_Full (1<<5)
308 #define ELINK_SUPPORTED_10000baseT_Full (1<<6)
309 #define ELINK_SUPPORTED_TP (1<<7)
310 #define ELINK_SUPPORTED_FIBRE (1<<8)
311 #define ELINK_SUPPORTED_Autoneg (1<<9)
312 #define ELINK_SUPPORTED_Pause (1<<10)
313 #define ELINK_SUPPORTED_Asym_Pause (1<<11)
314 #define ELINK_SUPPORTED_20000baseMLD2_Full (1<<21)
315 #define ELINK_SUPPORTED_20000baseKR2_Full (1<<22)
318 #define ELINK_ETH_PHY_UNSPECIFIED 0x0
319 #define ELINK_ETH_PHY_SFPP_10G_FIBER 0x1
320 #define ELINK_ETH_PHY_XFP_FIBER 0x2
321 #define ELINK_ETH_PHY_DA_TWINAX 0x3
322 #define ELINK_ETH_PHY_BASE_T 0x4
323 #define ELINK_ETH_PHY_SFP_1G_FIBER 0x5
324 #define ELINK_ETH_PHY_KR 0xf0
325 #define ELINK_ETH_PHY_CX4 0xf1
326 #define ELINK_ETH_PHY_NOT_PRESENT 0xff
328 /* The address in which version is located*/
331 uint16_t req_flow_ctrl;
333 uint16_t req_line_speed;
335 uint32_t speed_cap_mask;
339 /* Called per phy/port init, and it configures LASI, speed, autoneg,
340 duplex, flow control negotiation, etc. */
341 config_init_t config_init;
343 /* Called due to interrupt. It determines the link, speed */
344 read_status_t read_status;
346 /* Called when driver is unloading. Should reset the phy */
347 link_reset_t link_reset;
349 /* Set the loopback configuration for the phy */
350 config_loopback_t config_loopback;
352 /* Format the given raw number into str up to len */
353 format_fw_ver_t format_fw_ver;
355 /* Reset the phy (both ports) */
358 /* Set link led mode (on/off/oper)*/
359 set_link_led_t set_link_led;
361 /* PHY Specific tasks */
362 phy_specific_func_t phy_specific_func;
363 #define ELINK_DISABLE_TX 1
364 #define ELINK_ENABLE_TX 2
365 #define ELINK_PHY_INIT 3
368 /* Inputs parameters to the CLC */
369 struct elink_params {
373 /* Default / User Configuration */
374 uint8_t loopback_mode;
375 #define ELINK_LOOPBACK_NONE 0
376 #define ELINK_LOOPBACK_EMAC 1
377 #define ELINK_LOOPBACK_BMAC 2
378 #define ELINK_LOOPBACK_XGXS 3
379 #define ELINK_LOOPBACK_EXT_PHY 4
380 #define ELINK_LOOPBACK_EXT 5
381 #define ELINK_LOOPBACK_UMAC 6
382 #define ELINK_LOOPBACK_XMAC 7
384 /* Device parameters */
387 uint16_t req_duplex[ELINK_LINK_CONFIG_SIZE];
388 uint16_t req_flow_ctrl[ELINK_LINK_CONFIG_SIZE];
390 uint16_t req_line_speed[ELINK_LINK_CONFIG_SIZE]; /* Also determine AutoNeg */
392 /* shmem parameters */
394 uint32_t shmem2_base;
395 uint32_t speed_cap_mask[ELINK_LINK_CONFIG_SIZE];
397 #define ELINK_SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
398 #define ELINK_SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
399 #define ELINK_SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
401 uint32_t lane_config;
403 /* Phy register parameter */
407 uint32_t feature_config_flags;
408 #define ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
409 #define ELINK_FEATURE_CONFIG_PFC_ENABLED (1<<1)
410 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
411 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY (1<<3)
412 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC (1<<4)
413 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC (1<<5)
414 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC (1<<6)
415 #define ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC (1<<7)
416 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX (1<<8)
417 #define ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED (1<<9)
418 #define ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED (1<<10)
419 #define ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET (1<<11)
420 #define ELINK_FEATURE_CONFIG_IEEE_PHY_TEST (1<<12)
421 #define ELINK_FEATURE_CONFIG_MT_SUPPORT (1<<13)
422 #define ELINK_FEATURE_CONFIG_BOOT_FROM_SAN (1<<14)
424 /* Will be populated during common init */
425 struct elink_phy phy[ELINK_MAX_PHYS];
427 /* Will be populated during common init */
432 /* Used to configure the EEE Tx LPI timer, has several modes of
433 * operation, according to bits 29:28 -
434 * 2'b00: Timer will be configured by nvram, output will be the value
436 * 2'b01: Timer will be configured by nvram, output will be in
438 * 2'b10: bits 1:0 contain an nvram value which will be used instead
439 * of the one located in the nvram. Output will be that value.
440 * 2'b11: bits 19:0 contain the idle timer in microseconds; output
441 * will be in microseconds.
442 * Bits 31:30 should be 2'b11 in order for EEE to be enabled.
445 #define ELINK_EEE_MODE_NVRAM_BALANCED_TIME (0xa00)
446 #define ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME (0x100)
447 #define ELINK_EEE_MODE_NVRAM_LATENCY_TIME (0x6000)
448 #define ELINK_EEE_MODE_NVRAM_MASK (0x3)
449 #define ELINK_EEE_MODE_TIMER_MASK (0xfffff)
450 #define ELINK_EEE_MODE_OUTPUT_TIME (1<<28)
451 #define ELINK_EEE_MODE_OVERRIDE_NVRAM (1<<29)
452 #define ELINK_EEE_MODE_ENABLE_LPI (1<<30)
453 #define ELINK_EEE_MODE_ADV_LPI (1<<31)
455 uint16_t hw_led_mode; /* part of the hw_config read from the shmem */
456 uint32_t multi_phy_config;
458 /* Device pointer passed to all callback functions */
459 struct bxe_softc *sc;
460 uint16_t req_fc_auto_adv; /* Should be set to TX / BOTH when
461 req_flow_ctrl is set to AUTO */
463 #define ELINK_LINK_FLAGS_INT_DISABLED (1<<0)
464 #define ELINK_PHY_INITIALIZED (1<<1)
468 /* Output parameters */
471 #define PHY_XGXS_FLAG (1<<0)
472 #define PHY_SGMII_FLAG (1<<1)
473 #define PHY_PHYSICAL_LINK_FLAG (1<<2)
474 #define PHY_HALF_OPEN_CONN_FLAG (1<<3)
475 #define PHY_OVER_CURRENT_FLAG (1<<4)
476 #define PHY_SFP_TX_FAULT_FLAG (1<<5)
479 #define ELINK_MAC_TYPE_NONE 0
480 #define ELINK_MAC_TYPE_EMAC 1
481 #define ELINK_MAC_TYPE_BMAC 2
482 #define ELINK_MAC_TYPE_UMAC 3
483 #define ELINK_MAC_TYPE_XMAC 4
485 uint8_t phy_link_up; /* internal phy link indication */
494 /* The same definitions as the shmem parameter */
495 uint32_t link_status;
497 uint8_t fault_detected;
498 uint8_t check_kr2_recovery_cnt;
499 #define ELINK_CHECK_KR2_RECOVERY_CNT 5
500 uint16_t periodic_flags;
501 #define ELINK_PERIODIC_FLAGS_LINK_EVENT 0x0001
503 uint32_t aeu_int_mask;
504 uint8_t rx_tx_asic_rst;
505 uint8_t turn_to_run_wc_rt;
507 /* The same definitions as the shmem2 parameter */
508 uint32_t link_attr_sync;
511 /***********************************************************/
513 /***********************************************************/
514 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars);
516 /* Reset the link. Should be called when driver or interface goes down
517 Before calling phy firmware upgrade, the reset_ext_phy should be set
519 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
520 uint8_t reset_ext_phy);
521 elink_status_t elink_lfa_reset(struct elink_params *params, struct elink_vars *vars);
522 /* elink_link_update should be called upon link interrupt */
523 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars);
525 /* use the following phy functions to read/write from external_phy
526 In order to use it to read/write internal phy registers, use
527 ELINK_DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
529 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
530 uint8_t devad, uint16_t reg, uint16_t *ret_val);
532 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
533 uint8_t devad, uint16_t reg, uint16_t val);
535 /* Reads the link_status from the shmem,
536 and update the link vars accordingly */
537 void elink_link_status_update(struct elink_params *input,
538 struct elink_vars *output);
539 /* returns string representing the fw_version of the external phy */
540 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
544 Basically, the CLC takes care of the led for the link, but in case one needs
545 to set/unset the led unnaturally, set the "mode" to ELINK_LED_MODE_OPER to
546 blink the led, and ELINK_LED_MODE_OFF to set the led off.*/
547 elink_status_t elink_set_led(struct elink_params *params,
548 struct elink_vars *vars, uint8_t mode, uint32_t speed);
549 #define ELINK_LED_MODE_OFF 0
550 #define ELINK_LED_MODE_ON 1
551 #define ELINK_LED_MODE_OPER 2
552 #define ELINK_LED_MODE_FRONT_PANEL_OFF 3
554 /* elink_handle_module_detect_int should be called upon module detection
556 void elink_handle_module_detect_int(struct elink_params *params);
558 /* Get the actual link status. In case it returns ELINK_STATUS_OK, link is up,
559 otherwise link is down*/
560 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
564 /* One-time initialization for external phy after power up */
565 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
566 uint32_t shmem2_base_path[], uint32_t chip_id, uint8_t one_port_enabled);
568 /* Reset the external PHY using GPIO */
569 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
571 /* Reset the external of SFX7101 */
572 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy);
574 /* Read "byte_cnt" bytes from address "addr" from the SFP+ EEPROM */
575 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
576 struct elink_params *params, uint8_t dev_addr,
577 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf);
579 void elink_hw_reset_phy(struct elink_params *params);
581 /* Check swap bit and adjust PHY order */
582 uint32_t elink_phy_selection(struct elink_params *params);
584 /* Probe the phys on board, and populate them in "params" */
585 elink_status_t elink_phy_probe(struct elink_params *params);
587 /* Checks if fan failure detection is required on one of the phys on board */
588 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, uint32_t shmem_base,
589 uint32_t shmem2_base, uint8_t port);
591 /* Open / close the gate between the NIG and the BRB */
592 void elink_set_rx_filter(struct elink_params *params, uint8_t en);
596 /* Number of maximum COS per chip */
597 #define ELINK_DCBX_E2E3_MAX_NUM_COS (2)
598 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0 (6)
599 #define ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 (3)
600 #define ELINK_DCBX_E3B0_MAX_NUM_COS ( \
601 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0, \
602 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1))
604 #define ELINK_DCBX_MAX_NUM_COS ( \
605 ELINK_MAXVAL(ELINK_DCBX_E3B0_MAX_NUM_COS, \
606 ELINK_DCBX_E2E3_MAX_NUM_COS))
608 /* PFC port configuration params */
609 struct elink_nig_brb_pfc_port_params {
611 uint32_t pause_enable;
612 uint32_t llfc_out_en;
613 uint32_t llfc_enable;
614 uint32_t pkt_priority_to_cos;
615 uint8_t num_of_rx_cos_priority_mask;
616 uint32_t rx_cos_priority_mask[ELINK_DCBX_MAX_NUM_COS];
617 uint32_t llfc_high_priority_classes;
618 uint32_t llfc_low_priority_classes;
622 /* ETS port configuration params */
623 struct elink_ets_bw_params {
627 struct elink_ets_sp_params {
629 * valid values are 0 - 5. 0 is highest strict priority.
630 * There can't be two COS's with the same pri.
635 enum elink_cos_state {
636 elink_cos_state_strict = 0,
637 elink_cos_state_bw = 1,
640 struct elink_ets_cos_params {
641 enum elink_cos_state state ;
643 struct elink_ets_bw_params bw_params;
644 struct elink_ets_sp_params sp_params;
648 struct elink_ets_params {
649 uint8_t num_of_cos; /* Number of valid COS entries*/
650 struct elink_ets_cos_params cos[ELINK_DCBX_MAX_NUM_COS];
653 /* Used to update the PFC attributes in EMAC, BMAC, NIG and BRB
654 * when link is already up
656 elink_status_t elink_update_pfc(struct elink_params *params,
657 struct elink_vars *vars,
658 struct elink_nig_brb_pfc_port_params *pfc_params);
661 /* Used to configure the ETS to disable */
662 elink_status_t elink_ets_disabled(struct elink_params *params,
663 struct elink_vars *vars);
665 /* Used to configure the ETS to BW limited */
666 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
667 const uint32_t cos1_bw);
669 /* Used to configure the ETS to strict */
670 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos);
673 /* Configure the COS to ETS according to BW and SP settings.*/
674 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
675 const struct elink_vars *vars,
676 struct elink_ets_params *ets_params);
677 /* Read pfc statistic*/
678 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
679 uint32_t pfc_frames_sent[2],
680 uint32_t pfc_frames_received[2]);
681 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
682 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
685 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
686 struct elink_params *params);
688 void elink_period_func(struct elink_params *params, struct elink_vars *vars);
690 elink_status_t elink_check_half_open_conn(struct elink_params *params,
691 struct elink_vars *vars, uint8_t notify);
693 void elink_enable_pmd_tx(struct elink_params *params);