2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
38 #if defined(__BIG_ENDIAN)
39 uint16_t max_iscsi_init_conn;
40 uint16_t max_iscsi_trgt_conn;
41 #elif defined(__LITTLE_ENDIAN)
42 uint16_t max_iscsi_trgt_conn;
43 uint16_t max_iscsi_init_conn;
46 uint32_t reserved_a[6];
54 * Shared HW configuration
56 struct shared_hw_cfg { /* NVRAM Offset */
57 /* Up to 16 bytes of NULL-terminated string */
58 uint8_t part_num[16]; /* 0x104 */
60 uint32_t config; /* 0x114 */
61 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
62 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
63 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
64 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
65 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
67 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
69 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
71 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
72 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
74 * Whatever MFW found in NVM
75 * (if multiple found, priority order is: NC-SI, UMP, IPMI)
77 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
78 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
79 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
80 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
82 * Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
83 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
85 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
87 * Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
88 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
90 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
92 * Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
93 * (can only be used when an add-in board, not BMC, pulls-down SPIO4).
95 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
97 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
98 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
99 #define SHARED_HW_CFG_LED_MAC1 0x00000000
100 #define SHARED_HW_CFG_LED_PHY1 0x00010000
101 #define SHARED_HW_CFG_LED_PHY2 0x00020000
102 #define SHARED_HW_CFG_LED_PHY3 0x00030000
103 #define SHARED_HW_CFG_LED_MAC2 0x00040000
104 #define SHARED_HW_CFG_LED_PHY4 0x00050000
105 #define SHARED_HW_CFG_LED_PHY5 0x00060000
106 #define SHARED_HW_CFG_LED_PHY6 0x00070000
107 #define SHARED_HW_CFG_LED_MAC3 0x00080000
108 #define SHARED_HW_CFG_LED_PHY7 0x00090000
109 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
110 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
111 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
112 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
114 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
115 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
116 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
117 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
118 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
119 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
120 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
121 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
123 uint32_t config2; /* 0x118 */
124 /* one time auto detect grace period (in sec) */
125 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
126 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
128 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
131 * The default value for the core clock is 250MHz and it is
132 * achieved by setting the clock change to 4.
134 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
135 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
137 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
138 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
140 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
142 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
143 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
145 /* Output low when PERST is asserted. */
146 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
147 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
149 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
150 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
151 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
152 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 /* 0dB */
153 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 /* -3.5dB */
154 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 /* -6.0dB */
157 * The fan failure mechanism is usually related to the PHY type
158 * since the power consumption of the board is determined by the PHY.
159 * Currently, fan is required for most designs with SFX7101, BCM8727
160 * and BCM8481. If a fan is not required for a board which uses one
161 * of those PHYs, this field should be set to "Disabled". If a fan is
162 * required for a different PHY type, this option should be set to
164 * The fan failure indication is expected on
167 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
168 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
169 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
170 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
171 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
173 /* ASPM Power Management support */
174 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
175 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
176 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
177 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
178 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
179 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
182 * The value of PM_TL_IGNORE_REQS (bit0) in PCI register
183 * tl_control_0 (register 0x2800).
185 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
186 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
189 uint32_t power_dissipated; /* 0x11c */
190 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
191 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
193 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
194 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
195 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
196 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
197 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
198 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
200 uint32_t ump_nc_si_config; /* 0x120 */
201 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
202 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
203 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
204 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
205 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
206 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
208 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
209 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
211 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
212 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
213 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
214 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
216 uint32_t board; /* 0x124 */
217 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
218 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
220 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
221 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
223 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
224 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
226 uint32_t reserved; /* 0x128 */
230 * Port HW configuration
232 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
234 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
235 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
238 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
239 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
241 uint32_t power_dissipated;
242 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
243 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
244 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
245 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
246 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
247 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
248 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
249 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
251 uint32_t power_consumed;
252 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
253 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
254 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
255 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
256 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
257 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
258 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
259 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
262 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
263 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
266 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */
267 uint32_t iscsi_mac_lower;
269 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */
270 uint32_t rdma_mac_lower;
272 uint32_t serdes_config;
273 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
274 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
276 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
277 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
279 uint32_t reserved0[16]; /* 0x158 */
282 * 4 times 16 bits for all 4 lanes. In case external PHY is present
283 * (not direct mode), those values will not take effect on the 4 XGXS
284 * lanes. For some external PHYs (such as 8706 and 8726) the values
285 * will be used to configure the external PHY -- in those cases, not
286 * all 4 values are needed.
288 uint16_t xgxs_config_rx[4]; /* 0x198 */
289 uint16_t xgxs_config_tx[4]; /* 0x1A0 */
291 uint32_t reserved1[64]; /* 0x1A8 */
293 uint32_t lane_config;
294 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
295 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
296 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
297 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
298 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
299 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
300 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
301 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
303 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
305 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
307 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
309 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
311 uint32_t external_phy_config;
312 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
313 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
314 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
315 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
316 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
318 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
319 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
321 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
322 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
323 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
324 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
325 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
326 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
327 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
328 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
329 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
330 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
331 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
332 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
333 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
334 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
335 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
336 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
338 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
339 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
341 uint32_t speed_capability_mask;
342 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
343 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
344 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
345 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
346 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
347 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
348 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
349 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
350 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
351 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12G 0x00800000
352 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_12_5G 0x01000000
353 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_13G 0x02000000
354 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_15G 0x04000000
355 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_16G 0x08000000
356 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
358 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
359 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
360 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
361 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
362 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
363 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
364 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
365 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
366 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
367 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12G 0x00000080
368 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_12_5G 0x00000100
369 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_13G 0x00000200
370 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_15G 0x00000400
371 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_16G 0x00000800
372 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
374 /* A place to hold the original MAC address as a backup. */
375 uint32_t backup_mac_upper; /* 0x2B4 */
376 uint32_t backup_mac_lower; /* 0x2B8 */
380 * Shared Feature configuration
382 struct shared_feat_cfg { /* NVRAM Offset */
383 uint32_t config; /* 0x450 */
384 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
387 * Use the values from options 47 and 48 instead of the HW default
390 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED 0x00000000
391 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED 0x00000002
393 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
394 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
396 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
397 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
400 * Override the OTP back to single function mode. When using GPIO,
401 * high means only SF, 0 is according to CLP configuration.
403 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
404 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
405 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
406 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
407 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
410 * The interval in seconds between sending LLDP packets. Set to zero
411 * to disable the feature.
413 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
414 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
416 /* The assigned device type ID for LLDP usage. */
417 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
418 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
422 * Port Feature configuration
424 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
426 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
427 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
428 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
429 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
430 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
431 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
432 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
433 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
434 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
435 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
436 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
437 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
438 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
439 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
440 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
441 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
442 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
443 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
444 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
445 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
446 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
447 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
448 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
449 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
450 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
451 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
452 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
453 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
454 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
455 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
456 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
457 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
458 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
459 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
460 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
461 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
462 #define PORT_FEATURE_EN_SIZE_MASK 0x07000000
463 #define PORT_FEATURE_EN_SIZE_SHIFT 24
464 #define PORT_FEATURE_WOL_ENABLED 0x01000000
465 #define PORT_FEATURE_MBA_ENABLED 0x02000000
466 #define PORT_FEATURE_MFW_ENABLED 0x04000000
468 /* Advertise expansion ROM even if MBA is disabled. */
469 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
470 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
472 /* Reserved bits: 28-29 */
474 * Check the optic vendor via i2c against a list of approved modules
475 * in a separate nvram image.
477 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
478 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
479 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT 0x00000000
480 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER 0x20000000
481 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
482 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
485 /* Default is used when driver sets to "auto" mode. */
486 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
487 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
488 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
489 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
490 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
491 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
492 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
493 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
494 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
497 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
498 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
499 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
500 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
501 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
502 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
503 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
504 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
505 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
506 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
507 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
508 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
509 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
510 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
511 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
512 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
513 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
514 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
515 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
516 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
517 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
518 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
519 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
520 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
521 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
522 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
523 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
524 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
525 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
526 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
527 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
528 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
529 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
530 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
531 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
532 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
533 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
534 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
535 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
536 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
537 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
538 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
539 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
540 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
541 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
542 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
543 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
544 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
545 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KX4 0x20000000
546 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_KR 0x24000000
547 #define PORT_FEATURE_MBA_LINK_SPEED_12GBPS 0x28000000
548 #define PORT_FEATURE_MBA_LINK_SPEED_12_5GBPS 0x2c000000
549 #define PORT_FEATURE_MBA_LINK_SPEED_13GBPS 0x30000000
550 #define PORT_FEATURE_MBA_LINK_SPEED_15GBPS 0x34000000
551 #define PORT_FEATURE_MBA_LINK_SPEED_16GBPS 0x38000000
554 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
555 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
557 uint32_t mba_vlan_cfg;
558 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
559 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
560 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
562 uint32_t resource_cfg;
563 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
564 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
565 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
566 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
567 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
569 uint32_t smbus_config;
571 #define PORT_FEATURE_SMBUS_EN 0x00000001
572 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
573 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
577 uint32_t link_config; /* Used as HW defaults for the driver */
578 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
579 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
580 /* (forced) low speed switch (< 10G) */
581 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
582 /* (forced) high speed switch (>= 10G) */
583 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
584 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
585 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
587 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
588 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
589 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
590 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
591 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
592 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
593 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
594 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
595 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
596 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
597 #define PORT_FEATURE_LINK_SPEED_10G_KX4 0x00080000
598 #define PORT_FEATURE_LINK_SPEED_10G_KR 0x00090000
599 #define PORT_FEATURE_LINK_SPEED_12G 0x000a0000
600 #define PORT_FEATURE_LINK_SPEED_12_5G 0x000b0000
601 #define PORT_FEATURE_LINK_SPEED_13G 0x000c0000
602 #define PORT_FEATURE_LINK_SPEED_15G 0x000d0000
603 #define PORT_FEATURE_LINK_SPEED_16G 0x000e0000
605 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
606 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
607 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
608 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
609 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
610 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
611 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
614 * The default for MCP link configuration,
615 * uses the same defines as link_config.
617 uint32_t mfw_wol_link_cfg;
619 uint32_t reserved[19];
625 struct shm_dev_info { /* size */
626 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
628 struct shared_hw_cfg shared_hw_config; /* 40 */
630 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
632 struct shared_feat_cfg shared_feature_config; /* 4 */
634 struct port_feat_cfg port_feature_config[PORT_MAX]; /* 116*2=232 */
645 #define E1_FUNC_MAX 2
646 #define E1H_FUNC_MAX 8
656 * This value (in milliseconds) determines the frequency of the driver
657 * issuing the PULSE message code. The firmware monitors this periodic
658 * pulse to determine when to switch to an OS-absent mode.
660 #define DRV_PULSE_PERIOD_MS 250
663 * This value (in milliseconds) determines how long the driver should
664 * wait for an acknowledgement from the firmware before timing out. Once
665 * the firmware has timed out, the driver will assume there is no firmware
666 * running and there won't be any firmware-driver synchronization during a
669 #define FW_ACK_TIME_OUT_MS 5000
671 #define FW_ACK_POLL_TIME_MS 1
673 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
675 /* LED Blink rate that will achieve ~15.9Hz. */
676 #define LED_BLINK_RATE_VAL 480
679 * Driver <-> FW Mailbox
682 uint32_t link_status;
683 /* Driver should update this field on any link change event. */
685 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
686 #define LINK_STATUS_LINK_UP 0x00000001
687 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
688 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0 << 1)
689 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1 << 1)
690 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2 << 1)
691 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3 << 1)
692 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4 << 1)
693 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5 << 1)
694 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6 << 1)
695 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7 << 1)
696 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7 << 1)
697 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8 << 1)
698 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9 << 1)
699 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9 << 1)
700 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10 << 1)
701 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10 << 1)
702 #define LINK_STATUS_SPEED_AND_DUPLEX_12GTFD (11 << 1)
703 #define LINK_STATUS_SPEED_AND_DUPLEX_12GXFD (11 << 1)
704 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD (12 << 1)
705 #define LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD (12 << 1)
706 #define LINK_STATUS_SPEED_AND_DUPLEX_13GTFD (13 << 1)
707 #define LINK_STATUS_SPEED_AND_DUPLEX_13GXFD (13 << 1)
708 #define LINK_STATUS_SPEED_AND_DUPLEX_15GTFD (14 << 1)
709 #define LINK_STATUS_SPEED_AND_DUPLEX_15GXFD (14 << 1)
710 #define LINK_STATUS_SPEED_AND_DUPLEX_16GTFD (15 << 1)
711 #define LINK_STATUS_SPEED_AND_DUPLEX_16GXFD (15 << 1)
713 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
714 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
716 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
717 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
718 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
720 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
721 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
722 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
723 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
724 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
725 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
726 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
728 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
729 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
731 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
732 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
734 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
735 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18)
736 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18)
737 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18)
738 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18)
740 #define LINK_STATUS_SERDES_LINK 0x00100000
742 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
743 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
744 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
745 #define LINK_STATUS_LINK_PARTNER_12GXFD_CAPABLE 0x01000000
746 #define LINK_STATUS_LINK_PARTNER_12_5GXFD_CAPABLE 0x02000000
747 #define LINK_STATUS_LINK_PARTNER_13GXFD_CAPABLE 0x04000000
748 #define LINK_STATUS_LINK_PARTNER_15GXFD_CAPABLE 0x08000000
749 #define LINK_STATUS_LINK_PARTNER_16GXFD_CAPABLE 0x10000000
753 uint32_t stat_nig_timer;
755 /* MCP firmware does not use this field. */
756 uint32_t ext_phy_fw_version;
760 uint32_t drv_mb_header;
761 #define DRV_MSG_CODE_MASK 0xffff0000
762 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
763 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
764 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
765 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
766 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
767 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
768 #define DRV_MSG_CODE_DCC_OK 0x30000000
769 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
770 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
771 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
772 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
773 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
774 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
775 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
776 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
778 * The optic module verification commands requris bootcode
781 #define DRV_MSG_CODE_VRFY_OPT_MDL 0xa0000000
782 #define REQ_BC_VER_4_VRFY_OPT_MDL 0x00050006
784 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
785 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
786 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
787 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
789 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
791 uint32_t drv_mb_param;
793 uint32_t fw_mb_header;
794 #define FW_MSG_CODE_MASK 0xffff0000
795 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
796 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
797 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
798 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
799 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
800 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
801 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
802 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
803 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
804 #define FW_MSG_CODE_DCC_DONE 0x30100000
805 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
806 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
807 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
808 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
809 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
810 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
811 #define FW_MSG_CODE_NO_KEY 0x80f00000
812 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
813 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
814 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
815 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
816 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
817 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
818 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
819 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
820 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
822 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
823 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
824 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
825 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
827 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
829 uint32_t fw_mb_param;
831 uint32_t drv_pulse_mb;
832 #define DRV_PULSE_SEQ_MASK 0x00007fff
833 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
835 * The system time is in the format of
836 * (year-2001)*12*32 + month*32 + day.
838 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
840 * Indicate to the firmware not to go into the
841 * OS-absent when it is not getting driver pulse.
842 * This is used for debugging as well for PXE(MBA).
845 uint32_t mcp_pulse_mb;
846 #define MCP_PULSE_SEQ_MASK 0x00007fff
847 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
849 * Indicates to the driver not to assert due to lack
852 #define MCP_EVENT_MASK 0xffff0000
853 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
855 uint32_t iscsi_boot_signature;
856 uint32_t iscsi_boot_block_offset;
859 #define DRV_STATUS_PMF 0x00000001
861 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
862 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
863 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
864 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
865 #define DRV_STATUS_DCC_RESERVED1 0x00000800
866 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
867 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
869 uint32_t virt_mac_upper;
870 #define VIRT_MAC_SIGN_MASK 0xffff0000
871 #define VIRT_MAC_SIGNATURE 0x564d0000
872 uint32_t virt_mac_lower;
876 * Management firmware state
878 /* Allocate 440 bytes for management firmware. */
879 #define MGMTFW_STATE_WORD_SIZE 110
881 struct mgmtfw_state {
882 uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
886 * Multi-Function configuration
888 struct shared_mf_cfg {
890 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
892 #define SHARED_MF_CLP_EXIT 0x00000001
894 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
898 uint32_t dynamic_cfg; /* device control channel */
899 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
900 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
901 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
903 uint32_t reserved[3];
909 /* function 0 of each port cannot be hidden. */
910 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
912 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000007
913 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
914 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
915 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
916 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
917 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
919 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
922 /* 0 - low priority, 3 - high priority */
923 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
924 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
925 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
928 /* value range - 0..100, increments in 100Mbps */
929 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
930 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
931 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
932 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
933 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
934 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
936 uint32_t mac_upper; /* MAC */
937 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
938 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
939 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
941 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
943 uint32_t e1hov_tag; /* VNI */
944 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
945 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
946 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
948 uint32_t reserved[2];
952 struct shared_mf_cfg shared_mf_config;
953 struct port_mf_cfg port_mf_config[PORT_MAX];
954 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX];
958 * Shared Memory Region
960 struct shmem_region { /* SharedMem Offset (size) */
961 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
962 #define SHR_MEM_FORMAT_REV_ID ('A' << 24)
963 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
965 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
966 #define SHR_MEM_VALIDITY_MB 0x00200000
967 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
968 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
969 /* One licensing bit should be set */
970 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
971 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
972 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
973 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
975 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
976 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
977 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
978 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
979 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
980 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
982 struct shm_dev_info dev_info; /* 0x8 (0x438) */
984 struct license_key drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
986 /* FW information (for internal FW use) */
987 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
988 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
990 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
991 #if !defined(b710) /* BXE_UPSTREAM */
992 struct drv_func_mb func_mb[E1H_FUNC_MAX];
994 struct drv_func_mb func_mb[E1_FUNC_MAX]; /* 0x684 (44*2=0x58) */
997 #if !defined(b710) /* BXE_UPSTREAM */
998 struct mf_cfg mf_cfg;
1002 struct shmem2_region {
1005 uint32_t dcc_support;
1006 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1007 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1008 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1009 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1010 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1011 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1012 #define SHMEM_DCC_SUPPORT_DEFAULT SHMEM_DCC_SUPPORT_NONE
1016 uint32_t rx_stat_ifhcinoctets;
1017 uint32_t rx_stat_ifhcinbadoctets;
1018 uint32_t rx_stat_etherstatsfragments;
1019 uint32_t rx_stat_ifhcinucastpkts;
1020 uint32_t rx_stat_ifhcinmulticastpkts;
1021 uint32_t rx_stat_ifhcinbroadcastpkts;
1022 uint32_t rx_stat_dot3statsfcserrors;
1023 uint32_t rx_stat_dot3statsalignmenterrors;
1024 uint32_t rx_stat_dot3statscarriersenseerrors;
1025 uint32_t rx_stat_xonpauseframesreceived;
1026 uint32_t rx_stat_xoffpauseframesreceived;
1027 uint32_t rx_stat_maccontrolframesreceived;
1028 uint32_t rx_stat_xoffstateentered;
1029 uint32_t rx_stat_dot3statsframestoolong;
1030 uint32_t rx_stat_etherstatsjabbers;
1031 uint32_t rx_stat_etherstatsundersizepkts;
1032 uint32_t rx_stat_etherstatspkts64octets;
1033 uint32_t rx_stat_etherstatspkts65octetsto127octets;
1034 uint32_t rx_stat_etherstatspkts128octetsto255octets;
1035 uint32_t rx_stat_etherstatspkts256octetsto511octets;
1036 uint32_t rx_stat_etherstatspkts512octetsto1023octets;
1037 uint32_t rx_stat_etherstatspkts1024octetsto1522octets;
1038 uint32_t rx_stat_etherstatspktsover1522octets;
1040 uint32_t rx_stat_falsecarriererrors;
1042 uint32_t tx_stat_ifhcoutoctets;
1043 uint32_t tx_stat_ifhcoutbadoctets;
1044 uint32_t tx_stat_etherstatscollisions;
1045 uint32_t tx_stat_outxonsent;
1046 uint32_t tx_stat_outxoffsent;
1047 uint32_t tx_stat_flowcontroldone;
1048 uint32_t tx_stat_dot3statssinglecollisionframes;
1049 uint32_t tx_stat_dot3statsmultiplecollisionframes;
1050 uint32_t tx_stat_dot3statsdeferredtransmissions;
1051 uint32_t tx_stat_dot3statsexcessivecollisions;
1052 uint32_t tx_stat_dot3statslatecollisions;
1053 uint32_t tx_stat_ifhcoutucastpkts;
1054 uint32_t tx_stat_ifhcoutmulticastpkts;
1055 uint32_t tx_stat_ifhcoutbroadcastpkts;
1056 uint32_t tx_stat_etherstatspkts64octets;
1057 uint32_t tx_stat_etherstatspkts65octetsto127octets;
1058 uint32_t tx_stat_etherstatspkts128octetsto255octets;
1059 uint32_t tx_stat_etherstatspkts256octetsto511octets;
1060 uint32_t tx_stat_etherstatspkts512octetsto1023octets;
1061 uint32_t tx_stat_etherstatspkts1024octetsto1522octets;
1062 uint32_t tx_stat_etherstatspktsover1522octets;
1063 uint32_t tx_stat_dot3statsinternalmactransmiterrors;
1067 uint32_t tx_stat_gtpkt_lo;
1068 uint32_t tx_stat_gtpkt_hi;
1069 uint32_t tx_stat_gtxpf_lo;
1070 uint32_t tx_stat_gtxpf_hi;
1071 uint32_t tx_stat_gtfcs_lo;
1072 uint32_t tx_stat_gtfcs_hi;
1073 uint32_t tx_stat_gtmca_lo;
1074 uint32_t tx_stat_gtmca_hi;
1075 uint32_t tx_stat_gtbca_lo;
1076 uint32_t tx_stat_gtbca_hi;
1077 uint32_t tx_stat_gtfrg_lo;
1078 uint32_t tx_stat_gtfrg_hi;
1079 uint32_t tx_stat_gtovr_lo;
1080 uint32_t tx_stat_gtovr_hi;
1081 uint32_t tx_stat_gt64_lo;
1082 uint32_t tx_stat_gt64_hi;
1083 uint32_t tx_stat_gt127_lo;
1084 uint32_t tx_stat_gt127_hi;
1085 uint32_t tx_stat_gt255_lo;
1086 uint32_t tx_stat_gt255_hi;
1087 uint32_t tx_stat_gt511_lo;
1088 uint32_t tx_stat_gt511_hi;
1089 uint32_t tx_stat_gt1023_lo;
1090 uint32_t tx_stat_gt1023_hi;
1091 uint32_t tx_stat_gt1518_lo;
1092 uint32_t tx_stat_gt1518_hi;
1093 uint32_t tx_stat_gt2047_lo;
1094 uint32_t tx_stat_gt2047_hi;
1095 uint32_t tx_stat_gt4095_lo;
1096 uint32_t tx_stat_gt4095_hi;
1097 uint32_t tx_stat_gt9216_lo;
1098 uint32_t tx_stat_gt9216_hi;
1099 uint32_t tx_stat_gt16383_lo;
1100 uint32_t tx_stat_gt16383_hi;
1101 uint32_t tx_stat_gtmax_lo;
1102 uint32_t tx_stat_gtmax_hi;
1103 uint32_t tx_stat_gtufl_lo;
1104 uint32_t tx_stat_gtufl_hi;
1105 uint32_t tx_stat_gterr_lo;
1106 uint32_t tx_stat_gterr_hi;
1107 uint32_t tx_stat_gtbyt_lo;
1108 uint32_t tx_stat_gtbyt_hi;
1110 uint32_t rx_stat_gr64_lo;
1111 uint32_t rx_stat_gr64_hi;
1112 uint32_t rx_stat_gr127_lo;
1113 uint32_t rx_stat_gr127_hi;
1114 uint32_t rx_stat_gr255_lo;
1115 uint32_t rx_stat_gr255_hi;
1116 uint32_t rx_stat_gr511_lo;
1117 uint32_t rx_stat_gr511_hi;
1118 uint32_t rx_stat_gr1023_lo;
1119 uint32_t rx_stat_gr1023_hi;
1120 uint32_t rx_stat_gr1518_lo;
1121 uint32_t rx_stat_gr1518_hi;
1122 uint32_t rx_stat_gr2047_lo;
1123 uint32_t rx_stat_gr2047_hi;
1124 uint32_t rx_stat_gr4095_lo;
1125 uint32_t rx_stat_gr4095_hi;
1126 uint32_t rx_stat_gr9216_lo;
1127 uint32_t rx_stat_gr9216_hi;
1128 uint32_t rx_stat_gr16383_lo;
1129 uint32_t rx_stat_gr16383_hi;
1130 uint32_t rx_stat_grmax_lo;
1131 uint32_t rx_stat_grmax_hi;
1132 uint32_t rx_stat_grpkt_lo;
1133 uint32_t rx_stat_grpkt_hi;
1134 uint32_t rx_stat_grfcs_lo;
1135 uint32_t rx_stat_grfcs_hi;
1136 uint32_t rx_stat_grmca_lo;
1137 uint32_t rx_stat_grmca_hi;
1138 uint32_t rx_stat_grbca_lo;
1139 uint32_t rx_stat_grbca_hi;
1140 uint32_t rx_stat_grxcf_lo;
1141 uint32_t rx_stat_grxcf_hi;
1142 uint32_t rx_stat_grxpf_lo;
1143 uint32_t rx_stat_grxpf_hi;
1144 uint32_t rx_stat_grxuo_lo;
1145 uint32_t rx_stat_grxuo_hi;
1146 uint32_t rx_stat_grjbr_lo;
1147 uint32_t rx_stat_grjbr_hi;
1148 uint32_t rx_stat_grovr_lo;
1149 uint32_t rx_stat_grovr_hi;
1150 uint32_t rx_stat_grflr_lo;
1151 uint32_t rx_stat_grflr_hi;
1152 uint32_t rx_stat_grmeg_lo;
1153 uint32_t rx_stat_grmeg_hi;
1154 uint32_t rx_stat_grmeb_lo;
1155 uint32_t rx_stat_grmeb_hi;
1156 uint32_t rx_stat_grbyt_lo;
1157 uint32_t rx_stat_grbyt_hi;
1158 uint32_t rx_stat_grund_lo;
1159 uint32_t rx_stat_grund_hi;
1160 uint32_t rx_stat_grfrg_lo;
1161 uint32_t rx_stat_grfrg_hi;
1162 uint32_t rx_stat_grerb_lo;
1163 uint32_t rx_stat_grerb_hi;
1164 uint32_t rx_stat_grfre_lo;
1165 uint32_t rx_stat_grfre_hi;
1166 uint32_t rx_stat_gripj_lo;
1167 uint32_t rx_stat_gripj_hi;
1171 struct emac_stats emac_stats;
1172 struct bmac_stats bmac_stats;
1177 uint32_t rx_stat_ifhcinbadoctets_hi;
1178 uint32_t rx_stat_ifhcinbadoctets_lo;
1180 /* out_bad_octets */
1181 uint32_t tx_stat_ifhcoutbadoctets_hi;
1182 uint32_t tx_stat_ifhcoutbadoctets_lo;
1184 /* crc_receive_errors */
1185 uint32_t rx_stat_dot3statsfcserrors_hi;
1186 uint32_t rx_stat_dot3statsfcserrors_lo;
1187 /* alignment_errors */
1188 uint32_t rx_stat_dot3statsalignmenterrors_hi;
1189 uint32_t rx_stat_dot3statsalignmenterrors_lo;
1190 /* carrier_sense_errors */
1191 uint32_t rx_stat_dot3statscarriersenseerrors_hi;
1192 uint32_t rx_stat_dot3statscarriersenseerrors_lo;
1193 /* false_carrier_detections */
1194 uint32_t rx_stat_falsecarriererrors_hi;
1195 uint32_t rx_stat_falsecarriererrors_lo;
1197 /* runt_packets_received */
1198 uint32_t rx_stat_etherstatsundersizepkts_hi;
1199 uint32_t rx_stat_etherstatsundersizepkts_lo;
1200 /* jabber_packets_received */
1201 uint32_t rx_stat_dot3statsframestoolong_hi;
1202 uint32_t rx_stat_dot3statsframestoolong_lo;
1204 /* error_runt_packets_received */
1205 uint32_t rx_stat_etherstatsfragments_hi;
1206 uint32_t rx_stat_etherstatsfragments_lo;
1207 /* error_jabber_packets_received */
1208 uint32_t rx_stat_etherstatsjabbers_hi;
1209 uint32_t rx_stat_etherstatsjabbers_lo;
1211 /* control_frames_received */
1212 uint32_t rx_stat_maccontrolframesreceived_hi;
1213 uint32_t rx_stat_maccontrolframesreceived_lo;
1214 uint32_t rx_stat_bmac_xpf_hi;
1215 uint32_t rx_stat_bmac_xpf_lo;
1216 uint32_t rx_stat_bmac_xcf_hi;
1217 uint32_t rx_stat_bmac_xcf_lo;
1219 /* xoff_state_entered */
1220 uint32_t rx_stat_xoffstateentered_hi;
1221 uint32_t rx_stat_xoffstateentered_lo;
1222 /* pause_xon_frames_received */
1223 uint32_t rx_stat_xonpauseframesreceived_hi;
1224 uint32_t rx_stat_xonpauseframesreceived_lo;
1225 /* pause_xoff_frames_received */
1226 uint32_t rx_stat_xoffpauseframesreceived_hi;
1227 uint32_t rx_stat_xoffpauseframesreceived_lo;
1228 /* pause_xon_frames_transmitted */
1229 uint32_t tx_stat_outxonsent_hi;
1230 uint32_t tx_stat_outxonsent_lo;
1231 /* pause_xoff_frames_transmitted */
1232 uint32_t tx_stat_outxoffsent_hi;
1233 uint32_t tx_stat_outxoffsent_lo;
1234 /* flow_control_done */
1235 uint32_t tx_stat_flowcontroldone_hi;
1236 uint32_t tx_stat_flowcontroldone_lo;
1238 /* ether_stats_collisions */
1239 uint32_t tx_stat_etherstatscollisions_hi;
1240 uint32_t tx_stat_etherstatscollisions_lo;
1241 /* single_collision_transmit_frames */
1242 uint32_t tx_stat_dot3statssinglecollisionframes_hi;
1243 uint32_t tx_stat_dot3statssinglecollisionframes_lo;
1244 /* multiple_collision_transmit_frames */
1245 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
1246 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
1247 /* deferred_transmissions */
1248 uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
1249 uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
1250 /* excessive_collision_frames */
1251 uint32_t tx_stat_dot3statsexcessivecollisions_hi;
1252 uint32_t tx_stat_dot3statsexcessivecollisions_lo;
1253 /* late_collision_frames */
1254 uint32_t tx_stat_dot3statslatecollisions_hi;
1255 uint32_t tx_stat_dot3statslatecollisions_lo;
1257 /* frames_transmitted_64_bytes */
1258 uint32_t tx_stat_etherstatspkts64octets_hi;
1259 uint32_t tx_stat_etherstatspkts64octets_lo;
1260 /* frames_transmitted_65_127_bytes */
1261 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
1262 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
1263 /* frames_transmitted_128_255_bytes */
1264 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
1265 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
1266 /* frames_transmitted_256_511_bytes */
1267 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
1268 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
1269 /* frames_transmitted_512_1023_bytes */
1270 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
1271 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
1272 /* frames_transmitted_1024_1522_bytes */
1273 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
1274 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
1275 /* frames_transmitted_1523_9022_bytes */
1276 uint32_t tx_stat_etherstatspktsover1522octets_hi;
1277 uint32_t tx_stat_etherstatspktsover1522octets_lo;
1278 uint32_t tx_stat_bmac_2047_hi;
1279 uint32_t tx_stat_bmac_2047_lo;
1280 uint32_t tx_stat_bmac_4095_hi;
1281 uint32_t tx_stat_bmac_4095_lo;
1282 uint32_t tx_stat_bmac_9216_hi;
1283 uint32_t tx_stat_bmac_9216_lo;
1284 uint32_t tx_stat_bmac_16383_hi;
1285 uint32_t tx_stat_bmac_16383_lo;
1287 /* internal_mac_transmit_errors */
1288 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
1289 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
1291 /* if_out_discards */
1292 uint32_t tx_stat_bmac_ufl_hi;
1293 uint32_t tx_stat_bmac_ufl_lo;
1297 #define MAC_STX_IDX_MAX 2
1299 struct host_port_stats {
1300 uint32_t host_port_stats_start;
1302 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
1304 uint32_t brb_drop_hi;
1305 uint32_t brb_drop_lo;
1307 uint32_t host_port_stats_end;
1310 struct host_func_stats {
1311 uint32_t host_func_stats_start;
1313 uint32_t total_bytes_received_hi;
1314 uint32_t total_bytes_received_lo;
1316 uint32_t total_bytes_transmitted_hi;
1317 uint32_t total_bytes_transmitted_lo;
1319 uint32_t total_unicast_packets_received_hi;
1320 uint32_t total_unicast_packets_received_lo;
1322 uint32_t total_multicast_packets_received_hi;
1323 uint32_t total_multicast_packets_received_lo;
1325 uint32_t total_broadcast_packets_received_hi;
1326 uint32_t total_broadcast_packets_received_lo;
1328 uint32_t total_unicast_packets_transmitted_hi;
1329 uint32_t total_unicast_packets_transmitted_lo;
1331 uint32_t total_multicast_packets_transmitted_hi;
1332 uint32_t total_multicast_packets_transmitted_lo;
1334 uint32_t total_broadcast_packets_transmitted_hi;
1335 uint32_t total_broadcast_packets_transmitted_lo;
1337 uint32_t valid_bytes_received_hi;
1338 uint32_t valid_bytes_received_lo;
1340 uint32_t host_func_stats_end;
1343 #define BCM_5710_FW_MAJOR_VERSION 5
1344 #define BCM_5710_FW_MINOR_VERSION 2
1345 #define BCM_5710_FW_REVISION_VERSION 13
1346 #define BCM_5710_FW_ENGINEERING_VERSION 0
1347 #define BCM_5710_FW_COMPILE_FLAGS 1
1352 struct atten_def_status_block {
1354 uint32_t attn_bits_ack;
1355 uint8_t status_block_id;
1357 uint16_t attn_bits_index;
1362 * Common data for all protocols.
1364 struct doorbell_hdr {
1366 #define DOORBELL_HDR_RX (0x1 << 0)
1367 #define DOORBELL_HDR_RX_SHIFT 0
1368 #define DOORBELL_HDR_DB_TYPE (0x1 << 1)
1369 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
1370 #define DOORBELL_HDR_DPM_SIZE (0x3 << 2)
1371 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
1372 #define DOORBELL_HDR_CONN_TYPE (0xF << 4)
1373 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
1377 * Doorbell message sent to the chip.
1380 #if defined(__BIG_ENDIAN)
1381 uint16_t zero_fill2;
1383 struct doorbell_hdr header;
1384 #elif defined(__LITTLE_ENDIAN)
1385 struct doorbell_hdr header;
1387 uint16_t zero_fill2;
1392 * Doorbell message sent to the chip.
1394 struct doorbell_set_prod {
1395 #if defined(__BIG_ENDIAN)
1398 struct doorbell_hdr header;
1399 #elif defined(__LITTLE_ENDIAN)
1400 struct doorbell_hdr header;
1407 * IGU driver acknowledgement register.
1409 struct igu_ack_register {
1410 #if defined(__BIG_ENDIAN)
1411 uint16_t sb_id_and_flags;
1412 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
1413 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1414 #define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
1415 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1416 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
1417 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1418 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
1419 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1420 #define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
1421 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1422 uint16_t status_block_index;
1423 #elif defined(__LITTLE_ENDIAN)
1424 uint16_t status_block_index;
1425 uint16_t sb_id_and_flags;
1426 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F << 0)
1427 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
1428 #define IGU_ACK_REGISTER_STORM_ID (0x7 << 5)
1429 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
1430 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1 << 8)
1431 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
1432 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3 << 9)
1433 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
1434 #define IGU_ACK_REGISTER_RESERVED (0x1F << 11)
1435 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
1440 * IGU driver acknowledgement register.
1442 struct igu_backward_compatible {
1443 uint32_t sb_id_and_flags;
1444 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF << 0)
1445 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
1446 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F << 16)
1447 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
1448 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7 << 21)
1449 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
1450 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1 << 24)
1451 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
1452 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3 << 25)
1453 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
1454 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F << 27)
1455 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
1456 uint32_t reserved_2;
1460 * IGU driver acknowledgement register.
1462 struct igu_regular {
1463 uint32_t sb_id_and_flags;
1464 #define IGU_REGULAR_SB_INDEX (0xFFFFF << 0)
1465 #define IGU_REGULAR_SB_INDEX_SHIFT 0
1466 #define IGU_REGULAR_RESERVED0 (0x1 << 20)
1467 #define IGU_REGULAR_RESERVED0_SHIFT 20
1468 #define IGU_REGULAR_SEGMENT_ACCESS (0x7 << 21)
1469 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
1470 #define IGU_REGULAR_BUPDATE (0x1 << 24)
1471 #define IGU_REGULAR_BUPDATE_SHIFT 24
1472 #define IGU_REGULAR_ENABLE_INT (0x3 << 25)
1473 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
1474 #define IGU_REGULAR_RESERVED_1 (0x1 << 27)
1475 #define IGU_REGULAR_RESERVED_1_SHIFT 27
1476 #define IGU_REGULAR_CLEANUP_TYPE (0x3 << 28)
1477 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
1478 #define IGU_REGULAR_CLEANUP_SET (0x1 << 30)
1479 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
1480 #define IGU_REGULAR_BCLEANUP (0x1 << 31)
1481 #define IGU_REGULAR_BCLEANUP_SHIFT 31
1482 uint32_t reserved_2;
1486 * IGU driver acknowledgement register.
1488 union igu_consprod_reg {
1489 struct igu_regular regular;
1490 struct igu_backward_compatible backward_compatible;
1494 * Parser parsing flags field.
1496 struct parsing_flags {
1498 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1 << 0)
1499 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
1500 #define PARSING_FLAGS_VLAN (0x1 << 1)
1501 #define PARSING_FLAGS_VLAN_SHIFT 1
1502 #define PARSING_FLAGS_EXTRA_VLAN (0x1 << 2)
1503 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
1504 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3 << 3)
1505 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
1506 #define PARSING_FLAGS_IP_OPTIONS (0x1 << 5)
1507 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
1508 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1 << 6)
1509 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
1510 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3 << 7)
1511 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
1512 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1 << 9)
1513 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
1514 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1 << 10)
1515 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
1516 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1 << 11)
1517 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
1518 #define PARSING_FLAGS_CONNECTION_MATCH (0x1 << 12)
1519 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
1520 #define PARSING_FLAGS_LLC_SNAP (0x1 << 13)
1521 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
1522 #define PARSING_FLAGS_RESERVED0 (0x3 << 14)
1523 #define PARSING_FLAGS_RESERVED0_SHIFT 14
1532 * dmae command structure
1534 struct dmae_command {
1536 #define DMAE_COMMAND_SRC (0x1 << 0)
1537 #define DMAE_COMMAND_SRC_SHIFT 0
1538 #define DMAE_COMMAND_DST (0x3 << 1)
1539 #define DMAE_COMMAND_DST_SHIFT 1
1540 #define DMAE_COMMAND_C_DST (0x1 << 3)
1541 #define DMAE_COMMAND_C_DST_SHIFT 3
1542 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1 << 4)
1543 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
1544 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1 << 5)
1545 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
1546 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7 << 6)
1547 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
1548 #define DMAE_COMMAND_ENDIANITY (0x3 << 9)
1549 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
1550 #define DMAE_COMMAND_PORT (0x1 << 11)
1551 #define DMAE_COMMAND_PORT_SHIFT 11
1552 #define DMAE_COMMAND_CRC_RESET (0x1 << 12)
1553 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
1554 #define DMAE_COMMAND_SRC_RESET (0x1 << 13)
1555 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
1556 #define DMAE_COMMAND_DST_RESET (0x1 << 14)
1557 #define DMAE_COMMAND_DST_RESET_SHIFT 14
1558 #define DMAE_COMMAND_E1HVN (0x3 << 15)
1559 #define DMAE_COMMAND_E1HVN_SHIFT 15
1560 #define DMAE_COMMAND_RESERVED0 (0x7FFF << 17)
1561 #define DMAE_COMMAND_RESERVED0_SHIFT 17
1562 uint32_t src_addr_lo;
1563 uint32_t src_addr_hi;
1564 uint32_t dst_addr_lo;
1565 uint32_t dst_addr_hi;
1566 #if defined(__BIG_ENDIAN)
1569 #elif defined(__LITTLE_ENDIAN)
1573 uint32_t comp_addr_lo;
1574 uint32_t comp_addr_hi;
1578 #if defined(__BIG_ENDIAN)
1581 #elif defined(__LITTLE_ENDIAN)
1585 #if defined(__BIG_ENDIAN)
1588 #elif defined(__LITTLE_ENDIAN)
1592 #if defined(__BIG_ENDIAN)
1595 #elif defined(__LITTLE_ENDIAN)
1601 struct double_regpair {
1602 uint32_t regpair0_lo;
1603 uint32_t regpair0_hi;
1604 uint32_t regpair1_lo;
1605 uint32_t regpair1_hi;
1609 * The eth storm context of Ustorm (configuration part).
1611 struct ustorm_eth_st_context_config {
1612 #if defined(__BIG_ENDIAN)
1614 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1 << 0)
1615 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1616 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1 << 1)
1617 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1618 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1 << 2)
1619 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1620 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1 << 3)
1621 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1622 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF << 4)
1623 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1624 uint8_t status_block_id;
1626 uint8_t sb_index_numbers;
1627 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF << 0)
1628 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1629 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF << 4)
1630 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1631 #elif defined(__LITTLE_ENDIAN)
1632 uint8_t sb_index_numbers;
1633 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER (0xF << 0)
1634 #define USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT 0
1635 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER (0xF << 4)
1636 #define USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT 4
1638 uint8_t status_block_id;
1640 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT (0x1 << 0)
1641 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT_SHIFT 0
1642 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC (0x1 << 1)
1643 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_DYNAMIC_HC_SHIFT 1
1644 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA (0x1 << 2)
1645 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA_SHIFT 2
1646 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS (0x1 << 3)
1647 #define USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS_SHIFT 3
1648 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0 (0xF << 4)
1649 #define __USTORM_ETH_ST_CONTEXT_CONFIG_RESERVED0_SHIFT 4
1651 #if defined(__BIG_ENDIAN)
1652 uint16_t bd_buff_size;
1653 uint8_t statistics_counter_id;
1654 uint8_t mc_alignment_log_size;
1655 #elif defined(__LITTLE_ENDIAN)
1656 uint8_t mc_alignment_log_size;
1657 uint8_t statistics_counter_id;
1658 uint16_t bd_buff_size;
1660 #if defined(__BIG_ENDIAN)
1661 uint8_t __local_sge_prod;
1662 uint8_t __local_bd_prod;
1663 uint16_t sge_buff_size;
1664 #elif defined(__LITTLE_ENDIAN)
1665 uint16_t sge_buff_size;
1666 uint8_t __local_bd_prod;
1667 uint8_t __local_sge_prod;
1669 #if defined(__BIG_ENDIAN)
1670 uint16_t __sdm_bd_expected_counter;
1671 uint8_t cstorm_agg_int;
1672 uint8_t __expected_bds_on_ram;
1673 #elif defined(__LITTLE_ENDIAN)
1674 uint8_t __expected_bds_on_ram;
1675 uint8_t cstorm_agg_int;
1676 uint16_t __sdm_bd_expected_counter;
1678 #if defined(__BIG_ENDIAN)
1679 uint16_t __ring_data_ram_addr;
1680 uint16_t __hc_cstorm_ram_addr;
1681 #elif defined(__LITTLE_ENDIAN)
1682 uint16_t __hc_cstorm_ram_addr;
1683 uint16_t __ring_data_ram_addr;
1685 #if defined(__BIG_ENDIAN)
1687 uint8_t max_sges_for_packet;
1688 uint16_t __bd_ring_ram_addr;
1689 #elif defined(__LITTLE_ENDIAN)
1690 uint16_t __bd_ring_ram_addr;
1691 uint8_t max_sges_for_packet;
1694 uint32_t bd_page_base_lo;
1695 uint32_t bd_page_base_hi;
1696 uint32_t sge_page_base_lo;
1697 uint32_t sge_page_base_hi;
1698 struct regpair reserved2;
1702 * The eth Rx Buffer Descriptor.
1710 * The eth Rx SGE Descriptor.
1718 * Local BDs and SGEs rings (in ETH).
1720 struct eth_local_rx_rings {
1721 struct eth_rx_bd __local_bd_ring[8];
1722 struct eth_rx_sge __local_sge_ring[10];
1726 * The eth storm context of Ustorm.
1728 struct ustorm_eth_st_context {
1729 struct ustorm_eth_st_context_config common;
1730 struct eth_local_rx_rings __rings;
1734 * The eth storm context of Tstorm.
1736 struct tstorm_eth_st_context {
1737 uint32_t __reserved0[28];
1741 * The eth aggregative context section of Xstorm.
1743 struct xstorm_eth_extra_ag_context_section {
1744 #if defined(__BIG_ENDIAN)
1745 uint8_t __tcp_agg_vars1;
1746 uint8_t __reserved50;
1748 #elif defined(__LITTLE_ENDIAN)
1750 uint8_t __reserved50;
1751 uint8_t __tcp_agg_vars1;
1756 uint32_t __reserved53;
1757 #if defined(__BIG_ENDIAN)
1758 uint8_t __agg_val8_th;
1760 uint16_t __tcp_agg_vars2;
1761 #elif defined(__LITTLE_ENDIAN)
1762 uint16_t __tcp_agg_vars2;
1764 uint8_t __agg_val8_th;
1766 uint32_t __reserved58;
1767 uint32_t __reserved59;
1768 uint32_t __reserved60;
1769 uint32_t __reserved61;
1770 #if defined(__BIG_ENDIAN)
1771 uint16_t __agg_val7_th;
1772 uint16_t __agg_val7;
1773 #elif defined(__LITTLE_ENDIAN)
1774 uint16_t __agg_val7;
1775 uint16_t __agg_val7_th;
1777 #if defined(__BIG_ENDIAN)
1778 uint8_t __tcp_agg_vars5;
1779 uint8_t __tcp_agg_vars4;
1780 uint8_t __tcp_agg_vars3;
1781 uint8_t __reserved62;
1782 #elif defined(__LITTLE_ENDIAN)
1783 uint8_t __reserved62;
1784 uint8_t __tcp_agg_vars3;
1785 uint8_t __tcp_agg_vars4;
1786 uint8_t __tcp_agg_vars5;
1788 uint32_t __tcp_agg_vars6;
1789 #if defined(__BIG_ENDIAN)
1790 uint16_t __agg_misc6;
1791 uint16_t __tcp_agg_vars7;
1792 #elif defined(__LITTLE_ENDIAN)
1793 uint16_t __tcp_agg_vars7;
1794 uint16_t __agg_misc6;
1796 uint32_t __agg_val10;
1797 uint32_t __agg_val10_th;
1798 #if defined(__BIG_ENDIAN)
1799 uint16_t __reserved3;
1800 uint8_t __reserved2;
1801 uint8_t __da_only_cnt;
1802 #elif defined(__LITTLE_ENDIAN)
1803 uint8_t __da_only_cnt;
1804 uint8_t __reserved2;
1805 uint16_t __reserved3;
1810 * The eth aggregative context of Xstorm.
1812 struct xstorm_eth_ag_context {
1813 #if defined(__BIG_ENDIAN)
1815 uint8_t __agg_vars1;
1817 #elif defined(__LITTLE_ENDIAN)
1819 uint8_t __agg_vars1;
1822 #if defined(__BIG_ENDIAN)
1823 uint8_t cdu_reserved;
1824 uint8_t __agg_vars4;
1825 uint8_t __agg_vars3;
1826 uint8_t __agg_vars2;
1827 #elif defined(__LITTLE_ENDIAN)
1828 uint8_t __agg_vars2;
1829 uint8_t __agg_vars3;
1830 uint8_t __agg_vars4;
1831 uint8_t cdu_reserved;
1834 #if defined(__BIG_ENDIAN)
1835 uint16_t __agg_vars5;
1836 uint16_t __agg_val4_th;
1837 #elif defined(__LITTLE_ENDIAN)
1838 uint16_t __agg_val4_th;
1839 uint16_t __agg_vars5;
1841 struct xstorm_eth_extra_ag_context_section __extra_section;
1842 #if defined(__BIG_ENDIAN)
1843 uint16_t __agg_vars7;
1844 uint8_t __agg_val3_th;
1845 uint8_t __agg_vars6;
1846 #elif defined(__LITTLE_ENDIAN)
1847 uint8_t __agg_vars6;
1848 uint8_t __agg_val3_th;
1849 uint16_t __agg_vars7;
1851 #if defined(__BIG_ENDIAN)
1852 uint16_t __agg_val11_th;
1853 uint16_t __agg_val11;
1854 #elif defined(__LITTLE_ENDIAN)
1855 uint16_t __agg_val11;
1856 uint16_t __agg_val11_th;
1858 #if defined(__BIG_ENDIAN)
1859 uint8_t __reserved1;
1860 uint8_t __agg_val6_th;
1861 uint16_t __agg_val9;
1862 #elif defined(__LITTLE_ENDIAN)
1863 uint16_t __agg_val9;
1864 uint8_t __agg_val6_th;
1865 uint8_t __reserved1;
1867 #if defined(__BIG_ENDIAN)
1868 uint16_t __agg_val2_th;
1869 uint16_t __agg_val2;
1870 #elif defined(__LITTLE_ENDIAN)
1871 uint16_t __agg_val2;
1872 uint16_t __agg_val2_th;
1874 uint32_t __agg_vars8;
1875 #if defined(__BIG_ENDIAN)
1876 uint16_t __agg_misc0;
1877 uint16_t __agg_val4;
1878 #elif defined(__LITTLE_ENDIAN)
1879 uint16_t __agg_val4;
1880 uint16_t __agg_misc0;
1882 #if defined(__BIG_ENDIAN)
1885 uint8_t __agg_val5_th;
1887 #elif defined(__LITTLE_ENDIAN)
1889 uint8_t __agg_val5_th;
1893 #if defined(__BIG_ENDIAN)
1894 uint16_t __agg_misc1;
1895 uint16_t __bd_ind_max_val;
1896 #elif defined(__LITTLE_ENDIAN)
1897 uint16_t __bd_ind_max_val;
1898 uint16_t __agg_misc1;
1900 uint32_t __reserved57;
1901 uint32_t __agg_misc4;
1902 uint32_t __agg_misc5;
1906 * The eth extra aggregative context section of Tstorm.
1908 struct tstorm_eth_extra_ag_context_section {
1909 uint32_t __agg_val1;
1910 #if defined(__BIG_ENDIAN)
1911 uint8_t __tcp_agg_vars2;
1913 uint16_t __agg_val2;
1914 #elif defined(__LITTLE_ENDIAN)
1915 uint16_t __agg_val2;
1917 uint8_t __tcp_agg_vars2;
1919 #if defined(__BIG_ENDIAN)
1920 uint16_t __agg_val5;
1922 uint8_t __tcp_agg_vars3;
1923 #elif defined(__LITTLE_ENDIAN)
1924 uint8_t __tcp_agg_vars3;
1926 uint16_t __agg_val5;
1928 uint32_t __reserved63;
1929 uint32_t __reserved64;
1930 uint32_t __reserved65;
1931 uint32_t __reserved66;
1932 uint32_t __reserved67;
1933 uint32_t __tcp_agg_vars1;
1934 uint32_t __reserved61;
1935 uint32_t __reserved62;
1936 uint32_t __reserved2;
1940 * The eth aggregative context of Tstorm.
1942 struct tstorm_eth_ag_context {
1943 #if defined(__BIG_ENDIAN)
1944 uint16_t __reserved54;
1945 uint8_t __agg_vars1;
1947 #elif defined(__LITTLE_ENDIAN)
1949 uint8_t __agg_vars1;
1950 uint16_t __reserved54;
1952 #if defined(__BIG_ENDIAN)
1953 uint16_t __agg_val4;
1954 uint16_t __agg_vars2;
1955 #elif defined(__LITTLE_ENDIAN)
1956 uint16_t __agg_vars2;
1957 uint16_t __agg_val4;
1959 struct tstorm_eth_extra_ag_context_section __extra_section;
1963 * The eth aggregative context of Cstorm.
1965 struct cstorm_eth_ag_context {
1966 uint32_t __agg_vars1;
1967 #if defined(__BIG_ENDIAN)
1970 uint16_t __agg_vars2;
1971 #elif defined(__LITTLE_ENDIAN)
1972 uint16_t __agg_vars2;
1976 uint32_t __num_of_treated_packet;
1977 uint32_t __last_packet_treated;
1978 #if defined(__BIG_ENDIAN)
1979 uint16_t __reserved58;
1980 uint16_t __reserved57;
1981 #elif defined(__LITTLE_ENDIAN)
1982 uint16_t __reserved57;
1983 uint16_t __reserved58;
1985 #if defined(__BIG_ENDIAN)
1986 uint8_t __reserved62;
1987 uint8_t __reserved61;
1988 uint8_t __reserved60;
1989 uint8_t __reserved59;
1990 #elif defined(__LITTLE_ENDIAN)
1991 uint8_t __reserved59;
1992 uint8_t __reserved60;
1993 uint8_t __reserved61;
1994 uint8_t __reserved62;
1996 #if defined(__BIG_ENDIAN)
1997 uint16_t __reserved64;
1998 uint16_t __reserved63;
1999 #elif defined(__LITTLE_ENDIAN)
2000 uint16_t __reserved63;
2001 uint16_t __reserved64;
2003 uint32_t __reserved65;
2004 #if defined(__BIG_ENDIAN)
2005 uint16_t __agg_vars3;
2006 uint16_t __rq_inv_cnt;
2007 #elif defined(__LITTLE_ENDIAN)
2008 uint16_t __rq_inv_cnt;
2009 uint16_t __agg_vars3;
2011 #if defined(__BIG_ENDIAN)
2012 uint16_t __packet_index_th;
2013 uint16_t __packet_index;
2014 #elif defined(__LITTLE_ENDIAN)
2015 uint16_t __packet_index;
2016 uint16_t __packet_index_th;
2021 * The eth aggregative context of Ustorm.
2023 struct ustorm_eth_ag_context {
2024 #if defined(__BIG_ENDIAN)
2025 uint8_t __aux_counter_flags;
2026 uint8_t __agg_vars2;
2027 uint8_t __agg_vars1;
2029 #elif defined(__LITTLE_ENDIAN)
2031 uint8_t __agg_vars1;
2032 uint8_t __agg_vars2;
2033 uint8_t __aux_counter_flags;
2035 #if defined(__BIG_ENDIAN)
2037 uint8_t __agg_misc2;
2038 uint16_t __agg_misc1;
2039 #elif defined(__LITTLE_ENDIAN)
2040 uint16_t __agg_misc1;
2041 uint8_t __agg_misc2;
2044 uint32_t __agg_misc4;
2045 #if defined(__BIG_ENDIAN)
2046 uint8_t __agg_val3_th;
2048 uint16_t __agg_misc3;
2049 #elif defined(__LITTLE_ENDIAN)
2050 uint16_t __agg_misc3;
2052 uint8_t __agg_val3_th;
2054 uint32_t __agg_val1;
2055 uint32_t __agg_misc4_th;
2056 #if defined(__BIG_ENDIAN)
2057 uint16_t __agg_val2_th;
2058 uint16_t __agg_val2;
2059 #elif defined(__LITTLE_ENDIAN)
2060 uint16_t __agg_val2;
2061 uint16_t __agg_val2_th;
2063 #if defined(__BIG_ENDIAN)
2064 uint16_t __reserved2;
2065 uint8_t __decision_rules;
2066 uint8_t __decision_rule_enable_bits;
2067 #elif defined(__LITTLE_ENDIAN)
2068 uint8_t __decision_rule_enable_bits;
2069 uint8_t __decision_rules;
2070 uint16_t __reserved2;
2075 * Timers connection context.
2077 struct timers_block_context {
2078 uint32_t __reserved_0;
2079 uint32_t __reserved_1;
2080 uint32_t __reserved_2;
2082 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3 << 0)
2083 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
2084 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1 << 2)
2085 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
2086 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF << 3)
2087 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
2091 * Structure for easy accessibility to assembler.
2093 struct eth_tx_bd_flags {
2094 uint8_t as_bitfield;
2095 #define ETH_TX_BD_FLAGS_VLAN_TAG (0x1 << 0)
2096 #define ETH_TX_BD_FLAGS_VLAN_TAG_SHIFT 0
2097 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1 << 1)
2098 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 1
2099 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1 << 2)
2100 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 2
2101 #define ETH_TX_BD_FLAGS_END_BD (0x1 << 3)
2102 #define ETH_TX_BD_FLAGS_END_BD_SHIFT 3
2103 #define ETH_TX_BD_FLAGS_START_BD (0x1 << 4)
2104 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
2105 #define ETH_TX_BD_FLAGS_HDR_POOL (0x1 << 5)
2106 #define ETH_TX_BD_FLAGS_HDR_POOL_SHIFT 5
2107 #define ETH_TX_BD_FLAGS_SW_LSO (0x1 << 6)
2108 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
2109 #define ETH_TX_BD_FLAGS_IPV6 (0x1 << 7)
2110 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
2114 * The eth Tx Buffer Descriptor.
2116 struct eth_tx_start_bd {
2122 struct eth_tx_bd_flags bd_flags;
2123 uint8_t general_data;
2124 #define ETH_TX_START_BD_HDR_NBDS (0x3F << 0)
2125 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
2126 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3 << 6)
2127 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
2131 * Tx regular BD structure.
2136 uint16_t total_pkt_bytes;
2138 uint8_t reserved[4];
2142 * Tx parsing BD structure for ETH,Relevant in START.
2144 struct eth_tx_parse_bd {
2145 uint8_t global_data;
2146 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET (0xF << 0)
2147 #define ETH_TX_PARSE_BD_IP_HDR_START_OFFSET_SHIFT 0
2148 #define ETH_TX_PARSE_BD_UDP_CS_FLG (0x1 << 4)
2149 #define ETH_TX_PARSE_BD_UDP_CS_FLG_SHIFT 4
2150 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN (0x1 << 5)
2151 #define ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
2152 #define ETH_TX_PARSE_BD_LLC_SNAP_EN (0x1 << 6)
2153 #define ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT 6
2154 #define ETH_TX_PARSE_BD_NS_FLG (0x1 << 7)
2155 #define ETH_TX_PARSE_BD_NS_FLG_SHIFT 7
2157 #define ETH_TX_PARSE_BD_FIN_FLG (0x1 << 0)
2158 #define ETH_TX_PARSE_BD_FIN_FLG_SHIFT 0
2159 #define ETH_TX_PARSE_BD_SYN_FLG (0x1 << 1)
2160 #define ETH_TX_PARSE_BD_SYN_FLG_SHIFT 1
2161 #define ETH_TX_PARSE_BD_RST_FLG (0x1 << 2)
2162 #define ETH_TX_PARSE_BD_RST_FLG_SHIFT 2
2163 #define ETH_TX_PARSE_BD_PSH_FLG (0x1 << 3)
2164 #define ETH_TX_PARSE_BD_PSH_FLG_SHIFT 3
2165 #define ETH_TX_PARSE_BD_ACK_FLG (0x1 << 4)
2166 #define ETH_TX_PARSE_BD_ACK_FLG_SHIFT 4
2167 #define ETH_TX_PARSE_BD_URG_FLG (0x1 << 5)
2168 #define ETH_TX_PARSE_BD_URG_FLG_SHIFT 5
2169 #define ETH_TX_PARSE_BD_ECE_FLG (0x1 << 6)
2170 #define ETH_TX_PARSE_BD_ECE_FLG_SHIFT 6
2171 #define ETH_TX_PARSE_BD_CWR_FLG (0x1 << 7)
2172 #define ETH_TX_PARSE_BD_CWR_FLG_SHIFT 7
2175 uint16_t total_hlen;
2176 uint16_t tcp_pseudo_csum;
2179 uint32_t tcp_send_seq;
2183 * The last BD in the BD memory will hold a pointer to the next BD memory.
2185 struct eth_tx_next_bd {
2188 uint8_t reserved[8];
2192 * union for 4 Bd types.
2194 union eth_tx_bd_types {
2195 struct eth_tx_start_bd start_bd;
2196 struct eth_tx_bd reg_bd;
2197 struct eth_tx_parse_bd parse_bd;
2198 struct eth_tx_next_bd next_bd;
2202 * The eth storm context of Xstorm.
2204 struct xstorm_eth_st_context {
2205 uint32_t tx_bd_page_base_lo;
2206 uint32_t tx_bd_page_base_hi;
2207 #if defined(__BIG_ENDIAN)
2208 uint16_t tx_bd_cons;
2209 uint8_t statistics_data;
2210 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F << 0)
2211 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2212 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1 << 7)
2213 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2214 uint8_t __local_tx_bd_prod;
2215 #elif defined(__LITTLE_ENDIAN)
2216 uint8_t __local_tx_bd_prod;
2217 uint8_t statistics_data;
2218 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID (0x7F << 0)
2219 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_COUNTER_ID_SHIFT 0
2220 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE (0x1 << 7)
2221 #define XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE_SHIFT 7
2222 uint16_t tx_bd_cons;
2224 uint32_t __reserved1;
2225 uint32_t __reserved2;
2226 #if defined(__BIG_ENDIAN)
2227 uint8_t __ram_cache_index;
2228 uint8_t __double_buffer_client;
2229 uint16_t __pkt_cons;
2230 #elif defined(__LITTLE_ENDIAN)
2231 uint16_t __pkt_cons;
2232 uint8_t __double_buffer_client;
2233 uint8_t __ram_cache_index;
2235 #if defined(__BIG_ENDIAN)
2236 uint16_t __statistics_address;
2237 uint16_t __gso_next;
2238 #elif defined(__LITTLE_ENDIAN)
2239 uint16_t __gso_next;
2240 uint16_t __statistics_address;
2242 #if defined(__BIG_ENDIAN)
2243 uint8_t __local_tx_bd_cons;
2244 uint8_t safc_group_num;
2245 uint8_t safc_group_en;
2246 uint8_t __is_eth_conn;
2247 #elif defined(__LITTLE_ENDIAN)
2248 uint8_t __is_eth_conn;
2249 uint8_t safc_group_en;
2250 uint8_t safc_group_num;
2251 uint8_t __local_tx_bd_cons;
2253 union eth_tx_bd_types __bds[13];
2257 * The eth storm context of Cstorm.
2259 struct cstorm_eth_st_context {
2260 #if defined(__BIG_ENDIAN)
2261 uint16_t __reserved0;
2262 uint8_t sb_index_number;
2263 uint8_t status_block_id;
2264 #elif defined(__LITTLE_ENDIAN)
2265 uint8_t status_block_id;
2266 uint8_t sb_index_number;
2267 uint16_t __reserved0;
2269 uint32_t __reserved1[3];
2273 * Ethernet connection context.
2275 struct eth_context {
2276 struct ustorm_eth_st_context ustorm_st_context;
2277 struct tstorm_eth_st_context tstorm_st_context;
2278 struct xstorm_eth_ag_context xstorm_ag_context;
2279 struct tstorm_eth_ag_context tstorm_ag_context;
2280 struct cstorm_eth_ag_context cstorm_ag_context;
2281 struct ustorm_eth_ag_context ustorm_ag_context;
2282 struct timers_block_context timers_context;
2283 struct xstorm_eth_st_context xstorm_st_context;
2284 struct cstorm_eth_st_context cstorm_st_context;
2290 struct eth_tx_doorbell {
2291 #if defined(__BIG_ENDIAN)
2294 #define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
2295 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2296 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
2297 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2298 #define ETH_TX_DOORBELL_SPARE (0x1 << 7)
2299 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2300 struct doorbell_hdr hdr;
2301 #elif defined(__LITTLE_ENDIAN)
2302 struct doorbell_hdr hdr;
2304 #define ETH_TX_DOORBELL_NUM_BDS (0x3F << 0)
2305 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2306 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1 << 6)
2307 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2308 #define ETH_TX_DOORBELL_SPARE (0x1 << 7)
2309 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2315 * cstorm default status block, generated by ustorm.
2317 struct cstorm_def_status_block_u {
2318 uint16_t index_values[HC_USTORM_DEF_SB_NUM_INDICES];
2319 uint16_t status_block_index;
2321 uint8_t status_block_id;
2326 * cstorm default status block, generated by cstorm.
2328 struct cstorm_def_status_block_c {
2329 uint16_t index_values[HC_CSTORM_DEF_SB_NUM_INDICES];
2330 uint16_t status_block_index;
2332 uint8_t status_block_id;
2337 * xstorm status block
2339 struct xstorm_def_status_block {
2340 uint16_t index_values[HC_XSTORM_DEF_SB_NUM_INDICES];
2341 uint16_t status_block_index;
2343 uint8_t status_block_id;
2348 * tstorm status block
2350 struct tstorm_def_status_block {
2351 uint16_t index_values[HC_TSTORM_DEF_SB_NUM_INDICES];
2352 uint16_t status_block_index;
2354 uint8_t status_block_id;
2361 struct host_def_status_block {
2362 struct atten_def_status_block atten_status_block;
2363 struct cstorm_def_status_block_u u_def_status_block;
2364 struct cstorm_def_status_block_c c_def_status_block;
2365 struct xstorm_def_status_block x_def_status_block;
2366 struct tstorm_def_status_block t_def_status_block;
2370 * cstorm status block, generated by ustorm.
2372 struct cstorm_status_block_u {
2373 uint16_t index_values[HC_USTORM_SB_NUM_INDICES];
2374 uint16_t status_block_index;
2376 uint8_t status_block_id;
2381 * cstorm status block, generated by cstorm.
2383 struct cstorm_status_block_c {
2384 uint16_t index_values[HC_CSTORM_SB_NUM_INDICES];
2385 uint16_t status_block_index;
2387 uint8_t status_block_id;
2394 struct host_status_block {
2395 struct cstorm_status_block_u u_status_block;
2396 struct cstorm_status_block_c c_status_block;
2400 * The data for RSS setup ramrod.
2402 struct eth_client_setup_ramrod_data {
2410 * regular eth FP CQE parameters struct.
2412 struct eth_fast_path_rx_cqe {
2413 uint8_t type_error_flags;
2414 #define ETH_FAST_PATH_RX_CQE_TYPE (0x1 << 0)
2415 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
2416 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1 << 1)
2417 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 1
2418 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1 << 2)
2419 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 2
2420 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1 << 3)
2421 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 3
2422 #define ETH_FAST_PATH_RX_CQE_START_FLG (0x1 << 4)
2423 #define ETH_FAST_PATH_RX_CQE_START_FLG_SHIFT 4
2424 #define ETH_FAST_PATH_RX_CQE_END_FLG (0x1 << 5)
2425 #define ETH_FAST_PATH_RX_CQE_END_FLG_SHIFT 5
2426 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3 << 6)
2427 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
2428 uint8_t status_flags;
2429 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7 << 0)
2430 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
2431 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1 << 3)
2432 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
2433 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1 << 4)
2434 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
2435 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1 << 5)
2436 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
2437 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1 << 6)
2438 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
2439 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1 << 7)
2440 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
2441 uint8_t placement_offset;
2442 uint8_t queue_index;
2443 uint32_t rss_hash_result;
2447 struct parsing_flags pars_flags;
2452 * The data for RSS setup ramrod.
2454 struct eth_halt_ramrod_data {
2461 * The data for statistics query ramrod.
2463 struct eth_query_ramrod_data {
2464 #if defined(__BIG_ENDIAN)
2466 uint8_t collect_port;
2467 uint16_t drv_counter;
2468 #elif defined(__LITTLE_ENDIAN)
2469 uint16_t drv_counter;
2470 uint8_t collect_port;
2473 uint32_t ctr_id_vector;
2477 * Place holder for ramrods protocol specific data.
2479 struct ramrod_data {
2485 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits).
2487 union eth_ramrod_data {
2488 struct ramrod_data general;
2493 * Eth Rx Cqe structure- general structure for ramrods.
2495 struct common_ramrod_eth_rx_cqe {
2496 uint8_t ramrod_type;
2497 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x1 << 0)
2498 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
2499 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1 << 1)
2500 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 1
2501 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x3F << 2)
2502 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 2
2505 uint32_t conn_and_cmd_data;
2506 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF << 0)
2507 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
2508 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF << 24)
2509 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
2510 struct ramrod_data protocol_data;
2511 uint32_t reserved2[4];
2515 * Rx Last CQE in page (in ETH).
2517 struct eth_rx_cqe_next_page {
2520 uint32_t reserved[6];
2524 * union for all eth rx cqe types (fix their sizes).
2527 struct eth_fast_path_rx_cqe fast_path_cqe;
2528 struct common_ramrod_eth_rx_cqe ramrod_cqe;
2529 struct eth_rx_cqe_next_page next_page_cqe;
2533 * Common data for all protocols.
2536 uint32_t conn_and_cmd_data;
2537 #define SPE_HDR_CID (0xFFFFFF << 0)
2538 #define SPE_HDR_CID_SHIFT 0
2539 #define SPE_HDR_CMD_ID (0xFF << 24)
2540 #define SPE_HDR_CMD_ID_SHIFT 24
2542 #define SPE_HDR_CONN_TYPE (0xFF << 0)
2543 #define SPE_HDR_CONN_TYPE_SHIFT 0
2544 #define SPE_HDR_COMMON_RAMROD (0xFF << 8)
2545 #define SPE_HDR_COMMON_RAMROD_SHIFT 8
2550 * Ethernet slow path element
2552 union eth_specific_data {
2553 uint8_t protocol_data[8];
2554 struct regpair mac_config_addr;
2555 struct eth_client_setup_ramrod_data client_setup_ramrod_data;
2556 struct eth_halt_ramrod_data halt_ramrod_data;
2557 struct regpair leading_cqe_addr;
2558 struct regpair update_data_addr;
2559 struct eth_query_ramrod_data query_ramrod_data;
2563 * Ethernet slow path element.
2567 union eth_specific_data data;
2571 * Array of 13 bds as appears in the eth xstorm context.
2573 struct eth_tx_bds_array {
2574 union eth_tx_bd_types bds[13];
2578 * Common configuration parameters per function in Tstorm.
2580 struct tstorm_eth_function_common_config {
2581 #if defined(__BIG_ENDIAN)
2582 uint8_t leading_client_id;
2583 uint8_t rss_result_mask;
2584 uint16_t config_flags;
2585 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0)
2586 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2587 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
2588 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2589 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2)
2590 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2591 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
2592 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2593 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4)
2594 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2595 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1 << 7)
2596 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2597 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1 << 8)
2598 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2599 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1 << 9)
2600 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2601 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1 << 10)
2602 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2603 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F << 11)
2604 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2605 #elif defined(__LITTLE_ENDIAN)
2606 uint16_t config_flags;
2607 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1 << 0)
2608 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
2609 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1 << 1)
2610 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
2611 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1 << 2)
2612 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
2613 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1 << 3)
2614 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
2615 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7 << 4)
2616 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
2617 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE (0x1 << 7)
2618 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_DEFAULT_ENABLE_SHIFT 7
2619 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM (0x1 << 8)
2620 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_IN_CAM_SHIFT 8
2621 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM (0x1 << 9)
2622 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM_SHIFT 9
2623 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA (0x1 << 10)
2624 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA_SHIFT 10
2625 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0x1F << 11)
2626 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 11
2627 uint8_t rss_result_mask;
2628 uint8_t leading_client_id;
2630 uint16_t vlan_id[2];
2634 * RSS idirection table update configuration.
2636 struct rss_update_config {
2637 #if defined(__BIG_ENDIAN)
2638 uint16_t toe_rss_bitmap;
2640 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1 << 0)
2641 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2642 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1 << 1)
2643 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2644 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF << 2)
2645 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2646 #elif defined(__LITTLE_ENDIAN)
2648 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE (0x1 << 0)
2649 #define RSS_UPDATE_CONFIG_ETH_UPDATE_ENABLE_SHIFT 0
2650 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE (0x1 << 1)
2651 #define RSS_UPDATE_CONFIG_TOE_UPDATE_ENABLE_SHIFT 1
2652 #define __RSS_UPDATE_CONFIG_RESERVED0 (0x3FFF << 2)
2653 #define __RSS_UPDATE_CONFIG_RESERVED0_SHIFT 2
2654 uint16_t toe_rss_bitmap;
2660 * Parameters for eth update ramrod.
2662 struct eth_update_ramrod_data {
2663 struct tstorm_eth_function_common_config func_config;
2664 uint8_t indirectionTable[128];
2665 struct rss_update_config rss_config;
2669 * MAC filtering configuration command header.
2671 struct mac_configuration_hdr {
2679 * MAC address in list for ramrod.
2681 struct tstorm_cam_entry {
2682 uint16_t lsb_mac_addr;
2683 uint16_t middle_mac_addr;
2684 uint16_t msb_mac_addr;
2686 #define TSTORM_CAM_ENTRY_PORT_ID (0x1 << 0)
2687 #define TSTORM_CAM_ENTRY_PORT_ID_SHIFT 0
2688 #define TSTORM_CAM_ENTRY_RSRVVAL0 (0x7 << 1)
2689 #define TSTORM_CAM_ENTRY_RSRVVAL0_SHIFT 1
2690 #define TSTORM_CAM_ENTRY_RESERVED0 (0xFFF << 4)
2691 #define TSTORM_CAM_ENTRY_RESERVED0_SHIFT 4
2695 * MAC filtering: CAM target table entry
2697 struct tstorm_cam_target_table_entry {
2699 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST (0x1 << 0)
2700 #define TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST_SHIFT 0
2701 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1 << 1)
2702 #define TSTORM_CAM_TARGET_TABLE_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 1
2703 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE (0x1 << 2)
2704 #define TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE_SHIFT 2
2705 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC (0x1 << 3)
2706 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RDMA_MAC_SHIFT 3
2707 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0 (0xF << 4)
2708 #define TSTORM_CAM_TARGET_TABLE_ENTRY_RESERVED0_SHIFT 4
2711 uint32_t clients_bit_vector;
2715 * MAC address in list for ramrod.
2717 struct mac_configuration_entry {
2718 struct tstorm_cam_entry cam_entry;
2719 struct tstorm_cam_target_table_entry target_table_entry;
2723 * MAC filtering configuration command.
2725 struct mac_configuration_cmd {
2726 struct mac_configuration_hdr hdr;
2727 struct mac_configuration_entry config_table[64];
2731 * MAC address in list for ramrod.
2733 struct mac_configuration_entry_e1h {
2734 uint16_t lsb_mac_addr;
2735 uint16_t middle_mac_addr;
2736 uint16_t msb_mac_addr;
2741 #define MAC_CONFIGURATION_ENTRY_E1H_PORT (0x1 << 0)
2742 #define MAC_CONFIGURATION_ENTRY_E1H_PORT_SHIFT 0
2743 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE (0x1 << 1)
2744 #define MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE_SHIFT 1
2745 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC (0x1 << 2)
2746 #define MAC_CONFIGURATION_ENTRY_E1H_RDMA_MAC_SHIFT 2
2747 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1 (0x1F << 3)
2748 #define MAC_CONFIGURATION_ENTRY_E1H_RESERVED1_SHIFT 3
2749 uint32_t clients_bit_vector;
2753 * MAC filtering configuration command.
2755 struct mac_configuration_cmd_e1h {
2756 struct mac_configuration_hdr hdr;
2757 struct mac_configuration_entry_e1h config_table[32];
2761 * Approximate-match multicast filtering for E1H per function in Tstorm.
2763 struct tstorm_eth_approximate_match_multicast_filtering {
2764 uint32_t mcast_add_hash_bit_array[8];
2768 * Configuration parameters per client in Tstorm.
2770 struct tstorm_eth_client_config {
2771 #if defined(__BIG_ENDIAN)
2773 uint8_t statistics_counter_id;
2775 #elif defined(__LITTLE_ENDIAN)
2777 uint8_t statistics_counter_id;
2780 #if defined(__BIG_ENDIAN)
2781 uint16_t drop_flags;
2782 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1 << 0)
2783 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2784 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1 << 1)
2785 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2786 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1 << 2)
2787 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2788 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1 << 3)
2789 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2790 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF << 4)
2791 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2792 uint16_t config_flags;
2793 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1 << 0)
2794 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2795 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1 << 1)
2796 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2797 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1 << 2)
2798 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2799 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF << 3)
2800 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2801 #elif defined(__LITTLE_ENDIAN)
2802 uint16_t config_flags;
2803 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE (0x1 << 0)
2804 #define TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE_SHIFT 0
2805 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE (0x1 << 1)
2806 #define TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE_SHIFT 1
2807 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE (0x1 << 2)
2808 #define TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE_SHIFT 2
2809 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1 (0x1FFF << 3)
2810 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED1_SHIFT 3
2811 uint16_t drop_flags;
2812 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR (0x1 << 0)
2813 #define TSTORM_ETH_CLIENT_CONFIG_DROP_IP_CS_ERR_SHIFT 0
2814 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR (0x1 << 1)
2815 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TCP_CS_ERR_SHIFT 1
2816 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0 (0x1 << 2)
2817 #define TSTORM_ETH_CLIENT_CONFIG_DROP_TTL0_SHIFT 2
2818 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR (0x1 << 3)
2819 #define TSTORM_ETH_CLIENT_CONFIG_DROP_UDP_CS_ERR_SHIFT 3
2820 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2 (0xFFF << 4)
2821 #define __TSTORM_ETH_CLIENT_CONFIG_RESERVED2_SHIFT 4
2826 * MAC filtering configuration parameters per port in Tstorm.
2828 struct tstorm_eth_mac_filter_config {
2829 uint32_t ucast_drop_all;
2830 uint32_t ucast_accept_all;
2831 uint32_t mcast_drop_all;
2832 uint32_t mcast_accept_all;
2833 uint32_t bcast_drop_all;
2834 uint32_t bcast_accept_all;
2835 uint32_t strict_vlan;
2836 uint32_t vlan_filter[2];
2842 * Common flag to indicate existance of TPA.
2844 struct tstorm_eth_tpa_exist {
2845 #if defined(__BIG_ENDIAN)
2849 #elif defined(__LITTLE_ENDIAN)
2858 * rx rings pause data for E1h only.
2860 struct ustorm_eth_rx_pause_data_e1h {
2861 #if defined(__BIG_ENDIAN)
2862 uint16_t bd_thr_low;
2863 uint16_t cqe_thr_low;
2864 #elif defined(__LITTLE_ENDIAN)
2865 uint16_t cqe_thr_low;
2866 uint16_t bd_thr_low;
2868 #if defined(__BIG_ENDIAN)
2870 uint16_t sge_thr_low;
2871 #elif defined(__LITTLE_ENDIAN)
2872 uint16_t sge_thr_low;
2875 #if defined(__BIG_ENDIAN)
2876 uint16_t bd_thr_high;
2877 uint16_t cqe_thr_high;
2878 #elif defined(__LITTLE_ENDIAN)
2879 uint16_t cqe_thr_high;
2880 uint16_t bd_thr_high;
2882 #if defined(__BIG_ENDIAN)
2884 uint16_t sge_thr_high;
2885 #elif defined(__LITTLE_ENDIAN)
2886 uint16_t sge_thr_high;
2892 * Three RX producers for ETH.
2894 struct ustorm_eth_rx_producers {
2895 #if defined(__BIG_ENDIAN)
2898 #elif defined(__LITTLE_ENDIAN)
2902 #if defined(__BIG_ENDIAN)
2905 #elif defined(__LITTLE_ENDIAN)
2912 * Per-port SAFC demo variables.
2914 struct cmng_flags_per_port {
2915 uint8_t con_number[NUM_OF_PROTOCOLS];
2916 uint32_t cmng_enables;
2917 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1 << 0)
2918 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
2919 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1 << 1)
2920 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
2921 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL (0x1 << 2)
2922 #define CMNG_FLAGS_PER_PORT_FAIRNESS_PROTOCOL_SHIFT 2
2923 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL (0x1 << 3)
2924 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_PROTOCOL_SHIFT 3
2925 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1 << 4)
2926 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 4
2927 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0x7FFFFFF << 5)
2928 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 5
2932 * Per-port rate shaping variables.
2934 struct rate_shaping_vars_per_port {
2935 uint32_t rs_periodic_timeout;
2936 uint32_t rs_threshold;
2940 * Per-port fairness variables.
2942 struct fairness_vars_per_port {
2943 uint32_t upper_bound;
2944 uint32_t fair_threshold;
2945 uint32_t fairness_timeout;
2949 * Per-port SAFC variables.
2951 struct safc_struct_per_port {
2952 #if defined(__BIG_ENDIAN)
2953 uint16_t __reserved1;
2954 uint8_t __reserved0;
2955 uint8_t safc_timeout_usec;
2956 #elif defined(__LITTLE_ENDIAN)
2957 uint8_t safc_timeout_usec;
2958 uint8_t __reserved0;
2959 uint16_t __reserved1;
2961 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS];
2965 * Per-port congestion management variables.
2967 struct cmng_struct_per_port {
2968 struct rate_shaping_vars_per_port rs_vars;
2969 struct fairness_vars_per_port fair_vars;
2970 struct safc_struct_per_port safc_vars;
2971 struct cmng_flags_per_port flags;
2975 * Dynamic host coalescing init parameters.
2977 struct dynamic_hc_config {
2978 uint32_t threshold[3];
2979 uint8_t shift_per_protocol[HC_USTORM_SB_NUM_INDICES];
2980 uint8_t hc_timeout0[HC_USTORM_SB_NUM_INDICES];
2981 uint8_t hc_timeout1[HC_USTORM_SB_NUM_INDICES];
2982 uint8_t hc_timeout2[HC_USTORM_SB_NUM_INDICES];
2983 uint8_t hc_timeout3[HC_USTORM_SB_NUM_INDICES];
2987 * Protocol-common statistics collected by the Xstorm (per client).
2989 struct xstorm_per_client_stats {
2991 uint32_t unicast_pkts_sent;
2992 struct regpair unicast_bytes_sent;
2993 struct regpair multicast_bytes_sent;
2994 uint32_t multicast_pkts_sent;
2995 uint32_t broadcast_pkts_sent;
2996 struct regpair broadcast_bytes_sent;
2997 uint16_t stats_counter;
3003 * Common statistics collected by the Xstorm (per port).
3005 struct xstorm_common_stats {
3006 struct xstorm_per_client_stats client_statistics[MAX_X_STAT_COUNTER_ID];
3010 * Protocol-common statistics collected by the Tstorm (per port).
3012 struct tstorm_per_port_stats {
3013 uint32_t mac_filter_discard;
3014 uint32_t xxoverflow_discard;
3015 uint32_t brb_truncate_discard;
3016 uint32_t mac_discard;
3020 * Protocol-common statistics collected by the Tstorm (per client).
3022 struct tstorm_per_client_stats {
3023 struct regpair rcv_unicast_bytes;
3024 struct regpair rcv_broadcast_bytes;
3025 struct regpair rcv_multicast_bytes;
3026 struct regpair rcv_error_bytes;
3027 uint32_t checksum_discard;
3028 uint32_t packets_too_big_discard;
3029 uint32_t rcv_unicast_pkts;
3030 uint32_t rcv_broadcast_pkts;
3031 uint32_t rcv_multicast_pkts;
3032 uint32_t no_buff_discard;
3033 uint32_t ttl0_discard;
3034 uint16_t stats_counter;
3039 * Protocol-common statistics collected by the Tstorm.
3041 struct tstorm_common_stats {
3042 struct tstorm_per_port_stats port_statistics;
3043 struct tstorm_per_client_stats client_statistics[MAX_T_STAT_COUNTER_ID];
3047 * Protocol-common statistics collected by the Ustorm (per client).
3049 struct ustorm_per_client_stats {
3050 struct regpair ucast_no_buff_bytes;
3051 struct regpair mcast_no_buff_bytes;
3052 struct regpair bcast_no_buff_bytes;
3053 uint32_t ucast_no_buff_pkts;
3054 uint32_t mcast_no_buff_pkts;
3055 uint32_t bcast_no_buff_pkts;
3056 uint16_t stats_counter;
3061 * Protocol-common statistics collected by the Ustorm.
3063 struct ustorm_common_stats {
3064 struct ustorm_per_client_stats client_statistics[MAX_U_STAT_COUNTER_ID];
3068 * Eth statistics query structure for the eth_stats_query ramrod.
3070 struct eth_stats_query {
3071 struct xstorm_common_stats xstorm_common;
3072 struct tstorm_common_stats tstorm_common;
3073 struct ustorm_common_stats ustorm_common;
3077 * Per-vnic fairness variables.
3079 struct fairness_vars_per_vn {
3080 uint32_t cos_credit_delta[MAX_COS_NUMBER];
3081 uint32_t protocol_credit_delta[NUM_OF_PROTOCOLS];
3082 uint32_t vn_credit_delta;
3083 uint32_t __reserved0;
3087 * FW version stored in the Xstorm RAM.
3090 #if defined(__BIG_ENDIAN)
3091 uint8_t engineering;
3095 #elif defined(__LITTLE_ENDIAN)
3099 uint8_t engineering;
3102 #define FW_VERSION_OPTIMIZED (0x1 << 0)
3103 #define FW_VERSION_OPTIMIZED_SHIFT 0
3104 #define FW_VERSION_BIG_ENDIEN (0x1 << 1)
3105 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
3106 #define FW_VERSION_CHIP_VERSION (0x3 << 2)
3107 #define FW_VERSION_CHIP_VERSION_SHIFT 2
3108 #define __FW_VERSION_RESERVED (0xFFFFFFF << 4)
3109 #define __FW_VERSION_RESERVED_SHIFT 4
3113 * FW version stored in first line of pram.
3115 struct pram_fw_version {
3119 uint8_t engineering;
3121 #define PRAM_FW_VERSION_OPTIMIZED (0x1 << 0)
3122 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
3123 #define PRAM_FW_VERSION_STORM_ID (0x3 << 1)
3124 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
3125 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1 << 3)
3126 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
3127 #define PRAM_FW_VERSION_CHIP_VERSION (0x3 << 4)
3128 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
3129 #define __PRAM_FW_VERSION_RESERVED0 (0x3 << 6)
3130 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
3134 * The send queue element.
3136 struct protocol_common_spe {
3138 struct regpair phy_address;
3142 * A single rate shaping counter. can be used as protocol or vnic counter.
3144 struct rate_shaping_counter {
3146 #if defined(__BIG_ENDIAN)
3147 uint16_t __reserved0;
3149 #elif defined(__LITTLE_ENDIAN)
3151 uint16_t __reserved0;
3156 * Per-vnic rate shaping variables.
3158 struct rate_shaping_vars_per_vn {
3159 struct rate_shaping_counter protocol_counters[NUM_OF_PROTOCOLS];
3160 struct rate_shaping_counter vn_counter;
3164 * The send queue element.
3166 struct slow_path_element {
3168 uint8_t protocol_data[8];
3172 * eth/toe flags that indicate if to query.
3174 struct stats_indication_flags {
3175 uint32_t collect_eth;
3176 uint32_t collect_toe;