2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
38 * bxe_init.h: Broadcom Everest network driver.
39 * Structures and macros needed during the initialization.
42 /* RAM0 size in bytes */
43 #define STORM_INTMEM_SIZE_E1 0x5800
44 #define STORM_INTMEM_SIZE_E1H 0x10000
45 #define STORM_INTMEM_SIZE(sc) \
46 ((CHIP_IS_E1(sc) ? STORM_INTMEM_SIZE_E1 : STORM_INTMEM_SIZE_E1H) / 4)
49 /* Init operation types and structures */
50 /* Common for both E1 and E1H */
51 #define OP_RD 0x1 /* read single register */
52 #define OP_WR 0x2 /* write single register */
53 #define OP_IW 0x3 /* write single register using mailbox */
54 #define OP_SW 0x4 /* copy a string to the device */
55 #define OP_SI 0x5 /* copy a string using mailbox */
56 #define OP_ZR 0x6 /* clear memory */
57 #define OP_ZP 0x7 /* unzip then copy with DMAE */
58 #define OP_WR_64 0x8 /* write 64 bit pattern */
59 #define OP_WB 0x9 /* copy a string using DMAE */
61 /* FPGA and EMUL specific operations */
62 #define OP_WR_EMUL 0xa /* write single register on Emulation */
63 #define OP_WR_FPGA 0xb /* write single register on FPGA */
64 #define OP_WR_ASIC 0xc /* write single register on ASIC */
67 /* Never reorder stages !!! */
68 #define COMMON_STAGE 0
78 #define FUNC7_STAGE 10
79 #define STAGE_IDX_MAX 11
85 /* Indices of blocks */
101 #define CSDM_BLOCK 15
102 #define USDM_BLOCK 16
105 #define USEM_BLOCK 19
106 #define CSEM_BLOCK 20
109 #define TIMERS_BLOCK 23
110 #define XSDM_BLOCK 24
114 #define XSEM_BLOCK 28
116 #define DMAE_BLOCK 30
120 #define PXP2_BLOCK 34
121 #define MISC_AEU_BLOCK 35
122 #define PGLUE_B_BLOCK 36
125 /* Returns the index of start or end of a specific block stage in ops array. */
126 #define BLOCK_OPS_IDX(block, stage, end) \
127 (2 * (((block) * STAGE_IDX_MAX) + (stage)) + (end))
147 struct op_string_write {
150 #ifdef __LITTLE_ENDIAN
153 #else /* __BIG_ENDIAN */
167 struct op_write write;
168 struct op_string_write str_wr;
173 #include "bxe_init_values_e1.h"
174 #include "bxe_init_values_e1h.h"
176 #endif /* BXE_INIT_H */