2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #ifndef ECORE_INIT_OPS_H
38 #define ECORE_INIT_OPS_H
49 static int ecore_gunzip(struct bxe_softc *sc, const uint8_t *zbuf, int len);
50 static void ecore_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, uint32_t val);
51 static void ecore_write_dmae_phys_len(struct bxe_softc *sc,
52 ecore_dma_addr_t phys_addr, uint32_t addr,
55 static void ecore_init_str_wr(struct bxe_softc *sc, uint32_t addr,
56 const uint32_t *data, uint32_t len)
60 for (i = 0; i < len; i++)
61 REG_WR(sc, addr + i*4, data[i]);
64 static void ecore_init_ind_wr(struct bxe_softc *sc, uint32_t addr,
65 const uint32_t *data, uint32_t len)
69 for (i = 0; i < len; i++)
70 ecore_reg_wr_ind(sc, addr + i*4, data[i]);
73 static void ecore_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len,
77 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
79 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
80 else if (wb && CHIP_IS_E1(sc))
81 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
83 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
85 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
88 static void ecore_init_fill(struct bxe_softc *sc, uint32_t addr, int fill,
89 uint32_t len, uint8_t wb)
91 uint32_t buf_len = (((len*4) > FW_BUF_SIZE) ? FW_BUF_SIZE : (len*4));
92 uint32_t buf_len32 = buf_len/4;
95 ECORE_MEMSET(GUNZIP_BUF(sc), (uint8_t)fill, buf_len);
97 for (i = 0; i < len; i += buf_len32) {
98 uint32_t cur_len = min(buf_len32, len - i);
100 ecore_write_big_buf(sc, addr + i*4, cur_len, wb);
104 static void ecore_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
107 ecore_write_dmae_phys_len(sc, GUNZIP_PHYS(sc), addr, len);
109 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
110 else if (CHIP_IS_E1(sc))
111 ecore_init_ind_wr(sc, addr, GUNZIP_BUF(sc), len);
113 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
115 ecore_init_str_wr(sc, addr, GUNZIP_BUF(sc), len);
118 static void ecore_init_wr_64(struct bxe_softc *sc, uint32_t addr,
119 const uint32_t *data, uint32_t len64)
121 uint32_t buf_len32 = FW_BUF_SIZE/4;
122 uint32_t len = len64*2;
126 /* 64 bit value is in a blob: first low DWORD, then high DWORD */
127 data64 = HILO_U64((*(data + 1)), (*data));
129 len64 = min((uint32_t)(FW_BUF_SIZE/8), len64);
130 for (i = 0; i < len64; i++) {
131 uint64_t *pdata = ((uint64_t *)(GUNZIP_BUF(sc))) + i;
136 for (i = 0; i < len; i += buf_len32) {
137 uint32_t cur_len = min(buf_len32, len - i);
139 ecore_write_big_buf_wb(sc, addr + i*4, cur_len);
143 /*********************************************************
144 There are different blobs for each PRAM section.
145 In addition, each blob write operation is divided into a few operations
146 in order to decrease the amount of phys. contiguous buffer needed.
147 Thus, when we select a blob the address may be with some offset
148 from the beginning of PRAM section.
149 The same holds for the INT_TABLE sections.
150 **********************************************************/
151 #define IF_IS_INT_TABLE_ADDR(base, addr) \
152 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
154 #define IF_IS_PRAM_ADDR(base, addr) \
155 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
157 static const uint8_t *ecore_sel_blob(struct bxe_softc *sc, uint32_t addr,
160 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
161 data = INIT_TSEM_INT_TABLE_DATA(sc);
163 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
164 data = INIT_CSEM_INT_TABLE_DATA(sc);
166 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
167 data = INIT_USEM_INT_TABLE_DATA(sc);
169 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
170 data = INIT_XSEM_INT_TABLE_DATA(sc);
172 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
173 data = INIT_TSEM_PRAM_DATA(sc);
175 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
176 data = INIT_CSEM_PRAM_DATA(sc);
178 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
179 data = INIT_USEM_PRAM_DATA(sc);
181 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
182 data = INIT_XSEM_PRAM_DATA(sc);
187 static void ecore_init_wr_wb(struct bxe_softc *sc, uint32_t addr,
188 const uint32_t *data, uint32_t len)
191 VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
193 /* in E1 chips BIOS initiated ZLR may interrupt widebus writes */
194 else if (CHIP_IS_E1(sc))
195 ecore_init_ind_wr(sc, addr, data, len);
197 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
199 ecore_init_str_wr(sc, addr, data, len);
202 #ifndef FW_ZIP_SUPPORT
203 static void ecore_init_fw(struct bxe_softc *sc, uint32_t addr, uint32_t len)
205 const uint8_t *data = NULL;
207 data = ecore_sel_blob(sc, addr, (const uint8_t *)data);
210 VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
212 /* in E1 BIOS initiated ZLR may interrupt widebus writes */
213 else if (CHIP_IS_E1(sc))
214 ecore_init_ind_wr(sc, addr, (const uint32_t *)data, len);
216 /* in later chips PXP root complex handles BIOS ZLR w/o interrupting */
218 ecore_init_str_wr(sc, addr, (const uint32_t *)data, len);
223 static void ecore_wr_64(struct bxe_softc *sc, uint32_t reg, uint32_t val_lo,
226 uint32_t wb_write[2];
228 wb_write[0] = val_lo;
229 wb_write[1] = val_hi;
230 REG_WR_DMAE_LEN(sc, reg, wb_write, 2);
233 static void ecore_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
236 const uint8_t *data = NULL;
240 data = ecore_sel_blob(sc, addr, data) + blob_off*4;
242 rc = ecore_gunzip(sc, data, len);
246 /* gunzip_outlen is in dwords */
247 len = GUNZIP_OUTLEN(sc);
248 for (i = 0; i < len; i++)
249 ((uint32_t *)GUNZIP_BUF(sc))[i] = (uint32_t)
250 ECORE_CPU_TO_LE32(((uint32_t *)GUNZIP_BUF(sc))[i]);
252 ecore_write_big_buf_wb(sc, addr, len);
255 static void ecore_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
258 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
261 INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
263 const union init_op *op;
264 uint32_t op_idx, op_type, addr, len;
265 const uint32_t *data, *data_base;
268 if (op_start == op_end)
271 data_base = INIT_DATA(sc);
273 for (op_idx = op_start; op_idx < op_end; op_idx++) {
275 op = (const union init_op *)&(INIT_OPS(sc)[op_idx]);
276 /* Get generic data */
277 op_type = op->raw.op;
278 addr = op->raw.offset;
279 /* Get data that's used for OP_SW, OP_WB, OP_FW, OP_ZP and
280 * OP_WR64 (we assume that op_arr_write and op_write have the
283 len = op->arr_wr.data_len;
284 data = data_base + op->arr_wr.data_off;
291 REG_WR(sc, addr, op->write.val);
294 ecore_init_str_wr(sc, addr, data, len);
297 ecore_init_wr_wb(sc, addr, data, len);
299 #ifndef FW_ZIP_SUPPORT
301 ecore_init_fw(sc, addr, len);
305 ecore_init_fill(sc, addr, 0, op->zero.len, 0);
308 ecore_init_fill(sc, addr, 0, op->zero.len, 1);
311 ecore_init_wr_zp(sc, addr, len,
312 op->arr_wr.data_off);
315 ecore_init_wr_64(sc, addr, data, len);
318 /* if any of the flags doesn't match, skip the
321 if ((INIT_MODE_FLAGS(sc) &
322 op->if_mode.mode_bit_map) !=
323 op->if_mode.mode_bit_map)
324 op_idx += op->if_mode.cmd_offset;
327 /* if all the flags don't match, skip the conditional
330 if ((INIT_MODE_FLAGS(sc) &
331 op->if_mode.mode_bit_map) == 0)
332 op_idx += op->if_mode.cmd_offset;
334 /* the following opcodes are unused at the moment. */
340 /* Should never get here! */
348 /****************************************************************************
350 ****************************************************************************/
352 * This code configures the PCI read/write arbiter
353 * which implements a weighted round robin
354 * between the virtual queues in the chip.
356 * The values were derived for each PCI max payload and max request size.
357 * since max payload and max request size are only known at run time,
358 * this is done as a separate init stage.
366 /* configuration for one arbiter queue */
373 /* derived configuration for each read queue for each max request size */
374 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
375 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
376 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
377 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
378 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
379 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
380 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
381 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
382 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
383 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
384 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
385 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
386 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
387 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
388 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
389 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
390 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
391 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
392 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
393 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
394 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
395 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
396 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
397 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
398 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
399 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
400 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
401 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
402 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
403 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
406 /* derived configuration for each write queue for each max request size */
407 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
408 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
409 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
410 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
411 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
412 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
413 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
414 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
415 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
416 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
417 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
418 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
419 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
420 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
423 /* register addresses for read queues */
424 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
425 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
426 PXP2_REG_RQ_BW_RD_UBOUND0},
427 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
428 PXP2_REG_PSWRQ_BW_UB1},
429 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
430 PXP2_REG_PSWRQ_BW_UB2},
431 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
432 PXP2_REG_PSWRQ_BW_UB3},
433 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
434 PXP2_REG_RQ_BW_RD_UBOUND4},
435 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
436 PXP2_REG_RQ_BW_RD_UBOUND5},
437 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
438 PXP2_REG_PSWRQ_BW_UB6},
439 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
440 PXP2_REG_PSWRQ_BW_UB7},
441 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
442 PXP2_REG_PSWRQ_BW_UB8},
443 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
444 PXP2_REG_PSWRQ_BW_UB9},
445 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
446 PXP2_REG_PSWRQ_BW_UB10},
447 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
448 PXP2_REG_PSWRQ_BW_UB11},
449 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
450 PXP2_REG_RQ_BW_RD_UBOUND12},
451 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
452 PXP2_REG_RQ_BW_RD_UBOUND13},
453 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
454 PXP2_REG_RQ_BW_RD_UBOUND14},
455 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
456 PXP2_REG_RQ_BW_RD_UBOUND15},
457 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
458 PXP2_REG_RQ_BW_RD_UBOUND16},
459 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
460 PXP2_REG_RQ_BW_RD_UBOUND17},
461 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
462 PXP2_REG_RQ_BW_RD_UBOUND18},
463 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
464 PXP2_REG_RQ_BW_RD_UBOUND19},
465 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
466 PXP2_REG_RQ_BW_RD_UBOUND20},
467 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
468 PXP2_REG_RQ_BW_RD_UBOUND22},
469 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
470 PXP2_REG_RQ_BW_RD_UBOUND23},
471 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
472 PXP2_REG_RQ_BW_RD_UBOUND24},
473 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
474 PXP2_REG_RQ_BW_RD_UBOUND25},
475 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
476 PXP2_REG_RQ_BW_RD_UBOUND26},
477 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
478 PXP2_REG_RQ_BW_RD_UBOUND27},
479 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
480 PXP2_REG_PSWRQ_BW_UB28}
483 /* register addresses for write queues */
484 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
485 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
486 PXP2_REG_PSWRQ_BW_UB1},
487 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
488 PXP2_REG_PSWRQ_BW_UB2},
489 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
490 PXP2_REG_PSWRQ_BW_UB3},
491 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
492 PXP2_REG_PSWRQ_BW_UB6},
493 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
494 PXP2_REG_PSWRQ_BW_UB7},
495 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
496 PXP2_REG_PSWRQ_BW_UB8},
497 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
498 PXP2_REG_PSWRQ_BW_UB9},
499 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
500 PXP2_REG_PSWRQ_BW_UB10},
501 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
502 PXP2_REG_PSWRQ_BW_UB11},
503 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
504 PXP2_REG_PSWRQ_BW_UB28},
505 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
506 PXP2_REG_RQ_BW_WR_UBOUND29},
507 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
508 PXP2_REG_RQ_BW_WR_UBOUND30}
511 static void ecore_init_pxp_arb(struct bxe_softc *sc, int r_order,
516 if (r_order > MAX_RD_ORD) {
517 ECORE_MSG(sc, "read order of %d order adjusted to %d\n",
518 r_order, MAX_RD_ORD);
519 r_order = MAX_RD_ORD;
521 if (w_order > MAX_WR_ORD) {
522 ECORE_MSG(sc, "write order of %d order adjusted to %d\n",
523 w_order, MAX_WR_ORD);
524 w_order = MAX_WR_ORD;
526 if (CHIP_REV_IS_FPGA(sc)) {
527 ECORE_MSG(sc, "write order adjusted to 1 for FPGA\n");
530 ECORE_MSG(sc, "read order %d write order %d\n", r_order, w_order);
532 for (i = 0; i < NUM_RD_Q-1; i++) {
533 REG_WR(sc, read_arb_addr[i].l, read_arb_data[i][r_order].l);
534 REG_WR(sc, read_arb_addr[i].add,
535 read_arb_data[i][r_order].add);
536 REG_WR(sc, read_arb_addr[i].ubound,
537 read_arb_data[i][r_order].ubound);
540 for (i = 0; i < NUM_WR_Q-1; i++) {
541 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
542 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
544 REG_WR(sc, write_arb_addr[i].l,
545 write_arb_data[i][w_order].l);
547 REG_WR(sc, write_arb_addr[i].add,
548 write_arb_data[i][w_order].add);
550 REG_WR(sc, write_arb_addr[i].ubound,
551 write_arb_data[i][w_order].ubound);
554 val = REG_RD(sc, write_arb_addr[i].l);
555 REG_WR(sc, write_arb_addr[i].l,
556 val | (write_arb_data[i][w_order].l << 10));
558 val = REG_RD(sc, write_arb_addr[i].add);
559 REG_WR(sc, write_arb_addr[i].add,
560 val | (write_arb_data[i][w_order].add << 10));
562 val = REG_RD(sc, write_arb_addr[i].ubound);
563 REG_WR(sc, write_arb_addr[i].ubound,
564 val | (write_arb_data[i][w_order].ubound << 7));
568 val = write_arb_data[NUM_WR_Q-1][w_order].add;
569 val += write_arb_data[NUM_WR_Q-1][w_order].ubound << 10;
570 val += write_arb_data[NUM_WR_Q-1][w_order].l << 17;
571 REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
573 val = read_arb_data[NUM_RD_Q-1][r_order].add;
574 val += read_arb_data[NUM_RD_Q-1][r_order].ubound << 10;
575 val += read_arb_data[NUM_RD_Q-1][r_order].l << 17;
576 REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
578 REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
579 REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
580 REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
581 REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
583 if ((CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) && (r_order == MAX_RD_ORD))
584 REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
587 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x4 << w_order));
588 else if (CHIP_IS_E2(sc))
589 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x8 << w_order));
591 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
593 if (!CHIP_IS_E1(sc)) {
594 /* MPS w_order optimal TH presently TH
599 /* DMAE is special */
600 if (!CHIP_IS_E1H(sc)) {
601 /* E2 can use optimal TH */
603 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, val);
605 val = ((w_order == 0) ? 2 : 3);
606 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2);
609 REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
610 REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
611 REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
612 REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
613 REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
614 REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
615 REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
616 REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
617 REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
618 REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
621 /* Validate number of tags suppoted by device */
622 #define PCIE_REG_PCIER_TL_HDR_FC_ST 0x2980
623 val = REG_RD(sc, PCIE_REG_PCIER_TL_HDR_FC_ST);
626 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x20);
629 /****************************************************************************
631 ****************************************************************************/
633 * This codes hides the low level HW interaction for ILT management and
634 * configuration. The API consists of a shadow ILT table which is set by the
635 * driver and a set of routines to use it to configure the HW.
639 /* ILT HW init operations */
641 /* ILT memory management operations */
642 #define ILT_MEMOP_ALLOC 0
643 #define ILT_MEMOP_FREE 1
645 /* the phys address is shifted right 12 bits and has an added
646 * 1=valid bit added to the 53rd bit
647 * then since this is a wide register(TM)
648 * we split it into two 32 bit writes
650 #define ILT_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
651 #define ILT_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
652 #define ILT_RANGE(f, l) (((l) << 10) | f)
654 static int ecore_ilt_line_mem_op(struct bxe_softc *sc,
655 struct ilt_line *line, uint32_t size, uint8_t memop)
657 if (memop == ILT_MEMOP_FREE) {
658 ECORE_ILT_FREE(line->page, line->page_mapping, line->size);
661 ECORE_ILT_ZALLOC(line->page, &line->page_mapping, size);
669 static int ecore_ilt_client_mem_op(struct bxe_softc *sc, int cli_num,
673 struct ecore_ilt *ilt = SC_ILT(sc);
674 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
676 if (!ilt || !ilt->lines)
679 if (ilt_cli->flags & (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM))
682 for (rc = 0, i = ilt_cli->start; i <= ilt_cli->end && !rc; i++) {
683 rc = ecore_ilt_line_mem_op(sc, &ilt->lines[i],
684 ilt_cli->page_size, memop);
689 static inline int ecore_ilt_mem_op_cnic(struct bxe_softc *sc, uint8_t memop)
693 if (CONFIGURE_NIC_MODE(sc))
694 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
696 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_TM, memop);
701 static int ecore_ilt_mem_op(struct bxe_softc *sc, uint8_t memop)
703 int rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_CDU, memop);
705 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_QM, memop);
706 if (!rc && CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
707 rc = ecore_ilt_client_mem_op(sc, ILT_CLIENT_SRC, memop);
712 static void ecore_ilt_line_wr(struct bxe_softc *sc, int abs_idx,
713 ecore_dma_addr_t page_mapping)
718 reg = PXP2_REG_RQ_ONCHIP_AT + abs_idx*8;
720 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + abs_idx*8;
722 ecore_wr_64(sc, reg, ILT_ADDR1(page_mapping), ILT_ADDR2(page_mapping));
725 static void ecore_ilt_line_init_op(struct bxe_softc *sc,
726 struct ecore_ilt *ilt, int idx, uint8_t initop)
728 ecore_dma_addr_t null_mapping;
729 int abs_idx = ilt->start_line + idx;
734 /* set in the init-value array */
736 ecore_ilt_line_wr(sc, abs_idx, ilt->lines[idx].page_mapping);
740 ecore_ilt_line_wr(sc, abs_idx, null_mapping);
745 static void ecore_ilt_boundry_init_op(struct bxe_softc *sc,
746 struct ilt_client_info *ilt_cli,
747 uint32_t ilt_start, uint8_t initop)
749 uint32_t start_reg = 0;
750 uint32_t end_reg = 0;
752 /* The boundary is either SET or INIT,
753 CLEAR => SET and for now SET ~~ INIT */
755 /* find the appropriate regs */
756 if (CHIP_IS_E1(sc)) {
757 switch (ilt_cli->client_num) {
759 start_reg = PXP2_REG_PSWRQ_CDU0_L2P;
762 start_reg = PXP2_REG_PSWRQ_QM0_L2P;
765 start_reg = PXP2_REG_PSWRQ_SRC0_L2P;
768 start_reg = PXP2_REG_PSWRQ_TM0_L2P;
771 REG_WR(sc, start_reg + SC_FUNC(sc)*4,
772 ILT_RANGE((ilt_start + ilt_cli->start),
773 (ilt_start + ilt_cli->end)));
775 switch (ilt_cli->client_num) {
777 start_reg = PXP2_REG_RQ_CDU_FIRST_ILT;
778 end_reg = PXP2_REG_RQ_CDU_LAST_ILT;
781 start_reg = PXP2_REG_RQ_QM_FIRST_ILT;
782 end_reg = PXP2_REG_RQ_QM_LAST_ILT;
785 start_reg = PXP2_REG_RQ_SRC_FIRST_ILT;
786 end_reg = PXP2_REG_RQ_SRC_LAST_ILT;
789 start_reg = PXP2_REG_RQ_TM_FIRST_ILT;
790 end_reg = PXP2_REG_RQ_TM_LAST_ILT;
793 REG_WR(sc, start_reg, (ilt_start + ilt_cli->start));
794 REG_WR(sc, end_reg, (ilt_start + ilt_cli->end));
798 static void ecore_ilt_client_init_op_ilt(struct bxe_softc *sc,
799 struct ecore_ilt *ilt,
800 struct ilt_client_info *ilt_cli,
805 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
808 for (i = ilt_cli->start; i <= ilt_cli->end; i++)
809 ecore_ilt_line_init_op(sc, ilt, i, initop);
811 /* init/clear the ILT boundries */
812 ecore_ilt_boundry_init_op(sc, ilt_cli, ilt->start_line, initop);
815 static void ecore_ilt_client_init_op(struct bxe_softc *sc,
816 struct ilt_client_info *ilt_cli, uint8_t initop)
818 struct ecore_ilt *ilt = SC_ILT(sc);
820 ecore_ilt_client_init_op_ilt(sc, ilt, ilt_cli, initop);
823 static void ecore_ilt_client_id_init_op(struct bxe_softc *sc,
824 int cli_num, uint8_t initop)
826 struct ecore_ilt *ilt = SC_ILT(sc);
827 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
829 ecore_ilt_client_init_op(sc, ilt_cli, initop);
832 static inline void ecore_ilt_init_op_cnic(struct bxe_softc *sc, uint8_t initop)
834 if (CONFIGURE_NIC_MODE(sc))
835 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
836 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_TM, initop);
839 static void ecore_ilt_init_op(struct bxe_softc *sc, uint8_t initop)
841 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_CDU, initop);
842 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_QM, initop);
843 if (CNIC_SUPPORT(sc) && !CONFIGURE_NIC_MODE(sc))
844 ecore_ilt_client_id_init_op(sc, ILT_CLIENT_SRC, initop);
847 static void ecore_ilt_init_client_psz(struct bxe_softc *sc, int cli_num,
848 uint32_t psz_reg, uint8_t initop)
850 struct ecore_ilt *ilt = SC_ILT(sc);
851 struct ilt_client_info *ilt_cli = &ilt->clients[cli_num];
853 if (ilt_cli->flags & ILT_CLIENT_SKIP_INIT)
858 /* set in the init-value array */
860 REG_WR(sc, psz_reg, ILOG2(ilt_cli->page_size >> 12));
868 * called during init common stage, ilt clients should be initialized
869 * prioir to calling this function
871 static void ecore_ilt_init_page_size(struct bxe_softc *sc, uint8_t initop)
873 ecore_ilt_init_client_psz(sc, ILT_CLIENT_CDU,
874 PXP2_REG_RQ_CDU_P_SIZE, initop);
875 ecore_ilt_init_client_psz(sc, ILT_CLIENT_QM,
876 PXP2_REG_RQ_QM_P_SIZE, initop);
877 ecore_ilt_init_client_psz(sc, ILT_CLIENT_SRC,
878 PXP2_REG_RQ_SRC_P_SIZE, initop);
879 ecore_ilt_init_client_psz(sc, ILT_CLIENT_TM,
880 PXP2_REG_RQ_TM_P_SIZE, initop);
883 /****************************************************************************
885 ****************************************************************************/
886 #define QM_QUEUES_PER_FUNC 16 /* E1 has 32, but only 16 are used */
887 #define QM_INIT_MIN_CID_COUNT 31
888 #define QM_INIT(cid_cnt) (cid_cnt > QM_INIT_MIN_CID_COUNT)
890 /* called during init port stage */
891 static void ecore_qm_init_cid_count(struct bxe_softc *sc, int qm_cid_count,
894 int port = SC_PORT(sc);
896 if (QM_INIT(qm_cid_count)) {
899 /* set in the init-value array */
901 REG_WR(sc, QM_REG_CONNNUM_0 + port*4,
902 qm_cid_count/16 - 1);
910 static void ecore_qm_set_ptr_table(struct bxe_softc *sc, int qm_cid_count,
911 uint32_t base_reg, uint32_t reg)
914 uint32_t wb_data[2] = {0, 0};
915 for (i = 0; i < 4 * QM_QUEUES_PER_FUNC; i++) {
916 REG_WR(sc, base_reg + i*4,
917 qm_cid_count * 4 * (i % QM_QUEUES_PER_FUNC));
918 ecore_init_wr_wb(sc, reg + i*8,
923 /* called during init common stage */
924 static void ecore_qm_init_ptr_table(struct bxe_softc *sc, int qm_cid_count,
927 if (!QM_INIT(qm_cid_count))
932 /* set in the init-value array */
934 ecore_qm_set_ptr_table(sc, qm_cid_count,
935 QM_REG_BASEADDR, QM_REG_PTRTBL);
937 ecore_qm_set_ptr_table(sc, qm_cid_count,
938 QM_REG_BASEADDR_EXT_A,
939 QM_REG_PTRTBL_EXT_A);
946 /****************************************************************************
947 * SRC initializations
948 ****************************************************************************/
950 /* called during init func stage */
951 static void ecore_src_init_t2(struct bxe_softc *sc, struct src_ent *t2,
952 ecore_dma_addr_t t2_mapping, int src_cid_count)
955 int port = SC_PORT(sc);
958 for (i = 0; i < src_cid_count-1; i++)
959 t2[i].next = (uint64_t)(t2_mapping +
960 (i+1)*sizeof(struct src_ent));
962 /* tell the searcher where the T2 table is */
963 REG_WR(sc, SRC_REG_COUNTFREE0 + port*4, src_cid_count);
965 ecore_wr_64(sc, SRC_REG_FIRSTFREE0 + port*16,
966 U64_LO(t2_mapping), U64_HI(t2_mapping));
968 ecore_wr_64(sc, SRC_REG_LASTFREE0 + port*16,
969 U64_LO((uint64_t)t2_mapping +
970 (src_cid_count-1) * sizeof(struct src_ent)),
971 U64_HI((uint64_t)t2_mapping +
972 (src_cid_count-1) * sizeof(struct src_ent)));
975 #endif /* ECORE_INIT_OPS_H */