2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved.
4 * Eric Davis <edavis@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
6 * Gary Zambrano <zambrano@broadcom.com>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written consent.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 #include "ecore_init.h"
40 /**** Exe Queue interfaces ****/
43 * ecore_exe_queue_init - init the Exe Queue object
45 * @o: pointer to the object
47 * @owner: pointer to the owner
48 * @validate: validate function pointer
49 * @optimize: optimize function pointer
50 * @exec: execute function pointer
51 * @get: get function pointer
53 static inline void ecore_exe_queue_init(struct bxe_softc *sc,
54 struct ecore_exe_queue_obj *o,
56 union ecore_qable_obj *owner,
57 exe_q_validate validate,
59 exe_q_optimize optimize,
63 ECORE_MEMSET(o, 0, sizeof(*o));
65 ECORE_LIST_INIT(&o->exe_queue);
66 ECORE_LIST_INIT(&o->pending_comp);
68 ECORE_SPIN_LOCK_INIT(&o->lock, sc);
70 o->exe_chunk_len = exe_len;
73 /* Owner specific callbacks */
74 o->validate = validate;
76 o->optimize = optimize;
80 ECORE_MSG(sc, "Setup the execution queue with the chunk length of %d\n",
84 static inline void ecore_exe_queue_free_elem(struct bxe_softc *sc,
85 struct ecore_exeq_elem *elem)
87 ECORE_MSG(sc, "Deleting an exe_queue element\n");
88 ECORE_FREE(sc, elem, sizeof(*elem));
91 static inline int ecore_exe_queue_length(struct ecore_exe_queue_obj *o)
93 struct ecore_exeq_elem *elem;
96 ECORE_SPIN_LOCK_BH(&o->lock);
98 ECORE_LIST_FOR_EACH_ENTRY(elem, &o->exe_queue, link,
99 struct ecore_exeq_elem)
102 ECORE_SPIN_UNLOCK_BH(&o->lock);
108 * ecore_exe_queue_add - add a new element to the execution queue
112 * @cmd: new command to add
113 * @restore: true - do not optimize the command
115 * If the element is optimized or is illegal, frees it.
117 static inline int ecore_exe_queue_add(struct bxe_softc *sc,
118 struct ecore_exe_queue_obj *o,
119 struct ecore_exeq_elem *elem,
124 ECORE_SPIN_LOCK_BH(&o->lock);
127 /* Try to cancel this element queue */
128 rc = o->optimize(sc, o->owner, elem);
132 /* Check if this request is ok */
133 rc = o->validate(sc, o->owner, elem);
135 ECORE_MSG(sc, "Preamble failed: %d\n", rc);
140 /* If so, add it to the execution queue */
141 ECORE_LIST_PUSH_TAIL(&elem->link, &o->exe_queue);
143 ECORE_SPIN_UNLOCK_BH(&o->lock);
145 return ECORE_SUCCESS;
148 ecore_exe_queue_free_elem(sc, elem);
150 ECORE_SPIN_UNLOCK_BH(&o->lock);
155 static inline void __ecore_exe_queue_reset_pending(
156 struct bxe_softc *sc,
157 struct ecore_exe_queue_obj *o)
159 struct ecore_exeq_elem *elem;
161 while (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) {
162 elem = ECORE_LIST_FIRST_ENTRY(&o->pending_comp,
163 struct ecore_exeq_elem,
166 ECORE_LIST_REMOVE_ENTRY(&elem->link, &o->pending_comp);
167 ecore_exe_queue_free_elem(sc, elem);
172 * ecore_exe_queue_step - execute one execution chunk atomically
176 * @ramrod_flags: flags
178 * (Should be called while holding the exe_queue->lock).
180 static inline int ecore_exe_queue_step(struct bxe_softc *sc,
181 struct ecore_exe_queue_obj *o,
182 unsigned long *ramrod_flags)
184 struct ecore_exeq_elem *elem, spacer;
187 ECORE_MEMSET(&spacer, 0, sizeof(spacer));
189 /* Next step should not be performed until the current is finished,
190 * unless a DRV_CLEAR_ONLY bit is set. In this case we just want to
191 * properly clear object internals without sending any command to the FW
192 * which also implies there won't be any completion to clear the
195 if (!ECORE_LIST_IS_EMPTY(&o->pending_comp)) {
196 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
197 ECORE_MSG(sc, "RAMROD_DRV_CLR_ONLY requested: resetting a pending_comp list\n");
198 __ecore_exe_queue_reset_pending(sc, o);
200 return ECORE_PENDING;
204 /* Run through the pending commands list and create a next
207 while (!ECORE_LIST_IS_EMPTY(&o->exe_queue)) {
208 elem = ECORE_LIST_FIRST_ENTRY(&o->exe_queue,
209 struct ecore_exeq_elem,
211 ECORE_DBG_BREAK_IF(!elem->cmd_len);
213 if (cur_len + elem->cmd_len <= o->exe_chunk_len) {
214 cur_len += elem->cmd_len;
215 /* Prevent from both lists being empty when moving an
216 * element. This will allow the call of
217 * ecore_exe_queue_empty() without locking.
219 ECORE_LIST_PUSH_TAIL(&spacer.link, &o->pending_comp);
221 ECORE_LIST_REMOVE_ENTRY(&elem->link, &o->exe_queue);
222 ECORE_LIST_PUSH_TAIL(&elem->link, &o->pending_comp);
223 ECORE_LIST_REMOVE_ENTRY(&spacer.link, &o->pending_comp);
230 return ECORE_SUCCESS;
232 rc = o->execute(sc, o->owner, &o->pending_comp, ramrod_flags);
234 /* In case of an error return the commands back to the queue
235 * and reset the pending_comp.
237 ECORE_LIST_SPLICE_INIT(&o->pending_comp, &o->exe_queue);
239 /* If zero is returned, means there are no outstanding pending
240 * completions and we may dismiss the pending list.
242 __ecore_exe_queue_reset_pending(sc, o);
247 static inline bool ecore_exe_queue_empty(struct ecore_exe_queue_obj *o)
249 bool empty = ECORE_LIST_IS_EMPTY(&o->exe_queue);
251 /* Don't reorder!!! */
254 return empty && ECORE_LIST_IS_EMPTY(&o->pending_comp);
257 static inline struct ecore_exeq_elem *ecore_exe_queue_alloc_elem(
258 struct bxe_softc *sc)
260 ECORE_MSG(sc, "Allocating a new exe_queue element\n");
261 return ECORE_ZALLOC(sizeof(struct ecore_exeq_elem), GFP_ATOMIC,
265 /************************ raw_obj functions ***********************************/
266 static bool ecore_raw_check_pending(struct ecore_raw_obj *o)
269 * !! converts the value returned by ECORE_TEST_BIT such that it
270 * is guaranteed not to be truncated regardless of bool definition.
272 * Note we cannot simply define the function's return value type
273 * to match the type returned by ECORE_TEST_BIT, as it varies by
274 * platform/implementation.
277 return !!ECORE_TEST_BIT(o->state, o->pstate);
280 static void ecore_raw_clear_pending(struct ecore_raw_obj *o)
282 ECORE_SMP_MB_BEFORE_CLEAR_BIT();
283 ECORE_CLEAR_BIT(o->state, o->pstate);
284 ECORE_SMP_MB_AFTER_CLEAR_BIT();
287 static void ecore_raw_set_pending(struct ecore_raw_obj *o)
289 ECORE_SMP_MB_BEFORE_CLEAR_BIT();
290 ECORE_SET_BIT(o->state, o->pstate);
291 ECORE_SMP_MB_AFTER_CLEAR_BIT();
295 * ecore_state_wait - wait until the given bit(state) is cleared
298 * @state: state which is to be cleared
299 * @state_p: state buffer
302 static inline int ecore_state_wait(struct bxe_softc *sc, int state,
303 unsigned long *pstate)
305 /* can take a while if any port is running */
309 if (CHIP_REV_IS_EMUL(sc))
312 ECORE_MSG(sc, "waiting for state to become %d\n", state);
316 if (!ECORE_TEST_BIT(state, pstate)) {
317 #ifdef ECORE_STOP_ON_ERROR
318 ECORE_MSG(sc, "exit (cnt %d)\n", 5000 - cnt);
320 return ECORE_SUCCESS;
323 ECORE_WAIT(sc, delay_us);
330 ECORE_ERR("timeout waiting for state %d\n", state);
331 #ifdef ECORE_STOP_ON_ERROR
335 return ECORE_TIMEOUT;
338 static int ecore_raw_wait(struct bxe_softc *sc, struct ecore_raw_obj *raw)
340 return ecore_state_wait(sc, raw->state, raw->pstate);
343 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
344 /* credit handling callbacks */
345 static bool ecore_get_cam_offset_mac(struct ecore_vlan_mac_obj *o, int *offset)
347 struct ecore_credit_pool_obj *mp = o->macs_pool;
349 ECORE_DBG_BREAK_IF(!mp);
351 return mp->get_entry(mp, offset);
354 static bool ecore_get_credit_mac(struct ecore_vlan_mac_obj *o)
356 struct ecore_credit_pool_obj *mp = o->macs_pool;
358 ECORE_DBG_BREAK_IF(!mp);
360 return mp->get(mp, 1);
363 static bool ecore_get_cam_offset_vlan(struct ecore_vlan_mac_obj *o, int *offset)
365 struct ecore_credit_pool_obj *vp = o->vlans_pool;
367 ECORE_DBG_BREAK_IF(!vp);
369 return vp->get_entry(vp, offset);
372 static bool ecore_get_credit_vlan(struct ecore_vlan_mac_obj *o)
374 struct ecore_credit_pool_obj *vp = o->vlans_pool;
376 ECORE_DBG_BREAK_IF(!vp);
378 return vp->get(vp, 1);
381 static bool ecore_get_credit_vlan_mac(struct ecore_vlan_mac_obj *o)
383 struct ecore_credit_pool_obj *mp = o->macs_pool;
384 struct ecore_credit_pool_obj *vp = o->vlans_pool;
389 if (!vp->get(vp, 1)) {
397 static bool ecore_put_cam_offset_mac(struct ecore_vlan_mac_obj *o, int offset)
399 struct ecore_credit_pool_obj *mp = o->macs_pool;
401 return mp->put_entry(mp, offset);
404 static bool ecore_put_credit_mac(struct ecore_vlan_mac_obj *o)
406 struct ecore_credit_pool_obj *mp = o->macs_pool;
408 return mp->put(mp, 1);
411 static bool ecore_put_cam_offset_vlan(struct ecore_vlan_mac_obj *o, int offset)
413 struct ecore_credit_pool_obj *vp = o->vlans_pool;
415 return vp->put_entry(vp, offset);
418 static bool ecore_put_credit_vlan(struct ecore_vlan_mac_obj *o)
420 struct ecore_credit_pool_obj *vp = o->vlans_pool;
422 return vp->put(vp, 1);
425 static bool ecore_put_credit_vlan_mac(struct ecore_vlan_mac_obj *o)
427 struct ecore_credit_pool_obj *mp = o->macs_pool;
428 struct ecore_credit_pool_obj *vp = o->vlans_pool;
433 if (!vp->put(vp, 1)) {
442 * __ecore_vlan_mac_h_write_trylock - try getting the writer lock on vlan mac
446 * @o: vlan_mac object
448 * @details: Non-blocking implementation; should be called under execution
451 static int __ecore_vlan_mac_h_write_trylock(struct bxe_softc *sc,
452 struct ecore_vlan_mac_obj *o)
454 if (o->head_reader) {
455 ECORE_MSG(sc, "vlan_mac_lock writer - There are readers; Busy\n");
459 ECORE_MSG(sc, "vlan_mac_lock writer - Taken\n");
460 return ECORE_SUCCESS;
464 * __ecore_vlan_mac_h_exec_pending - execute step instead of a previous step
465 * which wasn't able to run due to a taken lock on vlan mac head list.
468 * @o: vlan_mac object
470 * @details Should be called under execution queue lock; notice it might release
471 * and reclaim it during its run.
473 static void __ecore_vlan_mac_h_exec_pending(struct bxe_softc *sc,
474 struct ecore_vlan_mac_obj *o)
477 unsigned long ramrod_flags = o->saved_ramrod_flags;
479 ECORE_MSG(sc, "vlan_mac_lock execute pending command with ramrod flags %lu\n",
481 o->head_exe_request = FALSE;
482 o->saved_ramrod_flags = 0;
483 rc = ecore_exe_queue_step(sc, &o->exe_queue, &ramrod_flags);
484 if (rc != ECORE_SUCCESS) {
485 ECORE_ERR("execution of pending commands failed with rc %d\n",
487 #ifdef ECORE_STOP_ON_ERROR
494 * __ecore_vlan_mac_h_pend - Pend an execution step which couldn't have been
495 * called due to vlan mac head list lock being taken.
498 * @o: vlan_mac object
499 * @ramrod_flags: ramrod flags of missed execution
501 * @details Should be called under execution queue lock.
503 static void __ecore_vlan_mac_h_pend(struct bxe_softc *sc,
504 struct ecore_vlan_mac_obj *o,
505 unsigned long ramrod_flags)
507 o->head_exe_request = TRUE;
508 o->saved_ramrod_flags = ramrod_flags;
509 ECORE_MSG(sc, "Placing pending execution with ramrod flags %lu\n",
514 * __ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock
517 * @o: vlan_mac object
519 * @details Should be called under execution queue lock. Notice if a pending
520 * execution exists, it would perform it - possibly releasing and
521 * reclaiming the execution queue lock.
523 static void __ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc,
524 struct ecore_vlan_mac_obj *o)
526 /* It's possible a new pending execution was added since this writer
527 * executed. If so, execute again. [Ad infinitum]
529 while(o->head_exe_request) {
530 ECORE_MSG(sc, "vlan_mac_lock - writer release encountered a pending request\n");
531 __ecore_vlan_mac_h_exec_pending(sc, o);
536 * ecore_vlan_mac_h_write_unlock - unlock the vlan mac head list writer lock
539 * @o: vlan_mac object
541 * @details Notice if a pending execution exists, it would perform it -
542 * possibly releasing and reclaiming the execution queue lock.
544 void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc,
545 struct ecore_vlan_mac_obj *o)
547 ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
548 __ecore_vlan_mac_h_write_unlock(sc, o);
549 ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);
553 * __ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
556 * @o: vlan_mac object
558 * @details Should be called under the execution queue lock. May sleep. May
559 * release and reclaim execution queue lock during its run.
561 static int __ecore_vlan_mac_h_read_lock(struct bxe_softc *sc,
562 struct ecore_vlan_mac_obj *o)
564 /* If we got here, we're holding lock --> no WRITER exists */
566 ECORE_MSG(sc, "vlan_mac_lock - locked reader - number %d\n",
569 return ECORE_SUCCESS;
573 * ecore_vlan_mac_h_read_lock - lock the vlan mac head list reader lock
576 * @o: vlan_mac object
578 * @details May sleep. Claims and releases execution queue lock during its run.
580 int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc,
581 struct ecore_vlan_mac_obj *o)
585 ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
586 rc = __ecore_vlan_mac_h_read_lock(sc, o);
587 ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);
593 * __ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
596 * @o: vlan_mac object
598 * @details Should be called under execution queue lock. Notice if a pending
599 * execution exists, it would be performed if this was the last
600 * reader. possibly releasing and reclaiming the execution queue lock.
602 static void __ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc,
603 struct ecore_vlan_mac_obj *o)
605 if (!o->head_reader) {
606 ECORE_ERR("Need to release vlan mac reader lock, but lock isn't taken\n");
607 #ifdef ECORE_STOP_ON_ERROR
612 ECORE_MSG(sc, "vlan_mac_lock - decreased readers to %d\n",
616 /* It's possible a new pending execution was added, and that this reader
617 * was last - if so we need to execute the command.
619 if (!o->head_reader && o->head_exe_request) {
620 ECORE_MSG(sc, "vlan_mac_lock - reader release encountered a pending request\n");
622 /* Writer release will do the trick */
623 __ecore_vlan_mac_h_write_unlock(sc, o);
628 * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
631 * @o: vlan_mac object
633 * @details Notice if a pending execution exists, it would be performed if this
634 * was the last reader. Claims and releases the execution queue lock
637 void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc,
638 struct ecore_vlan_mac_obj *o)
640 ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
641 __ecore_vlan_mac_h_read_unlock(sc, o);
642 ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);
646 * ecore_vlan_mac_h_read_unlock - unlock the vlan mac head list reader lock
649 * @o: vlan_mac object
650 * @n: number of elements to get
651 * @base: base address for element placement
652 * @stride: stride between elements (in bytes)
654 static int ecore_get_n_elements(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o,
655 int n, uint8_t *base, uint8_t stride, uint8_t size)
657 struct ecore_vlan_mac_registry_elem *pos;
658 uint8_t *next = base;
662 ECORE_MSG(sc, "get_n_elements - taking vlan_mac_lock (reader)\n");
663 read_lock = ecore_vlan_mac_h_read_lock(sc, o);
664 if (read_lock != ECORE_SUCCESS)
665 ECORE_ERR("get_n_elements failed to get vlan mac reader lock; Access without lock\n");
668 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
669 struct ecore_vlan_mac_registry_elem) {
671 ECORE_MEMCPY(next, &pos->u, size);
673 ECORE_MSG(sc, "copied element number %d to address %p element was:\n",
675 next += stride + size;
679 if (read_lock == ECORE_SUCCESS) {
680 ECORE_MSG(sc, "get_n_elements - releasing vlan_mac_lock (reader)\n");
681 ecore_vlan_mac_h_read_unlock(sc, o);
684 return counter * ETH_ALEN;
687 /* check_add() callbacks */
688 static int ecore_check_mac_add(struct bxe_softc *sc,
689 struct ecore_vlan_mac_obj *o,
690 union ecore_classification_ramrod_data *data)
692 struct ecore_vlan_mac_registry_elem *pos;
694 ECORE_MSG(sc, "Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for ADD command\n", data->mac.mac[0], data->mac.mac[1], data->mac.mac[2], data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);
696 if (!ECORE_IS_VALID_ETHER_ADDR(data->mac.mac))
699 /* Check if a requested MAC already exists */
700 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
701 struct ecore_vlan_mac_registry_elem)
702 if (!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN) &&
703 (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
706 return ECORE_SUCCESS;
709 static int ecore_check_vlan_add(struct bxe_softc *sc,
710 struct ecore_vlan_mac_obj *o,
711 union ecore_classification_ramrod_data *data)
713 struct ecore_vlan_mac_registry_elem *pos;
715 ECORE_MSG(sc, "Checking VLAN %d for ADD command\n", data->vlan.vlan);
717 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
718 struct ecore_vlan_mac_registry_elem)
719 if (data->vlan.vlan == pos->u.vlan.vlan)
722 return ECORE_SUCCESS;
725 static int ecore_check_vlan_mac_add(struct bxe_softc *sc,
726 struct ecore_vlan_mac_obj *o,
727 union ecore_classification_ramrod_data *data)
729 struct ecore_vlan_mac_registry_elem *pos;
731 ECORE_MSG(sc, "Checking VLAN_MAC (%02x:%02x:%02x:%02x:%02x:%02x, %d) for ADD command\n",
732 data->vlan_mac.mac[0], data->vlan_mac.mac[1], data->vlan_mac.mac[2], data->vlan_mac.mac[3], data->vlan_mac.mac[4], data->vlan_mac.mac[5], data->vlan_mac.vlan);
734 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
735 struct ecore_vlan_mac_registry_elem)
736 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
737 (!ECORE_MEMCMP(data->vlan_mac.mac, pos->u.vlan_mac.mac,
739 (data->vlan_mac.is_inner_mac ==
740 pos->u.vlan_mac.is_inner_mac))
743 return ECORE_SUCCESS;
746 /* check_del() callbacks */
747 static struct ecore_vlan_mac_registry_elem *
748 ecore_check_mac_del(struct bxe_softc *sc,
749 struct ecore_vlan_mac_obj *o,
750 union ecore_classification_ramrod_data *data)
752 struct ecore_vlan_mac_registry_elem *pos;
754 ECORE_MSG(sc, "Checking MAC %02x:%02x:%02x:%02x:%02x:%02x for DEL command\n", data->mac.mac[0], data->mac.mac[1], data->mac.mac[2], data->mac.mac[3], data->mac.mac[4], data->mac.mac[5]);
756 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
757 struct ecore_vlan_mac_registry_elem)
758 if ((!ECORE_MEMCMP(data->mac.mac, pos->u.mac.mac, ETH_ALEN)) &&
759 (data->mac.is_inner_mac == pos->u.mac.is_inner_mac))
765 static struct ecore_vlan_mac_registry_elem *
766 ecore_check_vlan_del(struct bxe_softc *sc,
767 struct ecore_vlan_mac_obj *o,
768 union ecore_classification_ramrod_data *data)
770 struct ecore_vlan_mac_registry_elem *pos;
772 ECORE_MSG(sc, "Checking VLAN %d for DEL command\n", data->vlan.vlan);
774 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
775 struct ecore_vlan_mac_registry_elem)
776 if (data->vlan.vlan == pos->u.vlan.vlan)
782 static struct ecore_vlan_mac_registry_elem *
783 ecore_check_vlan_mac_del(struct bxe_softc *sc,
784 struct ecore_vlan_mac_obj *o,
785 union ecore_classification_ramrod_data *data)
787 struct ecore_vlan_mac_registry_elem *pos;
789 ECORE_MSG(sc, "Checking VLAN_MAC (%02x:%02x:%02x:%02x:%02x:%02x, %d) for DEL command\n",
790 data->vlan_mac.mac[0], data->vlan_mac.mac[1], data->vlan_mac.mac[2], data->vlan_mac.mac[3], data->vlan_mac.mac[4], data->vlan_mac.mac[5], data->vlan_mac.vlan);
792 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
793 struct ecore_vlan_mac_registry_elem)
794 if ((data->vlan_mac.vlan == pos->u.vlan_mac.vlan) &&
795 (!ECORE_MEMCMP(data->vlan_mac.mac, pos->u.vlan_mac.mac,
797 (data->vlan_mac.is_inner_mac ==
798 pos->u.vlan_mac.is_inner_mac))
804 /* check_move() callback */
805 static bool ecore_check_move(struct bxe_softc *sc,
806 struct ecore_vlan_mac_obj *src_o,
807 struct ecore_vlan_mac_obj *dst_o,
808 union ecore_classification_ramrod_data *data)
810 struct ecore_vlan_mac_registry_elem *pos;
813 /* Check if we can delete the requested configuration from the first
816 pos = src_o->check_del(sc, src_o, data);
818 /* check if configuration can be added */
819 rc = dst_o->check_add(sc, dst_o, data);
821 /* If this classification can not be added (is already set)
822 * or can't be deleted - return an error.
830 static bool ecore_check_move_always_err(
831 struct bxe_softc *sc,
832 struct ecore_vlan_mac_obj *src_o,
833 struct ecore_vlan_mac_obj *dst_o,
834 union ecore_classification_ramrod_data *data)
839 static inline uint8_t ecore_vlan_mac_get_rx_tx_flag(struct ecore_vlan_mac_obj *o)
841 struct ecore_raw_obj *raw = &o->raw;
842 uint8_t rx_tx_flag = 0;
844 if ((raw->obj_type == ECORE_OBJ_TYPE_TX) ||
845 (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))
846 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_TX_CMD;
848 if ((raw->obj_type == ECORE_OBJ_TYPE_RX) ||
849 (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))
850 rx_tx_flag |= ETH_CLASSIFY_CMD_HEADER_RX_CMD;
855 void ecore_set_mac_in_nig(struct bxe_softc *sc,
856 bool add, unsigned char *dev_addr, int index)
859 uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM :
860 NIG_REG_LLH0_FUNC_MEM;
862 if (!ECORE_IS_MF_SI_MODE(sc) && !IS_MF_AFEX(sc))
865 if (index > ECORE_LLH_CAM_MAX_PF_LINE)
868 ECORE_MSG(sc, "Going to %s LLH configuration at entry %d\n",
869 (add ? "ADD" : "DELETE"), index);
872 /* LLH_FUNC_MEM is a uint64_t WB register */
873 reg_offset += 8*index;
875 wb_data[0] = ((dev_addr[2] << 24) | (dev_addr[3] << 16) |
876 (dev_addr[4] << 8) | dev_addr[5]);
877 wb_data[1] = ((dev_addr[0] << 8) | dev_addr[1]);
879 ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2);
882 REG_WR(sc, (ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM_ENABLE :
883 NIG_REG_LLH0_FUNC_MEM_ENABLE) + 4*index, add);
887 * ecore_vlan_mac_set_cmd_hdr_e2 - set a header in a single classify ramrod
890 * @o: queue for which we want to configure this rule
891 * @add: if TRUE the command is an ADD command, DEL otherwise
892 * @opcode: CLASSIFY_RULE_OPCODE_XXX
893 * @hdr: pointer to a header to setup
896 static inline void ecore_vlan_mac_set_cmd_hdr_e2(struct bxe_softc *sc,
897 struct ecore_vlan_mac_obj *o, bool add, int opcode,
898 struct eth_classify_cmd_header *hdr)
900 struct ecore_raw_obj *raw = &o->raw;
902 hdr->client_id = raw->cl_id;
903 hdr->func_id = raw->func_id;
905 /* Rx or/and Tx (internal switching) configuration ? */
906 hdr->cmd_general_data |=
907 ecore_vlan_mac_get_rx_tx_flag(o);
910 hdr->cmd_general_data |= ETH_CLASSIFY_CMD_HEADER_IS_ADD;
912 hdr->cmd_general_data |=
913 (opcode << ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT);
917 * ecore_vlan_mac_set_rdata_hdr_e2 - set the classify ramrod data header
919 * @cid: connection id
920 * @type: ECORE_FILTER_XXX_PENDING
921 * @hdr: pointer to header to setup
924 * currently we always configure one rule and echo field to contain a CID and an
927 static inline void ecore_vlan_mac_set_rdata_hdr_e2(uint32_t cid, int type,
928 struct eth_classify_header *hdr, int rule_cnt)
930 hdr->echo = ECORE_CPU_TO_LE32((cid & ECORE_SWCID_MASK) |
931 (type << ECORE_SWCID_SHIFT));
932 hdr->rule_cnt = (uint8_t)rule_cnt;
935 /* hw_config() callbacks */
936 static void ecore_set_one_mac_e2(struct bxe_softc *sc,
937 struct ecore_vlan_mac_obj *o,
938 struct ecore_exeq_elem *elem, int rule_idx,
941 struct ecore_raw_obj *raw = &o->raw;
942 struct eth_classify_rules_ramrod_data *data =
943 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
944 int rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;
945 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
946 bool add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE;
947 unsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;
948 uint8_t *mac = elem->cmd_data.vlan_mac.u.mac.mac;
950 /* Set LLH CAM entry: currently only iSCSI and ETH macs are
951 * relevant. In addition, current implementation is tuned for a
954 * When multiple unicast ETH MACs PF configuration in switch
955 * independent mode is required (NetQ, multiple netdev MACs,
956 * etc.), consider better utilisation of 8 per function MAC
957 * entries in the LLH register. There is also
958 * NIG_REG_P[01]_LLH_FUNC_MEM2 registers that complete the
959 * total number of CAM entries to 16.
961 * Currently we won't configure NIG for MACs other than a primary ETH
962 * MAC and iSCSI L2 MAC.
964 * If this MAC is moving from one Queue to another, no need to change
967 if (cmd != ECORE_VLAN_MAC_MOVE) {
968 if (ECORE_TEST_BIT(ECORE_ISCSI_ETH_MAC, vlan_mac_flags))
969 ecore_set_mac_in_nig(sc, add, mac,
970 ECORE_LLH_CAM_ISCSI_ETH_LINE);
971 else if (ECORE_TEST_BIT(ECORE_ETH_MAC, vlan_mac_flags))
972 ecore_set_mac_in_nig(sc, add, mac,
973 ECORE_LLH_CAM_ETH_LINE);
976 /* Reset the ramrod data buffer for the first rule */
978 ECORE_MEMSET(data, 0, sizeof(*data));
980 /* Setup a command header */
981 ecore_vlan_mac_set_cmd_hdr_e2(sc, o, add, CLASSIFY_RULE_OPCODE_MAC,
982 &rule_entry->mac.header);
984 ECORE_MSG(sc, "About to %s MAC %02x:%02x:%02x:%02x:%02x:%02x for Queue %d\n",
985 (add ? "add" : "delete"), mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], raw->cl_id);
987 /* Set a MAC itself */
988 ecore_set_fw_mac_addr(&rule_entry->mac.mac_msb,
989 &rule_entry->mac.mac_mid,
990 &rule_entry->mac.mac_lsb, mac);
991 rule_entry->mac.inner_mac =
992 elem->cmd_data.vlan_mac.u.mac.is_inner_mac;
994 /* MOVE: Add a rule that will add this MAC to the target Queue */
995 if (cmd == ECORE_VLAN_MAC_MOVE) {
999 /* Setup ramrod data */
1000 ecore_vlan_mac_set_cmd_hdr_e2(sc,
1001 elem->cmd_data.vlan_mac.target_obj,
1002 TRUE, CLASSIFY_RULE_OPCODE_MAC,
1003 &rule_entry->mac.header);
1005 /* Set a MAC itself */
1006 ecore_set_fw_mac_addr(&rule_entry->mac.mac_msb,
1007 &rule_entry->mac.mac_mid,
1008 &rule_entry->mac.mac_lsb, mac);
1009 rule_entry->mac.inner_mac =
1010 elem->cmd_data.vlan_mac.u.mac.is_inner_mac;
1013 /* Set the ramrod data header */
1014 /* TODO: take this to the higher level in order to prevent multiple
1016 ecore_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1021 * ecore_vlan_mac_set_rdata_hdr_e1x - set a header in a single classify ramrod
1023 * @sc: device handle
1026 * @cam_offset: offset in cam memory
1027 * @hdr: pointer to a header to setup
1031 static inline void ecore_vlan_mac_set_rdata_hdr_e1x(struct bxe_softc *sc,
1032 struct ecore_vlan_mac_obj *o, int type, int cam_offset,
1033 struct mac_configuration_hdr *hdr)
1035 struct ecore_raw_obj *r = &o->raw;
1038 hdr->offset = (uint8_t)cam_offset;
1039 hdr->client_id = ECORE_CPU_TO_LE16(0xff);
1040 hdr->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |
1041 (type << ECORE_SWCID_SHIFT));
1044 static inline void ecore_vlan_mac_set_cfg_entry_e1x(struct bxe_softc *sc,
1045 struct ecore_vlan_mac_obj *o, bool add, int opcode, uint8_t *mac,
1046 uint16_t vlan_id, struct mac_configuration_entry *cfg_entry)
1048 struct ecore_raw_obj *r = &o->raw;
1049 uint32_t cl_bit_vec = (1 << r->cl_id);
1051 cfg_entry->clients_bit_vector = ECORE_CPU_TO_LE32(cl_bit_vec);
1052 cfg_entry->pf_id = r->func_id;
1053 cfg_entry->vlan_id = ECORE_CPU_TO_LE16(vlan_id);
1056 ECORE_SET_FLAG(cfg_entry->flags,
1057 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1058 T_ETH_MAC_COMMAND_SET);
1059 ECORE_SET_FLAG(cfg_entry->flags,
1060 MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE,
1063 /* Set a MAC in a ramrod data */
1064 ecore_set_fw_mac_addr(&cfg_entry->msb_mac_addr,
1065 &cfg_entry->middle_mac_addr,
1066 &cfg_entry->lsb_mac_addr, mac);
1068 ECORE_SET_FLAG(cfg_entry->flags,
1069 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
1070 T_ETH_MAC_COMMAND_INVALIDATE);
1073 static inline void ecore_vlan_mac_set_rdata_e1x(struct bxe_softc *sc,
1074 struct ecore_vlan_mac_obj *o, int type, int cam_offset, bool add,
1075 uint8_t *mac, uint16_t vlan_id, int opcode, struct mac_configuration_cmd *config)
1077 struct mac_configuration_entry *cfg_entry = &config->config_table[0];
1078 struct ecore_raw_obj *raw = &o->raw;
1080 ecore_vlan_mac_set_rdata_hdr_e1x(sc, o, type, cam_offset,
1082 ecore_vlan_mac_set_cfg_entry_e1x(sc, o, add, opcode, mac, vlan_id,
1085 ECORE_MSG(sc, "%s MAC %02x:%02x:%02x:%02x:%02x:%02x CLID %d CAM offset %d\n",
1086 (add ? "setting" : "clearing"),
1087 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5], raw->cl_id, cam_offset);
1091 * ecore_set_one_mac_e1x - fill a single MAC rule ramrod data
1093 * @sc: device handle
1094 * @o: ecore_vlan_mac_obj
1095 * @elem: ecore_exeq_elem
1096 * @rule_idx: rule_idx
1097 * @cam_offset: cam_offset
1099 static void ecore_set_one_mac_e1x(struct bxe_softc *sc,
1100 struct ecore_vlan_mac_obj *o,
1101 struct ecore_exeq_elem *elem, int rule_idx,
1104 struct ecore_raw_obj *raw = &o->raw;
1105 struct mac_configuration_cmd *config =
1106 (struct mac_configuration_cmd *)(raw->rdata);
1107 /* 57710 and 57711 do not support MOVE command,
1108 * so it's either ADD or DEL
1110 bool add = (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?
1113 /* Reset the ramrod data buffer */
1114 ECORE_MEMSET(config, 0, sizeof(*config));
1116 ecore_vlan_mac_set_rdata_e1x(sc, o, raw->state,
1118 elem->cmd_data.vlan_mac.u.mac.mac, 0,
1119 ETH_VLAN_FILTER_ANY_VLAN, config);
1122 static void ecore_set_one_vlan_e2(struct bxe_softc *sc,
1123 struct ecore_vlan_mac_obj *o,
1124 struct ecore_exeq_elem *elem, int rule_idx,
1127 struct ecore_raw_obj *raw = &o->raw;
1128 struct eth_classify_rules_ramrod_data *data =
1129 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1130 int rule_cnt = rule_idx + 1;
1131 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1132 enum ecore_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1133 bool add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE;
1134 uint16_t vlan = elem->cmd_data.vlan_mac.u.vlan.vlan;
1136 /* Reset the ramrod data buffer for the first rule */
1138 ECORE_MEMSET(data, 0, sizeof(*data));
1140 /* Set a rule header */
1141 ecore_vlan_mac_set_cmd_hdr_e2(sc, o, add, CLASSIFY_RULE_OPCODE_VLAN,
1142 &rule_entry->vlan.header);
1144 ECORE_MSG(sc, "About to %s VLAN %d\n", (add ? "add" : "delete"),
1147 /* Set a VLAN itself */
1148 rule_entry->vlan.vlan = ECORE_CPU_TO_LE16(vlan);
1150 /* MOVE: Add a rule that will add this MAC to the target Queue */
1151 if (cmd == ECORE_VLAN_MAC_MOVE) {
1155 /* Setup ramrod data */
1156 ecore_vlan_mac_set_cmd_hdr_e2(sc,
1157 elem->cmd_data.vlan_mac.target_obj,
1158 TRUE, CLASSIFY_RULE_OPCODE_VLAN,
1159 &rule_entry->vlan.header);
1161 /* Set a VLAN itself */
1162 rule_entry->vlan.vlan = ECORE_CPU_TO_LE16(vlan);
1165 /* Set the ramrod data header */
1166 /* TODO: take this to the higher level in order to prevent multiple
1168 ecore_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1172 static void ecore_set_one_vlan_mac_e2(struct bxe_softc *sc,
1173 struct ecore_vlan_mac_obj *o,
1174 struct ecore_exeq_elem *elem,
1175 int rule_idx, int cam_offset)
1177 struct ecore_raw_obj *raw = &o->raw;
1178 struct eth_classify_rules_ramrod_data *data =
1179 (struct eth_classify_rules_ramrod_data *)(raw->rdata);
1180 int rule_cnt = rule_idx + 1;
1181 union eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];
1182 enum ecore_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1183 bool add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE;
1184 uint16_t vlan = elem->cmd_data.vlan_mac.u.vlan_mac.vlan;
1185 uint8_t *mac = elem->cmd_data.vlan_mac.u.vlan_mac.mac;
1187 /* Reset the ramrod data buffer for the first rule */
1189 ECORE_MEMSET(data, 0, sizeof(*data));
1191 /* Set a rule header */
1192 ecore_vlan_mac_set_cmd_hdr_e2(sc, o, add, CLASSIFY_RULE_OPCODE_PAIR,
1193 &rule_entry->pair.header);
1195 /* Set VLAN and MAC themselves */
1196 rule_entry->pair.vlan = ECORE_CPU_TO_LE16(vlan);
1197 ecore_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1198 &rule_entry->pair.mac_mid,
1199 &rule_entry->pair.mac_lsb, mac);
1200 rule_entry->pair.inner_mac =
1201 elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac;
1202 /* MOVE: Add a rule that will add this MAC to the target Queue */
1203 if (cmd == ECORE_VLAN_MAC_MOVE) {
1207 /* Setup ramrod data */
1208 ecore_vlan_mac_set_cmd_hdr_e2(sc,
1209 elem->cmd_data.vlan_mac.target_obj,
1210 TRUE, CLASSIFY_RULE_OPCODE_PAIR,
1211 &rule_entry->pair.header);
1213 /* Set a VLAN itself */
1214 rule_entry->pair.vlan = ECORE_CPU_TO_LE16(vlan);
1215 ecore_set_fw_mac_addr(&rule_entry->pair.mac_msb,
1216 &rule_entry->pair.mac_mid,
1217 &rule_entry->pair.mac_lsb, mac);
1218 rule_entry->pair.inner_mac =
1219 elem->cmd_data.vlan_mac.u.vlan_mac.is_inner_mac;
1222 /* Set the ramrod data header */
1223 /* TODO: take this to the higher level in order to prevent multiple
1225 ecore_vlan_mac_set_rdata_hdr_e2(raw->cid, raw->state, &data->header,
1230 * ecore_set_one_vlan_mac_e1h -
1232 * @sc: device handle
1233 * @o: ecore_vlan_mac_obj
1234 * @elem: ecore_exeq_elem
1235 * @rule_idx: rule_idx
1236 * @cam_offset: cam_offset
1238 static void ecore_set_one_vlan_mac_e1h(struct bxe_softc *sc,
1239 struct ecore_vlan_mac_obj *o,
1240 struct ecore_exeq_elem *elem,
1241 int rule_idx, int cam_offset)
1243 struct ecore_raw_obj *raw = &o->raw;
1244 struct mac_configuration_cmd *config =
1245 (struct mac_configuration_cmd *)(raw->rdata);
1246 /* 57710 and 57711 do not support MOVE command,
1247 * so it's either ADD or DEL
1249 bool add = (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?
1252 /* Reset the ramrod data buffer */
1253 ECORE_MEMSET(config, 0, sizeof(*config));
1255 ecore_vlan_mac_set_rdata_e1x(sc, o, ECORE_FILTER_VLAN_MAC_PENDING,
1257 elem->cmd_data.vlan_mac.u.vlan_mac.mac,
1258 elem->cmd_data.vlan_mac.u.vlan_mac.vlan,
1259 ETH_VLAN_FILTER_CLASSIFY, config);
1262 #define list_next_entry(pos, member) \
1263 list_entry((pos)->member.next, typeof(*(pos)), member)
1266 * ecore_vlan_mac_restore - reconfigure next MAC/VLAN/VLAN-MAC element
1268 * @sc: device handle
1269 * @p: command parameters
1270 * @ppos: pointer to the cookie
1272 * reconfigure next MAC/VLAN/VLAN-MAC element from the
1273 * previously configured elements list.
1275 * from command parameters only RAMROD_COMP_WAIT bit in ramrod_flags is taken
1278 * pointer to the cookie - that should be given back in the next call to make
1279 * function handle the next element. If *ppos is set to NULL it will restart the
1280 * iterator. If returned *ppos == NULL this means that the last element has been
1284 static int ecore_vlan_mac_restore(struct bxe_softc *sc,
1285 struct ecore_vlan_mac_ramrod_params *p,
1286 struct ecore_vlan_mac_registry_elem **ppos)
1288 struct ecore_vlan_mac_registry_elem *pos;
1289 struct ecore_vlan_mac_obj *o = p->vlan_mac_obj;
1291 /* If list is empty - there is nothing to do here */
1292 if (ECORE_LIST_IS_EMPTY(&o->head)) {
1297 /* make a step... */
1299 *ppos = ECORE_LIST_FIRST_ENTRY(&o->head,
1300 struct ecore_vlan_mac_registry_elem,
1303 *ppos = ECORE_LIST_NEXT(*ppos, link,
1304 struct ecore_vlan_mac_registry_elem);
1308 /* If it's the last step - return NULL */
1309 if (ECORE_LIST_IS_LAST(&pos->link, &o->head))
1312 /* Prepare a 'user_req' */
1313 ECORE_MEMCPY(&p->user_req.u, &pos->u, sizeof(pos->u));
1315 /* Set the command */
1316 p->user_req.cmd = ECORE_VLAN_MAC_ADD;
1318 /* Set vlan_mac_flags */
1319 p->user_req.vlan_mac_flags = pos->vlan_mac_flags;
1321 /* Set a restore bit */
1322 ECORE_SET_BIT_NA(RAMROD_RESTORE, &p->ramrod_flags);
1324 return ecore_config_vlan_mac(sc, p);
1327 /* ecore_exeq_get_mac/ecore_exeq_get_vlan/ecore_exeq_get_vlan_mac return a
1328 * pointer to an element with a specific criteria and NULL if such an element
1329 * hasn't been found.
1331 static struct ecore_exeq_elem *ecore_exeq_get_mac(
1332 struct ecore_exe_queue_obj *o,
1333 struct ecore_exeq_elem *elem)
1335 struct ecore_exeq_elem *pos;
1336 struct ecore_mac_ramrod_data *data = &elem->cmd_data.vlan_mac.u.mac;
1338 /* Check pending for execution commands */
1339 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->exe_queue, link,
1340 struct ecore_exeq_elem)
1341 if (!ECORE_MEMCMP(&pos->cmd_data.vlan_mac.u.mac, data,
1343 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1349 static struct ecore_exeq_elem *ecore_exeq_get_vlan(
1350 struct ecore_exe_queue_obj *o,
1351 struct ecore_exeq_elem *elem)
1353 struct ecore_exeq_elem *pos;
1354 struct ecore_vlan_ramrod_data *data = &elem->cmd_data.vlan_mac.u.vlan;
1356 /* Check pending for execution commands */
1357 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->exe_queue, link,
1358 struct ecore_exeq_elem)
1359 if (!ECORE_MEMCMP(&pos->cmd_data.vlan_mac.u.vlan, data,
1361 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1367 static struct ecore_exeq_elem *ecore_exeq_get_vlan_mac(
1368 struct ecore_exe_queue_obj *o,
1369 struct ecore_exeq_elem *elem)
1371 struct ecore_exeq_elem *pos;
1372 struct ecore_vlan_mac_ramrod_data *data =
1373 &elem->cmd_data.vlan_mac.u.vlan_mac;
1375 /* Check pending for execution commands */
1376 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->exe_queue, link,
1377 struct ecore_exeq_elem)
1378 if (!ECORE_MEMCMP(&pos->cmd_data.vlan_mac.u.vlan_mac, data,
1380 (pos->cmd_data.vlan_mac.cmd == elem->cmd_data.vlan_mac.cmd))
1387 * ecore_validate_vlan_mac_add - check if an ADD command can be executed
1389 * @sc: device handle
1390 * @qo: ecore_qable_obj
1391 * @elem: ecore_exeq_elem
1393 * Checks that the requested configuration can be added. If yes and if
1394 * requested, consume CAM credit.
1396 * The 'validate' is run after the 'optimize'.
1399 static inline int ecore_validate_vlan_mac_add(struct bxe_softc *sc,
1400 union ecore_qable_obj *qo,
1401 struct ecore_exeq_elem *elem)
1403 struct ecore_vlan_mac_obj *o = &qo->vlan_mac;
1404 struct ecore_exe_queue_obj *exeq = &o->exe_queue;
1407 /* Check the registry */
1408 rc = o->check_add(sc, o, &elem->cmd_data.vlan_mac.u);
1410 ECORE_MSG(sc, "ADD command is not allowed considering current registry state.\n");
1414 /* Check if there is a pending ADD command for this
1415 * MAC/VLAN/VLAN-MAC. Return an error if there is.
1417 if (exeq->get(exeq, elem)) {
1418 ECORE_MSG(sc, "There is a pending ADD command already\n");
1419 return ECORE_EXISTS;
1422 /* TODO: Check the pending MOVE from other objects where this
1423 * object is a destination object.
1426 /* Consume the credit if not requested not to */
1427 if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
1428 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1432 return ECORE_SUCCESS;
1436 * ecore_validate_vlan_mac_del - check if the DEL command can be executed
1438 * @sc: device handle
1439 * @qo: quable object to check
1440 * @elem: element that needs to be deleted
1442 * Checks that the requested configuration can be deleted. If yes and if
1443 * requested, returns a CAM credit.
1445 * The 'validate' is run after the 'optimize'.
1447 static inline int ecore_validate_vlan_mac_del(struct bxe_softc *sc,
1448 union ecore_qable_obj *qo,
1449 struct ecore_exeq_elem *elem)
1451 struct ecore_vlan_mac_obj *o = &qo->vlan_mac;
1452 struct ecore_vlan_mac_registry_elem *pos;
1453 struct ecore_exe_queue_obj *exeq = &o->exe_queue;
1454 struct ecore_exeq_elem query_elem;
1456 /* If this classification can not be deleted (doesn't exist)
1457 * - return a ECORE_EXIST.
1459 pos = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u);
1461 ECORE_MSG(sc, "DEL command is not allowed considering current registry state\n");
1462 return ECORE_EXISTS;
1465 /* Check if there are pending DEL or MOVE commands for this
1466 * MAC/VLAN/VLAN-MAC. Return an error if so.
1468 ECORE_MEMCPY(&query_elem, elem, sizeof(query_elem));
1470 /* Check for MOVE commands */
1471 query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_MOVE;
1472 if (exeq->get(exeq, &query_elem)) {
1473 ECORE_ERR("There is a pending MOVE command already\n");
1477 /* Check for DEL commands */
1478 if (exeq->get(exeq, elem)) {
1479 ECORE_MSG(sc, "There is a pending DEL command already\n");
1480 return ECORE_EXISTS;
1483 /* Return the credit to the credit pool if not requested not to */
1484 if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
1485 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1486 o->put_credit(o))) {
1487 ECORE_ERR("Failed to return a credit\n");
1491 return ECORE_SUCCESS;
1495 * ecore_validate_vlan_mac_move - check if the MOVE command can be executed
1497 * @sc: device handle
1498 * @qo: quable object to check (source)
1499 * @elem: element that needs to be moved
1501 * Checks that the requested configuration can be moved. If yes and if
1502 * requested, returns a CAM credit.
1504 * The 'validate' is run after the 'optimize'.
1506 static inline int ecore_validate_vlan_mac_move(struct bxe_softc *sc,
1507 union ecore_qable_obj *qo,
1508 struct ecore_exeq_elem *elem)
1510 struct ecore_vlan_mac_obj *src_o = &qo->vlan_mac;
1511 struct ecore_vlan_mac_obj *dest_o = elem->cmd_data.vlan_mac.target_obj;
1512 struct ecore_exeq_elem query_elem;
1513 struct ecore_exe_queue_obj *src_exeq = &src_o->exe_queue;
1514 struct ecore_exe_queue_obj *dest_exeq = &dest_o->exe_queue;
1516 /* Check if we can perform this operation based on the current registry
1519 if (!src_o->check_move(sc, src_o, dest_o,
1520 &elem->cmd_data.vlan_mac.u)) {
1521 ECORE_MSG(sc, "MOVE command is not allowed considering current registry state\n");
1525 /* Check if there is an already pending DEL or MOVE command for the
1526 * source object or ADD command for a destination object. Return an
1529 ECORE_MEMCPY(&query_elem, elem, sizeof(query_elem));
1531 /* Check DEL on source */
1532 query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL;
1533 if (src_exeq->get(src_exeq, &query_elem)) {
1534 ECORE_ERR("There is a pending DEL command on the source queue already\n");
1538 /* Check MOVE on source */
1539 if (src_exeq->get(src_exeq, elem)) {
1540 ECORE_MSG(sc, "There is a pending MOVE command already\n");
1541 return ECORE_EXISTS;
1544 /* Check ADD on destination */
1545 query_elem.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD;
1546 if (dest_exeq->get(dest_exeq, &query_elem)) {
1547 ECORE_ERR("There is a pending ADD command on the destination queue already\n");
1551 /* Consume the credit if not requested not to */
1552 if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT_DEST,
1553 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1554 dest_o->get_credit(dest_o)))
1557 if (!(ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
1558 &elem->cmd_data.vlan_mac.vlan_mac_flags) ||
1559 src_o->put_credit(src_o))) {
1560 /* return the credit taken from dest... */
1561 dest_o->put_credit(dest_o);
1565 return ECORE_SUCCESS;
1568 static int ecore_validate_vlan_mac(struct bxe_softc *sc,
1569 union ecore_qable_obj *qo,
1570 struct ecore_exeq_elem *elem)
1572 switch (elem->cmd_data.vlan_mac.cmd) {
1573 case ECORE_VLAN_MAC_ADD:
1574 return ecore_validate_vlan_mac_add(sc, qo, elem);
1575 case ECORE_VLAN_MAC_DEL:
1576 return ecore_validate_vlan_mac_del(sc, qo, elem);
1577 case ECORE_VLAN_MAC_MOVE:
1578 return ecore_validate_vlan_mac_move(sc, qo, elem);
1584 static int ecore_remove_vlan_mac(struct bxe_softc *sc,
1585 union ecore_qable_obj *qo,
1586 struct ecore_exeq_elem *elem)
1590 /* If consumption wasn't required, nothing to do */
1591 if (ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
1592 &elem->cmd_data.vlan_mac.vlan_mac_flags))
1593 return ECORE_SUCCESS;
1595 switch (elem->cmd_data.vlan_mac.cmd) {
1596 case ECORE_VLAN_MAC_ADD:
1597 case ECORE_VLAN_MAC_MOVE:
1598 rc = qo->vlan_mac.put_credit(&qo->vlan_mac);
1600 case ECORE_VLAN_MAC_DEL:
1601 rc = qo->vlan_mac.get_credit(&qo->vlan_mac);
1610 return ECORE_SUCCESS;
1614 * ecore_wait_vlan_mac - passively wait for 5 seconds until all work completes.
1616 * @sc: device handle
1617 * @o: ecore_vlan_mac_obj
1620 static int ecore_wait_vlan_mac(struct bxe_softc *sc,
1621 struct ecore_vlan_mac_obj *o)
1624 struct ecore_exe_queue_obj *exeq = &o->exe_queue;
1625 struct ecore_raw_obj *raw = &o->raw;
1628 /* Wait for the current command to complete */
1629 rc = raw->wait_comp(sc, raw);
1633 /* Wait until there are no pending commands */
1634 if (!ecore_exe_queue_empty(exeq))
1635 ECORE_WAIT(sc, 1000);
1637 return ECORE_SUCCESS;
1640 return ECORE_TIMEOUT;
1643 static int __ecore_vlan_mac_execute_step(struct bxe_softc *sc,
1644 struct ecore_vlan_mac_obj *o,
1645 unsigned long *ramrod_flags)
1647 int rc = ECORE_SUCCESS;
1649 ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
1651 ECORE_MSG(sc, "vlan_mac_execute_step - trying to take writer lock\n");
1652 rc = __ecore_vlan_mac_h_write_trylock(sc, o);
1654 if (rc != ECORE_SUCCESS) {
1655 __ecore_vlan_mac_h_pend(sc, o, *ramrod_flags);
1657 /** Calling function should not diffrentiate between this case
1658 * and the case in which there is already a pending ramrod
1662 rc = ecore_exe_queue_step(sc, &o->exe_queue, ramrod_flags);
1664 ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);
1670 * ecore_complete_vlan_mac - complete one VLAN-MAC ramrod
1672 * @sc: device handle
1673 * @o: ecore_vlan_mac_obj
1675 * @cont: if TRUE schedule next execution chunk
1678 static int ecore_complete_vlan_mac(struct bxe_softc *sc,
1679 struct ecore_vlan_mac_obj *o,
1680 union event_ring_elem *cqe,
1681 unsigned long *ramrod_flags)
1683 struct ecore_raw_obj *r = &o->raw;
1686 /* Clearing the pending list & raw state should be made
1687 * atomically (as execution flow assumes they represent the same)
1689 ECORE_SPIN_LOCK_BH(&o->exe_queue.lock);
1691 /* Reset pending list */
1692 __ecore_exe_queue_reset_pending(sc, &o->exe_queue);
1695 r->clear_pending(r);
1697 ECORE_SPIN_UNLOCK_BH(&o->exe_queue.lock);
1699 /* If ramrod failed this is most likely a SW bug */
1700 if (cqe->message.error)
1703 /* Run the next bulk of pending commands if requested */
1704 if (ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags)) {
1705 rc = __ecore_vlan_mac_execute_step(sc, o, ramrod_flags);
1710 /* If there is more work to do return PENDING */
1711 if (!ecore_exe_queue_empty(&o->exe_queue))
1712 return ECORE_PENDING;
1714 return ECORE_SUCCESS;
1718 * ecore_optimize_vlan_mac - optimize ADD and DEL commands.
1720 * @sc: device handle
1721 * @o: ecore_qable_obj
1722 * @elem: ecore_exeq_elem
1724 static int ecore_optimize_vlan_mac(struct bxe_softc *sc,
1725 union ecore_qable_obj *qo,
1726 struct ecore_exeq_elem *elem)
1728 struct ecore_exeq_elem query, *pos;
1729 struct ecore_vlan_mac_obj *o = &qo->vlan_mac;
1730 struct ecore_exe_queue_obj *exeq = &o->exe_queue;
1732 ECORE_MEMCPY(&query, elem, sizeof(query));
1734 switch (elem->cmd_data.vlan_mac.cmd) {
1735 case ECORE_VLAN_MAC_ADD:
1736 query.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_DEL;
1738 case ECORE_VLAN_MAC_DEL:
1739 query.cmd_data.vlan_mac.cmd = ECORE_VLAN_MAC_ADD;
1742 /* Don't handle anything other than ADD or DEL */
1746 /* If we found the appropriate element - delete it */
1747 pos = exeq->get(exeq, &query);
1750 /* Return the credit of the optimized command */
1751 if (!ECORE_TEST_BIT(ECORE_DONT_CONSUME_CAM_CREDIT,
1752 &pos->cmd_data.vlan_mac.vlan_mac_flags)) {
1753 if ((query.cmd_data.vlan_mac.cmd ==
1754 ECORE_VLAN_MAC_ADD) && !o->put_credit(o)) {
1755 ECORE_ERR("Failed to return the credit for the optimized ADD command\n");
1757 } else if (!o->get_credit(o)) { /* VLAN_MAC_DEL */
1758 ECORE_ERR("Failed to recover the credit from the optimized DEL command\n");
1763 ECORE_MSG(sc, "Optimizing %s command\n",
1764 (elem->cmd_data.vlan_mac.cmd == ECORE_VLAN_MAC_ADD) ?
1767 ECORE_LIST_REMOVE_ENTRY(&pos->link, &exeq->exe_queue);
1768 ecore_exe_queue_free_elem(sc, pos);
1776 * ecore_vlan_mac_get_registry_elem - prepare a registry element
1778 * @sc: device handle
1784 * prepare a registry element according to the current command request.
1786 static inline int ecore_vlan_mac_get_registry_elem(
1787 struct bxe_softc *sc,
1788 struct ecore_vlan_mac_obj *o,
1789 struct ecore_exeq_elem *elem,
1791 struct ecore_vlan_mac_registry_elem **re)
1793 enum ecore_vlan_mac_cmd cmd = elem->cmd_data.vlan_mac.cmd;
1794 struct ecore_vlan_mac_registry_elem *reg_elem;
1796 /* Allocate a new registry element if needed. */
1798 ((cmd == ECORE_VLAN_MAC_ADD) || (cmd == ECORE_VLAN_MAC_MOVE))) {
1799 reg_elem = ECORE_ZALLOC(sizeof(*reg_elem), GFP_ATOMIC, sc);
1803 /* Get a new CAM offset */
1804 if (!o->get_cam_offset(o, ®_elem->cam_offset)) {
1805 /* This shall never happen, because we have checked the
1806 * CAM availability in the 'validate'.
1808 ECORE_DBG_BREAK_IF(1);
1809 ECORE_FREE(sc, reg_elem, sizeof(*reg_elem));
1813 ECORE_MSG(sc, "Got cam offset %d\n", reg_elem->cam_offset);
1815 /* Set a VLAN-MAC data */
1816 ECORE_MEMCPY(®_elem->u, &elem->cmd_data.vlan_mac.u,
1817 sizeof(reg_elem->u));
1819 /* Copy the flags (needed for DEL and RESTORE flows) */
1820 reg_elem->vlan_mac_flags =
1821 elem->cmd_data.vlan_mac.vlan_mac_flags;
1822 } else /* DEL, RESTORE */
1823 reg_elem = o->check_del(sc, o, &elem->cmd_data.vlan_mac.u);
1826 return ECORE_SUCCESS;
1830 * ecore_execute_vlan_mac - execute vlan mac command
1832 * @sc: device handle
1837 * go and send a ramrod!
1839 static int ecore_execute_vlan_mac(struct bxe_softc *sc,
1840 union ecore_qable_obj *qo,
1841 ecore_list_t *exe_chunk,
1842 unsigned long *ramrod_flags)
1844 struct ecore_exeq_elem *elem;
1845 struct ecore_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;
1846 struct ecore_raw_obj *r = &o->raw;
1848 bool restore = ECORE_TEST_BIT(RAMROD_RESTORE, ramrod_flags);
1849 bool drv_only = ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags);
1850 struct ecore_vlan_mac_registry_elem *reg_elem;
1851 enum ecore_vlan_mac_cmd cmd;
1853 /* If DRIVER_ONLY execution is requested, cleanup a registry
1854 * and exit. Otherwise send a ramrod to FW.
1857 ECORE_DBG_BREAK_IF(r->check_pending(r));
1862 /* Fill the ramrod data */
1863 ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link,
1864 struct ecore_exeq_elem) {
1865 cmd = elem->cmd_data.vlan_mac.cmd;
1866 /* We will add to the target object in MOVE command, so
1867 * change the object for a CAM search.
1869 if (cmd == ECORE_VLAN_MAC_MOVE)
1870 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1874 rc = ecore_vlan_mac_get_registry_elem(sc, cam_obj,
1880 ECORE_DBG_BREAK_IF(!reg_elem);
1882 /* Push a new entry into the registry */
1884 ((cmd == ECORE_VLAN_MAC_ADD) ||
1885 (cmd == ECORE_VLAN_MAC_MOVE)))
1886 ECORE_LIST_PUSH_HEAD(®_elem->link,
1889 /* Configure a single command in a ramrod data buffer */
1890 o->set_one_rule(sc, o, elem, idx,
1891 reg_elem->cam_offset);
1893 /* MOVE command consumes 2 entries in the ramrod data */
1894 if (cmd == ECORE_VLAN_MAC_MOVE)
1901 * No need for an explicit memory barrier here as long we would
1902 * need to ensure the ordering of writing to the SPQ element
1903 * and updating of the SPQ producer which involves a memory
1904 * read and we will have to put a full memory barrier there
1905 * (inside ecore_sp_post()).
1908 rc = ecore_sp_post(sc, o->ramrod_cmd, r->cid,
1910 ETH_CONNECTION_TYPE);
1915 /* Now, when we are done with the ramrod - clean up the registry */
1916 ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link,
1917 struct ecore_exeq_elem) {
1918 cmd = elem->cmd_data.vlan_mac.cmd;
1919 if ((cmd == ECORE_VLAN_MAC_DEL) ||
1920 (cmd == ECORE_VLAN_MAC_MOVE)) {
1921 reg_elem = o->check_del(sc, o,
1922 &elem->cmd_data.vlan_mac.u);
1924 ECORE_DBG_BREAK_IF(!reg_elem);
1926 o->put_cam_offset(o, reg_elem->cam_offset);
1927 ECORE_LIST_REMOVE_ENTRY(®_elem->link, &o->head);
1928 ECORE_FREE(sc, reg_elem, sizeof(*reg_elem));
1933 return ECORE_PENDING;
1935 return ECORE_SUCCESS;
1938 r->clear_pending(r);
1940 /* Cleanup a registry in case of a failure */
1941 ECORE_LIST_FOR_EACH_ENTRY(elem, exe_chunk, link,
1942 struct ecore_exeq_elem) {
1943 cmd = elem->cmd_data.vlan_mac.cmd;
1945 if (cmd == ECORE_VLAN_MAC_MOVE)
1946 cam_obj = elem->cmd_data.vlan_mac.target_obj;
1950 /* Delete all newly added above entries */
1952 ((cmd == ECORE_VLAN_MAC_ADD) ||
1953 (cmd == ECORE_VLAN_MAC_MOVE))) {
1954 reg_elem = o->check_del(sc, cam_obj,
1955 &elem->cmd_data.vlan_mac.u);
1957 ECORE_LIST_REMOVE_ENTRY(®_elem->link,
1959 ECORE_FREE(sc, reg_elem, sizeof(*reg_elem));
1967 static inline int ecore_vlan_mac_push_new_cmd(
1968 struct bxe_softc *sc,
1969 struct ecore_vlan_mac_ramrod_params *p)
1971 struct ecore_exeq_elem *elem;
1972 struct ecore_vlan_mac_obj *o = p->vlan_mac_obj;
1973 bool restore = ECORE_TEST_BIT(RAMROD_RESTORE, &p->ramrod_flags);
1975 /* Allocate the execution queue element */
1976 elem = ecore_exe_queue_alloc_elem(sc);
1980 /* Set the command 'length' */
1981 switch (p->user_req.cmd) {
1982 case ECORE_VLAN_MAC_MOVE:
1989 /* Fill the object specific info */
1990 ECORE_MEMCPY(&elem->cmd_data.vlan_mac, &p->user_req, sizeof(p->user_req));
1992 /* Try to add a new command to the pending list */
1993 return ecore_exe_queue_add(sc, &o->exe_queue, elem, restore);
1997 * ecore_config_vlan_mac - configure VLAN/MAC/VLAN_MAC filtering rules.
1999 * @sc: device handle
2003 int ecore_config_vlan_mac(struct bxe_softc *sc,
2004 struct ecore_vlan_mac_ramrod_params *p)
2006 int rc = ECORE_SUCCESS;
2007 struct ecore_vlan_mac_obj *o = p->vlan_mac_obj;
2008 unsigned long *ramrod_flags = &p->ramrod_flags;
2009 bool cont = ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags);
2010 struct ecore_raw_obj *raw = &o->raw;
2013 * Add new elements to the execution list for commands that require it.
2016 rc = ecore_vlan_mac_push_new_cmd(sc, p);
2021 /* If nothing will be executed further in this iteration we want to
2022 * return PENDING if there are pending commands
2024 if (!ecore_exe_queue_empty(&o->exe_queue))
2027 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ramrod_flags)) {
2028 ECORE_MSG(sc, "RAMROD_DRV_CLR_ONLY requested: clearing a pending bit.\n");
2029 raw->clear_pending(raw);
2032 /* Execute commands if required */
2033 if (cont || ECORE_TEST_BIT(RAMROD_EXEC, ramrod_flags) ||
2034 ECORE_TEST_BIT(RAMROD_COMP_WAIT, ramrod_flags)) {
2035 rc = __ecore_vlan_mac_execute_step(sc, p->vlan_mac_obj,
2041 /* RAMROD_COMP_WAIT is a superset of RAMROD_EXEC. If it was set
2042 * then user want to wait until the last command is done.
2044 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2045 /* Wait maximum for the current exe_queue length iterations plus
2046 * one (for the current pending command).
2048 int max_iterations = ecore_exe_queue_length(&o->exe_queue) + 1;
2050 while (!ecore_exe_queue_empty(&o->exe_queue) &&
2053 /* Wait for the current command to complete */
2054 rc = raw->wait_comp(sc, raw);
2058 /* Make a next step */
2059 rc = __ecore_vlan_mac_execute_step(sc,
2066 return ECORE_SUCCESS;
2073 * ecore_vlan_mac_del_all - delete elements with given vlan_mac_flags spec
2075 * @sc: device handle
2078 * @ramrod_flags: execution flags to be used for this deletion
2080 * if the last operation has completed successfully and there are no
2081 * more elements left, positive value if the last operation has completed
2082 * successfully and there are more previously configured elements, negative
2083 * value is current operation has failed.
2085 static int ecore_vlan_mac_del_all(struct bxe_softc *sc,
2086 struct ecore_vlan_mac_obj *o,
2087 unsigned long *vlan_mac_flags,
2088 unsigned long *ramrod_flags)
2090 struct ecore_vlan_mac_registry_elem *pos = NULL;
2091 struct ecore_vlan_mac_ramrod_params p;
2092 struct ecore_exe_queue_obj *exeq = &o->exe_queue;
2093 struct ecore_exeq_elem *exeq_pos, *exeq_pos_n;
2097 /* Clear pending commands first */
2099 ECORE_SPIN_LOCK_BH(&exeq->lock);
2101 ECORE_LIST_FOR_EACH_ENTRY_SAFE(exeq_pos, exeq_pos_n,
2102 &exeq->exe_queue, link,
2103 struct ecore_exeq_elem) {
2104 if (exeq_pos->cmd_data.vlan_mac.vlan_mac_flags ==
2106 rc = exeq->remove(sc, exeq->owner, exeq_pos);
2108 ECORE_ERR("Failed to remove command\n");
2109 ECORE_SPIN_UNLOCK_BH(&exeq->lock);
2112 ECORE_LIST_REMOVE_ENTRY(&exeq_pos->link,
2114 ecore_exe_queue_free_elem(sc, exeq_pos);
2118 ECORE_SPIN_UNLOCK_BH(&exeq->lock);
2120 /* Prepare a command request */
2121 ECORE_MEMSET(&p, 0, sizeof(p));
2123 p.ramrod_flags = *ramrod_flags;
2124 p.user_req.cmd = ECORE_VLAN_MAC_DEL;
2126 /* Add all but the last VLAN-MAC to the execution queue without actually
2127 * execution anything.
2129 ECORE_CLEAR_BIT_NA(RAMROD_COMP_WAIT, &p.ramrod_flags);
2130 ECORE_CLEAR_BIT_NA(RAMROD_EXEC, &p.ramrod_flags);
2131 ECORE_CLEAR_BIT_NA(RAMROD_CONT, &p.ramrod_flags);
2133 ECORE_MSG(sc, "vlan_mac_del_all -- taking vlan_mac_lock (reader)\n");
2134 read_lock = ecore_vlan_mac_h_read_lock(sc, o);
2135 if (read_lock != ECORE_SUCCESS)
2138 ECORE_LIST_FOR_EACH_ENTRY(pos, &o->head, link,
2139 struct ecore_vlan_mac_registry_elem) {
2140 if (pos->vlan_mac_flags == *vlan_mac_flags) {
2141 p.user_req.vlan_mac_flags = pos->vlan_mac_flags;
2142 ECORE_MEMCPY(&p.user_req.u, &pos->u, sizeof(pos->u));
2143 rc = ecore_config_vlan_mac(sc, &p);
2145 ECORE_ERR("Failed to add a new DEL command\n");
2146 ecore_vlan_mac_h_read_unlock(sc, o);
2152 ECORE_MSG(sc, "vlan_mac_del_all -- releasing vlan_mac_lock (reader)\n");
2153 ecore_vlan_mac_h_read_unlock(sc, o);
2155 p.ramrod_flags = *ramrod_flags;
2156 ECORE_SET_BIT_NA(RAMROD_CONT, &p.ramrod_flags);
2158 return ecore_config_vlan_mac(sc, &p);
2161 static inline void ecore_init_raw_obj(struct ecore_raw_obj *raw, uint8_t cl_id,
2162 uint32_t cid, uint8_t func_id, void *rdata, ecore_dma_addr_t rdata_mapping, int state,
2163 unsigned long *pstate, ecore_obj_type type)
2165 raw->func_id = func_id;
2169 raw->rdata_mapping = rdata_mapping;
2171 raw->pstate = pstate;
2172 raw->obj_type = type;
2173 raw->check_pending = ecore_raw_check_pending;
2174 raw->clear_pending = ecore_raw_clear_pending;
2175 raw->set_pending = ecore_raw_set_pending;
2176 raw->wait_comp = ecore_raw_wait;
2179 static inline void ecore_init_vlan_mac_common(struct ecore_vlan_mac_obj *o,
2180 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, ecore_dma_addr_t rdata_mapping,
2181 int state, unsigned long *pstate, ecore_obj_type type,
2182 struct ecore_credit_pool_obj *macs_pool,
2183 struct ecore_credit_pool_obj *vlans_pool)
2185 ECORE_LIST_INIT(&o->head);
2187 o->head_exe_request = FALSE;
2188 o->saved_ramrod_flags = 0;
2190 o->macs_pool = macs_pool;
2191 o->vlans_pool = vlans_pool;
2193 o->delete_all = ecore_vlan_mac_del_all;
2194 o->restore = ecore_vlan_mac_restore;
2195 o->complete = ecore_complete_vlan_mac;
2196 o->wait = ecore_wait_vlan_mac;
2198 ecore_init_raw_obj(&o->raw, cl_id, cid, func_id, rdata, rdata_mapping,
2199 state, pstate, type);
2202 void ecore_init_mac_obj(struct bxe_softc *sc,
2203 struct ecore_vlan_mac_obj *mac_obj,
2204 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
2205 ecore_dma_addr_t rdata_mapping, int state,
2206 unsigned long *pstate, ecore_obj_type type,
2207 struct ecore_credit_pool_obj *macs_pool)
2209 union ecore_qable_obj *qable_obj = (union ecore_qable_obj *)mac_obj;
2211 ecore_init_vlan_mac_common(mac_obj, cl_id, cid, func_id, rdata,
2212 rdata_mapping, state, pstate, type,
2215 /* CAM credit pool handling */
2216 mac_obj->get_credit = ecore_get_credit_mac;
2217 mac_obj->put_credit = ecore_put_credit_mac;
2218 mac_obj->get_cam_offset = ecore_get_cam_offset_mac;
2219 mac_obj->put_cam_offset = ecore_put_cam_offset_mac;
2221 if (CHIP_IS_E1x(sc)) {
2222 mac_obj->set_one_rule = ecore_set_one_mac_e1x;
2223 mac_obj->check_del = ecore_check_mac_del;
2224 mac_obj->check_add = ecore_check_mac_add;
2225 mac_obj->check_move = ecore_check_move_always_err;
2226 mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
2229 ecore_exe_queue_init(sc,
2230 &mac_obj->exe_queue, 1, qable_obj,
2231 ecore_validate_vlan_mac,
2232 ecore_remove_vlan_mac,
2233 ecore_optimize_vlan_mac,
2234 ecore_execute_vlan_mac,
2235 ecore_exeq_get_mac);
2237 mac_obj->set_one_rule = ecore_set_one_mac_e2;
2238 mac_obj->check_del = ecore_check_mac_del;
2239 mac_obj->check_add = ecore_check_mac_add;
2240 mac_obj->check_move = ecore_check_move;
2241 mac_obj->ramrod_cmd =
2242 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2243 mac_obj->get_n_elements = ecore_get_n_elements;
2246 ecore_exe_queue_init(sc,
2247 &mac_obj->exe_queue, CLASSIFY_RULES_COUNT,
2248 qable_obj, ecore_validate_vlan_mac,
2249 ecore_remove_vlan_mac,
2250 ecore_optimize_vlan_mac,
2251 ecore_execute_vlan_mac,
2252 ecore_exeq_get_mac);
2256 void ecore_init_vlan_obj(struct bxe_softc *sc,
2257 struct ecore_vlan_mac_obj *vlan_obj,
2258 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
2259 ecore_dma_addr_t rdata_mapping, int state,
2260 unsigned long *pstate, ecore_obj_type type,
2261 struct ecore_credit_pool_obj *vlans_pool)
2263 union ecore_qable_obj *qable_obj = (union ecore_qable_obj *)vlan_obj;
2265 ecore_init_vlan_mac_common(vlan_obj, cl_id, cid, func_id, rdata,
2266 rdata_mapping, state, pstate, type, NULL,
2269 vlan_obj->get_credit = ecore_get_credit_vlan;
2270 vlan_obj->put_credit = ecore_put_credit_vlan;
2271 vlan_obj->get_cam_offset = ecore_get_cam_offset_vlan;
2272 vlan_obj->put_cam_offset = ecore_put_cam_offset_vlan;
2274 if (CHIP_IS_E1x(sc)) {
2275 ECORE_ERR("Do not support chips others than E2 and newer\n");
2278 vlan_obj->set_one_rule = ecore_set_one_vlan_e2;
2279 vlan_obj->check_del = ecore_check_vlan_del;
2280 vlan_obj->check_add = ecore_check_vlan_add;
2281 vlan_obj->check_move = ecore_check_move;
2282 vlan_obj->ramrod_cmd =
2283 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2284 vlan_obj->get_n_elements = ecore_get_n_elements;
2287 ecore_exe_queue_init(sc,
2288 &vlan_obj->exe_queue, CLASSIFY_RULES_COUNT,
2289 qable_obj, ecore_validate_vlan_mac,
2290 ecore_remove_vlan_mac,
2291 ecore_optimize_vlan_mac,
2292 ecore_execute_vlan_mac,
2293 ecore_exeq_get_vlan);
2297 void ecore_init_vlan_mac_obj(struct bxe_softc *sc,
2298 struct ecore_vlan_mac_obj *vlan_mac_obj,
2299 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,
2300 ecore_dma_addr_t rdata_mapping, int state,
2301 unsigned long *pstate, ecore_obj_type type,
2302 struct ecore_credit_pool_obj *macs_pool,
2303 struct ecore_credit_pool_obj *vlans_pool)
2305 union ecore_qable_obj *qable_obj =
2306 (union ecore_qable_obj *)vlan_mac_obj;
2308 ecore_init_vlan_mac_common(vlan_mac_obj, cl_id, cid, func_id, rdata,
2309 rdata_mapping, state, pstate, type,
2310 macs_pool, vlans_pool);
2312 /* CAM pool handling */
2313 vlan_mac_obj->get_credit = ecore_get_credit_vlan_mac;
2314 vlan_mac_obj->put_credit = ecore_put_credit_vlan_mac;
2315 /* CAM offset is relevant for 57710 and 57711 chips only which have a
2316 * single CAM for both MACs and VLAN-MAC pairs. So the offset
2317 * will be taken from MACs' pool object only.
2319 vlan_mac_obj->get_cam_offset = ecore_get_cam_offset_mac;
2320 vlan_mac_obj->put_cam_offset = ecore_put_cam_offset_mac;
2322 if (CHIP_IS_E1(sc)) {
2323 ECORE_ERR("Do not support chips others than E2\n");
2325 } else if (CHIP_IS_E1H(sc)) {
2326 vlan_mac_obj->set_one_rule = ecore_set_one_vlan_mac_e1h;
2327 vlan_mac_obj->check_del = ecore_check_vlan_mac_del;
2328 vlan_mac_obj->check_add = ecore_check_vlan_mac_add;
2329 vlan_mac_obj->check_move = ecore_check_move_always_err;
2330 vlan_mac_obj->ramrod_cmd = RAMROD_CMD_ID_ETH_SET_MAC;
2333 ecore_exe_queue_init(sc,
2334 &vlan_mac_obj->exe_queue, 1, qable_obj,
2335 ecore_validate_vlan_mac,
2336 ecore_remove_vlan_mac,
2337 ecore_optimize_vlan_mac,
2338 ecore_execute_vlan_mac,
2339 ecore_exeq_get_vlan_mac);
2341 vlan_mac_obj->set_one_rule = ecore_set_one_vlan_mac_e2;
2342 vlan_mac_obj->check_del = ecore_check_vlan_mac_del;
2343 vlan_mac_obj->check_add = ecore_check_vlan_mac_add;
2344 vlan_mac_obj->check_move = ecore_check_move;
2345 vlan_mac_obj->ramrod_cmd =
2346 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES;
2349 ecore_exe_queue_init(sc,
2350 &vlan_mac_obj->exe_queue,
2351 CLASSIFY_RULES_COUNT,
2352 qable_obj, ecore_validate_vlan_mac,
2353 ecore_remove_vlan_mac,
2354 ecore_optimize_vlan_mac,
2355 ecore_execute_vlan_mac,
2356 ecore_exeq_get_vlan_mac);
2360 /* RX_MODE verbs: DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
2361 static inline void __storm_memset_mac_filters(struct bxe_softc *sc,
2362 struct tstorm_eth_mac_filter_config *mac_filters,
2365 size_t size = sizeof(struct tstorm_eth_mac_filter_config);
2367 uint32_t addr = BAR_TSTRORM_INTMEM +
2368 TSTORM_MAC_FILTER_CONFIG_OFFSET(pf_id);
2370 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)mac_filters);
2373 static int ecore_set_rx_mode_e1x(struct bxe_softc *sc,
2374 struct ecore_rx_mode_ramrod_params *p)
2376 /* update the sc MAC filter structure */
2377 uint32_t mask = (1 << p->cl_id);
2379 struct tstorm_eth_mac_filter_config *mac_filters =
2380 (struct tstorm_eth_mac_filter_config *)p->rdata;
2382 /* initial setting is drop-all */
2383 uint8_t drop_all_ucast = 1, drop_all_mcast = 1;
2384 uint8_t accp_all_ucast = 0, accp_all_bcast = 0, accp_all_mcast = 0;
2385 uint8_t unmatched_unicast = 0;
2387 /* In e1x there we only take into account rx accept flag since tx switching
2389 if (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, &p->rx_accept_flags))
2390 /* accept matched ucast */
2393 if (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, &p->rx_accept_flags))
2394 /* accept matched mcast */
2397 if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, &p->rx_accept_flags)) {
2398 /* accept all mcast */
2402 if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, &p->rx_accept_flags)) {
2403 /* accept all mcast */
2407 if (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, &p->rx_accept_flags))
2408 /* accept (all) bcast */
2410 if (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, &p->rx_accept_flags))
2411 /* accept unmatched unicasts */
2412 unmatched_unicast = 1;
2414 mac_filters->ucast_drop_all = drop_all_ucast ?
2415 mac_filters->ucast_drop_all | mask :
2416 mac_filters->ucast_drop_all & ~mask;
2418 mac_filters->mcast_drop_all = drop_all_mcast ?
2419 mac_filters->mcast_drop_all | mask :
2420 mac_filters->mcast_drop_all & ~mask;
2422 mac_filters->ucast_accept_all = accp_all_ucast ?
2423 mac_filters->ucast_accept_all | mask :
2424 mac_filters->ucast_accept_all & ~mask;
2426 mac_filters->mcast_accept_all = accp_all_mcast ?
2427 mac_filters->mcast_accept_all | mask :
2428 mac_filters->mcast_accept_all & ~mask;
2430 mac_filters->bcast_accept_all = accp_all_bcast ?
2431 mac_filters->bcast_accept_all | mask :
2432 mac_filters->bcast_accept_all & ~mask;
2434 mac_filters->unmatched_unicast = unmatched_unicast ?
2435 mac_filters->unmatched_unicast | mask :
2436 mac_filters->unmatched_unicast & ~mask;
2438 ECORE_MSG(sc, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
2439 "accp_mcast 0x%x\naccp_bcast 0x%x\n",
2440 mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
2441 mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
2442 mac_filters->bcast_accept_all);
2444 /* write the MAC filter structure*/
2445 __storm_memset_mac_filters(sc, mac_filters, p->func_id);
2447 /* The operation is completed */
2448 ECORE_CLEAR_BIT(p->state, p->pstate);
2449 ECORE_SMP_MB_AFTER_CLEAR_BIT();
2451 return ECORE_SUCCESS;
2454 /* Setup ramrod data */
2455 static inline void ecore_rx_mode_set_rdata_hdr_e2(uint32_t cid,
2456 struct eth_classify_header *hdr,
2459 hdr->echo = ECORE_CPU_TO_LE32(cid);
2460 hdr->rule_cnt = rule_cnt;
2463 static inline void ecore_rx_mode_set_cmd_state_e2(struct bxe_softc *sc,
2464 unsigned long *accept_flags,
2465 struct eth_filter_rules_cmd *cmd,
2466 bool clear_accept_all)
2470 /* start with 'drop-all' */
2471 state = ETH_FILTER_RULES_CMD_UCAST_DROP_ALL |
2472 ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2474 if (ECORE_TEST_BIT(ECORE_ACCEPT_UNICAST, accept_flags))
2475 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2477 if (ECORE_TEST_BIT(ECORE_ACCEPT_MULTICAST, accept_flags))
2478 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2480 if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_UNICAST, accept_flags)) {
2481 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2482 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2485 if (ECORE_TEST_BIT(ECORE_ACCEPT_ALL_MULTICAST, accept_flags)) {
2486 state |= ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2487 state &= ~ETH_FILTER_RULES_CMD_MCAST_DROP_ALL;
2489 if (ECORE_TEST_BIT(ECORE_ACCEPT_BROADCAST, accept_flags))
2490 state |= ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2492 if (ECORE_TEST_BIT(ECORE_ACCEPT_UNMATCHED, accept_flags)) {
2493 state &= ~ETH_FILTER_RULES_CMD_UCAST_DROP_ALL;
2494 state |= ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2496 if (ECORE_TEST_BIT(ECORE_ACCEPT_ANY_VLAN, accept_flags))
2497 state |= ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN;
2499 /* Clear ACCEPT_ALL_XXX flags for FCoE L2 Queue */
2500 if (clear_accept_all) {
2501 state &= ~ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL;
2502 state &= ~ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL;
2503 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL;
2504 state &= ~ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED;
2507 cmd->state = ECORE_CPU_TO_LE16(state);
2510 static int ecore_set_rx_mode_e2(struct bxe_softc *sc,
2511 struct ecore_rx_mode_ramrod_params *p)
2513 struct eth_filter_rules_ramrod_data *data = p->rdata;
2515 uint8_t rule_idx = 0;
2517 /* Reset the ramrod data buffer */
2518 ECORE_MEMSET(data, 0, sizeof(*data));
2520 /* Setup ramrod data */
2522 /* Tx (internal switching) */
2523 if (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) {
2524 data->rules[rule_idx].client_id = p->cl_id;
2525 data->rules[rule_idx].func_id = p->func_id;
2527 data->rules[rule_idx].cmd_general_data =
2528 ETH_FILTER_RULES_CMD_TX_CMD;
2530 ecore_rx_mode_set_cmd_state_e2(sc, &p->tx_accept_flags,
2531 &(data->rules[rule_idx++]),
2536 if (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) {
2537 data->rules[rule_idx].client_id = p->cl_id;
2538 data->rules[rule_idx].func_id = p->func_id;
2540 data->rules[rule_idx].cmd_general_data =
2541 ETH_FILTER_RULES_CMD_RX_CMD;
2543 ecore_rx_mode_set_cmd_state_e2(sc, &p->rx_accept_flags,
2544 &(data->rules[rule_idx++]),
2548 /* If FCoE Queue configuration has been requested configure the Rx and
2549 * internal switching modes for this queue in separate rules.
2551 * FCoE queue shell never be set to ACCEPT_ALL packets of any sort:
2552 * MCAST_ALL, UCAST_ALL, BCAST_ALL and UNMATCHED.
2554 if (ECORE_TEST_BIT(ECORE_RX_MODE_FCOE_ETH, &p->rx_mode_flags)) {
2555 /* Tx (internal switching) */
2556 if (ECORE_TEST_BIT(RAMROD_TX, &p->ramrod_flags)) {
2557 data->rules[rule_idx].client_id = ECORE_FCOE_CID(sc);
2558 data->rules[rule_idx].func_id = p->func_id;
2560 data->rules[rule_idx].cmd_general_data =
2561 ETH_FILTER_RULES_CMD_TX_CMD;
2563 ecore_rx_mode_set_cmd_state_e2(sc, &p->tx_accept_flags,
2564 &(data->rules[rule_idx]),
2570 if (ECORE_TEST_BIT(RAMROD_RX, &p->ramrod_flags)) {
2571 data->rules[rule_idx].client_id = ECORE_FCOE_CID(sc);
2572 data->rules[rule_idx].func_id = p->func_id;
2574 data->rules[rule_idx].cmd_general_data =
2575 ETH_FILTER_RULES_CMD_RX_CMD;
2577 ecore_rx_mode_set_cmd_state_e2(sc, &p->rx_accept_flags,
2578 &(data->rules[rule_idx]),
2584 /* Set the ramrod header (most importantly - number of rules to
2587 ecore_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);
2589 ECORE_MSG(sc, "About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\n",
2590 data->header.rule_cnt, p->rx_accept_flags,
2591 p->tx_accept_flags);
2593 /* No need for an explicit memory barrier here as long we would
2594 * need to ensure the ordering of writing to the SPQ element
2595 * and updating of the SPQ producer which involves a memory
2596 * read and we will have to put a full memory barrier there
2597 * (inside ecore_sp_post()).
2601 rc = ecore_sp_post(sc,
2602 RAMROD_CMD_ID_ETH_FILTER_RULES,
2605 ETH_CONNECTION_TYPE);
2609 /* Ramrod completion is pending */
2610 return ECORE_PENDING;
2613 static int ecore_wait_rx_mode_comp_e2(struct bxe_softc *sc,
2614 struct ecore_rx_mode_ramrod_params *p)
2616 return ecore_state_wait(sc, p->state, p->pstate);
2619 static int ecore_empty_rx_mode_wait(struct bxe_softc *sc,
2620 struct ecore_rx_mode_ramrod_params *p)
2623 return ECORE_SUCCESS;
2626 int ecore_config_rx_mode(struct bxe_softc *sc,
2627 struct ecore_rx_mode_ramrod_params *p)
2631 /* Configure the new classification in the chip */
2632 rc = p->rx_mode_obj->config_rx_mode(sc, p);
2636 /* Wait for a ramrod completion if was requested */
2637 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags)) {
2638 rc = p->rx_mode_obj->wait_comp(sc, p);
2646 void ecore_init_rx_mode_obj(struct bxe_softc *sc,
2647 struct ecore_rx_mode_obj *o)
2649 if (CHIP_IS_E1x(sc)) {
2650 o->wait_comp = ecore_empty_rx_mode_wait;
2651 o->config_rx_mode = ecore_set_rx_mode_e1x;
2653 o->wait_comp = ecore_wait_rx_mode_comp_e2;
2654 o->config_rx_mode = ecore_set_rx_mode_e2;
2658 /********************* Multicast verbs: SET, CLEAR ****************************/
2659 static inline uint8_t ecore_mcast_bin_from_mac(uint8_t *mac)
2661 return (ECORE_CRC32_LE(0, mac, ETH_ALEN) >> 24) & 0xff;
2664 struct ecore_mcast_mac_elem {
2665 ecore_list_entry_t link;
2666 uint8_t mac[ETH_ALEN];
2667 uint8_t pad[2]; /* For a natural alignment of the following buffer */
2670 struct ecore_pending_mcast_cmd {
2671 ecore_list_entry_t link;
2672 int type; /* ECORE_MCAST_CMD_X */
2674 ecore_list_t macs_head;
2675 uint32_t macs_num; /* Needed for DEL command */
2676 int next_bin; /* Needed for RESTORE flow with aprox match */
2679 bool done; /* set to TRUE, when the command has been handled,
2680 * practically used in 57712 handling only, where one pending
2681 * command may be handled in a few operations. As long as for
2682 * other chips every operation handling is completed in a
2683 * single ramrod, there is no need to utilize this field.
2687 static int ecore_mcast_wait(struct bxe_softc *sc,
2688 struct ecore_mcast_obj *o)
2690 if (ecore_state_wait(sc, o->sched_state, o->raw.pstate) ||
2691 o->raw.wait_comp(sc, &o->raw))
2692 return ECORE_TIMEOUT;
2694 return ECORE_SUCCESS;
2697 static int ecore_mcast_enqueue_cmd(struct bxe_softc *sc,
2698 struct ecore_mcast_obj *o,
2699 struct ecore_mcast_ramrod_params *p,
2700 enum ecore_mcast_cmd cmd)
2703 struct ecore_pending_mcast_cmd *new_cmd;
2704 struct ecore_mcast_mac_elem *cur_mac = NULL;
2705 struct ecore_mcast_list_elem *pos;
2706 int macs_list_len = ((cmd == ECORE_MCAST_CMD_ADD) ?
2707 p->mcast_list_len : 0);
2709 /* If the command is empty ("handle pending commands only"), break */
2710 if (!p->mcast_list_len)
2711 return ECORE_SUCCESS;
2713 total_sz = sizeof(*new_cmd) +
2714 macs_list_len * sizeof(struct ecore_mcast_mac_elem);
2716 /* Add mcast is called under spin_lock, thus calling with GFP_ATOMIC */
2717 new_cmd = ECORE_ZALLOC(total_sz, GFP_ATOMIC, sc);
2722 ECORE_MSG(sc, "About to enqueue a new %d command. macs_list_len=%d\n",
2723 cmd, macs_list_len);
2725 ECORE_LIST_INIT(&new_cmd->data.macs_head);
2727 new_cmd->type = cmd;
2728 new_cmd->done = FALSE;
2731 case ECORE_MCAST_CMD_ADD:
2732 cur_mac = (struct ecore_mcast_mac_elem *)
2733 ((uint8_t *)new_cmd + sizeof(*new_cmd));
2735 /* Push the MACs of the current command into the pending command
2738 ECORE_LIST_FOR_EACH_ENTRY(pos, &p->mcast_list, link,
2739 struct ecore_mcast_list_elem) {
2740 ECORE_MEMCPY(cur_mac->mac, pos->mac, ETH_ALEN);
2741 ECORE_LIST_PUSH_TAIL(&cur_mac->link,
2742 &new_cmd->data.macs_head);
2748 case ECORE_MCAST_CMD_DEL:
2749 new_cmd->data.macs_num = p->mcast_list_len;
2752 case ECORE_MCAST_CMD_RESTORE:
2753 new_cmd->data.next_bin = 0;
2757 ECORE_FREE(sc, new_cmd, total_sz);
2758 ECORE_ERR("Unknown command: %d\n", cmd);
2762 /* Push the new pending command to the tail of the pending list: FIFO */
2763 ECORE_LIST_PUSH_TAIL(&new_cmd->link, &o->pending_cmds_head);
2767 return ECORE_PENDING;
2771 * ecore_mcast_get_next_bin - get the next set bin (index)
2774 * @last: index to start looking from (including)
2776 * returns the next found (set) bin or a negative value if none is found.
2778 static inline int ecore_mcast_get_next_bin(struct ecore_mcast_obj *o, int last)
2780 int i, j, inner_start = last % BIT_VEC64_ELEM_SZ;
2782 for (i = last / BIT_VEC64_ELEM_SZ; i < ECORE_MCAST_VEC_SZ; i++) {
2783 if (o->registry.aprox_match.vec[i])
2784 for (j = inner_start; j < BIT_VEC64_ELEM_SZ; j++) {
2785 int cur_bit = j + BIT_VEC64_ELEM_SZ * i;
2786 if (BIT_VEC64_TEST_BIT(o->registry.aprox_match.
2799 * ecore_mcast_clear_first_bin - find the first set bin and clear it
2803 * returns the index of the found bin or -1 if none is found
2805 static inline int ecore_mcast_clear_first_bin(struct ecore_mcast_obj *o)
2807 int cur_bit = ecore_mcast_get_next_bin(o, 0);
2810 BIT_VEC64_CLEAR_BIT(o->registry.aprox_match.vec, cur_bit);
2815 static inline uint8_t ecore_mcast_get_rx_tx_flag(struct ecore_mcast_obj *o)
2817 struct ecore_raw_obj *raw = &o->raw;
2818 uint8_t rx_tx_flag = 0;
2820 if ((raw->obj_type == ECORE_OBJ_TYPE_TX) ||
2821 (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))
2822 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_TX_CMD;
2824 if ((raw->obj_type == ECORE_OBJ_TYPE_RX) ||
2825 (raw->obj_type == ECORE_OBJ_TYPE_RX_TX))
2826 rx_tx_flag |= ETH_MULTICAST_RULES_CMD_RX_CMD;
2831 static void ecore_mcast_set_one_rule_e2(struct bxe_softc *sc,
2832 struct ecore_mcast_obj *o, int idx,
2833 union ecore_mcast_config_data *cfg_data,
2834 enum ecore_mcast_cmd cmd)
2836 struct ecore_raw_obj *r = &o->raw;
2837 struct eth_multicast_rules_ramrod_data *data =
2838 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
2839 uint8_t func_id = r->func_id;
2840 uint8_t rx_tx_add_flag = ecore_mcast_get_rx_tx_flag(o);
2843 if ((cmd == ECORE_MCAST_CMD_ADD) || (cmd == ECORE_MCAST_CMD_RESTORE))
2844 rx_tx_add_flag |= ETH_MULTICAST_RULES_CMD_IS_ADD;
2846 data->rules[idx].cmd_general_data |= rx_tx_add_flag;
2848 /* Get a bin and update a bins' vector */
2850 case ECORE_MCAST_CMD_ADD:
2851 bin = ecore_mcast_bin_from_mac(cfg_data->mac);
2852 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec, bin);
2855 case ECORE_MCAST_CMD_DEL:
2856 /* If there were no more bins to clear
2857 * (ecore_mcast_clear_first_bin() returns -1) then we would
2858 * clear any (0xff) bin.
2859 * See ecore_mcast_validate_e2() for explanation when it may
2862 bin = ecore_mcast_clear_first_bin(o);
2865 case ECORE_MCAST_CMD_RESTORE:
2866 bin = cfg_data->bin;
2870 ECORE_ERR("Unknown command: %d\n", cmd);
2874 ECORE_MSG(sc, "%s bin %d\n",
2875 ((rx_tx_add_flag & ETH_MULTICAST_RULES_CMD_IS_ADD) ?
2876 "Setting" : "Clearing"), bin);
2878 data->rules[idx].bin_id = (uint8_t)bin;
2879 data->rules[idx].func_id = func_id;
2880 data->rules[idx].engine_id = o->engine_id;
2884 * ecore_mcast_handle_restore_cmd_e2 - restore configuration from the registry
2886 * @sc: device handle
2888 * @start_bin: index in the registry to start from (including)
2889 * @rdata_idx: index in the ramrod data to start from
2891 * returns last handled bin index or -1 if all bins have been handled
2893 static inline int ecore_mcast_handle_restore_cmd_e2(
2894 struct bxe_softc *sc, struct ecore_mcast_obj *o , int start_bin,
2897 int cur_bin, cnt = *rdata_idx;
2898 union ecore_mcast_config_data cfg_data = {NULL};
2900 /* go through the registry and configure the bins from it */
2901 for (cur_bin = ecore_mcast_get_next_bin(o, start_bin); cur_bin >= 0;
2902 cur_bin = ecore_mcast_get_next_bin(o, cur_bin + 1)) {
2904 cfg_data.bin = (uint8_t)cur_bin;
2905 o->set_one_rule(sc, o, cnt, &cfg_data,
2906 ECORE_MCAST_CMD_RESTORE);
2910 ECORE_MSG(sc, "About to configure a bin %d\n", cur_bin);
2912 /* Break if we reached the maximum number
2915 if (cnt >= o->max_cmd_len)
2924 static inline void ecore_mcast_hdl_pending_add_e2(struct bxe_softc *sc,
2925 struct ecore_mcast_obj *o, struct ecore_pending_mcast_cmd *cmd_pos,
2928 struct ecore_mcast_mac_elem *pmac_pos, *pmac_pos_n;
2929 int cnt = *line_idx;
2930 union ecore_mcast_config_data cfg_data = {NULL};
2932 ECORE_LIST_FOR_EACH_ENTRY_SAFE(pmac_pos, pmac_pos_n,
2933 &cmd_pos->data.macs_head, link, struct ecore_mcast_mac_elem) {
2935 cfg_data.mac = &pmac_pos->mac[0];
2936 o->set_one_rule(sc, o, cnt, &cfg_data, cmd_pos->type);
2940 ECORE_MSG(sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\n",
2941 pmac_pos->mac[0], pmac_pos->mac[1], pmac_pos->mac[2], pmac_pos->mac[3], pmac_pos->mac[4], pmac_pos->mac[5]);
2943 ECORE_LIST_REMOVE_ENTRY(&pmac_pos->link,
2944 &cmd_pos->data.macs_head);
2946 /* Break if we reached the maximum number
2949 if (cnt >= o->max_cmd_len)
2955 /* if no more MACs to configure - we are done */
2956 if (ECORE_LIST_IS_EMPTY(&cmd_pos->data.macs_head))
2957 cmd_pos->done = TRUE;
2960 static inline void ecore_mcast_hdl_pending_del_e2(struct bxe_softc *sc,
2961 struct ecore_mcast_obj *o, struct ecore_pending_mcast_cmd *cmd_pos,
2964 int cnt = *line_idx;
2966 while (cmd_pos->data.macs_num) {
2967 o->set_one_rule(sc, o, cnt, NULL, cmd_pos->type);
2971 cmd_pos->data.macs_num--;
2973 ECORE_MSG(sc, "Deleting MAC. %d left,cnt is %d\n",
2974 cmd_pos->data.macs_num, cnt);
2976 /* Break if we reached the maximum
2979 if (cnt >= o->max_cmd_len)
2985 /* If we cleared all bins - we are done */
2986 if (!cmd_pos->data.macs_num)
2987 cmd_pos->done = TRUE;
2990 static inline void ecore_mcast_hdl_pending_restore_e2(struct bxe_softc *sc,
2991 struct ecore_mcast_obj *o, struct ecore_pending_mcast_cmd *cmd_pos,
2994 cmd_pos->data.next_bin = o->hdl_restore(sc, o, cmd_pos->data.next_bin,
2997 if (cmd_pos->data.next_bin < 0)
2998 /* If o->set_restore returned -1 we are done */
2999 cmd_pos->done = TRUE;
3001 /* Start from the next bin next time */
3002 cmd_pos->data.next_bin++;
3005 static inline int ecore_mcast_handle_pending_cmds_e2(struct bxe_softc *sc,
3006 struct ecore_mcast_ramrod_params *p)
3008 struct ecore_pending_mcast_cmd *cmd_pos, *cmd_pos_n;
3010 struct ecore_mcast_obj *o = p->mcast_obj;
3012 ECORE_LIST_FOR_EACH_ENTRY_SAFE(cmd_pos, cmd_pos_n,
3013 &o->pending_cmds_head, link, struct ecore_pending_mcast_cmd) {
3014 switch (cmd_pos->type) {
3015 case ECORE_MCAST_CMD_ADD:
3016 ecore_mcast_hdl_pending_add_e2(sc, o, cmd_pos, &cnt);
3019 case ECORE_MCAST_CMD_DEL:
3020 ecore_mcast_hdl_pending_del_e2(sc, o, cmd_pos, &cnt);
3023 case ECORE_MCAST_CMD_RESTORE:
3024 ecore_mcast_hdl_pending_restore_e2(sc, o, cmd_pos,
3029 ECORE_ERR("Unknown command: %d\n", cmd_pos->type);
3033 /* If the command has been completed - remove it from the list
3034 * and free the memory
3036 if (cmd_pos->done) {
3037 ECORE_LIST_REMOVE_ENTRY(&cmd_pos->link,
3038 &o->pending_cmds_head);
3039 ECORE_FREE(sc, cmd_pos, cmd_pos->alloc_len);
3042 /* Break if we reached the maximum number of rules */
3043 if (cnt >= o->max_cmd_len)
3050 static inline void ecore_mcast_hdl_add(struct bxe_softc *sc,
3051 struct ecore_mcast_obj *o, struct ecore_mcast_ramrod_params *p,
3054 struct ecore_mcast_list_elem *mlist_pos;
3055 union ecore_mcast_config_data cfg_data = {NULL};
3056 int cnt = *line_idx;
3058 ECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link,
3059 struct ecore_mcast_list_elem) {
3060 cfg_data.mac = mlist_pos->mac;
3061 o->set_one_rule(sc, o, cnt, &cfg_data, ECORE_MCAST_CMD_ADD);
3065 ECORE_MSG(sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\n",
3066 mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2], mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5]);
3072 static inline void ecore_mcast_hdl_del(struct bxe_softc *sc,
3073 struct ecore_mcast_obj *o, struct ecore_mcast_ramrod_params *p,
3076 int cnt = *line_idx, i;
3078 for (i = 0; i < p->mcast_list_len; i++) {
3079 o->set_one_rule(sc, o, cnt, NULL, ECORE_MCAST_CMD_DEL);
3083 ECORE_MSG(sc, "Deleting MAC. %d left\n",
3084 p->mcast_list_len - i - 1);
3091 * ecore_mcast_handle_current_cmd -
3093 * @sc: device handle
3096 * @start_cnt: first line in the ramrod data that may be used
3098 * This function is called iff there is enough place for the current command in
3100 * Returns number of lines filled in the ramrod data in total.
3102 static inline int ecore_mcast_handle_current_cmd(struct bxe_softc *sc,
3103 struct ecore_mcast_ramrod_params *p,
3104 enum ecore_mcast_cmd cmd,
3107 struct ecore_mcast_obj *o = p->mcast_obj;
3108 int cnt = start_cnt;
3110 ECORE_MSG(sc, "p->mcast_list_len=%d\n", p->mcast_list_len);
3113 case ECORE_MCAST_CMD_ADD:
3114 ecore_mcast_hdl_add(sc, o, p, &cnt);
3117 case ECORE_MCAST_CMD_DEL:
3118 ecore_mcast_hdl_del(sc, o, p, &cnt);
3121 case ECORE_MCAST_CMD_RESTORE:
3122 o->hdl_restore(sc, o, 0, &cnt);
3126 ECORE_ERR("Unknown command: %d\n", cmd);
3130 /* The current command has been handled */
3131 p->mcast_list_len = 0;
3136 static int ecore_mcast_validate_e2(struct bxe_softc *sc,
3137 struct ecore_mcast_ramrod_params *p,
3138 enum ecore_mcast_cmd cmd)
3140 struct ecore_mcast_obj *o = p->mcast_obj;
3141 int reg_sz = o->get_registry_size(o);
3144 /* DEL command deletes all currently configured MACs */
3145 case ECORE_MCAST_CMD_DEL:
3146 o->set_registry_size(o, 0);
3149 /* RESTORE command will restore the entire multicast configuration */
3150 case ECORE_MCAST_CMD_RESTORE:
3151 /* Here we set the approximate amount of work to do, which in
3152 * fact may be only less as some MACs in postponed ADD
3153 * command(s) scheduled before this command may fall into
3154 * the same bin and the actual number of bins set in the
3155 * registry would be less than we estimated here. See
3156 * ecore_mcast_set_one_rule_e2() for further details.
3158 p->mcast_list_len = reg_sz;
3161 case ECORE_MCAST_CMD_ADD:
3162 case ECORE_MCAST_CMD_CONT:
3163 /* Here we assume that all new MACs will fall into new bins.
3164 * However we will correct the real registry size after we
3165 * handle all pending commands.
3167 o->set_registry_size(o, reg_sz + p->mcast_list_len);
3171 ECORE_ERR("Unknown command: %d\n", cmd);
3175 /* Increase the total number of MACs pending to be configured */
3176 o->total_pending_num += p->mcast_list_len;
3178 return ECORE_SUCCESS;
3181 static void ecore_mcast_revert_e2(struct bxe_softc *sc,
3182 struct ecore_mcast_ramrod_params *p,
3185 struct ecore_mcast_obj *o = p->mcast_obj;
3187 o->set_registry_size(o, old_num_bins);
3188 o->total_pending_num -= p->mcast_list_len;
3192 * ecore_mcast_set_rdata_hdr_e2 - sets a header values
3194 * @sc: device handle
3196 * @len: number of rules to handle
3198 static inline void ecore_mcast_set_rdata_hdr_e2(struct bxe_softc *sc,
3199 struct ecore_mcast_ramrod_params *p,
3202 struct ecore_raw_obj *r = &p->mcast_obj->raw;
3203 struct eth_multicast_rules_ramrod_data *data =
3204 (struct eth_multicast_rules_ramrod_data *)(r->rdata);
3206 data->header.echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |
3207 (ECORE_FILTER_MCAST_PENDING <<
3208 ECORE_SWCID_SHIFT));
3209 data->header.rule_cnt = len;
3213 * ecore_mcast_refresh_registry_e2 - recalculate the actual number of set bins
3215 * @sc: device handle
3218 * Recalculate the actual number of set bins in the registry using Brian
3219 * Kernighan's algorithm: it's execution complexity is as a number of set bins.
3221 * returns 0 for the compliance with ecore_mcast_refresh_registry_e1().
3223 static inline int ecore_mcast_refresh_registry_e2(struct bxe_softc *sc,
3224 struct ecore_mcast_obj *o)
3229 for (i = 0; i < ECORE_MCAST_VEC_SZ; i++) {
3230 elem = o->registry.aprox_match.vec[i];
3235 o->set_registry_size(o, cnt);
3237 return ECORE_SUCCESS;
3240 static int ecore_mcast_setup_e2(struct bxe_softc *sc,
3241 struct ecore_mcast_ramrod_params *p,
3242 enum ecore_mcast_cmd cmd)
3244 struct ecore_raw_obj *raw = &p->mcast_obj->raw;
3245 struct ecore_mcast_obj *o = p->mcast_obj;
3246 struct eth_multicast_rules_ramrod_data *data =
3247 (struct eth_multicast_rules_ramrod_data *)(raw->rdata);
3250 /* Reset the ramrod data buffer */
3251 ECORE_MEMSET(data, 0, sizeof(*data));
3253 cnt = ecore_mcast_handle_pending_cmds_e2(sc, p);
3255 /* If there are no more pending commands - clear SCHEDULED state */
3256 if (ECORE_LIST_IS_EMPTY(&o->pending_cmds_head))
3259 /* The below may be TRUE iff there was enough room in ramrod
3260 * data for all pending commands and for the current
3261 * command. Otherwise the current command would have been added
3262 * to the pending commands and p->mcast_list_len would have been
3265 if (p->mcast_list_len > 0)
3266 cnt = ecore_mcast_handle_current_cmd(sc, p, cmd, cnt);
3268 /* We've pulled out some MACs - update the total number of
3271 o->total_pending_num -= cnt;
3274 ECORE_DBG_BREAK_IF(o->total_pending_num < 0);
3275 ECORE_DBG_BREAK_IF(cnt > o->max_cmd_len);
3277 ecore_mcast_set_rdata_hdr_e2(sc, p, (uint8_t)cnt);
3279 /* Update a registry size if there are no more pending operations.
3281 * We don't want to change the value of the registry size if there are
3282 * pending operations because we want it to always be equal to the
3283 * exact or the approximate number (see ecore_mcast_validate_e2()) of
3284 * set bins after the last requested operation in order to properly
3285 * evaluate the size of the next DEL/RESTORE operation.
3287 * Note that we update the registry itself during command(s) handling
3288 * - see ecore_mcast_set_one_rule_e2(). That's because for 57712 we
3289 * aggregate multiple commands (ADD/DEL/RESTORE) into one ramrod but
3290 * with a limited amount of update commands (per MAC/bin) and we don't
3291 * know in this scope what the actual state of bins configuration is
3292 * going to be after this ramrod.
3294 if (!o->total_pending_num)
3295 ecore_mcast_refresh_registry_e2(sc, o);
3297 /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3298 * RAMROD_PENDING status immediately.
3300 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3301 raw->clear_pending(raw);
3302 return ECORE_SUCCESS;
3304 /* No need for an explicit memory barrier here as long we would
3305 * need to ensure the ordering of writing to the SPQ element
3306 * and updating of the SPQ producer which involves a memory
3307 * read and we will have to put a full memory barrier there
3308 * (inside ecore_sp_post()).
3312 rc = ecore_sp_post( sc,
3313 RAMROD_CMD_ID_ETH_MULTICAST_RULES,
3316 ETH_CONNECTION_TYPE);
3320 /* Ramrod completion is pending */
3321 return ECORE_PENDING;
3325 static int ecore_mcast_validate_e1h(struct bxe_softc *sc,
3326 struct ecore_mcast_ramrod_params *p,
3327 enum ecore_mcast_cmd cmd)
3329 /* Mark, that there is a work to do */
3330 if ((cmd == ECORE_MCAST_CMD_DEL) || (cmd == ECORE_MCAST_CMD_RESTORE))
3331 p->mcast_list_len = 1;
3333 return ECORE_SUCCESS;
3336 static void ecore_mcast_revert_e1h(struct bxe_softc *sc,
3337 struct ecore_mcast_ramrod_params *p,
3343 #define ECORE_57711_SET_MC_FILTER(filter, bit) \
3345 (filter)[(bit) >> 5] |= (1 << ((bit) & 0x1f)); \
3348 static inline void ecore_mcast_hdl_add_e1h(struct bxe_softc *sc,
3349 struct ecore_mcast_obj *o,
3350 struct ecore_mcast_ramrod_params *p,
3351 uint32_t *mc_filter)
3353 struct ecore_mcast_list_elem *mlist_pos;
3356 ECORE_LIST_FOR_EACH_ENTRY(mlist_pos, &p->mcast_list, link,
3357 struct ecore_mcast_list_elem) {
3358 bit = ecore_mcast_bin_from_mac(mlist_pos->mac);
3359 ECORE_57711_SET_MC_FILTER(mc_filter, bit);
3361 ECORE_MSG(sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC, bin %d\n",
3362 mlist_pos->mac[0], mlist_pos->mac[1], mlist_pos->mac[2], mlist_pos->mac[3], mlist_pos->mac[4], mlist_pos->mac[5], bit);
3364 /* bookkeeping... */
3365 BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
3370 static inline void ecore_mcast_hdl_restore_e1h(struct bxe_softc *sc,
3371 struct ecore_mcast_obj *o, struct ecore_mcast_ramrod_params *p,
3372 uint32_t *mc_filter)
3376 for (bit = ecore_mcast_get_next_bin(o, 0);
3378 bit = ecore_mcast_get_next_bin(o, bit + 1)) {
3379 ECORE_57711_SET_MC_FILTER(mc_filter, bit);
3380 ECORE_MSG(sc, "About to set bin %d\n", bit);
3384 /* On 57711 we write the multicast MACs' approximate match
3385 * table by directly into the TSTORM's internal RAM. So we don't
3386 * really need to handle any tricks to make it work.
3388 static int ecore_mcast_setup_e1h(struct bxe_softc *sc,
3389 struct ecore_mcast_ramrod_params *p,
3390 enum ecore_mcast_cmd cmd)
3393 struct ecore_mcast_obj *o = p->mcast_obj;
3394 struct ecore_raw_obj *r = &o->raw;
3396 /* If CLEAR_ONLY has been requested - clear the registry
3397 * and clear a pending bit.
3399 if (!ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3400 uint32_t mc_filter[ECORE_MC_HASH_SIZE] = {0};
3402 /* Set the multicast filter bits before writing it into
3403 * the internal memory.
3406 case ECORE_MCAST_CMD_ADD:
3407 ecore_mcast_hdl_add_e1h(sc, o, p, mc_filter);
3410 case ECORE_MCAST_CMD_DEL:
3412 "Invalidating multicast MACs configuration\n");
3414 /* clear the registry */
3415 ECORE_MEMSET(o->registry.aprox_match.vec, 0,
3416 sizeof(o->registry.aprox_match.vec));
3419 case ECORE_MCAST_CMD_RESTORE:
3420 ecore_mcast_hdl_restore_e1h(sc, o, p, mc_filter);
3424 ECORE_ERR("Unknown command: %d\n", cmd);
3428 /* Set the mcast filter in the internal memory */
3429 for (i = 0; i < ECORE_MC_HASH_SIZE; i++)
3430 REG_WR(sc, ECORE_MC_HASH_OFFSET(sc, i), mc_filter[i]);
3432 /* clear the registry */
3433 ECORE_MEMSET(o->registry.aprox_match.vec, 0,
3434 sizeof(o->registry.aprox_match.vec));
3437 r->clear_pending(r);
3439 return ECORE_SUCCESS;
3442 static int ecore_mcast_validate_e1(struct bxe_softc *sc,
3443 struct ecore_mcast_ramrod_params *p,
3444 enum ecore_mcast_cmd cmd)
3446 struct ecore_mcast_obj *o = p->mcast_obj;
3447 int reg_sz = o->get_registry_size(o);
3450 /* DEL command deletes all currently configured MACs */
3451 case ECORE_MCAST_CMD_DEL:
3452 o->set_registry_size(o, 0);
3455 /* RESTORE command will restore the entire multicast configuration */
3456 case ECORE_MCAST_CMD_RESTORE:
3457 p->mcast_list_len = reg_sz;
3458 ECORE_MSG(sc, "Command %d, p->mcast_list_len=%d\n",
3459 cmd, p->mcast_list_len);
3462 case ECORE_MCAST_CMD_ADD:
3463 case ECORE_MCAST_CMD_CONT:
3464 /* Multicast MACs on 57710 are configured as unicast MACs and
3465 * there is only a limited number of CAM entries for that
3468 if (p->mcast_list_len > o->max_cmd_len) {
3469 ECORE_ERR("Can't configure more than %d multicast MACs on 57710\n",
3473 /* Every configured MAC should be cleared if DEL command is
3474 * called. Only the last ADD command is relevant as long as
3475 * every ADD commands overrides the previous configuration.
3477 ECORE_MSG(sc, "p->mcast_list_len=%d\n", p->mcast_list_len);
3478 if (p->mcast_list_len > 0)
3479 o->set_registry_size(o, p->mcast_list_len);
3484 ECORE_ERR("Unknown command: %d\n", cmd);
3488 /* We want to ensure that commands are executed one by one for 57710.
3489 * Therefore each none-empty command will consume o->max_cmd_len.
3491 if (p->mcast_list_len)
3492 o->total_pending_num += o->max_cmd_len;
3494 return ECORE_SUCCESS;
3497 static void ecore_mcast_revert_e1(struct bxe_softc *sc,
3498 struct ecore_mcast_ramrod_params *p,
3501 struct ecore_mcast_obj *o = p->mcast_obj;
3503 o->set_registry_size(o, old_num_macs);
3505 /* If current command hasn't been handled yet and we are
3506 * here means that it's meant to be dropped and we have to
3507 * update the number of outstanding MACs accordingly.
3509 if (p->mcast_list_len)
3510 o->total_pending_num -= o->max_cmd_len;
3513 static void ecore_mcast_set_one_rule_e1(struct bxe_softc *sc,
3514 struct ecore_mcast_obj *o, int idx,
3515 union ecore_mcast_config_data *cfg_data,
3516 enum ecore_mcast_cmd cmd)
3518 struct ecore_raw_obj *r = &o->raw;
3519 struct mac_configuration_cmd *data =
3520 (struct mac_configuration_cmd *)(r->rdata);
3523 if ((cmd == ECORE_MCAST_CMD_ADD) || (cmd == ECORE_MCAST_CMD_RESTORE)) {
3524 ecore_set_fw_mac_addr(&data->config_table[idx].msb_mac_addr,
3525 &data->config_table[idx].middle_mac_addr,
3526 &data->config_table[idx].lsb_mac_addr,
3529 data->config_table[idx].vlan_id = 0;
3530 data->config_table[idx].pf_id = r->func_id;
3531 data->config_table[idx].clients_bit_vector =
3532 ECORE_CPU_TO_LE32(1 << r->cl_id);
3534 ECORE_SET_FLAG(data->config_table[idx].flags,
3535 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3536 T_ETH_MAC_COMMAND_SET);
3541 * ecore_mcast_set_rdata_hdr_e1 - set header values in mac_configuration_cmd
3543 * @sc: device handle
3545 * @len: number of rules to handle
3547 static inline void ecore_mcast_set_rdata_hdr_e1(struct bxe_softc *sc,
3548 struct ecore_mcast_ramrod_params *p,
3551 struct ecore_raw_obj *r = &p->mcast_obj->raw;
3552 struct mac_configuration_cmd *data =
3553 (struct mac_configuration_cmd *)(r->rdata);
3555 uint8_t offset = (CHIP_REV_IS_SLOW(sc) ?
3556 ECORE_MAX_EMUL_MULTI*(1 + r->func_id) :
3557 ECORE_MAX_MULTICAST*(1 + r->func_id));
3559 data->hdr.offset = offset;
3560 data->hdr.client_id = ECORE_CPU_TO_LE16(0xff);
3561 data->hdr.echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |
3562 (ECORE_FILTER_MCAST_PENDING <<
3563 ECORE_SWCID_SHIFT));
3564 data->hdr.length = len;
3568 * ecore_mcast_handle_restore_cmd_e1 - restore command for 57710
3570 * @sc: device handle
3572 * @start_idx: index in the registry to start from
3573 * @rdata_idx: index in the ramrod data to start from
3575 * restore command for 57710 is like all other commands - always a stand alone
3576 * command - start_idx and rdata_idx will always be 0. This function will always
3578 * returns -1 to comply with 57712 variant.
3580 static inline int ecore_mcast_handle_restore_cmd_e1(
3581 struct bxe_softc *sc, struct ecore_mcast_obj *o , int start_idx,
3584 struct ecore_mcast_mac_elem *elem;
3586 union ecore_mcast_config_data cfg_data = {NULL};
3588 /* go through the registry and configure the MACs from it. */
3589 ECORE_LIST_FOR_EACH_ENTRY(elem, &o->registry.exact_match.macs, link,
3590 struct ecore_mcast_mac_elem) {
3591 cfg_data.mac = &elem->mac[0];
3592 o->set_one_rule(sc, o, i, &cfg_data, ECORE_MCAST_CMD_RESTORE);
3596 ECORE_MSG(sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\n",
3597 cfg_data.mac[0], cfg_data.mac[1], cfg_data.mac[2], cfg_data.mac[3], cfg_data.mac[4], cfg_data.mac[5]);
3605 static inline int ecore_mcast_handle_pending_cmds_e1(
3606 struct bxe_softc *sc, struct ecore_mcast_ramrod_params *p)
3608 struct ecore_pending_mcast_cmd *cmd_pos;
3609 struct ecore_mcast_mac_elem *pmac_pos;
3610 struct ecore_mcast_obj *o = p->mcast_obj;
3611 union ecore_mcast_config_data cfg_data = {NULL};
3614 /* If nothing to be done - return */
3615 if (ECORE_LIST_IS_EMPTY(&o->pending_cmds_head))
3618 /* Handle the first command */
3619 cmd_pos = ECORE_LIST_FIRST_ENTRY(&o->pending_cmds_head,
3620 struct ecore_pending_mcast_cmd, link);
3622 switch (cmd_pos->type) {
3623 case ECORE_MCAST_CMD_ADD:
3624 ECORE_LIST_FOR_EACH_ENTRY(pmac_pos, &cmd_pos->data.macs_head,
3625 link, struct ecore_mcast_mac_elem) {
3626 cfg_data.mac = &pmac_pos->mac[0];
3627 o->set_one_rule(sc, o, cnt, &cfg_data, cmd_pos->type);
3631 ECORE_MSG(sc, "About to configure %02x:%02x:%02x:%02x:%02x:%02x mcast MAC\n",
3632 pmac_pos->mac[0], pmac_pos->mac[1], pmac_pos->mac[2], pmac_pos->mac[3], pmac_pos->mac[4], pmac_pos->mac[5]);
3636 case ECORE_MCAST_CMD_DEL:
3637 cnt = cmd_pos->data.macs_num;
3638 ECORE_MSG(sc, "About to delete %d multicast MACs\n", cnt);
3641 case ECORE_MCAST_CMD_RESTORE:
3642 o->hdl_restore(sc, o, 0, &cnt);
3646 ECORE_ERR("Unknown command: %d\n", cmd_pos->type);
3650 ECORE_LIST_REMOVE_ENTRY(&cmd_pos->link, &o->pending_cmds_head);
3651 ECORE_FREE(sc, cmd_pos, cmd_pos->alloc_len);
3657 * ecore_get_fw_mac_addr - revert the ecore_set_fw_mac_addr().
3664 static inline void ecore_get_fw_mac_addr(uint16_t *fw_hi, uint16_t *fw_mid,
3665 uint16_t *fw_lo, uint8_t *mac)
3667 mac[1] = ((uint8_t *)fw_hi)[0];
3668 mac[0] = ((uint8_t *)fw_hi)[1];
3669 mac[3] = ((uint8_t *)fw_mid)[0];
3670 mac[2] = ((uint8_t *)fw_mid)[1];
3671 mac[5] = ((uint8_t *)fw_lo)[0];
3672 mac[4] = ((uint8_t *)fw_lo)[1];
3676 * ecore_mcast_refresh_registry_e1 -
3678 * @sc: device handle
3681 * Check the ramrod data first entry flag to see if it's a DELETE or ADD command
3682 * and update the registry correspondingly: if ADD - allocate a memory and add
3683 * the entries to the registry (list), if DELETE - clear the registry and free
3686 static inline int ecore_mcast_refresh_registry_e1(struct bxe_softc *sc,
3687 struct ecore_mcast_obj *o)
3689 struct ecore_raw_obj *raw = &o->raw;
3690 struct ecore_mcast_mac_elem *elem;
3691 struct mac_configuration_cmd *data =
3692 (struct mac_configuration_cmd *)(raw->rdata);
3694 /* If first entry contains a SET bit - the command was ADD,
3695 * otherwise - DEL_ALL
3697 if (ECORE_GET_FLAG(data->config_table[0].flags,
3698 MAC_CONFIGURATION_ENTRY_ACTION_TYPE)) {
3699 int i, len = data->hdr.length;
3701 /* Break if it was a RESTORE command */
3702 if (!ECORE_LIST_IS_EMPTY(&o->registry.exact_match.macs))
3703 return ECORE_SUCCESS;
3705 elem = ECORE_CALLOC(len, sizeof(*elem), GFP_ATOMIC, sc);
3707 ECORE_ERR("Failed to allocate registry memory\n");
3711 for (i = 0; i < len; i++, elem++) {
3712 ecore_get_fw_mac_addr(
3713 &data->config_table[i].msb_mac_addr,
3714 &data->config_table[i].middle_mac_addr,
3715 &data->config_table[i].lsb_mac_addr,
3717 ECORE_MSG(sc, "Adding registry entry for [%02x:%02x:%02x:%02x:%02x:%02x]\n",
3718 elem->mac[0], elem->mac[1], elem->mac[2], elem->mac[3], elem->mac[4], elem->mac[5]);
3719 ECORE_LIST_PUSH_TAIL(&elem->link,
3720 &o->registry.exact_match.macs);
3723 elem = ECORE_LIST_FIRST_ENTRY(&o->registry.exact_match.macs,
3724 struct ecore_mcast_mac_elem,
3726 ECORE_MSG(sc, "Deleting a registry\n");
3727 ECORE_FREE(sc, elem, sizeof(*elem));
3728 ECORE_LIST_INIT(&o->registry.exact_match.macs);
3731 return ECORE_SUCCESS;
3734 static int ecore_mcast_setup_e1(struct bxe_softc *sc,
3735 struct ecore_mcast_ramrod_params *p,
3736 enum ecore_mcast_cmd cmd)
3738 struct ecore_mcast_obj *o = p->mcast_obj;
3739 struct ecore_raw_obj *raw = &o->raw;
3740 struct mac_configuration_cmd *data =
3741 (struct mac_configuration_cmd *)(raw->rdata);
3744 /* Reset the ramrod data buffer */
3745 ECORE_MEMSET(data, 0, sizeof(*data));
3747 /* First set all entries as invalid */
3748 for (i = 0; i < o->max_cmd_len ; i++)
3749 ECORE_SET_FLAG(data->config_table[i].flags,
3750 MAC_CONFIGURATION_ENTRY_ACTION_TYPE,
3751 T_ETH_MAC_COMMAND_INVALIDATE);
3753 /* Handle pending commands first */
3754 cnt = ecore_mcast_handle_pending_cmds_e1(sc, p);
3756 /* If there are no more pending commands - clear SCHEDULED state */
3757 if (ECORE_LIST_IS_EMPTY(&o->pending_cmds_head))
3760 /* The below may be TRUE iff there were no pending commands */
3762 cnt = ecore_mcast_handle_current_cmd(sc, p, cmd, 0);
3764 /* For 57710 every command has o->max_cmd_len length to ensure that
3765 * commands are done one at a time.
3767 o->total_pending_num -= o->max_cmd_len;
3771 ECORE_DBG_BREAK_IF(cnt > o->max_cmd_len);
3773 /* Set ramrod header (in particular, a number of entries to update) */
3774 ecore_mcast_set_rdata_hdr_e1(sc, p, (uint8_t)cnt);
3776 /* update a registry: we need the registry contents to be always up
3777 * to date in order to be able to execute a RESTORE opcode. Here
3778 * we use the fact that for 57710 we sent one command at a time
3779 * hence we may take the registry update out of the command handling
3780 * and do it in a simpler way here.
3782 rc = ecore_mcast_refresh_registry_e1(sc, o);
3786 /* If CLEAR_ONLY was requested - don't send a ramrod and clear
3787 * RAMROD_PENDING status immediately.
3789 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags)) {
3790 raw->clear_pending(raw);
3791 return ECORE_SUCCESS;
3793 /* No need for an explicit memory barrier here as long we would
3794 * need to ensure the ordering of writing to the SPQ element
3795 * and updating of the SPQ producer which involves a memory
3796 * read and we will have to put a full memory barrier there
3797 * (inside ecore_sp_post()).
3801 rc = ecore_sp_post( sc,
3802 RAMROD_CMD_ID_ETH_SET_MAC,
3805 ETH_CONNECTION_TYPE);
3809 /* Ramrod completion is pending */
3810 return ECORE_PENDING;
3814 static int ecore_mcast_get_registry_size_exact(struct ecore_mcast_obj *o)
3816 return o->registry.exact_match.num_macs_set;
3819 static int ecore_mcast_get_registry_size_aprox(struct ecore_mcast_obj *o)
3821 return o->registry.aprox_match.num_bins_set;
3824 static void ecore_mcast_set_registry_size_exact(struct ecore_mcast_obj *o,
3827 o->registry.exact_match.num_macs_set = n;
3830 static void ecore_mcast_set_registry_size_aprox(struct ecore_mcast_obj *o,
3833 o->registry.aprox_match.num_bins_set = n;
3836 int ecore_config_mcast(struct bxe_softc *sc,
3837 struct ecore_mcast_ramrod_params *p,
3838 enum ecore_mcast_cmd cmd)
3840 struct ecore_mcast_obj *o = p->mcast_obj;
3841 struct ecore_raw_obj *r = &o->raw;
3842 int rc = 0, old_reg_size;
3844 /* This is needed to recover number of currently configured mcast macs
3845 * in case of failure.
3847 old_reg_size = o->get_registry_size(o);
3849 /* Do some calculations and checks */
3850 rc = o->validate(sc, p, cmd);
3854 /* Return if there is no work to do */
3855 if ((!p->mcast_list_len) && (!o->check_sched(o)))
3856 return ECORE_SUCCESS;
3858 ECORE_MSG(sc, "o->total_pending_num=%d p->mcast_list_len=%d o->max_cmd_len=%d\n",
3859 o->total_pending_num, p->mcast_list_len, o->max_cmd_len);
3861 /* Enqueue the current command to the pending list if we can't complete
3862 * it in the current iteration
3864 if (r->check_pending(r) ||
3865 ((o->max_cmd_len > 0) && (o->total_pending_num > o->max_cmd_len))) {
3866 rc = o->enqueue_cmd(sc, p->mcast_obj, p, cmd);
3870 /* As long as the current command is in a command list we
3871 * don't need to handle it separately.
3873 p->mcast_list_len = 0;
3876 if (!r->check_pending(r)) {
3878 /* Set 'pending' state */
3881 /* Configure the new classification in the chip */
3882 rc = o->config_mcast(sc, p, cmd);
3886 /* Wait for a ramrod completion if was requested */
3887 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags))
3888 rc = o->wait_comp(sc, o);
3894 r->clear_pending(r);
3897 o->revert(sc, p, old_reg_size);
3902 static void ecore_mcast_clear_sched(struct ecore_mcast_obj *o)
3904 ECORE_SMP_MB_BEFORE_CLEAR_BIT();
3905 ECORE_CLEAR_BIT(o->sched_state, o->raw.pstate);
3906 ECORE_SMP_MB_AFTER_CLEAR_BIT();
3909 static void ecore_mcast_set_sched(struct ecore_mcast_obj *o)
3911 ECORE_SMP_MB_BEFORE_CLEAR_BIT();
3912 ECORE_SET_BIT(o->sched_state, o->raw.pstate);
3913 ECORE_SMP_MB_AFTER_CLEAR_BIT();
3916 static bool ecore_mcast_check_sched(struct ecore_mcast_obj *o)
3918 return !!ECORE_TEST_BIT(o->sched_state, o->raw.pstate);
3921 static bool ecore_mcast_check_pending(struct ecore_mcast_obj *o)
3923 return o->raw.check_pending(&o->raw) || o->check_sched(o);
3926 void ecore_init_mcast_obj(struct bxe_softc *sc,
3927 struct ecore_mcast_obj *mcast_obj,
3928 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,
3929 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,
3930 int state, unsigned long *pstate, ecore_obj_type type)
3932 ECORE_MEMSET(mcast_obj, 0, sizeof(*mcast_obj));
3934 ecore_init_raw_obj(&mcast_obj->raw, mcast_cl_id, mcast_cid, func_id,
3935 rdata, rdata_mapping, state, pstate, type);
3937 mcast_obj->engine_id = engine_id;
3939 ECORE_LIST_INIT(&mcast_obj->pending_cmds_head);
3941 mcast_obj->sched_state = ECORE_FILTER_MCAST_SCHED;
3942 mcast_obj->check_sched = ecore_mcast_check_sched;
3943 mcast_obj->set_sched = ecore_mcast_set_sched;
3944 mcast_obj->clear_sched = ecore_mcast_clear_sched;
3946 if (CHIP_IS_E1(sc)) {
3947 mcast_obj->config_mcast = ecore_mcast_setup_e1;
3948 mcast_obj->enqueue_cmd = ecore_mcast_enqueue_cmd;
3949 mcast_obj->hdl_restore =
3950 ecore_mcast_handle_restore_cmd_e1;
3951 mcast_obj->check_pending = ecore_mcast_check_pending;
3953 if (CHIP_REV_IS_SLOW(sc))
3954 mcast_obj->max_cmd_len = ECORE_MAX_EMUL_MULTI;
3956 mcast_obj->max_cmd_len = ECORE_MAX_MULTICAST;
3958 mcast_obj->wait_comp = ecore_mcast_wait;
3959 mcast_obj->set_one_rule = ecore_mcast_set_one_rule_e1;
3960 mcast_obj->validate = ecore_mcast_validate_e1;
3961 mcast_obj->revert = ecore_mcast_revert_e1;
3962 mcast_obj->get_registry_size =
3963 ecore_mcast_get_registry_size_exact;
3964 mcast_obj->set_registry_size =
3965 ecore_mcast_set_registry_size_exact;
3967 /* 57710 is the only chip that uses the exact match for mcast
3970 ECORE_LIST_INIT(&mcast_obj->registry.exact_match.macs);
3972 } else if (CHIP_IS_E1H(sc)) {
3973 mcast_obj->config_mcast = ecore_mcast_setup_e1h;
3974 mcast_obj->enqueue_cmd = NULL;
3975 mcast_obj->hdl_restore = NULL;
3976 mcast_obj->check_pending = ecore_mcast_check_pending;
3978 /* 57711 doesn't send a ramrod, so it has unlimited credit
3981 mcast_obj->max_cmd_len = -1;
3982 mcast_obj->wait_comp = ecore_mcast_wait;
3983 mcast_obj->set_one_rule = NULL;
3984 mcast_obj->validate = ecore_mcast_validate_e1h;
3985 mcast_obj->revert = ecore_mcast_revert_e1h;
3986 mcast_obj->get_registry_size =
3987 ecore_mcast_get_registry_size_aprox;
3988 mcast_obj->set_registry_size =
3989 ecore_mcast_set_registry_size_aprox;
3991 mcast_obj->config_mcast = ecore_mcast_setup_e2;
3992 mcast_obj->enqueue_cmd = ecore_mcast_enqueue_cmd;
3993 mcast_obj->hdl_restore =
3994 ecore_mcast_handle_restore_cmd_e2;
3995 mcast_obj->check_pending = ecore_mcast_check_pending;
3996 /* TODO: There should be a proper HSI define for this number!!!
3998 mcast_obj->max_cmd_len = 16;
3999 mcast_obj->wait_comp = ecore_mcast_wait;
4000 mcast_obj->set_one_rule = ecore_mcast_set_one_rule_e2;
4001 mcast_obj->validate = ecore_mcast_validate_e2;
4002 mcast_obj->revert = ecore_mcast_revert_e2;
4003 mcast_obj->get_registry_size =
4004 ecore_mcast_get_registry_size_aprox;
4005 mcast_obj->set_registry_size =
4006 ecore_mcast_set_registry_size_aprox;
4010 /*************************** Credit handling **********************************/
4013 * atomic_add_ifless - add if the result is less than a given value.
4015 * @v: pointer of type ecore_atomic_t
4016 * @a: the amount to add to v...
4017 * @u: ...if (v + a) is less than u.
4019 * returns TRUE if (v + a) was less than u, and FALSE otherwise.
4022 static inline bool __atomic_add_ifless(ecore_atomic_t *v, int a, int u)
4026 c = ECORE_ATOMIC_READ(v);
4028 if (ECORE_UNLIKELY(c + a >= u))
4031 old = ECORE_ATOMIC_CMPXCHG((v), c, c + a);
4032 if (ECORE_LIKELY(old == c))
4041 * atomic_dec_ifmoe - dec if the result is more or equal than a given value.
4043 * @v: pointer of type ecore_atomic_t
4044 * @a: the amount to dec from v...
4045 * @u: ...if (v - a) is more or equal than u.
4047 * returns TRUE if (v - a) was more or equal than u, and FALSE
4050 static inline bool __atomic_dec_ifmoe(ecore_atomic_t *v, int a, int u)
4054 c = ECORE_ATOMIC_READ(v);
4056 if (ECORE_UNLIKELY(c - a < u))
4059 old = ECORE_ATOMIC_CMPXCHG((v), c, c - a);
4060 if (ECORE_LIKELY(old == c))
4068 static bool ecore_credit_pool_get(struct ecore_credit_pool_obj *o, int cnt)
4073 rc = __atomic_dec_ifmoe(&o->credit, cnt, 0);
4079 static bool ecore_credit_pool_put(struct ecore_credit_pool_obj *o, int cnt)
4085 /* Don't let to refill if credit + cnt > pool_sz */
4086 rc = __atomic_add_ifless(&o->credit, cnt, o->pool_sz + 1);
4093 static int ecore_credit_pool_check(struct ecore_credit_pool_obj *o)
4098 cur_credit = ECORE_ATOMIC_READ(&o->credit);
4103 static bool ecore_credit_pool_always_TRUE(struct ecore_credit_pool_obj *o,
4109 static bool ecore_credit_pool_get_entry(
4110 struct ecore_credit_pool_obj *o,
4117 /* Find "internal cam-offset" then add to base for this object... */
4118 for (vec = 0; vec < ECORE_POOL_VEC_SIZE; vec++) {
4120 /* Skip the current vector if there are no free entries in it */
4121 if (!o->pool_mirror[vec])
4124 /* If we've got here we are going to find a free entry */
4125 for (idx = vec * BIT_VEC64_ELEM_SZ, i = 0;
4126 i < BIT_VEC64_ELEM_SZ; idx++, i++)
4128 if (BIT_VEC64_TEST_BIT(o->pool_mirror, idx)) {
4130 BIT_VEC64_CLEAR_BIT(o->pool_mirror, idx);
4131 *offset = o->base_pool_offset + idx;
4139 static bool ecore_credit_pool_put_entry(
4140 struct ecore_credit_pool_obj *o,
4143 if (offset < o->base_pool_offset)
4146 offset -= o->base_pool_offset;
4148 if (offset >= o->pool_sz)
4151 /* Return the entry to the pool */
4152 BIT_VEC64_SET_BIT(o->pool_mirror, offset);
4157 static bool ecore_credit_pool_put_entry_always_TRUE(
4158 struct ecore_credit_pool_obj *o,
4164 static bool ecore_credit_pool_get_entry_always_TRUE(
4165 struct ecore_credit_pool_obj *o,
4172 * ecore_init_credit_pool - initialize credit pool internals.
4175 * @base: Base entry in the CAM to use.
4176 * @credit: pool size.
4178 * If base is negative no CAM entries handling will be performed.
4179 * If credit is negative pool operations will always succeed (unlimited pool).
4182 static inline void ecore_init_credit_pool(struct ecore_credit_pool_obj *p,
4183 int base, int credit)
4185 /* Zero the object first */
4186 ECORE_MEMSET(p, 0, sizeof(*p));
4188 /* Set the table to all 1s */
4189 ECORE_MEMSET(&p->pool_mirror, 0xff, sizeof(p->pool_mirror));
4191 /* Init a pool as full */
4192 ECORE_ATOMIC_SET(&p->credit, credit);
4194 /* The total poll size */
4195 p->pool_sz = credit;
4197 p->base_pool_offset = base;
4199 /* Commit the change */
4202 p->check = ecore_credit_pool_check;
4204 /* if pool credit is negative - disable the checks */
4206 p->put = ecore_credit_pool_put;
4207 p->get = ecore_credit_pool_get;
4208 p->put_entry = ecore_credit_pool_put_entry;
4209 p->get_entry = ecore_credit_pool_get_entry;
4211 p->put = ecore_credit_pool_always_TRUE;
4212 p->get = ecore_credit_pool_always_TRUE;
4213 p->put_entry = ecore_credit_pool_put_entry_always_TRUE;
4214 p->get_entry = ecore_credit_pool_get_entry_always_TRUE;
4217 /* If base is negative - disable entries handling */
4219 p->put_entry = ecore_credit_pool_put_entry_always_TRUE;
4220 p->get_entry = ecore_credit_pool_get_entry_always_TRUE;
4224 void ecore_init_mac_credit_pool(struct bxe_softc *sc,
4225 struct ecore_credit_pool_obj *p, uint8_t func_id,
4228 /* TODO: this will be defined in consts as well... */
4229 #define ECORE_CAM_SIZE_EMUL 5
4233 if (CHIP_IS_E1(sc)) {
4234 /* In E1, Multicast is saved in cam... */
4235 if (!CHIP_REV_IS_SLOW(sc))
4236 cam_sz = (MAX_MAC_CREDIT_E1 / 2) - ECORE_MAX_MULTICAST;
4238 cam_sz = ECORE_CAM_SIZE_EMUL - ECORE_MAX_EMUL_MULTI;
4240 ecore_init_credit_pool(p, func_id * cam_sz, cam_sz);
4242 } else if (CHIP_IS_E1H(sc)) {
4243 /* CAM credit is equally divided between all active functions
4246 if ((func_num > 0)) {
4247 if (!CHIP_REV_IS_SLOW(sc))
4248 cam_sz = (MAX_MAC_CREDIT_E1H / (2*func_num));
4250 cam_sz = ECORE_CAM_SIZE_EMUL;
4251 ecore_init_credit_pool(p, func_id * cam_sz, cam_sz);
4253 /* this should never happen! Block MAC operations. */
4254 ecore_init_credit_pool(p, 0, 0);
4260 * CAM credit is equaly divided between all active functions
4263 if ((func_num > 1)) {
4264 if (!CHIP_REV_IS_SLOW(sc))
4265 cam_sz = (MAX_MAC_CREDIT_E2
4266 - GET_NUM_VFS_PER_PATH(sc))
4268 + GET_NUM_VFS_PER_PF(sc);
4270 cam_sz = ECORE_CAM_SIZE_EMUL;
4272 /* No need for CAM entries handling for 57712 and
4275 ecore_init_credit_pool(p, -1, cam_sz);
4276 } else if (func_num == 1) {
4277 if (!CHIP_REV_IS_SLOW(sc))
4278 cam_sz = MAX_MAC_CREDIT_E2;
4280 cam_sz = ECORE_CAM_SIZE_EMUL;
4282 /* No need for CAM entries handling for 57712 and
4285 ecore_init_credit_pool(p, -1, cam_sz);
4287 /* this should never happen! Block MAC operations. */
4288 ecore_init_credit_pool(p, 0, 0);
4293 void ecore_init_vlan_credit_pool(struct bxe_softc *sc,
4294 struct ecore_credit_pool_obj *p,
4298 if (CHIP_IS_E1x(sc)) {
4299 /* There is no VLAN credit in HW on 57710 and 57711 only
4300 * MAC / MAC-VLAN can be set
4302 ecore_init_credit_pool(p, 0, -1);
4304 /* CAM credit is equally divided between all active functions
4308 int credit = MAX_VLAN_CREDIT_E2 / func_num;
4309 ecore_init_credit_pool(p, func_id * credit, credit);
4311 /* this should never happen! Block VLAN operations. */
4312 ecore_init_credit_pool(p, 0, 0);
4316 /****************** RSS Configuration ******************/
4319 * ecore_setup_rss - configure RSS
4321 * @sc: device handle
4322 * @p: rss configuration
4324 * sends on UPDATE ramrod for that matter.
4326 static int ecore_setup_rss(struct bxe_softc *sc,
4327 struct ecore_config_rss_params *p)
4329 struct ecore_rss_config_obj *o = p->rss_obj;
4330 struct ecore_raw_obj *r = &o->raw;
4331 struct eth_rss_update_ramrod_data *data =
4332 (struct eth_rss_update_ramrod_data *)(r->rdata);
4333 uint8_t rss_mode = 0;
4336 ECORE_MEMSET(data, 0, sizeof(*data));
4338 ECORE_MSG(sc, "Configuring RSS\n");
4340 /* Set an echo field */
4341 data->echo = ECORE_CPU_TO_LE32((r->cid & ECORE_SWCID_MASK) |
4342 (r->state << ECORE_SWCID_SHIFT));
4345 if (ECORE_TEST_BIT(ECORE_RSS_MODE_DISABLED, &p->rss_flags))
4346 rss_mode = ETH_RSS_MODE_DISABLED;
4347 else if (ECORE_TEST_BIT(ECORE_RSS_MODE_REGULAR, &p->rss_flags))
4348 rss_mode = ETH_RSS_MODE_REGULAR;
4349 #if defined(__VMKLNX__) && (VMWARE_ESX_DDK_VERSION < 55000) /* ! BNX2X_UPSTREAM */
4350 else if (ECORE_TEST_BIT(ECORE_RSS_MODE_ESX51, &p->rss_flags))
4351 rss_mode = ETH_RSS_MODE_ESX51;
4354 data->rss_mode = rss_mode;
4356 ECORE_MSG(sc, "rss_mode=%d\n", rss_mode);
4358 /* RSS capabilities */
4359 if (ECORE_TEST_BIT(ECORE_RSS_IPV4, &p->rss_flags))
4360 data->capabilities |=
4361 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
4363 if (ECORE_TEST_BIT(ECORE_RSS_IPV4_TCP, &p->rss_flags))
4364 data->capabilities |=
4365 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
4367 if (ECORE_TEST_BIT(ECORE_RSS_IPV4_UDP, &p->rss_flags))
4368 data->capabilities |=
4369 ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
4371 if (ECORE_TEST_BIT(ECORE_RSS_IPV6, &p->rss_flags))
4372 data->capabilities |=
4373 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
4375 if (ECORE_TEST_BIT(ECORE_RSS_IPV6_TCP, &p->rss_flags))
4376 data->capabilities |=
4377 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
4379 if (ECORE_TEST_BIT(ECORE_RSS_IPV6_UDP, &p->rss_flags))
4380 data->capabilities |=
4381 ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
4383 if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {
4384 data->udp_4tuple_dst_port_mask = ECORE_CPU_TO_LE16(p->tunnel_mask);
4385 data->udp_4tuple_dst_port_value =
4386 ECORE_CPU_TO_LE16(p->tunnel_value);
4390 data->rss_result_mask = p->rss_result_mask;
4393 data->rss_engine_id = o->engine_id;
4395 ECORE_MSG(sc, "rss_engine_id=%d\n", data->rss_engine_id);
4397 /* Indirection table */
4398 ECORE_MEMCPY(data->indirection_table, p->ind_table,
4399 T_ETH_INDIRECTION_TABLE_SIZE);
4401 /* Remember the last configuration */
4402 ECORE_MEMCPY(o->ind_table, p->ind_table, T_ETH_INDIRECTION_TABLE_SIZE);
4406 if (ECORE_TEST_BIT(ECORE_RSS_SET_SRCH, &p->rss_flags)) {
4407 ECORE_MEMCPY(&data->rss_key[0], &p->rss_key[0],
4408 sizeof(data->rss_key));
4409 data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
4412 /* No need for an explicit memory barrier here as long we would
4413 * need to ensure the ordering of writing to the SPQ element
4414 * and updating of the SPQ producer which involves a memory
4415 * read and we will have to put a full memory barrier there
4416 * (inside ecore_sp_post()).
4420 rc = ecore_sp_post(sc,
4421 RAMROD_CMD_ID_ETH_RSS_UPDATE,
4424 ETH_CONNECTION_TYPE);
4429 return ECORE_PENDING;
4432 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj,
4435 ECORE_MEMCPY(ind_table, rss_obj->ind_table, sizeof(rss_obj->ind_table));
4438 int ecore_config_rss(struct bxe_softc *sc,
4439 struct ecore_config_rss_params *p)
4442 struct ecore_rss_config_obj *o = p->rss_obj;
4443 struct ecore_raw_obj *r = &o->raw;
4445 /* Do nothing if only driver cleanup was requested */
4446 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &p->ramrod_flags))
4447 return ECORE_SUCCESS;
4451 rc = o->config_rss(sc, p);
4453 r->clear_pending(r);
4457 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, &p->ramrod_flags))
4458 rc = r->wait_comp(sc, r);
4463 void ecore_init_rss_config_obj(struct bxe_softc *sc,
4464 struct ecore_rss_config_obj *rss_obj,
4465 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,
4466 void *rdata, ecore_dma_addr_t rdata_mapping,
4467 int state, unsigned long *pstate,
4468 ecore_obj_type type)
4470 ecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,
4471 rdata_mapping, state, pstate, type);
4473 rss_obj->engine_id = engine_id;
4474 rss_obj->config_rss = ecore_setup_rss;
4477 int validate_vlan_mac(struct bxe_softc *sc,
4478 struct ecore_vlan_mac_obj *vlan_mac)
4480 if (!vlan_mac->get_n_elements) {
4481 ECORE_ERR("vlan mac object was not intialized\n");
4487 /********************** Queue state object ***********************************/
4490 * ecore_queue_state_change - perform Queue state change transition
4492 * @sc: device handle
4493 * @params: parameters to perform the transition
4495 * returns 0 in case of successfully completed transition, negative error
4496 * code in case of failure, positive (EBUSY) value if there is a completion
4497 * to that is still pending (possible only if RAMROD_COMP_WAIT is
4498 * not set in params->ramrod_flags for asynchronous commands).
4501 int ecore_queue_state_change(struct bxe_softc *sc,
4502 struct ecore_queue_state_params *params)
4504 struct ecore_queue_sp_obj *o = params->q_obj;
4505 int rc, pending_bit;
4506 unsigned long *pending = &o->pending;
4508 /* Check that the requested transition is legal */
4509 rc = o->check_transition(sc, o, params);
4511 ECORE_ERR("check transition returned an error. rc %d\n", rc);
4515 /* Set "pending" bit */
4516 ECORE_MSG(sc, "pending bit was=%lx\n", o->pending);
4517 pending_bit = o->set_pending(o, params);
4518 ECORE_MSG(sc, "pending bit now=%lx\n", o->pending);
4520 /* Don't send a command if only driver cleanup was requested */
4521 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags))
4522 o->complete_cmd(sc, o, pending_bit);
4525 rc = o->send_cmd(sc, params);
4527 o->next_state = ECORE_Q_STATE_MAX;
4528 ECORE_CLEAR_BIT(pending_bit, pending);
4529 ECORE_SMP_MB_AFTER_CLEAR_BIT();
4533 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
4534 rc = o->wait_comp(sc, o, pending_bit);
4538 return ECORE_SUCCESS;
4542 return ECORE_RET_PENDING(pending_bit, pending);
4545 static int ecore_queue_set_pending(struct ecore_queue_sp_obj *obj,
4546 struct ecore_queue_state_params *params)
4548 enum ecore_queue_cmd cmd = params->cmd, bit;
4550 /* ACTIVATE and DEACTIVATE commands are implemented on top of
4553 if ((cmd == ECORE_Q_CMD_ACTIVATE) ||
4554 (cmd == ECORE_Q_CMD_DEACTIVATE))
4555 bit = ECORE_Q_CMD_UPDATE;
4559 ECORE_SET_BIT(bit, &obj->pending);
4563 static int ecore_queue_wait_comp(struct bxe_softc *sc,
4564 struct ecore_queue_sp_obj *o,
4565 enum ecore_queue_cmd cmd)
4567 return ecore_state_wait(sc, cmd, &o->pending);
4571 * ecore_queue_comp_cmd - complete the state change command.
4573 * @sc: device handle
4577 * Checks that the arrived completion is expected.
4579 static int ecore_queue_comp_cmd(struct bxe_softc *sc,
4580 struct ecore_queue_sp_obj *o,
4581 enum ecore_queue_cmd cmd)
4583 unsigned long cur_pending = o->pending;
4585 if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {
4586 ECORE_ERR("Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\n",
4587 cmd, o->cids[ECORE_PRIMARY_CID_INDEX],
4588 o->state, cur_pending, o->next_state);
4592 if (o->next_tx_only >= o->max_cos)
4593 /* >= because tx only must always be smaller than cos since the
4594 * primary connection supports COS 0
4596 ECORE_ERR("illegal value for next tx_only: %d. max cos was %d",
4597 o->next_tx_only, o->max_cos);
4600 "Completing command %d for queue %d, setting state to %d\n",
4601 cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->next_state);
4603 if (o->next_tx_only) /* print num tx-only if any exist */
4604 ECORE_MSG(sc, "primary cid %d: num tx-only cons %d\n",
4605 o->cids[ECORE_PRIMARY_CID_INDEX], o->next_tx_only);
4607 o->state = o->next_state;
4608 o->num_tx_only = o->next_tx_only;
4609 o->next_state = ECORE_Q_STATE_MAX;
4611 /* It's important that o->state and o->next_state are
4612 * updated before o->pending.
4616 ECORE_CLEAR_BIT(cmd, &o->pending);
4617 ECORE_SMP_MB_AFTER_CLEAR_BIT();
4619 return ECORE_SUCCESS;
4622 static void ecore_q_fill_setup_data_e2(struct bxe_softc *sc,
4623 struct ecore_queue_state_params *cmd_params,
4624 struct client_init_ramrod_data *data)
4626 struct ecore_queue_setup_params *params = &cmd_params->params.setup;
4630 /* IPv6 TPA supported for E2 and above only */
4631 data->rx.tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_IPV6,
4633 CLIENT_INIT_RX_DATA_TPA_EN_IPV6;
4636 static void ecore_q_fill_init_general_data(struct bxe_softc *sc,
4637 struct ecore_queue_sp_obj *o,
4638 struct ecore_general_setup_params *params,
4639 struct client_init_general_data *gen_data,
4640 unsigned long *flags)
4642 gen_data->client_id = o->cl_id;
4644 if (ECORE_TEST_BIT(ECORE_Q_FLG_STATS, flags)) {
4645 gen_data->statistics_counter_id =
4647 gen_data->statistics_en_flg = 1;
4648 gen_data->statistics_zero_flg =
4649 ECORE_TEST_BIT(ECORE_Q_FLG_ZERO_STATS, flags);
4651 gen_data->statistics_counter_id =
4652 DISABLE_STATISTIC_COUNTER_ID_VALUE;
4654 gen_data->is_fcoe_flg = ECORE_TEST_BIT(ECORE_Q_FLG_FCOE,
4656 gen_data->activate_flg = ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE,
4658 gen_data->sp_client_id = params->spcl_id;
4659 gen_data->mtu = ECORE_CPU_TO_LE16(params->mtu);
4660 gen_data->func_id = o->func_id;
4662 gen_data->cos = params->cos;
4664 gen_data->traffic_type =
4665 ECORE_TEST_BIT(ECORE_Q_FLG_FCOE, flags) ?
4666 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
4668 ECORE_MSG(sc, "flags: active %d, cos %d, stats en %d\n",
4669 gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
4672 static void ecore_q_fill_init_tx_data(struct ecore_queue_sp_obj *o,
4673 struct ecore_txq_setup_params *params,
4674 struct client_init_tx_data *tx_data,
4675 unsigned long *flags)
4677 tx_data->enforce_security_flg =
4678 ECORE_TEST_BIT(ECORE_Q_FLG_TX_SEC, flags);
4679 tx_data->default_vlan =
4680 ECORE_CPU_TO_LE16(params->default_vlan);
4681 tx_data->default_vlan_flg =
4682 ECORE_TEST_BIT(ECORE_Q_FLG_DEF_VLAN, flags);
4683 tx_data->tx_switching_flg =
4684 ECORE_TEST_BIT(ECORE_Q_FLG_TX_SWITCH, flags);
4685 tx_data->anti_spoofing_flg =
4686 ECORE_TEST_BIT(ECORE_Q_FLG_ANTI_SPOOF, flags);
4687 tx_data->force_default_pri_flg =
4688 ECORE_TEST_BIT(ECORE_Q_FLG_FORCE_DEFAULT_PRI, flags);
4689 tx_data->refuse_outband_vlan_flg =
4690 ECORE_TEST_BIT(ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
4691 tx_data->tunnel_lso_inc_ip_id =
4692 ECORE_TEST_BIT(ECORE_Q_FLG_TUN_INC_INNER_IP_ID, flags);
4693 tx_data->tunnel_non_lso_pcsum_location =
4694 ECORE_TEST_BIT(ECORE_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
4697 tx_data->tx_status_block_id = params->fw_sb_id;
4698 tx_data->tx_sb_index_number = params->sb_cq_index;
4699 tx_data->tss_leading_client_id = params->tss_leading_cl_id;
4701 tx_data->tx_bd_page_base.lo =
4702 ECORE_CPU_TO_LE32(U64_LO(params->dscr_map));
4703 tx_data->tx_bd_page_base.hi =
4704 ECORE_CPU_TO_LE32(U64_HI(params->dscr_map));
4706 /* Don't configure any Tx switching mode during queue SETUP */
4710 static void ecore_q_fill_init_pause_data(struct ecore_queue_sp_obj *o,
4711 struct rxq_pause_params *params,
4712 struct client_init_rx_data *rx_data)
4714 /* flow control data */
4715 rx_data->cqe_pause_thr_low = ECORE_CPU_TO_LE16(params->rcq_th_lo);
4716 rx_data->cqe_pause_thr_high = ECORE_CPU_TO_LE16(params->rcq_th_hi);
4717 rx_data->bd_pause_thr_low = ECORE_CPU_TO_LE16(params->bd_th_lo);
4718 rx_data->bd_pause_thr_high = ECORE_CPU_TO_LE16(params->bd_th_hi);
4719 rx_data->sge_pause_thr_low = ECORE_CPU_TO_LE16(params->sge_th_lo);
4720 rx_data->sge_pause_thr_high = ECORE_CPU_TO_LE16(params->sge_th_hi);
4721 rx_data->rx_cos_mask = ECORE_CPU_TO_LE16(params->pri_map);
4724 static void ecore_q_fill_init_rx_data(struct ecore_queue_sp_obj *o,
4725 struct ecore_rxq_setup_params *params,
4726 struct client_init_rx_data *rx_data,
4727 unsigned long *flags)
4729 rx_data->tpa_en = ECORE_TEST_BIT(ECORE_Q_FLG_TPA, flags) *
4730 CLIENT_INIT_RX_DATA_TPA_EN_IPV4;
4731 rx_data->tpa_en |= ECORE_TEST_BIT(ECORE_Q_FLG_TPA_GRO, flags) *
4732 CLIENT_INIT_RX_DATA_TPA_MODE;
4733 rx_data->vmqueue_mode_en_flg = 0;
4735 rx_data->extra_data_over_sgl_en_flg =
4736 ECORE_TEST_BIT(ECORE_Q_FLG_OOO, flags);
4737 rx_data->cache_line_alignment_log_size =
4738 params->cache_line_log;
4739 rx_data->enable_dynamic_hc =
4740 ECORE_TEST_BIT(ECORE_Q_FLG_DHC, flags);
4741 rx_data->max_sges_for_packet = params->max_sges_pkt;
4742 rx_data->client_qzone_id = params->cl_qzone_id;
4743 rx_data->max_agg_size = ECORE_CPU_TO_LE16(params->tpa_agg_sz);
4745 /* Always start in DROP_ALL mode */
4746 rx_data->state = ECORE_CPU_TO_LE16(CLIENT_INIT_RX_DATA_UCAST_DROP_ALL |
4747 CLIENT_INIT_RX_DATA_MCAST_DROP_ALL);
4749 /* We don't set drop flags */
4750 rx_data->drop_ip_cs_err_flg = 0;
4751 rx_data->drop_tcp_cs_err_flg = 0;
4752 rx_data->drop_ttl0_flg = 0;
4753 rx_data->drop_udp_cs_err_flg = 0;
4754 rx_data->inner_vlan_removal_enable_flg =
4755 ECORE_TEST_BIT(ECORE_Q_FLG_VLAN, flags);
4756 rx_data->outer_vlan_removal_enable_flg =
4757 ECORE_TEST_BIT(ECORE_Q_FLG_OV, flags);
4758 rx_data->status_block_id = params->fw_sb_id;
4759 rx_data->rx_sb_index_number = params->sb_cq_index;
4760 rx_data->max_tpa_queues = params->max_tpa_queues;
4761 rx_data->max_bytes_on_bd = ECORE_CPU_TO_LE16(params->buf_sz);
4762 rx_data->sge_buff_size = ECORE_CPU_TO_LE16(params->sge_buf_sz);
4763 rx_data->bd_page_base.lo =
4764 ECORE_CPU_TO_LE32(U64_LO(params->dscr_map));
4765 rx_data->bd_page_base.hi =
4766 ECORE_CPU_TO_LE32(U64_HI(params->dscr_map));
4767 rx_data->sge_page_base.lo =
4768 ECORE_CPU_TO_LE32(U64_LO(params->sge_map));
4769 rx_data->sge_page_base.hi =
4770 ECORE_CPU_TO_LE32(U64_HI(params->sge_map));
4771 rx_data->cqe_page_base.lo =
4772 ECORE_CPU_TO_LE32(U64_LO(params->rcq_map));
4773 rx_data->cqe_page_base.hi =
4774 ECORE_CPU_TO_LE32(U64_HI(params->rcq_map));
4775 rx_data->is_leading_rss = ECORE_TEST_BIT(ECORE_Q_FLG_LEADING_RSS,
4778 if (ECORE_TEST_BIT(ECORE_Q_FLG_MCAST, flags)) {
4779 rx_data->approx_mcast_engine_id = params->mcast_engine_id;
4780 rx_data->is_approx_mcast = 1;
4783 rx_data->rss_engine_id = params->rss_engine_id;
4785 /* silent vlan removal */
4786 rx_data->silent_vlan_removal_flg =
4787 ECORE_TEST_BIT(ECORE_Q_FLG_SILENT_VLAN_REM, flags);
4788 rx_data->silent_vlan_value =
4789 ECORE_CPU_TO_LE16(params->silent_removal_value);
4790 rx_data->silent_vlan_mask =
4791 ECORE_CPU_TO_LE16(params->silent_removal_mask);
4794 /* initialize the general, tx and rx parts of a queue object */
4795 static void ecore_q_fill_setup_data_cmn(struct bxe_softc *sc,
4796 struct ecore_queue_state_params *cmd_params,
4797 struct client_init_ramrod_data *data)
4799 ecore_q_fill_init_general_data(sc, cmd_params->q_obj,
4800 &cmd_params->params.setup.gen_params,
4802 &cmd_params->params.setup.flags);
4804 ecore_q_fill_init_tx_data(cmd_params->q_obj,
4805 &cmd_params->params.setup.txq_params,
4807 &cmd_params->params.setup.flags);
4809 ecore_q_fill_init_rx_data(cmd_params->q_obj,
4810 &cmd_params->params.setup.rxq_params,
4812 &cmd_params->params.setup.flags);
4814 ecore_q_fill_init_pause_data(cmd_params->q_obj,
4815 &cmd_params->params.setup.pause_params,
4819 /* initialize the general and tx parts of a tx-only queue object */
4820 static void ecore_q_fill_setup_tx_only(struct bxe_softc *sc,
4821 struct ecore_queue_state_params *cmd_params,
4822 struct tx_queue_init_ramrod_data *data)
4824 ecore_q_fill_init_general_data(sc, cmd_params->q_obj,
4825 &cmd_params->params.tx_only.gen_params,
4827 &cmd_params->params.tx_only.flags);
4829 ecore_q_fill_init_tx_data(cmd_params->q_obj,
4830 &cmd_params->params.tx_only.txq_params,
4832 &cmd_params->params.tx_only.flags);
4834 ECORE_MSG(sc, "cid %d, tx bd page lo %x hi %x",
4835 cmd_params->q_obj->cids[0],
4836 data->tx.tx_bd_page_base.lo,
4837 data->tx.tx_bd_page_base.hi);
4841 * ecore_q_init - init HW/FW queue
4843 * @sc: device handle
4846 * HW/FW initial Queue configuration:
4848 * - CDU context validation
4851 static inline int ecore_q_init(struct bxe_softc *sc,
4852 struct ecore_queue_state_params *params)
4854 struct ecore_queue_sp_obj *o = params->q_obj;
4855 struct ecore_queue_init_params *init = ¶ms->params.init;
4859 /* Tx HC configuration */
4860 if (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_TX, &o->type) &&
4861 ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->tx.flags)) {
4862 hc_usec = init->tx.hc_rate ? 1000000 / init->tx.hc_rate : 0;
4864 ECORE_UPDATE_COALESCE_SB_INDEX(sc, init->tx.fw_sb_id,
4865 init->tx.sb_cq_index,
4866 !ECORE_TEST_BIT(ECORE_Q_FLG_HC_EN, &init->tx.flags),
4870 /* Rx HC configuration */
4871 if (ECORE_TEST_BIT(ECORE_Q_TYPE_HAS_RX, &o->type) &&
4872 ECORE_TEST_BIT(ECORE_Q_FLG_HC, &init->rx.flags)) {
4873 hc_usec = init->rx.hc_rate ? 1000000 / init->rx.hc_rate : 0;
4875 ECORE_UPDATE_COALESCE_SB_INDEX(sc, init->rx.fw_sb_id,
4876 init->rx.sb_cq_index,
4877 !ECORE_TEST_BIT(ECORE_Q_FLG_HC_EN, &init->rx.flags),
4881 /* Set CDU context validation values */
4882 for (cos = 0; cos < o->max_cos; cos++) {
4883 ECORE_MSG(sc, "setting context validation. cid %d, cos %d\n",
4885 ECORE_MSG(sc, "context pointer %p\n", init->cxts[cos]);
4886 ECORE_SET_CTX_VALIDATION(sc, init->cxts[cos], o->cids[cos]);
4889 /* As no ramrod is sent, complete the command immediately */
4890 o->complete_cmd(sc, o, ECORE_Q_CMD_INIT);
4895 return ECORE_SUCCESS;
4898 static inline int ecore_q_send_setup_e1x(struct bxe_softc *sc,
4899 struct ecore_queue_state_params *params)
4901 struct ecore_queue_sp_obj *o = params->q_obj;
4902 struct client_init_ramrod_data *rdata =
4903 (struct client_init_ramrod_data *)o->rdata;
4904 ecore_dma_addr_t data_mapping = o->rdata_mapping;
4905 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4907 /* Clear the ramrod data */
4908 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
4910 /* Fill the ramrod data */
4911 ecore_q_fill_setup_data_cmn(sc, params, rdata);
4913 /* No need for an explicit memory barrier here as long we would
4914 * need to ensure the ordering of writing to the SPQ element
4915 * and updating of the SPQ producer which involves a memory
4916 * read and we will have to put a full memory barrier there
4917 * (inside ecore_sp_post()).
4920 return ecore_sp_post(sc,
4922 o->cids[ECORE_PRIMARY_CID_INDEX],
4924 ETH_CONNECTION_TYPE);
4927 static inline int ecore_q_send_setup_e2(struct bxe_softc *sc,
4928 struct ecore_queue_state_params *params)
4930 struct ecore_queue_sp_obj *o = params->q_obj;
4931 struct client_init_ramrod_data *rdata =
4932 (struct client_init_ramrod_data *)o->rdata;
4933 ecore_dma_addr_t data_mapping = o->rdata_mapping;
4934 int ramrod = RAMROD_CMD_ID_ETH_CLIENT_SETUP;
4936 /* Clear the ramrod data */
4937 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
4939 /* Fill the ramrod data */
4940 ecore_q_fill_setup_data_cmn(sc, params, rdata);
4941 ecore_q_fill_setup_data_e2(sc, params, rdata);
4943 /* No need for an explicit memory barrier here as long we would
4944 * need to ensure the ordering of writing to the SPQ element
4945 * and updating of the SPQ producer which involves a memory
4946 * read and we will have to put a full memory barrier there
4947 * (inside ecore_sp_post()).
4950 return ecore_sp_post(sc,
4952 o->cids[ECORE_PRIMARY_CID_INDEX],
4954 ETH_CONNECTION_TYPE);
4957 static inline int ecore_q_send_setup_tx_only(struct bxe_softc *sc,
4958 struct ecore_queue_state_params *params)
4960 struct ecore_queue_sp_obj *o = params->q_obj;
4961 struct tx_queue_init_ramrod_data *rdata =
4962 (struct tx_queue_init_ramrod_data *)o->rdata;
4963 ecore_dma_addr_t data_mapping = o->rdata_mapping;
4964 int ramrod = RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP;
4965 struct ecore_queue_setup_tx_only_params *tx_only_params =
4966 ¶ms->params.tx_only;
4967 uint8_t cid_index = tx_only_params->cid_index;
4969 if (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &o->type))
4970 ramrod = RAMROD_CMD_ID_ETH_FORWARD_SETUP;
4971 ECORE_MSG(sc, "sending forward tx-only ramrod");
4973 if (cid_index >= o->max_cos) {
4974 ECORE_ERR("queue[%d]: cid_index (%d) is out of range\n",
4975 o->cl_id, cid_index);
4979 ECORE_MSG(sc, "parameters received: cos: %d sp-id: %d\n",
4980 tx_only_params->gen_params.cos,
4981 tx_only_params->gen_params.spcl_id);
4983 /* Clear the ramrod data */
4984 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
4986 /* Fill the ramrod data */
4987 ecore_q_fill_setup_tx_only(sc, params, rdata);
4989 ECORE_MSG(sc, "sending tx-only ramrod: cid %d, client-id %d, sp-client id %d, cos %d\n",
4990 o->cids[cid_index], rdata->general.client_id,
4991 rdata->general.sp_client_id, rdata->general.cos);
4993 /* No need for an explicit memory barrier here as long we would
4994 * need to ensure the ordering of writing to the SPQ element
4995 * and updating of the SPQ producer which involves a memory
4996 * read and we will have to put a full memory barrier there
4997 * (inside ecore_sp_post()).
5000 return ecore_sp_post(sc, ramrod, o->cids[cid_index],
5001 data_mapping, ETH_CONNECTION_TYPE);
5004 static void ecore_q_fill_update_data(struct bxe_softc *sc,
5005 struct ecore_queue_sp_obj *obj,
5006 struct ecore_queue_update_params *params,
5007 struct client_update_ramrod_data *data)
5009 /* Client ID of the client to update */
5010 data->client_id = obj->cl_id;
5012 /* Function ID of the client to update */
5013 data->func_id = obj->func_id;
5015 /* Default VLAN value */
5016 data->default_vlan = ECORE_CPU_TO_LE16(params->def_vlan);
5018 /* Inner VLAN stripping */
5019 data->inner_vlan_removal_enable_flg =
5020 ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM,
5021 ¶ms->update_flags);
5022 data->inner_vlan_removal_change_flg =
5023 ECORE_TEST_BIT(ECORE_Q_UPDATE_IN_VLAN_REM_CHNG,
5024 ¶ms->update_flags);
5026 /* Outer VLAN stripping */
5027 data->outer_vlan_removal_enable_flg =
5028 ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM,
5029 ¶ms->update_flags);
5030 data->outer_vlan_removal_change_flg =
5031 ECORE_TEST_BIT(ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG,
5032 ¶ms->update_flags);
5034 /* Drop packets that have source MAC that doesn't belong to this
5037 data->anti_spoofing_enable_flg =
5038 ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF,
5039 ¶ms->update_flags);
5040 data->anti_spoofing_change_flg =
5041 ECORE_TEST_BIT(ECORE_Q_UPDATE_ANTI_SPOOF_CHNG,
5042 ¶ms->update_flags);
5044 /* Activate/Deactivate */
5045 data->activate_flg =
5046 ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE, ¶ms->update_flags);
5047 data->activate_change_flg =
5048 ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,
5049 ¶ms->update_flags);
5051 /* Enable default VLAN */
5052 data->default_vlan_enable_flg =
5053 ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN,
5054 ¶ms->update_flags);
5055 data->default_vlan_change_flg =
5056 ECORE_TEST_BIT(ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG,
5057 ¶ms->update_flags);
5059 /* silent vlan removal */
5060 data->silent_vlan_change_flg =
5061 ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG,
5062 ¶ms->update_flags);
5063 data->silent_vlan_removal_flg =
5064 ECORE_TEST_BIT(ECORE_Q_UPDATE_SILENT_VLAN_REM,
5065 ¶ms->update_flags);
5066 data->silent_vlan_value = ECORE_CPU_TO_LE16(params->silent_removal_value);
5067 data->silent_vlan_mask = ECORE_CPU_TO_LE16(params->silent_removal_mask);
5070 data->tx_switching_flg =
5071 ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING,
5072 ¶ms->update_flags);
5073 data->tx_switching_change_flg =
5074 ECORE_TEST_BIT(ECORE_Q_UPDATE_TX_SWITCHING_CHNG,
5075 ¶ms->update_flags);
5078 static inline int ecore_q_send_update(struct bxe_softc *sc,
5079 struct ecore_queue_state_params *params)
5081 struct ecore_queue_sp_obj *o = params->q_obj;
5082 struct client_update_ramrod_data *rdata =
5083 (struct client_update_ramrod_data *)o->rdata;
5084 ecore_dma_addr_t data_mapping = o->rdata_mapping;
5085 struct ecore_queue_update_params *update_params =
5086 ¶ms->params.update;
5087 uint8_t cid_index = update_params->cid_index;
5089 if (cid_index >= o->max_cos) {
5090 ECORE_ERR("queue[%d]: cid_index (%d) is out of range\n",
5091 o->cl_id, cid_index);
5095 /* Clear the ramrod data */
5096 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
5098 /* Fill the ramrod data */
5099 ecore_q_fill_update_data(sc, o, update_params, rdata);
5101 /* No need for an explicit memory barrier here as long we would
5102 * need to ensure the ordering of writing to the SPQ element
5103 * and updating of the SPQ producer which involves a memory
5104 * read and we will have to put a full memory barrier there
5105 * (inside ecore_sp_post()).
5108 return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_CLIENT_UPDATE,
5109 o->cids[cid_index], data_mapping,
5110 ETH_CONNECTION_TYPE);
5114 * ecore_q_send_deactivate - send DEACTIVATE command
5116 * @sc: device handle
5119 * implemented using the UPDATE command.
5121 static inline int ecore_q_send_deactivate(struct bxe_softc *sc,
5122 struct ecore_queue_state_params *params)
5124 struct ecore_queue_update_params *update = ¶ms->params.update;
5126 ECORE_MEMSET(update, 0, sizeof(*update));
5128 ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5130 return ecore_q_send_update(sc, params);
5134 * ecore_q_send_activate - send ACTIVATE command
5136 * @sc: device handle
5139 * implemented using the UPDATE command.
5141 static inline int ecore_q_send_activate(struct bxe_softc *sc,
5142 struct ecore_queue_state_params *params)
5144 struct ecore_queue_update_params *update = ¶ms->params.update;
5146 ECORE_MEMSET(update, 0, sizeof(*update));
5148 ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE, &update->update_flags);
5149 ECORE_SET_BIT_NA(ECORE_Q_UPDATE_ACTIVATE_CHNG, &update->update_flags);
5151 return ecore_q_send_update(sc, params);
5154 static inline int ecore_q_send_update_tpa(struct bxe_softc *sc,
5155 struct ecore_queue_state_params *params)
5157 /* TODO: Not implemented yet. */
5161 static inline int ecore_q_send_halt(struct bxe_softc *sc,
5162 struct ecore_queue_state_params *params)
5164 struct ecore_queue_sp_obj *o = params->q_obj;
5166 /* build eth_halt_ramrod_data.client_id in a big-endian friendly way */
5167 ecore_dma_addr_t data_mapping = 0;
5168 data_mapping = (ecore_dma_addr_t)o->cl_id;
5170 return ecore_sp_post(sc,
5171 RAMROD_CMD_ID_ETH_HALT,
5172 o->cids[ECORE_PRIMARY_CID_INDEX],
5174 ETH_CONNECTION_TYPE);
5177 static inline int ecore_q_send_cfc_del(struct bxe_softc *sc,
5178 struct ecore_queue_state_params *params)
5180 struct ecore_queue_sp_obj *o = params->q_obj;
5181 uint8_t cid_idx = params->params.cfc_del.cid_index;
5183 if (cid_idx >= o->max_cos) {
5184 ECORE_ERR("queue[%d]: cid_index (%d) is out of range\n",
5189 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_CFC_DEL,
5190 o->cids[cid_idx], 0,
5191 NONE_CONNECTION_TYPE);
5194 static inline int ecore_q_send_terminate(struct bxe_softc *sc,
5195 struct ecore_queue_state_params *params)
5197 struct ecore_queue_sp_obj *o = params->q_obj;
5198 uint8_t cid_index = params->params.terminate.cid_index;
5200 if (cid_index >= o->max_cos) {
5201 ECORE_ERR("queue[%d]: cid_index (%d) is out of range\n",
5202 o->cl_id, cid_index);
5206 return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_TERMINATE,
5207 o->cids[cid_index], 0,
5208 ETH_CONNECTION_TYPE);
5211 static inline int ecore_q_send_empty(struct bxe_softc *sc,
5212 struct ecore_queue_state_params *params)
5214 struct ecore_queue_sp_obj *o = params->q_obj;
5216 return ecore_sp_post(sc, RAMROD_CMD_ID_ETH_EMPTY,
5217 o->cids[ECORE_PRIMARY_CID_INDEX], 0,
5218 ETH_CONNECTION_TYPE);
5221 static inline int ecore_queue_send_cmd_cmn(struct bxe_softc *sc,
5222 struct ecore_queue_state_params *params)
5224 switch (params->cmd) {
5225 case ECORE_Q_CMD_INIT:
5226 return ecore_q_init(sc, params);
5227 case ECORE_Q_CMD_SETUP_TX_ONLY:
5228 return ecore_q_send_setup_tx_only(sc, params);
5229 case ECORE_Q_CMD_DEACTIVATE:
5230 return ecore_q_send_deactivate(sc, params);
5231 case ECORE_Q_CMD_ACTIVATE:
5232 return ecore_q_send_activate(sc, params);
5233 case ECORE_Q_CMD_UPDATE:
5234 return ecore_q_send_update(sc, params);
5235 case ECORE_Q_CMD_UPDATE_TPA:
5236 return ecore_q_send_update_tpa(sc, params);
5237 case ECORE_Q_CMD_HALT:
5238 return ecore_q_send_halt(sc, params);
5239 case ECORE_Q_CMD_CFC_DEL:
5240 return ecore_q_send_cfc_del(sc, params);
5241 case ECORE_Q_CMD_TERMINATE:
5242 return ecore_q_send_terminate(sc, params);
5243 case ECORE_Q_CMD_EMPTY:
5244 return ecore_q_send_empty(sc, params);
5246 ECORE_ERR("Unknown command: %d\n", params->cmd);
5251 static int ecore_queue_send_cmd_e1x(struct bxe_softc *sc,
5252 struct ecore_queue_state_params *params)
5254 switch (params->cmd) {
5255 case ECORE_Q_CMD_SETUP:
5256 return ecore_q_send_setup_e1x(sc, params);
5257 case ECORE_Q_CMD_INIT:
5258 case ECORE_Q_CMD_SETUP_TX_ONLY:
5259 case ECORE_Q_CMD_DEACTIVATE:
5260 case ECORE_Q_CMD_ACTIVATE:
5261 case ECORE_Q_CMD_UPDATE:
5262 case ECORE_Q_CMD_UPDATE_TPA:
5263 case ECORE_Q_CMD_HALT:
5264 case ECORE_Q_CMD_CFC_DEL:
5265 case ECORE_Q_CMD_TERMINATE:
5266 case ECORE_Q_CMD_EMPTY:
5267 return ecore_queue_send_cmd_cmn(sc, params);
5269 ECORE_ERR("Unknown command: %d\n", params->cmd);
5274 static int ecore_queue_send_cmd_e2(struct bxe_softc *sc,
5275 struct ecore_queue_state_params *params)
5277 switch (params->cmd) {
5278 case ECORE_Q_CMD_SETUP:
5279 return ecore_q_send_setup_e2(sc, params);
5280 case ECORE_Q_CMD_INIT:
5281 case ECORE_Q_CMD_SETUP_TX_ONLY:
5282 case ECORE_Q_CMD_DEACTIVATE:
5283 case ECORE_Q_CMD_ACTIVATE:
5284 case ECORE_Q_CMD_UPDATE:
5285 case ECORE_Q_CMD_UPDATE_TPA:
5286 case ECORE_Q_CMD_HALT:
5287 case ECORE_Q_CMD_CFC_DEL:
5288 case ECORE_Q_CMD_TERMINATE:
5289 case ECORE_Q_CMD_EMPTY:
5290 return ecore_queue_send_cmd_cmn(sc, params);
5292 ECORE_ERR("Unknown command: %d\n", params->cmd);
5298 * ecore_queue_chk_transition - check state machine of a regular Queue
5300 * @sc: device handle
5305 * It both checks if the requested command is legal in a current
5306 * state and, if it's legal, sets a `next_state' in the object
5307 * that will be used in the completion flow to set the `state'
5310 * returns 0 if a requested command is a legal transition,
5311 * ECORE_INVAL otherwise.
5313 static int ecore_queue_chk_transition(struct bxe_softc *sc,
5314 struct ecore_queue_sp_obj *o,
5315 struct ecore_queue_state_params *params)
5317 enum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX;
5318 enum ecore_queue_cmd cmd = params->cmd;
5319 struct ecore_queue_update_params *update_params =
5320 ¶ms->params.update;
5321 uint8_t next_tx_only = o->num_tx_only;
5323 /* Forget all pending for completion commands if a driver only state
5324 * transition has been requested.
5326 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5328 o->next_state = ECORE_Q_STATE_MAX;
5331 /* Don't allow a next state transition if we are in the middle of
5335 ECORE_ERR("Blocking transition since pending was %lx\n",
5341 case ECORE_Q_STATE_RESET:
5342 if (cmd == ECORE_Q_CMD_INIT)
5343 next_state = ECORE_Q_STATE_INITIALIZED;
5346 case ECORE_Q_STATE_INITIALIZED:
5347 if (cmd == ECORE_Q_CMD_SETUP) {
5348 if (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE,
5349 ¶ms->params.setup.flags))
5350 next_state = ECORE_Q_STATE_ACTIVE;
5352 next_state = ECORE_Q_STATE_INACTIVE;
5356 case ECORE_Q_STATE_ACTIVE:
5357 if (cmd == ECORE_Q_CMD_DEACTIVATE)
5358 next_state = ECORE_Q_STATE_INACTIVE;
5360 else if ((cmd == ECORE_Q_CMD_EMPTY) ||
5361 (cmd == ECORE_Q_CMD_UPDATE_TPA))
5362 next_state = ECORE_Q_STATE_ACTIVE;
5364 else if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {
5365 next_state = ECORE_Q_STATE_MULTI_COS;
5369 else if (cmd == ECORE_Q_CMD_HALT)
5370 next_state = ECORE_Q_STATE_STOPPED;
5372 else if (cmd == ECORE_Q_CMD_UPDATE) {
5373 /* If "active" state change is requested, update the
5374 * state accordingly.
5376 if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,
5377 &update_params->update_flags) &&
5378 !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,
5379 &update_params->update_flags))
5380 next_state = ECORE_Q_STATE_INACTIVE;
5382 next_state = ECORE_Q_STATE_ACTIVE;
5386 case ECORE_Q_STATE_MULTI_COS:
5387 if (cmd == ECORE_Q_CMD_TERMINATE)
5388 next_state = ECORE_Q_STATE_MCOS_TERMINATED;
5390 else if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {
5391 next_state = ECORE_Q_STATE_MULTI_COS;
5392 next_tx_only = o->num_tx_only + 1;
5395 else if ((cmd == ECORE_Q_CMD_EMPTY) ||
5396 (cmd == ECORE_Q_CMD_UPDATE_TPA))
5397 next_state = ECORE_Q_STATE_MULTI_COS;
5399 else if (cmd == ECORE_Q_CMD_UPDATE) {
5400 /* If "active" state change is requested, update the
5401 * state accordingly.
5403 if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,
5404 &update_params->update_flags) &&
5405 !ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,
5406 &update_params->update_flags))
5407 next_state = ECORE_Q_STATE_INACTIVE;
5409 next_state = ECORE_Q_STATE_MULTI_COS;
5413 case ECORE_Q_STATE_MCOS_TERMINATED:
5414 if (cmd == ECORE_Q_CMD_CFC_DEL) {
5415 next_tx_only = o->num_tx_only - 1;
5416 if (next_tx_only == 0)
5417 next_state = ECORE_Q_STATE_ACTIVE;
5419 next_state = ECORE_Q_STATE_MULTI_COS;
5423 case ECORE_Q_STATE_INACTIVE:
5424 if (cmd == ECORE_Q_CMD_ACTIVATE)
5425 next_state = ECORE_Q_STATE_ACTIVE;
5427 else if ((cmd == ECORE_Q_CMD_EMPTY) ||
5428 (cmd == ECORE_Q_CMD_UPDATE_TPA))
5429 next_state = ECORE_Q_STATE_INACTIVE;
5431 else if (cmd == ECORE_Q_CMD_HALT)
5432 next_state = ECORE_Q_STATE_STOPPED;
5434 else if (cmd == ECORE_Q_CMD_UPDATE) {
5435 /* If "active" state change is requested, update the
5436 * state accordingly.
5438 if (ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE_CHNG,
5439 &update_params->update_flags) &&
5440 ECORE_TEST_BIT(ECORE_Q_UPDATE_ACTIVATE,
5441 &update_params->update_flags)){
5442 if (o->num_tx_only == 0)
5443 next_state = ECORE_Q_STATE_ACTIVE;
5444 else /* tx only queues exist for this queue */
5445 next_state = ECORE_Q_STATE_MULTI_COS;
5447 next_state = ECORE_Q_STATE_INACTIVE;
5451 case ECORE_Q_STATE_STOPPED:
5452 if (cmd == ECORE_Q_CMD_TERMINATE)
5453 next_state = ECORE_Q_STATE_TERMINATED;
5456 case ECORE_Q_STATE_TERMINATED:
5457 if (cmd == ECORE_Q_CMD_CFC_DEL)
5458 next_state = ECORE_Q_STATE_RESET;
5462 ECORE_ERR("Illegal state: %d\n", state);
5465 /* Transition is assured */
5466 if (next_state != ECORE_Q_STATE_MAX) {
5467 ECORE_MSG(sc, "Good state transition: %d(%d)->%d\n",
5468 state, cmd, next_state);
5469 o->next_state = next_state;
5470 o->next_tx_only = next_tx_only;
5471 return ECORE_SUCCESS;
5474 ECORE_MSG(sc, "Bad state transition request: %d %d\n", state, cmd);
5480 * ecore_queue_chk_fwd_transition - check state machine of a Forwarding Queue.
5482 * @sc: device handle
5486 * It both checks if the requested command is legal in a current
5487 * state and, if it's legal, sets a `next_state' in the object
5488 * that will be used in the completion flow to set the `state'
5491 * returns 0 if a requested command is a legal transition,
5492 * ECORE_INVAL otherwise.
5494 static int ecore_queue_chk_fwd_transition(struct bxe_softc *sc,
5495 struct ecore_queue_sp_obj *o,
5496 struct ecore_queue_state_params *params)
5498 enum ecore_q_state state = o->state, next_state = ECORE_Q_STATE_MAX;
5499 enum ecore_queue_cmd cmd = params->cmd;
5502 case ECORE_Q_STATE_RESET:
5503 if (cmd == ECORE_Q_CMD_INIT)
5504 next_state = ECORE_Q_STATE_INITIALIZED;
5507 case ECORE_Q_STATE_INITIALIZED:
5508 if (cmd == ECORE_Q_CMD_SETUP_TX_ONLY) {
5509 if (ECORE_TEST_BIT(ECORE_Q_FLG_ACTIVE,
5510 ¶ms->params.tx_only.flags))
5511 next_state = ECORE_Q_STATE_ACTIVE;
5513 next_state = ECORE_Q_STATE_INACTIVE;
5517 case ECORE_Q_STATE_ACTIVE:
5518 case ECORE_Q_STATE_INACTIVE:
5519 if (cmd == ECORE_Q_CMD_CFC_DEL)
5520 next_state = ECORE_Q_STATE_RESET;
5524 ECORE_ERR("Illegal state: %d\n", state);
5527 /* Transition is assured */
5528 if (next_state != ECORE_Q_STATE_MAX) {
5529 ECORE_MSG(sc, "Good state transition: %d(%d)->%d\n",
5530 state, cmd, next_state);
5531 o->next_state = next_state;
5532 return ECORE_SUCCESS;
5535 ECORE_MSG(sc, "Bad state transition request: %d %d\n", state, cmd);
5539 void ecore_init_queue_obj(struct bxe_softc *sc,
5540 struct ecore_queue_sp_obj *obj,
5541 uint8_t cl_id, uint32_t *cids, uint8_t cid_cnt, uint8_t func_id,
5543 ecore_dma_addr_t rdata_mapping, unsigned long type)
5545 ECORE_MEMSET(obj, 0, sizeof(*obj));
5547 /* We support only ECORE_MULTI_TX_COS Tx CoS at the moment */
5548 ECORE_BUG_ON(ECORE_MULTI_TX_COS < cid_cnt);
5550 memcpy(obj->cids, cids, sizeof(obj->cids[0]) * cid_cnt);
5551 obj->max_cos = cid_cnt;
5553 obj->func_id = func_id;
5555 obj->rdata_mapping = rdata_mapping;
5557 obj->next_state = ECORE_Q_STATE_MAX;
5559 if (CHIP_IS_E1x(sc))
5560 obj->send_cmd = ecore_queue_send_cmd_e1x;
5562 obj->send_cmd = ecore_queue_send_cmd_e2;
5564 if (ECORE_TEST_BIT(ECORE_Q_TYPE_FWD, &type))
5565 obj->check_transition = ecore_queue_chk_fwd_transition;
5567 obj->check_transition = ecore_queue_chk_transition;
5569 obj->complete_cmd = ecore_queue_comp_cmd;
5570 obj->wait_comp = ecore_queue_wait_comp;
5571 obj->set_pending = ecore_queue_set_pending;
5574 /* return a queue object's logical state*/
5575 int ecore_get_q_logical_state(struct bxe_softc *sc,
5576 struct ecore_queue_sp_obj *obj)
5578 switch (obj->state) {
5579 case ECORE_Q_STATE_ACTIVE:
5580 case ECORE_Q_STATE_MULTI_COS:
5581 return ECORE_Q_LOGICAL_STATE_ACTIVE;
5582 case ECORE_Q_STATE_RESET:
5583 case ECORE_Q_STATE_INITIALIZED:
5584 case ECORE_Q_STATE_MCOS_TERMINATED:
5585 case ECORE_Q_STATE_INACTIVE:
5586 case ECORE_Q_STATE_STOPPED:
5587 case ECORE_Q_STATE_TERMINATED:
5588 case ECORE_Q_STATE_FLRED:
5589 return ECORE_Q_LOGICAL_STATE_STOPPED;
5595 /********************** Function state object *********************************/
5596 enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc,
5597 struct ecore_func_sp_obj *o)
5599 /* in the middle of transaction - return INVALID state */
5601 return ECORE_F_STATE_MAX;
5603 /* unsure the order of reading of o->pending and o->state
5604 * o->pending should be read first
5611 static int ecore_func_wait_comp(struct bxe_softc *sc,
5612 struct ecore_func_sp_obj *o,
5613 enum ecore_func_cmd cmd)
5615 return ecore_state_wait(sc, cmd, &o->pending);
5619 * ecore_func_state_change_comp - complete the state machine transition
5621 * @sc: device handle
5625 * Called on state change transition. Completes the state
5626 * machine transition only - no HW interaction.
5628 static inline int ecore_func_state_change_comp(struct bxe_softc *sc,
5629 struct ecore_func_sp_obj *o,
5630 enum ecore_func_cmd cmd)
5632 unsigned long cur_pending = o->pending;
5634 if (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {
5635 ECORE_ERR("Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\n",
5636 cmd, ECORE_FUNC_ID(sc), o->state,
5637 cur_pending, o->next_state);
5642 "Completing command %d for func %d, setting state to %d\n",
5643 cmd, ECORE_FUNC_ID(sc), o->next_state);
5645 o->state = o->next_state;
5646 o->next_state = ECORE_F_STATE_MAX;
5648 /* It's important that o->state and o->next_state are
5649 * updated before o->pending.
5653 ECORE_CLEAR_BIT(cmd, &o->pending);
5654 ECORE_SMP_MB_AFTER_CLEAR_BIT();
5656 return ECORE_SUCCESS;
5660 * ecore_func_comp_cmd - complete the state change command
5662 * @sc: device handle
5666 * Checks that the arrived completion is expected.
5668 static int ecore_func_comp_cmd(struct bxe_softc *sc,
5669 struct ecore_func_sp_obj *o,
5670 enum ecore_func_cmd cmd)
5672 /* Complete the state machine part first, check if it's a
5675 int rc = ecore_func_state_change_comp(sc, o, cmd);
5680 * ecore_func_chk_transition - perform function state machine transition
5682 * @sc: device handle
5686 * It both checks if the requested command is legal in a current
5687 * state and, if it's legal, sets a `next_state' in the object
5688 * that will be used in the completion flow to set the `state'
5691 * returns 0 if a requested command is a legal transition,
5692 * ECORE_INVAL otherwise.
5694 static int ecore_func_chk_transition(struct bxe_softc *sc,
5695 struct ecore_func_sp_obj *o,
5696 struct ecore_func_state_params *params)
5698 enum ecore_func_state state = o->state, next_state = ECORE_F_STATE_MAX;
5699 enum ecore_func_cmd cmd = params->cmd;
5701 /* Forget all pending for completion commands if a driver only state
5702 * transition has been requested.
5704 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
5706 o->next_state = ECORE_F_STATE_MAX;
5709 /* Don't allow a next state transition if we are in the middle of
5716 case ECORE_F_STATE_RESET:
5717 if (cmd == ECORE_F_CMD_HW_INIT)
5718 next_state = ECORE_F_STATE_INITIALIZED;
5721 case ECORE_F_STATE_INITIALIZED:
5722 if (cmd == ECORE_F_CMD_START)
5723 next_state = ECORE_F_STATE_STARTED;
5725 else if (cmd == ECORE_F_CMD_HW_RESET)
5726 next_state = ECORE_F_STATE_RESET;
5729 case ECORE_F_STATE_STARTED:
5730 if (cmd == ECORE_F_CMD_STOP)
5731 next_state = ECORE_F_STATE_INITIALIZED;
5732 /* afex ramrods can be sent only in started mode, and only
5733 * if not pending for function_stop ramrod completion
5734 * for these events - next state remained STARTED.
5736 else if ((cmd == ECORE_F_CMD_AFEX_UPDATE) &&
5737 (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))
5738 next_state = ECORE_F_STATE_STARTED;
5740 else if ((cmd == ECORE_F_CMD_AFEX_VIFLISTS) &&
5741 (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))
5742 next_state = ECORE_F_STATE_STARTED;
5744 /* Switch_update ramrod can be sent in either started or
5745 * tx_stopped state, and it doesn't change the state.
5747 else if ((cmd == ECORE_F_CMD_SWITCH_UPDATE) &&
5748 (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))
5749 next_state = ECORE_F_STATE_STARTED;
5751 else if (cmd == ECORE_F_CMD_TX_STOP)
5752 next_state = ECORE_F_STATE_TX_STOPPED;
5755 case ECORE_F_STATE_TX_STOPPED:
5756 if ((cmd == ECORE_F_CMD_SWITCH_UPDATE) &&
5757 (!ECORE_TEST_BIT(ECORE_F_CMD_STOP, &o->pending)))
5758 next_state = ECORE_F_STATE_TX_STOPPED;
5760 else if (cmd == ECORE_F_CMD_TX_START)
5761 next_state = ECORE_F_STATE_STARTED;
5765 ECORE_ERR("Unknown state: %d\n", state);
5768 /* Transition is assured */
5769 if (next_state != ECORE_F_STATE_MAX) {
5770 ECORE_MSG(sc, "Good function state transition: %d(%d)->%d\n",
5771 state, cmd, next_state);
5772 o->next_state = next_state;
5773 return ECORE_SUCCESS;
5776 ECORE_MSG(sc, "Bad function state transition request: %d %d\n",
5783 * ecore_func_init_func - performs HW init at function stage
5785 * @sc: device handle
5788 * Init HW when the current phase is
5789 * FW_MSG_CODE_DRV_LOAD_FUNCTION: initialize only FUNCTION-only
5792 static inline int ecore_func_init_func(struct bxe_softc *sc,
5793 const struct ecore_func_sp_drv_ops *drv)
5795 return drv->init_hw_func(sc);
5799 * ecore_func_init_port - performs HW init at port stage
5801 * @sc: device handle
5804 * Init HW when the current phase is
5805 * FW_MSG_CODE_DRV_LOAD_PORT: initialize PORT-only and
5806 * FUNCTION-only HW blocks.
5809 static inline int ecore_func_init_port(struct bxe_softc *sc,
5810 const struct ecore_func_sp_drv_ops *drv)
5812 int rc = drv->init_hw_port(sc);
5816 return ecore_func_init_func(sc, drv);
5820 * ecore_func_init_cmn_chip - performs HW init at chip-common stage
5822 * @sc: device handle
5825 * Init HW when the current phase is
5826 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON_CHIP,
5827 * PORT-only and FUNCTION-only HW blocks.
5829 static inline int ecore_func_init_cmn_chip(struct bxe_softc *sc,
5830 const struct ecore_func_sp_drv_ops *drv)
5832 int rc = drv->init_hw_cmn_chip(sc);
5836 return ecore_func_init_port(sc, drv);
5840 * ecore_func_init_cmn - performs HW init at common stage
5842 * @sc: device handle
5845 * Init HW when the current phase is
5846 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: initialize COMMON,
5847 * PORT-only and FUNCTION-only HW blocks.
5849 static inline int ecore_func_init_cmn(struct bxe_softc *sc,
5850 const struct ecore_func_sp_drv_ops *drv)
5852 int rc = drv->init_hw_cmn(sc);
5856 return ecore_func_init_port(sc, drv);
5859 static int ecore_func_hw_init(struct bxe_softc *sc,
5860 struct ecore_func_state_params *params)
5862 uint32_t load_code = params->params.hw_init.load_phase;
5863 struct ecore_func_sp_obj *o = params->f_obj;
5864 const struct ecore_func_sp_drv_ops *drv = o->drv;
5867 ECORE_MSG(sc, "function %d load_code %x\n",
5868 ECORE_ABS_FUNC_ID(sc), load_code);
5870 /* Prepare buffers for unzipping the FW */
5871 rc = drv->gunzip_init(sc);
5876 rc = drv->init_fw(sc);
5878 ECORE_ERR("Error loading firmware\n");
5882 /* Handle the beginning of COMMON_XXX pases separately... */
5883 switch (load_code) {
5884 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5885 rc = ecore_func_init_cmn_chip(sc, drv);
5890 case FW_MSG_CODE_DRV_LOAD_COMMON:
5891 rc = ecore_func_init_cmn(sc, drv);
5896 case FW_MSG_CODE_DRV_LOAD_PORT:
5897 rc = ecore_func_init_port(sc, drv);
5902 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5903 rc = ecore_func_init_func(sc, drv);
5909 ECORE_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5914 drv->gunzip_end(sc);
5916 /* In case of success, complete the command immediately: no ramrods
5920 o->complete_cmd(sc, o, ECORE_F_CMD_HW_INIT);
5926 * ecore_func_reset_func - reset HW at function stage
5928 * @sc: device handle
5931 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_FUNCTION stage: reset only
5932 * FUNCTION-only HW blocks.
5934 static inline void ecore_func_reset_func(struct bxe_softc *sc,
5935 const struct ecore_func_sp_drv_ops *drv)
5937 drv->reset_hw_func(sc);
5941 * ecore_func_reset_port - reser HW at port stage
5943 * @sc: device handle
5946 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_PORT stage: reset
5947 * FUNCTION-only and PORT-only HW blocks.
5951 * It's important to call reset_port before reset_func() as the last thing
5952 * reset_func does is pf_disable() thus disabling PGLUE_B, which
5953 * makes impossible any DMAE transactions.
5955 static inline void ecore_func_reset_port(struct bxe_softc *sc,
5956 const struct ecore_func_sp_drv_ops *drv)
5958 drv->reset_hw_port(sc);
5959 ecore_func_reset_func(sc, drv);
5963 * ecore_func_reset_cmn - reser HW at common stage
5965 * @sc: device handle
5968 * Reset HW at FW_MSG_CODE_DRV_UNLOAD_COMMON and
5969 * FW_MSG_CODE_DRV_UNLOAD_COMMON_CHIP stages: reset COMMON,
5970 * COMMON_CHIP, FUNCTION-only and PORT-only HW blocks.
5972 static inline void ecore_func_reset_cmn(struct bxe_softc *sc,
5973 const struct ecore_func_sp_drv_ops *drv)
5975 ecore_func_reset_port(sc, drv);
5976 drv->reset_hw_cmn(sc);
5979 static inline int ecore_func_hw_reset(struct bxe_softc *sc,
5980 struct ecore_func_state_params *params)
5982 uint32_t reset_phase = params->params.hw_reset.reset_phase;
5983 struct ecore_func_sp_obj *o = params->f_obj;
5984 const struct ecore_func_sp_drv_ops *drv = o->drv;
5986 ECORE_MSG(sc, "function %d reset_phase %x\n", ECORE_ABS_FUNC_ID(sc),
5989 switch (reset_phase) {
5990 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
5991 ecore_func_reset_cmn(sc, drv);
5993 case FW_MSG_CODE_DRV_UNLOAD_PORT:
5994 ecore_func_reset_port(sc, drv);
5996 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
5997 ecore_func_reset_func(sc, drv);
6000 ECORE_ERR("Unknown reset_phase (0x%x) from MCP\n",
6005 /* Complete the command immediately: no ramrods have been sent. */
6006 o->complete_cmd(sc, o, ECORE_F_CMD_HW_RESET);
6008 return ECORE_SUCCESS;
6011 static inline int ecore_func_send_start(struct bxe_softc *sc,
6012 struct ecore_func_state_params *params)
6014 struct ecore_func_sp_obj *o = params->f_obj;
6015 struct function_start_data *rdata =
6016 (struct function_start_data *)o->rdata;
6017 ecore_dma_addr_t data_mapping = o->rdata_mapping;
6018 struct ecore_func_start_params *start_params = ¶ms->params.start;
6020 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
6022 /* Fill the ramrod data with provided parameters */
6023 rdata->function_mode = (uint8_t)start_params->mf_mode;
6024 rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);
6025 rdata->path_id = ECORE_PATH_ID(sc);
6026 rdata->network_cos_mode = start_params->network_cos_mode;
6027 rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
6028 rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
6031 * No need for an explicit memory barrier here as long we would
6032 * need to ensure the ordering of writing to the SPQ element
6033 * and updating of the SPQ producer which involves a memory
6034 * read and we will have to put a full memory barrier there
6035 * (inside ecore_sp_post()).
6038 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_START, 0,
6039 data_mapping, NONE_CONNECTION_TYPE);
6042 static inline int ecore_func_send_switch_update(struct bxe_softc *sc,
6043 struct ecore_func_state_params *params)
6045 struct ecore_func_sp_obj *o = params->f_obj;
6046 struct function_update_data *rdata =
6047 (struct function_update_data *)o->rdata;
6048 ecore_dma_addr_t data_mapping = o->rdata_mapping;
6049 struct ecore_func_switch_update_params *switch_update_params =
6050 ¶ms->params.switch_update;
6052 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
6054 /* Fill the ramrod data with provided parameters */
6055 rdata->tx_switch_suspend_change_flg = 1;
6056 rdata->tx_switch_suspend = switch_update_params->suspend;
6057 rdata->echo = SWITCH_UPDATE;
6059 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6060 data_mapping, NONE_CONNECTION_TYPE);
6063 static inline int ecore_func_send_afex_update(struct bxe_softc *sc,
6064 struct ecore_func_state_params *params)
6066 struct ecore_func_sp_obj *o = params->f_obj;
6067 struct function_update_data *rdata =
6068 (struct function_update_data *)o->afex_rdata;
6069 ecore_dma_addr_t data_mapping = o->afex_rdata_mapping;
6070 struct ecore_func_afex_update_params *afex_update_params =
6071 ¶ms->params.afex_update;
6073 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
6075 /* Fill the ramrod data with provided parameters */
6076 rdata->vif_id_change_flg = 1;
6077 rdata->vif_id = ECORE_CPU_TO_LE16(afex_update_params->vif_id);
6078 rdata->afex_default_vlan_change_flg = 1;
6079 rdata->afex_default_vlan =
6080 ECORE_CPU_TO_LE16(afex_update_params->afex_default_vlan);
6081 rdata->allowed_priorities_change_flg = 1;
6082 rdata->allowed_priorities = afex_update_params->allowed_priorities;
6083 rdata->echo = AFEX_UPDATE;
6085 /* No need for an explicit memory barrier here as long we would
6086 * need to ensure the ordering of writing to the SPQ element
6087 * and updating of the SPQ producer which involves a memory
6088 * read and we will have to put a full memory barrier there
6089 * (inside ecore_sp_post()).
6092 "afex: sending func_update vif_id 0x%x dvlan 0x%x prio 0x%x\n",
6094 rdata->afex_default_vlan, rdata->allowed_priorities);
6096 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE, 0,
6097 data_mapping, NONE_CONNECTION_TYPE);
6101 inline int ecore_func_send_afex_viflists(struct bxe_softc *sc,
6102 struct ecore_func_state_params *params)
6104 struct ecore_func_sp_obj *o = params->f_obj;
6105 struct afex_vif_list_ramrod_data *rdata =
6106 (struct afex_vif_list_ramrod_data *)o->afex_rdata;
6107 struct ecore_func_afex_viflists_params *afex_vif_params =
6108 ¶ms->params.afex_viflists;
6109 uint64_t *p_rdata = (uint64_t *)rdata;
6111 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
6113 /* Fill the ramrod data with provided parameters */
6114 rdata->vif_list_index = ECORE_CPU_TO_LE16(afex_vif_params->vif_list_index);
6115 rdata->func_bit_map = afex_vif_params->func_bit_map;
6116 rdata->afex_vif_list_command = afex_vif_params->afex_vif_list_command;
6117 rdata->func_to_clear = afex_vif_params->func_to_clear;
6119 /* send in echo type of sub command */
6120 rdata->echo = afex_vif_params->afex_vif_list_command;
6122 /* No need for an explicit memory barrier here as long we would
6123 * need to ensure the ordering of writing to the SPQ element
6124 * and updating of the SPQ producer which involves a memory
6125 * read and we will have to put a full memory barrier there
6126 * (inside ecore_sp_post()).
6129 ECORE_MSG(sc, "afex: ramrod lists, cmd 0x%x index 0x%x func_bit_map 0x%x func_to_clr 0x%x\n",
6130 rdata->afex_vif_list_command, rdata->vif_list_index,
6131 rdata->func_bit_map, rdata->func_to_clear);
6133 /* this ramrod sends data directly and not through DMA mapping */
6134 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS, 0,
6135 *p_rdata, NONE_CONNECTION_TYPE);
6138 static inline int ecore_func_send_stop(struct bxe_softc *sc,
6139 struct ecore_func_state_params *params)
6141 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_FUNCTION_STOP, 0, 0,
6142 NONE_CONNECTION_TYPE);
6145 static inline int ecore_func_send_tx_stop(struct bxe_softc *sc,
6146 struct ecore_func_state_params *params)
6148 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_STOP_TRAFFIC, 0, 0,
6149 NONE_CONNECTION_TYPE);
6151 static inline int ecore_func_send_tx_start(struct bxe_softc *sc,
6152 struct ecore_func_state_params *params)
6154 struct ecore_func_sp_obj *o = params->f_obj;
6155 struct flow_control_configuration *rdata =
6156 (struct flow_control_configuration *)o->rdata;
6157 ecore_dma_addr_t data_mapping = o->rdata_mapping;
6158 struct ecore_func_tx_start_params *tx_start_params =
6159 ¶ms->params.tx_start;
6162 ECORE_MEMSET(rdata, 0, sizeof(*rdata));
6164 rdata->dcb_enabled = tx_start_params->dcb_enabled;
6165 rdata->dcb_version = tx_start_params->dcb_version;
6166 rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;
6168 for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
6169 rdata->traffic_type_to_priority_cos[i] =
6170 tx_start_params->traffic_type_to_priority_cos[i];
6172 return ecore_sp_post(sc, RAMROD_CMD_ID_COMMON_START_TRAFFIC, 0,
6173 data_mapping, NONE_CONNECTION_TYPE);
6176 static int ecore_func_send_cmd(struct bxe_softc *sc,
6177 struct ecore_func_state_params *params)
6179 switch (params->cmd) {
6180 case ECORE_F_CMD_HW_INIT:
6181 return ecore_func_hw_init(sc, params);
6182 case ECORE_F_CMD_START:
6183 return ecore_func_send_start(sc, params);
6184 case ECORE_F_CMD_STOP:
6185 return ecore_func_send_stop(sc, params);
6186 case ECORE_F_CMD_HW_RESET:
6187 return ecore_func_hw_reset(sc, params);
6188 case ECORE_F_CMD_AFEX_UPDATE:
6189 return ecore_func_send_afex_update(sc, params);
6190 case ECORE_F_CMD_AFEX_VIFLISTS:
6191 return ecore_func_send_afex_viflists(sc, params);
6192 case ECORE_F_CMD_TX_STOP:
6193 return ecore_func_send_tx_stop(sc, params);
6194 case ECORE_F_CMD_TX_START:
6195 return ecore_func_send_tx_start(sc, params);
6196 case ECORE_F_CMD_SWITCH_UPDATE:
6197 return ecore_func_send_switch_update(sc, params);
6199 ECORE_ERR("Unknown command: %d\n", params->cmd);
6204 void ecore_init_func_obj(struct bxe_softc *sc,
6205 struct ecore_func_sp_obj *obj,
6206 void *rdata, ecore_dma_addr_t rdata_mapping,
6207 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping,
6208 struct ecore_func_sp_drv_ops *drv_iface)
6210 ECORE_MEMSET(obj, 0, sizeof(*obj));
6212 ECORE_MUTEX_INIT(&obj->one_pending_mutex);
6215 obj->rdata_mapping = rdata_mapping;
6216 obj->afex_rdata = afex_rdata;
6217 obj->afex_rdata_mapping = afex_rdata_mapping;
6218 obj->send_cmd = ecore_func_send_cmd;
6219 obj->check_transition = ecore_func_chk_transition;
6220 obj->complete_cmd = ecore_func_comp_cmd;
6221 obj->wait_comp = ecore_func_wait_comp;
6222 obj->drv = drv_iface;
6226 * ecore_func_state_change - perform Function state change transition
6228 * @sc: device handle
6229 * @params: parameters to perform the transaction
6231 * returns 0 in case of successfully completed transition,
6232 * negative error code in case of failure, positive
6233 * (EBUSY) value if there is a completion to that is
6234 * still pending (possible only if RAMROD_COMP_WAIT is
6235 * not set in params->ramrod_flags for asynchronous
6238 int ecore_func_state_change(struct bxe_softc *sc,
6239 struct ecore_func_state_params *params)
6241 struct ecore_func_sp_obj *o = params->f_obj;
6243 enum ecore_func_cmd cmd = params->cmd;
6244 unsigned long *pending = &o->pending;
6246 ECORE_MUTEX_LOCK(&o->one_pending_mutex);
6248 /* Check that the requested transition is legal */
6249 rc = o->check_transition(sc, o, params);
6250 if ((rc == ECORE_BUSY) &&
6251 (ECORE_TEST_BIT(RAMROD_RETRY, ¶ms->ramrod_flags))) {
6252 while ((rc == ECORE_BUSY) && (--cnt > 0)) {
6253 ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
6255 ECORE_MUTEX_LOCK(&o->one_pending_mutex);
6256 rc = o->check_transition(sc, o, params);
6258 if (rc == ECORE_BUSY) {
6259 ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
6260 ECORE_ERR("timeout waiting for previous ramrod completion\n");
6264 ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
6268 /* Set "pending" bit */
6269 ECORE_SET_BIT(cmd, pending);
6271 /* Don't send a command if only driver cleanup was requested */
6272 if (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, ¶ms->ramrod_flags)) {
6273 ecore_func_state_change_comp(sc, o, cmd);
6274 ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
6277 rc = o->send_cmd(sc, params);
6279 ECORE_MUTEX_UNLOCK(&o->one_pending_mutex);
6282 o->next_state = ECORE_F_STATE_MAX;
6283 ECORE_CLEAR_BIT(cmd, pending);
6284 ECORE_SMP_MB_AFTER_CLEAR_BIT();
6288 if (ECORE_TEST_BIT(RAMROD_COMP_WAIT, ¶ms->ramrod_flags)) {
6289 rc = o->wait_comp(sc, o, cmd);
6293 return ECORE_SUCCESS;
6297 return ECORE_RET_PENDING(cmd, pending);