2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
37 * The following controllers are supported by this driver:
42 * The following controllers are not supported by this driver:
43 * BCM57710 A0 (pre-production)
45 * External PHY References:
46 * ------------------------
47 * BCM8073 - Dual Port 10GBase-KR Ethernet PHY
48 * BCM8705 - 10Gb Ethernet Serial Transceiver
49 * BCM8706 - 10Gb Ethernet LRM PHY
50 * BCM8726 - Dual Port 10Gb Ethernet LRM PHY
51 * BCM8727 - Dual Port 10Gb Ethernet LRM PHY
52 * BCM8481 - Single Port 10GBase-T Ethernet PHY
53 * BCM84823 - Dual Port 10GBase-T Ethernet PHY
54 * SFX7101 - Solarflare 10GBase-T Ethernet PHY
59 #include "bxe_include.h"
63 #include "hw_dump_reg_st.h"
67 #include "bxe_self_test.h"
69 /* BXE Debug Options */
71 uint32_t bxe_debug = BXE_WARN;
74 /* 1 = 1 in 2,147,483,648 */
75 /* 256 = 1 in 8,388,608 */
76 /* 2048 = 1 in 1,048,576 */
77 /* 65536 = 1 in 32,768 */
78 /* 1048576 = 1 in 2,048 */
79 /* 268435456 = 1 in 8 */
80 /* 536870912 = 1 in 4 */
81 /* 1073741824 = 1 in 2 */
83 /* Controls how often to simulate an mbuf allocation failure. */
84 int bxe_debug_mbuf_allocation_failure = 0;
86 /* Controls how often to simulate a DMA mapping failure. */
87 int bxe_debug_dma_map_addr_failure = 0;
89 /* Controls how often to simulate a bootcode failure. */
90 int bxe_debug_bootcode_running_failure = 0;
93 #define MDIO_INDIRECT_REG_ADDR 0x1f
94 #define MDIO_SET_REG_BANK(sc, reg_bank) \
95 bxe_mdio22_write(sc, MDIO_INDIRECT_REG_ADDR, reg_bank)
97 #define MDIO_ACCESS_TIMEOUT 1000
98 #define BMAC_CONTROL_RX_ENABLE 2
100 /* BXE Build Time Options */
101 /* #define BXE_NVRAM_WRITE 1 */
102 #define BXE_USE_DMAE 1
105 * PCI Device ID Table
106 * Used by bxe_probe() to identify the devices supported by this driver.
108 #define BXE_DEVDESC_MAX 64
110 static struct bxe_type bxe_devs[] = {
111 /* BCM57710 Controllers and OEM boards. */
112 { BRCM_VENDORID, BRCM_DEVICEID_BCM57710, PCI_ANY_ID, PCI_ANY_ID,
113 "Broadcom NetXtreme II BCM57710 10GbE" },
114 /* BCM57711 Controllers and OEM boards. */
115 { BRCM_VENDORID, BRCM_DEVICEID_BCM57711, PCI_ANY_ID, PCI_ANY_ID,
116 "Broadcom NetXtreme II BCM57711 10GbE" },
117 /* BCM57711E Controllers and OEM boards. */
118 { BRCM_VENDORID, BRCM_DEVICEID_BCM57711E, PCI_ANY_ID, PCI_ANY_ID,
119 "Broadcom NetXtreme II BCM57711E 10GbE" },
124 * FreeBSD device entry points.
126 static int bxe_probe(device_t);
127 static int bxe_attach(device_t);
128 static int bxe_detach(device_t);
129 static int bxe_shutdown(device_t);
132 * Driver local functions.
134 static void bxe_tunables_set(struct bxe_softc *);
135 static void bxe_print_adapter_info(struct bxe_softc *);
136 static void bxe_probe_pci_caps(struct bxe_softc *);
137 static void bxe_link_settings_supported(struct bxe_softc *, uint32_t);
138 static void bxe_link_settings_requested(struct bxe_softc *);
139 static int bxe_hwinfo_function_get(struct bxe_softc *);
140 static int bxe_hwinfo_port_get(struct bxe_softc *);
141 static int bxe_hwinfo_common_get(struct bxe_softc *);
142 static void bxe_undi_unload(struct bxe_softc *);
143 static int bxe_setup_leading(struct bxe_softc *);
144 static int bxe_stop_leading(struct bxe_softc *);
145 static int bxe_setup_multi(struct bxe_softc *, int);
146 static int bxe_stop_multi(struct bxe_softc *, int);
147 static int bxe_stop_locked(struct bxe_softc *, int);
148 static int bxe_alloc_buf_rings(struct bxe_softc *);
149 static void bxe_free_buf_rings(struct bxe_softc *);
150 static void bxe_init_locked(struct bxe_softc *, int);
151 static int bxe_wait_ramrod(struct bxe_softc *, int, int, int *, int);
152 static void bxe_init_str_wr(struct bxe_softc *, uint32_t, const uint32_t *,
154 static void bxe_init_ind_wr(struct bxe_softc *, uint32_t, const uint32_t *,
156 static void bxe_init_wr_64(struct bxe_softc *, uint32_t, const uint32_t *,
158 static void bxe_write_big_buf(struct bxe_softc *, uint32_t, uint32_t);
159 static void bxe_init_fill(struct bxe_softc *, uint32_t, int, uint32_t);
160 static void bxe_init_block(struct bxe_softc *, uint32_t, uint32_t);
161 static void bxe_init(void *);
162 static void bxe_release_resources(struct bxe_softc *);
163 static void bxe_reg_wr_ind(struct bxe_softc *, uint32_t, uint32_t);
164 static uint32_t bxe_reg_rd_ind(struct bxe_softc *, uint32_t);
165 static void bxe_post_dmae(struct bxe_softc *, struct dmae_command *, int);
166 static void bxe_wb_wr(struct bxe_softc *, int, uint32_t, uint32_t);
167 static __inline uint32_t bxe_reg_poll(struct bxe_softc *, uint32_t,
169 static int bxe_mc_assert(struct bxe_softc *);
170 static void bxe_panic_dump(struct bxe_softc *);
171 static void bxe_int_enable(struct bxe_softc *);
172 static void bxe_int_disable(struct bxe_softc *);
174 static int bxe_nvram_acquire_lock(struct bxe_softc *);
175 static int bxe_nvram_release_lock(struct bxe_softc *);
176 static void bxe_nvram_enable_access(struct bxe_softc *);
177 static void bxe_nvram_disable_access(struct bxe_softc *);
178 static int bxe_nvram_read_dword (struct bxe_softc *, uint32_t, uint32_t *,
180 static int bxe_nvram_read(struct bxe_softc *, uint32_t, uint8_t *, int);
182 #ifdef BXE_NVRAM_WRITE_SUPPORT
183 static int bxe_nvram_write_dword(struct bxe_softc *, uint32_t, uint32_t,
185 static int bxe_nvram_write1(struct bxe_softc *, uint32_t, uint8_t *, int);
186 static int bxe_nvram_write(struct bxe_softc *, uint32_t, uint8_t *, int);
189 static int bxe_nvram_test(struct bxe_softc *);
191 static __inline void bxe_ack_sb(struct bxe_softc *, uint8_t, uint8_t, uint16_t,
193 static __inline uint16_t bxe_update_fpsb_idx(struct bxe_fastpath *);
194 static uint16_t bxe_ack_int(struct bxe_softc *);
195 static void bxe_sp_event(struct bxe_fastpath *, union eth_rx_cqe *);
196 static int bxe_acquire_hw_lock(struct bxe_softc *, uint32_t);
197 static int bxe_release_hw_lock(struct bxe_softc *, uint32_t);
198 static void bxe_acquire_phy_lock(struct bxe_softc *);
199 static void bxe_release_phy_lock(struct bxe_softc *);
200 static void bxe_pmf_update(struct bxe_softc *);
201 static void bxe_init_port_minmax(struct bxe_softc *);
202 static void bxe_link_attn(struct bxe_softc *);
204 static int bxe_sp_post(struct bxe_softc *, int, int, uint32_t, uint32_t, int);
205 static int bxe_acquire_alr(struct bxe_softc *);
206 static void bxe_release_alr(struct bxe_softc *);
207 static uint16_t bxe_update_dsb_idx(struct bxe_softc *);
208 static void bxe_attn_int_asserted(struct bxe_softc *, uint32_t);
209 static __inline void bxe_attn_int_deasserted0(struct bxe_softc *, uint32_t);
210 static __inline void bxe_attn_int_deasserted1(struct bxe_softc *, uint32_t);
211 static __inline void bxe_attn_int_deasserted2(struct bxe_softc *, uint32_t);
212 static __inline void bxe_attn_int_deasserted3(struct bxe_softc *, uint32_t);
213 static void bxe_attn_int_deasserted(struct bxe_softc *, uint32_t);
214 static void bxe_attn_int(struct bxe_softc *);
216 static void bxe_stats_storm_post(struct bxe_softc *);
217 static void bxe_stats_init(struct bxe_softc *);
218 static void bxe_stats_hw_post(struct bxe_softc *);
219 static int bxe_stats_comp(struct bxe_softc *);
220 static void bxe_stats_pmf_update(struct bxe_softc *);
221 static void bxe_stats_port_base_init(struct bxe_softc *);
222 static void bxe_stats_port_init(struct bxe_softc *);
223 static void bxe_stats_func_base_init(struct bxe_softc *);
224 static void bxe_stats_func_init(struct bxe_softc *);
225 static void bxe_stats_start(struct bxe_softc *);
226 static void bxe_stats_pmf_start(struct bxe_softc *);
227 static void bxe_stats_restart(struct bxe_softc *);
228 static void bxe_stats_bmac_update(struct bxe_softc *);
229 static void bxe_stats_emac_update(struct bxe_softc *);
230 static int bxe_stats_hw_update(struct bxe_softc *);
231 static int bxe_stats_storm_update(struct bxe_softc *);
232 static void bxe_stats_func_base_update(struct bxe_softc *);
233 static void bxe_stats_update(struct bxe_softc *);
234 static void bxe_stats_port_stop(struct bxe_softc *);
235 static void bxe_stats_stop(struct bxe_softc *);
236 static void bxe_stats_do_nothing(struct bxe_softc *);
237 static void bxe_stats_handle(struct bxe_softc *, enum bxe_stats_event);
239 static int bxe_tx_encap(struct bxe_fastpath *, struct mbuf **);
240 static void bxe_tx_start(struct ifnet *);
241 static void bxe_tx_start_locked(struct ifnet *, struct bxe_fastpath *);
242 static int bxe_tx_mq_start(struct ifnet *, struct mbuf *);
243 static int bxe_tx_mq_start_locked(struct ifnet *,
244 struct bxe_fastpath *, struct mbuf *);
245 static void bxe_mq_flush(struct ifnet *ifp);
246 static int bxe_ioctl(struct ifnet *, u_long, caddr_t);
247 static __inline int bxe_has_rx_work(struct bxe_fastpath *);
248 static __inline int bxe_has_tx_work(struct bxe_fastpath *);
250 static void bxe_intr_legacy(void *);
251 static void bxe_task_sp(void *, int);
252 static void bxe_intr_sp(void *);
253 static void bxe_task_fp(void *, int);
254 static void bxe_intr_fp(void *);
255 static void bxe_zero_sb(struct bxe_softc *, int);
256 static void bxe_init_sb(struct bxe_softc *,
257 struct host_status_block *, bus_addr_t, int);
258 static void bxe_zero_def_sb(struct bxe_softc *);
259 static void bxe_init_def_sb(struct bxe_softc *,
260 struct host_def_status_block *, bus_addr_t, int);
261 static void bxe_update_coalesce(struct bxe_softc *);
262 static __inline void bxe_update_rx_prod(struct bxe_softc *,
263 struct bxe_fastpath *, uint16_t, uint16_t, uint16_t);
264 static void bxe_clear_sge_mask_next_elems(struct bxe_fastpath *);
265 static __inline void bxe_init_sge_ring_bit_mask(struct bxe_fastpath *);
266 static int bxe_alloc_tpa_mbuf(struct bxe_fastpath *, int);
267 static int bxe_fill_tpa_pool(struct bxe_fastpath *);
268 static void bxe_free_tpa_pool(struct bxe_fastpath *);
270 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *, uint16_t);
271 static int bxe_fill_sg_chain(struct bxe_fastpath *);
272 static void bxe_free_sg_chain(struct bxe_fastpath *);
274 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *, uint16_t);
275 static int bxe_fill_rx_bd_chain(struct bxe_fastpath *);
276 static void bxe_free_rx_bd_chain(struct bxe_fastpath *);
278 static void bxe_mutexes_alloc(struct bxe_softc *);
279 static void bxe_mutexes_free(struct bxe_softc *);
280 static void bxe_clear_rx_chains(struct bxe_softc *);
281 static int bxe_init_rx_chains(struct bxe_softc *);
282 static void bxe_clear_tx_chains(struct bxe_softc *);
283 static void bxe_init_tx_chains(struct bxe_softc *);
284 static void bxe_init_sp_ring(struct bxe_softc *);
285 static void bxe_init_context(struct bxe_softc *);
286 static void bxe_init_ind_table(struct bxe_softc *);
287 static void bxe_set_client_config(struct bxe_softc *);
288 static void bxe_set_storm_rx_mode(struct bxe_softc *);
289 static void bxe_init_internal_common(struct bxe_softc *);
290 static void bxe_init_internal_port(struct bxe_softc *);
292 static void bxe_init_internal_func(struct bxe_softc *);
293 static void bxe_init_internal(struct bxe_softc *, uint32_t);
294 static int bxe_init_nic(struct bxe_softc *, uint32_t);
295 static void bxe_lb_pckt(struct bxe_softc *);
296 static int bxe_int_mem_test(struct bxe_softc *);
297 static void bxe_enable_blocks_attention (struct bxe_softc *);
299 static void bxe_init_pxp(struct bxe_softc *);
300 static int bxe_init_common(struct bxe_softc *);
301 static int bxe_init_port(struct bxe_softc *);
302 static void bxe_ilt_wr(struct bxe_softc *, uint32_t, bus_addr_t);
303 static int bxe_init_func(struct bxe_softc *);
304 static int bxe_init_hw(struct bxe_softc *, uint32_t);
305 static int bxe_fw_command(struct bxe_softc *, uint32_t);
306 static void bxe_host_structures_free(struct bxe_softc *);
307 static void bxe_dma_map_addr(void *, bus_dma_segment_t *, int, int);
308 static int bxe_host_structures_alloc(device_t);
309 static void bxe_set_mac_addr_e1(struct bxe_softc *, int);
310 static void bxe_set_mac_addr_e1h(struct bxe_softc *, int);
311 static void bxe_set_rx_mode(struct bxe_softc *);
312 static void bxe_reset_func(struct bxe_softc *);
313 static void bxe_reset_port(struct bxe_softc *);
314 static void bxe_reset_common(struct bxe_softc *);
315 static void bxe_reset_chip(struct bxe_softc *, uint32_t);
316 static int bxe_ifmedia_upd(struct ifnet *);
317 static void bxe_ifmedia_status(struct ifnet *, struct ifmediareq *);
318 static __inline void bxe_update_last_max_sge(struct bxe_fastpath *, uint16_t);
319 static void bxe_update_sge_prod(struct bxe_fastpath *,
320 struct eth_fast_path_rx_cqe *);
321 static void bxe_tpa_start(struct bxe_fastpath *, uint16_t, uint16_t, uint16_t);
322 static int bxe_fill_frag_mbuf(struct bxe_softc *, struct bxe_fastpath *,
323 struct mbuf *, struct eth_fast_path_rx_cqe *, uint16_t);
324 static void bxe_tpa_stop(struct bxe_softc *, struct bxe_fastpath *, uint16_t,
325 int, int, union eth_rx_cqe *, uint16_t);
326 static void bxe_rxeof(struct bxe_fastpath *);
327 static void bxe_txeof(struct bxe_fastpath *);
328 static int bxe_watchdog(struct bxe_fastpath *fp);
329 static void bxe_tick(void *);
330 static void bxe_add_sysctls(struct bxe_softc *);
332 static void bxe_write_dmae_phys_len(struct bxe_softc *,
333 bus_addr_t, uint32_t, uint32_t);
335 void bxe_write_dmae(struct bxe_softc *, bus_addr_t, uint32_t, uint32_t);
336 void bxe_read_dmae(struct bxe_softc *, uint32_t, uint32_t);
337 int bxe_set_gpio(struct bxe_softc *, int, uint32_t, uint8_t);
338 int bxe_get_gpio(struct bxe_softc *, int, uint8_t);
339 int bxe_set_spio(struct bxe_softc *, int, uint32_t);
340 int bxe_set_gpio_int(struct bxe_softc *, int, uint32_t, uint8_t);
343 * BXE Debug Data Structure Dump Routines
347 static int bxe_sysctl_driver_state(SYSCTL_HANDLER_ARGS);
348 static int bxe_sysctl_hw_state(SYSCTL_HANDLER_ARGS);
349 static int bxe_sysctl_dump_fw(SYSCTL_HANDLER_ARGS);
350 static int bxe_sysctl_dump_rx_cq_chain(SYSCTL_HANDLER_ARGS);
351 static int bxe_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS);
352 static int bxe_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS);
353 static int bxe_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
354 static int bxe_sysctl_breakpoint(SYSCTL_HANDLER_ARGS);
355 static __noinline void bxe_validate_rx_packet(struct bxe_fastpath *,
356 uint16_t, union eth_rx_cqe *, struct mbuf *);
357 static void bxe_grcdump(struct bxe_softc *, int);
358 static __noinline void bxe_dump_enet(struct bxe_softc *,struct mbuf *);
359 static __noinline void bxe_dump_mbuf (struct bxe_softc *, struct mbuf *);
360 static __noinline void bxe_dump_tx_mbuf_chain(struct bxe_softc *, int, int);
361 static __noinline void bxe_dump_rx_mbuf_chain(struct bxe_softc *, int, int);
362 static __noinline void bxe_dump_tx_parsing_bd(struct bxe_fastpath *,int,
363 struct eth_tx_parse_bd *);
364 static __noinline void bxe_dump_txbd(struct bxe_fastpath *, int,
365 union eth_tx_bd_types *);
366 static __noinline void bxe_dump_rxbd(struct bxe_fastpath *, int,
368 static __noinline void bxe_dump_cqe(struct bxe_fastpath *,
369 int, union eth_rx_cqe *);
370 static __noinline void bxe_dump_tx_chain(struct bxe_fastpath *, int, int);
371 static __noinline void bxe_dump_rx_cq_chain(struct bxe_fastpath *, int, int);
372 static __noinline void bxe_dump_rx_bd_chain(struct bxe_fastpath *, int, int);
373 static __noinline void bxe_dump_status_block(struct bxe_softc *);
374 static __noinline void bxe_dump_stats_block(struct bxe_softc *);
375 static __noinline void bxe_dump_fp_state(struct bxe_fastpath *);
376 static __noinline void bxe_dump_port_state_locked(struct bxe_softc *);
377 static __noinline void bxe_dump_link_vars_state_locked(struct bxe_softc *);
378 static __noinline void bxe_dump_link_params_state_locked(struct bxe_softc *);
379 static __noinline void bxe_dump_driver_state(struct bxe_softc *);
380 static __noinline void bxe_dump_hw_state(struct bxe_softc *);
381 static __noinline void bxe_dump_fw(struct bxe_softc *);
382 static void bxe_decode_mb_msgs(struct bxe_softc *, uint32_t, uint32_t);
383 static void bxe_decode_ramrod_cmd(struct bxe_softc *, int);
384 static void bxe_breakpoint(struct bxe_softc *);
388 #define BXE_DRIVER_VERSION "1.5.52"
390 static void bxe_init_e1_firmware(struct bxe_softc *sc);
391 static void bxe_init_e1h_firmware(struct bxe_softc *sc);
394 * FreeBSD device dispatch table.
396 static device_method_t bxe_methods[] = {
397 /* Device interface (device_if.h) */
398 DEVMETHOD(device_probe, bxe_probe),
399 DEVMETHOD(device_attach, bxe_attach),
400 DEVMETHOD(device_detach, bxe_detach),
401 DEVMETHOD(device_shutdown, bxe_shutdown),
407 static driver_t bxe_driver = {
410 sizeof(struct bxe_softc)
413 static devclass_t bxe_devclass;
415 MODULE_DEPEND(bxe, pci, 1, 1, 1);
416 MODULE_DEPEND(bxe, ether, 1, 1, 1);
417 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0);
420 * Tunable device values
422 static SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters");
423 /* Allowable values are TRUE (1) or FALSE (0). */
425 static int bxe_dcc_enable = FALSE;
426 TUNABLE_INT("hw.bxe.dcc_enable", &bxe_dcc_enable);
427 SYSCTL_UINT(_hw_bxe, OID_AUTO, dcc_enable, CTLFLAG_RDTUN, &bxe_dcc_enable,
428 0, "dcc Enable/Disable");
430 /* Allowable values are TRUE (1) or FALSE (0). */
431 static int bxe_tso_enable = TRUE;
432 TUNABLE_INT("hw.bxe.tso_enable", &bxe_tso_enable);
433 SYSCTL_UINT(_hw_bxe, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bxe_tso_enable,
434 0, "TSO Enable/Disable");
436 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ). */
437 static int bxe_int_mode = 2;
438 TUNABLE_INT("hw.bxe.int_mode", &bxe_int_mode);
439 SYSCTL_UINT(_hw_bxe, OID_AUTO, int_mode, CTLFLAG_RDTUN, &bxe_int_mode,
440 0, "Interrupt (MSI-X|MSI|INTx) mode");
443 * Specifies the number of queues that will be used when a multi-queue
444 * RSS mode is selected using bxe_multi_mode below.
446 * Allowable values are 0 (Auto) or 1 to MAX_CONTEXT (fixed queue number).
448 static int bxe_queue_count = 0;
449 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count);
450 SYSCTL_UINT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN, &bxe_queue_count,
451 0, "Multi-Queue queue count");
454 * ETH_RSS_MODE_DISABLED (0)
455 * Disables all multi-queue/packet sorting algorithms. All
456 * received frames are routed to a single receive queue.
458 * ETH_RSS_MODE_REGULAR (1)
459 * The default mode which assigns incoming frames to receive
460 * queues according to RSS (i.e a 2-tuple match on the source/
461 * destination IP address or a 4-tuple match on the source/
462 * destination IP address and the source/destination TCP port).
465 static int bxe_multi_mode = ETH_RSS_MODE_REGULAR;
466 TUNABLE_INT("hw.bxe.multi_mode", &bxe_multi_mode);
467 SYSCTL_UINT(_hw_bxe, OID_AUTO, multi_mode, CTLFLAG_RDTUN, &bxe_multi_mode,
468 0, "Multi-Queue Mode");
471 * Host interrupt coalescing is controller by these values.
472 * The first frame always causes an interrupt but subsequent
473 * frames are coalesced until the RX/TX ticks timer value
474 * expires and another interrupt occurs. (Ticks are measured
477 static uint32_t bxe_rx_ticks = 25;
478 TUNABLE_INT("hw.bxe.rx_ticks", &bxe_rx_ticks);
479 SYSCTL_UINT(_hw_bxe, OID_AUTO, rx_ticks, CTLFLAG_RDTUN, &bxe_rx_ticks,
482 static uint32_t bxe_tx_ticks = 50;
483 TUNABLE_INT("hw.bxe.tx_ticks", &bxe_tx_ticks);
484 SYSCTL_UINT(_hw_bxe, OID_AUTO, tx_ticks, CTLFLAG_RDTUN, &bxe_tx_ticks,
485 0, "Transmit ticks");
488 * Allows the PCIe maximum read request size value to be manually
489 * set during initialization rather than automatically determined
492 * Allowable values are:
493 * -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB)
495 static int bxe_mrrs = -1;
496 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs);
497 SYSCTL_UINT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN, &bxe_mrrs,
498 0, "PCIe maximum read request size.");
502 * Allows setting the maximum number of received frames to process
503 * during an interrupt.
505 * Allowable values are:
506 * -1 (Unlimited), 0 (None), otherwise specifies the number of RX frames.
508 static int bxe_rx_limit = -1;
509 TUNABLE_INT("hw.bxe.rx_limit", &bxe_rx_limit);
510 SYSCTL_UINT(_hw_bxe, OID_AUTO, rx_limit, CTLFLAG_RDTUN, &bxe_rx_limit,
511 0, "Maximum received frames processed during an interrupt.");
514 * Allows setting the maximum number of transmit frames to process
515 * during an interrupt.
517 * Allowable values are:
518 * -1 (Unlimited), 0 (None), otherwise specifies the number of TX frames.
520 static int bxe_tx_limit = -1;
521 TUNABLE_INT("hw.bxe.tx_limit", &bxe_tx_limit);
522 SYSCTL_UINT(_hw_bxe, OID_AUTO, tx_limit, CTLFLAG_RDTUN, &bxe_tx_limit,
523 0, "Maximum transmit frames processed during an interrupt.");
530 /* 0 is common, 1 is port 0, 2 is port 1. */
531 static int load_count[3];
533 /* Tracks whether MCP firmware is running. */
538 * A debug version of the 32 bit OS register write function to
539 * capture/display values written to the controller.
545 bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val)
548 if ((offset % 4) != 0) {
549 DBPRINT(sc, BXE_WARN,
550 "%s(): Warning! Unaligned write to 0x%jX!\n", __FUNCTION__,
554 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%08X\n",
555 __FUNCTION__, (uintmax_t)offset, val);
557 bus_space_write_4(sc->bxe_btag, sc->bxe_bhandle, offset, val);
561 * A debug version of the 16 bit OS register write function to
562 * capture/display values written to the controller.
568 bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val)
571 if ((offset % 2) != 0) {
572 DBPRINT(sc, BXE_WARN,
573 "%s(): Warning! Unaligned write to 0x%jX!\n", __FUNCTION__,
577 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%04X\n",
578 __FUNCTION__, (uintmax_t)offset, val);
580 bus_space_write_2(sc->bxe_btag, sc->bxe_bhandle, offset, val);
584 * A debug version of the 8 bit OS register write function to
585 * capture/display values written to the controller.
591 bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val)
594 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%02X\n",
595 __FUNCTION__, (uintmax_t)offset, val);
597 bus_space_write_1(sc->bxe_btag, sc->bxe_bhandle, offset, val);
601 * A debug version of the 32 bit OS register read function to
602 * capture/display values read from the controller.
608 bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset)
612 if ((offset % 4) != 0) {
613 DBPRINT(sc, BXE_WARN,
614 "%s(): Warning! Unaligned read from 0x%jX!\n",
615 __FUNCTION__, (uintmax_t)offset);
618 val = bus_space_read_4(sc->bxe_btag, sc->bxe_bhandle, offset);
620 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%08X\n",
621 __FUNCTION__, (uintmax_t)offset, val);
627 * A debug version of the 16 bit OS register read function to
628 * capture/display values read from the controller.
634 bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset)
638 if ((offset % 2) != 0) {
639 DBPRINT(sc, BXE_WARN,
640 "%s(): Warning! Unaligned read from 0x%jX!\n",
641 __FUNCTION__, (uintmax_t)offset);
644 val = bus_space_read_2(sc->bxe_btag, sc->bxe_bhandle, offset);
646 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%08X\n",
647 __FUNCTION__, (uintmax_t)offset, val);
654 * A debug version of the 8 bit OS register write function to
655 * capture/display values written to the controller.
661 bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset)
663 uint8_t val = bus_space_read_1(sc->bxe_btag, sc->bxe_bhandle, offset);
665 DBPRINT(sc, BXE_INSANE_REGS, "%s(): offset = 0x%jX, val = 0x%02X\n",
666 __FUNCTION__, (uintmax_t)offset, val);
673 bxe_read_mf_cfg(struct bxe_softc *sc)
677 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
678 func = 2 * vn + BP_PORT(sc);
680 SHMEM_RD(sc,mf_cfg.func_mf_config[func].config);
686 bxe_e1h_disable(struct bxe_softc *sc)
691 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
692 sc->bxe_ifp->if_drv_flags = 0;
696 bxe_e1h_enable(struct bxe_softc *sc)
701 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
702 sc->bxe_ifp->if_drv_flags = IFF_DRV_RUNNING;
706 * Calculates the sum of vn_min_rates.
707 * It's needed for further normalizing of the min_rates.
709 * sum of vn_min_rates.
711 * 0 - if all the min_rates are 0. In the later case fainess
712 * algorithm should be deactivated. If not all min_rates are
713 * zero then those that are zeroes will be set to 1.
716 bxe_calc_vn_wsum(struct bxe_softc *sc)
718 uint32_t vn_cfg, vn_min_rate;
721 DBENTER(BXE_VERBOSE_LOAD);
725 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
726 vn_cfg = sc->mf_config[vn];
727 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
728 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
729 /* Skip hidden vns */
730 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
732 /* If min rate is zero - set it to 1. */
734 vn_min_rate = DEF_MIN_RATE;
738 sc->vn_wsum += vn_min_rate;
741 /* ... only if all min rates are zeros - disable fairness */
743 sc->cmng.flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
745 sc->cmng.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
747 DBEXIT(BXE_VERBOSE_LOAD);
756 bxe_init_vn_minmax(struct bxe_softc *sc, int vn)
758 struct rate_shaping_vars_per_vn m_rs_vn;
759 struct fairness_vars_per_vn m_fair_vn;
761 uint16_t vn_min_rate, vn_max_rate;
764 vn_cfg = sc->mf_config[vn];
765 func = 2 * vn + BP_PORT(sc);
767 DBENTER(BXE_VERBOSE_LOAD);
769 /* If function is hidden - set min and max to zeroes. */
770 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) {
774 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
775 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
777 * If fairness is enabled (i.e. not all min rates are zero),
778 * and if the current min rate is zero, set it to 1.
779 * This is a requirement of the algorithm.
781 if (sc->vn_wsum && (vn_min_rate == 0))
782 vn_min_rate = DEF_MIN_RATE;
784 vn_max_rate = ((vn_cfg & FUNC_MF_CFG_MAX_BW_MASK) >>
785 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
787 if (vn_max_rate == 0)
790 DBPRINT(sc, BXE_INFO_LOAD,
791 "%s(): func %d: vn_min_rate = %d, vn_max_rate = %d, wsum = %d.\n",
792 __FUNCTION__, func, vn_min_rate, vn_max_rate, sc->vn_wsum);
794 memset(&m_rs_vn, 0, sizeof(struct rate_shaping_vars_per_vn));
795 memset(&m_fair_vn, 0, sizeof(struct fairness_vars_per_vn));
797 /* Global VNIC counter - maximal Mbps for this VNIC. */
798 m_rs_vn.vn_counter.rate = vn_max_rate;
800 /* Quota - number of bytes transmitted in this period. */
801 m_rs_vn.vn_counter.quota =
802 (vn_max_rate * RS_PERIODIC_TIMEOUT_USEC) / 8;
806 * Credit for each period of the fairness algorithm. The
807 * number of bytes in T_FAIR (the VNIC shares the port rate).
808 * vn_wsum should not be larger than 10000, thus
809 * T_FAIR_COEF / (8 * vn_wsum) will always be grater than zero.
811 m_fair_vn.vn_credit_delta =
812 max((uint32_t)(vn_min_rate * (T_FAIR_COEF /
814 (uint32_t)(sc->cmng.fair_vars.fair_threshold * 2));
819 /* Store it to internal memory */
820 for (i = 0; i < sizeof(struct rate_shaping_vars_per_vn) / 4; i++)
821 REG_WR(sc, BAR_XSTORM_INTMEM +
822 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func) + (i * 4),
823 ((uint32_t *)(&m_rs_vn))[i]);
825 for (i = 0; i < sizeof(struct fairness_vars_per_vn) / 4; i++)
826 REG_WR(sc, BAR_XSTORM_INTMEM +
827 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func) + (i * 4),
828 ((uint32_t *)(&m_fair_vn))[i]);
830 DBEXIT(BXE_VERBOSE_LOAD);
834 bxe_congestionmgmt(struct bxe_softc *sc, uint8_t readshm)
838 DBENTER(BXE_VERBOSE_LOAD);
840 /* Read mf conf from shmem. */
844 /* Init rate shaping and fairness contexts */
845 bxe_init_port_minmax(sc);
847 /* vn_weight_sum and enable fairness if not 0 */
848 bxe_calc_vn_wsum(sc);
850 /* calculate and set min-max rate for each vn */
851 for (vn = 0; vn < E1HVN_MAX; vn++)
852 bxe_init_vn_minmax(sc, vn);
854 /* Always enable rate shaping and fairness. */
855 sc->cmng.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
857 DBPRINT(sc, BXE_VERBOSE_LOAD,
858 "%s(): Rate shaping set\n", __FUNCTION__);
861 DBPRINT(sc, BXE_INFO_LOAD, "%s(): All MIN values "
862 "are zeroes, fairness is disabled\n", __FUNCTION__);
864 DBEXIT(BXE_VERBOSE_LOAD);
868 bxe_dcc_event(struct bxe_softc *sc, uint32_t dcc_event)
872 DBENTER(BXE_VERBOSE_LOAD);
874 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
875 if (sc->mf_config[BP_E1HVN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
876 DBPRINT(sc, BXE_INFO_LOAD, "%s(): mf_cfg function "
877 "disabled\n", __FUNCTION__);
878 sc->state = BXE_STATE_DISABLED;
881 DBPRINT(sc, BXE_INFO_LOAD, "%s(): mf_cfg function "
882 "enabled\n", __FUNCTION__);
883 sc->state = BXE_STATE_OPEN;
886 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
888 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
890 bxe_congestionmgmt(sc, TRUE);
891 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
892 REG_WR(sc, BAR_XSTORM_INTMEM +
893 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i*4,
894 ((uint32_t *)(&sc->cmng))[i]);
895 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
898 /* Report results to MCP */
900 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE);
902 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK);
904 DBEXIT(BXE_VERBOSE_LOAD);
908 * Device probe function.
910 * Compares the device to the driver's list of supported devices and
911 * reports back to the OS whether this is the right driver for the device.
914 * BUS_PROBE_DEFAULT on success, positive value on failure.
917 bxe_probe(device_t dev)
919 struct bxe_softc *sc;
922 uint16_t did, sdid, svid, vid;
924 sc = device_get_softc(dev);
928 /* Get the data for the device to be probed. */
929 vid = pci_get_vendor(dev);
930 did = pci_get_device(dev);
931 svid = pci_get_subvendor(dev);
932 sdid = pci_get_subdevice(dev);
934 DBPRINT(sc, BXE_VERBOSE_LOAD,
935 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
936 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
938 /* Look through the list of known devices for a match. */
939 while (t->bxe_name != NULL) {
940 if ((vid == t->bxe_vid) && (did == t->bxe_did) &&
941 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) &&
942 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) {
943 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
947 /* Print out the device identity. */
948 snprintf(descbuf, BXE_DEVDESC_MAX,
949 "%s (%c%d) BXE v:%s\n", t->bxe_name,
950 (((pci_read_config(dev, PCIR_REVID, 4) &
952 (pci_read_config(dev, PCIR_REVID, 4) & 0xf),
955 device_set_desc_copy(dev, descbuf);
956 free(descbuf, M_TEMP);
957 return (BUS_PROBE_DEFAULT);
966 * Prints useful adapter info.
971 /* ToDo: Create a sysctl for this info. */
973 bxe_print_adapter_info(struct bxe_softc *sc)
977 DBENTER(BXE_EXTREME_LOAD);
979 /* Hardware chip info. */
980 BXE_PRINTF("ASIC (0x%08X); ", sc->common.chip_id);
981 printf("Rev (%c%d); ", (CHIP_REV(sc) >> 12) + 'A',
982 (CHIP_METAL(sc) >> 4));
985 printf("Bus (PCIe x%d, ", sc->pcie_link_width);
986 switch (sc->pcie_link_speed) {
994 printf("Unknown link speed");
997 /* Device features. */
998 printf("); Flags (");
1000 /* Miscellaneous flags. */
1001 if (sc->msi_count > 0)
1004 if (sc->msix_count > 0) {
1005 if (i > 0) printf("|");
1006 printf("MSI-X"); i++;
1009 if (TPA_ENABLED(sc)) {
1010 if (i > 0) printf("|");
1014 printf("); Queues (");
1015 switch (sc->multi_mode) {
1016 case ETH_RSS_MODE_DISABLED:
1019 case ETH_RSS_MODE_REGULAR:
1020 printf("RSS:%d", sc->num_queues);
1027 printf("); BD's (RX:%d,TX:%d",
1028 (int) USABLE_RX_BD, (int) USABLE_TX_BD);
1030 /* Firmware versions and device features. */
1031 printf("); Firmware (%d.%d.%d); Bootcode (%d.%d.%d)\n",
1032 BCM_5710_FW_MAJOR_VERSION,
1033 BCM_5710_FW_MINOR_VERSION,
1034 BCM_5710_FW_REVISION_VERSION,
1035 (int)((sc->common.bc_ver & 0xff0000) >> 16),
1036 (int)((sc->common.bc_ver & 0x00ff00) >> 8),
1037 (int)((sc->common.bc_ver & 0x0000ff)));
1039 DBEXIT(BXE_EXTREME_LOAD);
1043 * Release any interrupts allocated by the driver.
1049 bxe_interrupt_free(struct bxe_softc *sc)
1054 DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
1058 if (sc->msix_count > 0) {
1059 /* Free MSI-X resources. */
1061 for (i = 0; i < sc->msix_count; i++) {
1062 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
1063 BXE_VERBOSE_INTR), "%s(): Releasing MSI-X[%d] "
1064 "vector.\n", __FUNCTION__, i);
1065 if (sc->bxe_msix_res[i] && sc->bxe_msix_rid[i])
1066 bus_release_resource(dev, SYS_RES_IRQ,
1067 sc->bxe_msix_rid[i], sc->bxe_msix_res[i]);
1070 pci_release_msi(dev);
1072 } else if (sc->msi_count > 0) {
1073 /* Free MSI resources. */
1075 for (i = 0; i < sc->msi_count; i++) {
1076 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
1077 BXE_VERBOSE_INTR), "%s(): Releasing MSI[%d] "
1078 "vector.\n", __FUNCTION__, i);
1079 if (sc->bxe_msi_res[i] && sc->bxe_msi_rid[i])
1080 bus_release_resource(dev, SYS_RES_IRQ,
1081 sc->bxe_msi_rid[i], sc->bxe_msi_res[i]);
1084 pci_release_msi(dev);
1087 /* Free legacy interrupt resources. */
1089 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
1090 BXE_VERBOSE_INTR), "%s(): Releasing legacy interrupt.\n",
1092 if (sc->bxe_irq_res != NULL)
1093 bus_release_resource(dev, SYS_RES_IRQ,
1094 sc->bxe_irq_rid, sc->bxe_irq_res);
1097 DBEXIT(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
1101 * This function determines and allocates the appropriate
1102 * interrupt based on system capabilites and user request.
1104 * The user may force a particular interrupt mode, specify
1105 * the number of receive queues, specify the method for
1106 * distribuitng received frames to receive queues, or use
1107 * the default settings which will automatically select the
1108 * best supported combination. In addition, the OS may or
1109 * may not support certain combinations of these settings.
1110 * This routine attempts to reconcile the settings requested
1111 * by the user with the capabilites available from the system
1112 * to select the optimal combination of features.
1115 * 0 = Success, !0 = Failure.
1118 bxe_interrupt_alloc(struct bxe_softc *sc)
1121 int error, i, rid, rc;
1122 int msi_count, msi_required, msi_allocated;
1123 int msix_count, msix_required, msix_allocated;
1125 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
1129 msi_count = msi_required = msi_allocated = 0;
1130 msix_count = msix_required = msix_allocated = 0;
1132 /* Get the number of available MSI/MSI-X interrupts from the OS. */
1133 if (sc->int_mode > 0) {
1134 if (sc->bxe_cap_flags & BXE_MSIX_CAPABLE_FLAG)
1135 msix_count = pci_msix_count(dev);
1137 if (sc->bxe_cap_flags & BXE_MSI_CAPABLE_FLAG)
1138 msi_count = pci_msi_count(dev);
1140 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1141 "%s(): %d MSI and %d MSI-X vectors available.\n",
1142 __FUNCTION__, msi_count, msix_count);
1145 /* Try allocating MSI-X interrupt resources. */
1146 if ((sc->bxe_cap_flags & BXE_MSIX_CAPABLE_FLAG) &&
1147 (sc->int_mode > 1) && (msix_count > 0) &&
1148 (msix_count >= sc->num_queues)) {
1149 /* Ask for the necessary number of MSI-X vectors. */
1150 if (sc->num_queues == 1)
1151 msix_allocated = msix_required = 2;
1153 msix_allocated = msix_required = sc->num_queues + 1;
1155 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1156 "%s(): Requesting %d MSI-X vectors.\n",
1157 __FUNCTION__, msix_required);
1159 /* BSD resource identifier */
1161 error = pci_alloc_msix(dev, &msix_allocated);
1163 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1164 "%s(): Required/Allocated (%d/%d) MSI-X vector(s).\n",
1165 __FUNCTION__, msix_required, msix_allocated);
1167 /* Make sure we got all the interrupts we asked for. */
1168 if (msix_allocated >= msix_required) {
1169 sc->msix_count = msix_required;
1172 /* Allocate the MSI-X vectors. */
1173 for (i = 0; i < msix_required; i++) {
1174 sc->bxe_msix_rid[i] = rid + i +
1176 sc->bxe_msix_res[i] =
1177 bus_alloc_resource_any(dev,
1178 SYS_RES_IRQ, &sc->bxe_msix_rid[i],
1180 /* Report any IRQ allocation errors. */
1181 if (sc->bxe_msix_res[i] == NULL) {
1183 "%s(%d): Failed to map MSI-X[%d] vector!\n",
1184 __FILE__, __LINE__, (3));
1186 goto bxe_interrupt_alloc_exit;
1191 DBPRINT(sc, BXE_WARN,
1192 "%s(): MSI-X allocation failed!\n",
1195 /* Release any resources acquired. */
1196 pci_release_msi(dev);
1197 sc->msix_count = msix_count = 0;
1199 /* We'll try MSI next. */
1205 /* Try allocating MSI vector resources. */
1206 if ((sc->bxe_cap_flags & BXE_MSI_CAPABLE_FLAG) &&
1207 (sc->int_mode > 0) && (msi_count > 0) &&
1208 (msi_count >= sc->num_queues)) {
1209 /* Ask for the necessary number of MSI vectors. */
1210 if (sc->num_queues == 1)
1211 msi_required = msi_allocated = 1;
1213 msi_required = msi_allocated = BXE_MSI_VECTOR_COUNT;
1215 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1216 "%s(): Requesting %d MSI vectors.\n", __FUNCTION__,
1220 error = pci_alloc_msi(dev, &msi_allocated);
1222 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1223 "%s(): Required/Allocated (%d/%d) MSI vector(s).\n",
1224 __FUNCTION__, msi_required, msi_allocated);
1227 * Make sure we got all the vectors we asked for.
1229 * FreeBSD always gives 8 even if we ask for less.
1231 if (msi_required >= msi_allocated) {
1232 sc->msi_count = msi_required;
1233 /* Allocate the MSI vectors. */
1234 for (i = 0; i < msi_required; i++) {
1235 sc->bxe_msi_rid[i] = i + rid;
1236 sc->bxe_msi_res[i] =
1237 bus_alloc_resource_any(dev,
1238 SYS_RES_IRQ, &sc->bxe_msi_rid[i],
1240 /* Report any IRQ allocation errors. */
1241 if (sc->bxe_msi_res[i] == NULL) {
1243 "%s(%d): Failed to map MSI vector (%d)!\n",
1244 __FILE__, __LINE__, (i));
1246 goto bxe_interrupt_alloc_exit;
1252 DBPRINT(sc, BXE_WARN, "%s(): MSI allocation failed!\n",
1255 /* Release any resources acquired. */
1256 pci_release_msi(dev);
1257 sc->msi_count = msi_count = 0;
1259 /* We'll try INTx next. */
1264 /* Try allocating INTx resources. */
1265 if (sc->int_mode == 0) {
1267 sc->multi_mode = ETH_RSS_MODE_DISABLED;
1269 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1270 "%s(): Requesting legacy INTx interrupt.\n",
1274 sc->bxe_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1275 RF_SHAREABLE | RF_ACTIVE);
1276 /* Report any IRQ allocation errors. */
1277 if (sc->bxe_irq_res == NULL) {
1278 BXE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1279 __FILE__, __LINE__);
1281 goto bxe_interrupt_alloc_exit;
1283 sc->bxe_irq_rid = rid;
1286 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1287 "%s(): Actual: int_mode = %d, multi_mode = %d, num_queues = %d\n",
1288 __FUNCTION__, sc->int_mode, sc->multi_mode, sc->num_queues);
1290 bxe_interrupt_alloc_exit:
1291 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
1296 * This function releases taskqueues.
1302 bxe_interrupt_detach(struct bxe_softc *sc)
1305 struct bxe_fastpath *fp;
1310 DBENTER(BXE_VERBOSE_UNLOAD);
1315 /* Free the OS taskqueue resources. */
1316 for (i = 0; i < sc->num_queues; i++) {
1319 if (fp->tq != NULL) {
1320 taskqueue_drain(fp->tq, &fp->task);
1321 taskqueue_free(fp->tq);
1325 if (sc->tq != NULL) {
1326 taskqueue_drain(sc->tq, &sc->task);
1327 taskqueue_free(sc->tq);
1331 /* Release interrupt resources. */
1332 if (sc->msix_count > 0) {
1333 for (i = 0; i < sc->msix_count; i++) {
1334 if (sc->bxe_msix_tag[i] && sc->bxe_msix_res[i])
1335 bus_teardown_intr(dev, sc->bxe_msix_res[i],
1336 sc->bxe_msix_tag[i]);
1338 } else if (sc->msi_count > 0) {
1339 for (i = 0; i < sc->msi_count; i++) {
1340 if (sc->bxe_msi_tag[i] && sc->bxe_msi_res[i])
1341 bus_teardown_intr(dev, sc->bxe_msi_res[i],
1342 sc->bxe_msi_tag[i]);
1345 if (sc->bxe_irq_tag != NULL)
1346 bus_teardown_intr(dev, sc->bxe_irq_res,
1350 DBEXIT(BXE_VERBOSE_UNLOAD);
1354 * This function enables interrupts and attachs to the ISR.
1356 * When using multiple MSI/MSI-X vectors the first vector
1357 * is used for slowpath operations while all remaining
1358 * vectors are used for fastpath operations. If only a
1359 * single MSI/MSI-X vector is used (SINGLE_ISR) then the
1360 * ISR must look for both slowpath and fastpath completions.
1363 * 0 = Success, !0 = Failure.
1366 bxe_interrupt_attach(struct bxe_softc *sc)
1368 struct bxe_fastpath *fp;
1371 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
1376 /* Setup the slowpath deferred task queue. */
1377 TASK_INIT(&sc->task, 0, bxe_task_sp, sc);
1378 sc->tq = taskqueue_create_fast("bxe_spq", M_NOWAIT,
1379 taskqueue_thread_enqueue, &sc->tq);
1380 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s spq",
1381 device_get_nameunit(sc->dev));
1384 /* Setup interrupt handlers. */
1385 if (sc->msix_count > 0) {
1386 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1387 "%s(): Enabling slowpath MSI-X[0] vector.\n",__FUNCTION__);
1389 * Setup the interrupt handler. Note that we pass the
1390 * driver instance to the interrupt handler for the
1393 rc = bus_setup_intr(sc->dev, sc->bxe_msix_res[0],
1394 INTR_TYPE_NET | INTR_MPSAFE, NULL, bxe_intr_sp,
1395 sc, &sc->bxe_msix_tag[0]);
1399 "%s(%d): Failed to allocate MSI-X[0] vector!\n",
1400 __FILE__, __LINE__);
1401 goto bxe_interrupt_attach_exit;
1404 #if __FreeBSD_version >= 800504
1405 bus_describe_intr(sc->dev, sc->bxe_msix_res[0],
1406 sc->bxe_msix_tag[0], "sp");
1409 /* Now initialize the fastpath vectors. */
1410 for (i = 0; i < (sc->num_queues); i++) {
1412 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1413 "%s(): Enabling MSI-X[%d] vector.\n",
1414 __FUNCTION__, i + 1);
1416 * Setup the interrupt handler. Note that we pass the
1417 * fastpath context to the interrupt handler in this
1418 * case. Also the first msix_res was used by the sp.
1420 rc = bus_setup_intr(sc->dev, sc->bxe_msix_res[i + 1],
1421 INTR_TYPE_NET | INTR_MPSAFE, NULL, bxe_intr_fp,
1422 fp, &sc->bxe_msix_tag[i + 1]);
1426 "%s(%d): Failed to allocate MSI-X[%d] vector!\n",
1427 __FILE__, __LINE__, (i + 1));
1428 goto bxe_interrupt_attach_exit;
1431 #if __FreeBSD_version >= 800504
1432 bus_describe_intr(sc->dev, sc->bxe_msix_res[i + 1],
1433 sc->bxe_msix_tag[i + 1], "fp[%02d]", i);
1436 /* Bind the fastpath instance to a CPU. */
1437 if (sc->num_queues > 1) {
1438 bus_bind_intr(sc->dev,
1439 sc->bxe_msix_res[i + 1], i);
1443 TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
1444 fp->tq = taskqueue_create_fast("bxe_fpq", M_NOWAIT,
1445 taskqueue_thread_enqueue, &fp->tq);
1446 taskqueue_start_threads(&fp->tq, 1, PI_NET, "%s fpq",
1447 device_get_nameunit(sc->dev));
1449 fp->state = BXE_FP_STATE_IRQ;
1451 } else if (sc->msi_count > 0) {
1452 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1453 "%s(): Enabling slowpath MSI[0] vector.\n",
1456 * Setup the interrupt handler. Note that we pass the driver
1457 * instance to the interrupt handler for the slowpath.
1459 rc = bus_setup_intr(sc->dev,sc->bxe_msi_res[0],
1460 INTR_TYPE_NET | INTR_MPSAFE, NULL, bxe_intr_sp,
1461 sc, &sc->bxe_msi_tag[0]);
1465 "%s(%d): Failed to allocate MSI[0] vector!\n",
1466 __FILE__, __LINE__);
1467 goto bxe_interrupt_attach_exit;
1470 #if __FreeBSD_version >= 800504
1471 bus_describe_intr(sc->dev, sc->bxe_msi_res[0],
1472 sc->bxe_msi_tag[0], "sp");
1475 /* Now initialize the fastpath vectors. */
1476 for (i = 0; i < (sc->num_queues); i++) {
1479 (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1480 "%s(): Enabling MSI[%d] vector.\n",
1481 __FUNCTION__, i + 1);
1483 * Setup the interrupt handler. Note that we pass the
1484 * fastpath context to the interrupt handler in this
1487 rc = bus_setup_intr(sc->dev, sc->bxe_msi_res[i + 1],
1488 INTR_TYPE_NET | INTR_MPSAFE, NULL, bxe_intr_fp,
1489 fp, &sc->bxe_msi_tag[i + 1]);
1493 "%s(%d): Failed to allocate MSI[%d] vector!\n",
1494 __FILE__, __LINE__, (i + 1));
1495 goto bxe_interrupt_attach_exit;
1498 #if __FreeBSD_version >= 800504
1499 bus_describe_intr(sc->dev, sc->bxe_msi_res[i + 1],
1500 sc->bxe_msi_tag[i + 1], "fp[%02d]", i);
1504 TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
1505 fp->tq = taskqueue_create_fast("bxe_fpq", M_NOWAIT,
1506 taskqueue_thread_enqueue, &fp->tq);
1507 taskqueue_start_threads(&fp->tq, 1, PI_NET, "%s fpq",
1508 device_get_nameunit(sc->dev));
1516 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1517 "%s(): Enabling INTx interrupts.\n", __FUNCTION__);
1520 * Setup the interrupt handler. Note that we pass the
1521 * driver instance to the interrupt handler which
1522 * will handle both the slowpath and fastpath.
1524 rc = bus_setup_intr(sc->dev,sc->bxe_irq_res, INTR_TYPE_NET |
1525 INTR_MPSAFE, NULL, bxe_intr_legacy, sc, &sc->bxe_irq_tag);
1528 BXE_PRINTF("%s(%d): Failed to allocate interrupt!\n",
1529 __FILE__, __LINE__);
1530 goto bxe_interrupt_attach_exit;
1533 TASK_INIT(&fp->task, 0, bxe_task_fp, fp);
1534 fp->tq = taskqueue_create_fast("bxe_fpq",
1535 M_NOWAIT, taskqueue_thread_enqueue, &fp->tq);
1536 taskqueue_start_threads(&fp->tq, 1,
1537 PI_NET, "%s fpq", device_get_nameunit(sc->dev));
1541 bxe_interrupt_attach_exit:
1542 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR);
1548 * PCI Capabilities Probe Function.
1550 * Walks the PCI capabiites list for the device to find what features are
1551 * supported. These capabilites may be enabled/disabled by firmware so it's
1552 * best to walk the list rather than hard code any values.
1558 bxe_probe_pci_caps(struct bxe_softc *sc)
1562 uint16_t link_status;
1565 DBENTER(BXE_EXTREME_LOAD);
1567 /* Check if PCI Power Management capability is enabled. */
1568 if (pci_find_cap(dev, PCIY_PMG, ®) == 0) {
1570 DBPRINT(sc, BXE_EXTREME_LOAD,
1571 "%s(): Found PM capability at 0x%04X\n",
1577 /* Check if PCIe capability is enabled. */
1578 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) {
1580 link_status = pci_read_config(dev, reg + 0x12, 2);
1582 DBPRINT(sc, BXE_EXTREME_LOAD,
1583 "%s(): Found PCIe capability at 0x%04X\n",
1586 /* Handle PCIe 2.0 workarounds for the 57710. */
1587 if (CHIP_IS_E1(sc)) {
1588 /* Workaround for 57710 errata E4_57710_27462. */
1589 sc->pcie_link_speed =
1590 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1;
1592 /* Workaround for 57710 errata E4_57710_27488. */
1593 sc->pcie_link_width = (link_status >> 4) & 0x3f;
1594 if (sc->pcie_link_speed > 1)
1595 sc->pcie_link_width =
1596 ((link_status >> 4) & 0x3f) >> 1;
1600 sc->pcie_link_speed = link_status & 0xf;
1601 sc->pcie_link_width = (link_status >> 4) & 0x3f;
1605 sc->bxe_cap_flags |= BXE_PCIE_CAPABLE_FLAG;
1611 /* Check if MSI capability is enabled. */
1612 if (pci_find_cap(dev, PCIY_MSI, ®) == 0) {
1614 DBPRINT(sc, BXE_EXTREME_LOAD,
1615 "%s(): Found MSI capability at 0x%04X\n",
1617 sc->bxe_cap_flags |= BXE_MSI_CAPABLE_FLAG;
1621 /* Check if MSI-X capability is enabled. */
1622 if (pci_find_cap(dev, PCIY_MSIX, ®) == 0) {
1624 DBPRINT(sc, BXE_EXTREME_LOAD,
1625 "%s(): Found MSI-X capability at 0x%04X\n",
1627 sc->bxe_cap_flags |= BXE_MSIX_CAPABLE_FLAG;
1631 DBEXIT(BXE_EXTREME_LOAD);
1635 * Setup firmware pointers for BCM57710.
1641 bxe_init_e1_firmware(struct bxe_softc *sc)
1643 INIT_OPS(sc) = (struct raw_op *)init_ops_e1;
1644 INIT_DATA(sc) = (const uint32_t *)init_data_e1;
1645 INIT_OPS_OFFSETS(sc) = (const uint16_t *)init_ops_offsets_e1;
1646 INIT_TSEM_INT_TABLE_DATA(sc) = tsem_int_table_data_e1;
1647 INIT_TSEM_PRAM_DATA(sc) = tsem_pram_data_e1;
1648 INIT_USEM_INT_TABLE_DATA(sc) = usem_int_table_data_e1;
1649 INIT_USEM_PRAM_DATA(sc) = usem_pram_data_e1;
1650 INIT_XSEM_INT_TABLE_DATA(sc) = xsem_int_table_data_e1;
1651 INIT_XSEM_PRAM_DATA(sc) = xsem_pram_data_e1;
1652 INIT_CSEM_INT_TABLE_DATA(sc) = csem_int_table_data_e1;
1653 INIT_CSEM_PRAM_DATA(sc) = csem_pram_data_e1;
1657 * Setup firmware pointers for BCM57711.
1663 bxe_init_e1h_firmware(struct bxe_softc *sc)
1665 INIT_OPS(sc) = (struct raw_op *)init_ops_e1h;
1666 INIT_DATA(sc) = (const uint32_t *)init_data_e1h;
1667 INIT_OPS_OFFSETS(sc) = (const uint16_t *)init_ops_offsets_e1h;
1668 INIT_TSEM_INT_TABLE_DATA(sc) = tsem_int_table_data_e1h;
1669 INIT_TSEM_PRAM_DATA(sc) = tsem_pram_data_e1h;
1670 INIT_USEM_INT_TABLE_DATA(sc) = usem_int_table_data_e1h;
1671 INIT_USEM_PRAM_DATA(sc) = usem_pram_data_e1h;
1672 INIT_XSEM_INT_TABLE_DATA(sc) = xsem_int_table_data_e1h;
1673 INIT_XSEM_PRAM_DATA(sc) = xsem_pram_data_e1h;
1674 INIT_CSEM_INT_TABLE_DATA(sc) = csem_int_table_data_e1h;
1675 INIT_CSEM_PRAM_DATA(sc) = csem_pram_data_e1h;
1679 * Sets up pointers for loading controller firmware.
1682 * 0 = Success, !0 = Failure
1685 bxe_init_firmware(struct bxe_softc *sc)
1692 bxe_init_e1_firmware(sc);
1693 else if (CHIP_IS_E1H(sc))
1694 bxe_init_e1h_firmware(sc);
1696 BXE_PRINTF("%s(%d): No firmware to support chip revision!\n",
1697 __FILE__, __LINE__);
1705 bxe_tunables_set(struct bxe_softc *sc)
1708 * Get our starting point for interrupt mode/number of queues.
1709 * We will progressively step down from MSI-X to MSI to INTx
1710 * and reduce the number of receive queues as necessary to
1711 * match the system capabilities.
1713 sc->multi_mode = bxe_multi_mode;
1714 sc->int_mode = bxe_int_mode;
1715 sc->tso_enable = bxe_tso_enable;
1718 * Verify the Priority -> Receive Queue mappings.
1720 if (sc->int_mode > 0) {
1721 /* Multi-queue modes require MSI/MSI-X. */
1722 switch (sc->multi_mode) {
1723 case ETH_RSS_MODE_DISABLED:
1724 /* No multi-queue mode requested. */
1727 case ETH_RSS_MODE_REGULAR:
1728 if (sc->int_mode > 1) {
1730 * Assume we can use MSI-X
1731 * (max of 16 receive queues).
1733 sc->num_queues = min((bxe_queue_count ?
1734 bxe_queue_count : mp_ncpus), MAX_CONTEXT);
1737 * Assume we can use MSI
1738 * (max of 7 receive queues).
1740 sc->num_queues = min((bxe_queue_count ?
1741 bxe_queue_count : mp_ncpus),
1742 BXE_MSI_VECTOR_COUNT - 1);
1747 "%s(%d): Unsupported multi_mode parameter (%d), "
1748 "disabling multi-queue support!\n", __FILE__,
1749 __LINE__, sc->multi_mode);
1750 sc->multi_mode = ETH_RSS_MODE_DISABLED;
1755 /* User has forced INTx mode. */
1756 sc->multi_mode = ETH_RSS_MODE_DISABLED;
1760 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_INTR),
1761 "%s(): Requested: int_mode = %d, multi_mode = %d num_queues = %d\n",
1762 __FUNCTION__, sc->int_mode, sc->multi_mode, sc->num_queues);
1764 sc->stats_enable = TRUE;
1766 /* Select the host coalescing tick count values (limit values). */
1767 if (bxe_tx_ticks > 100) {
1768 BXE_PRINTF("%s(%d): bxe_tx_ticks too large "
1769 "(%d), setting default value of 50.\n",
1770 __FILE__, __LINE__, bxe_tx_ticks);
1773 sc->tx_ticks = bxe_tx_ticks;
1775 if (bxe_rx_ticks > 100) {
1776 BXE_PRINTF("%s(%d): bxe_rx_ticks too large "
1777 "(%d), setting default value of 25.\n",
1778 __FILE__, __LINE__, bxe_rx_ticks);
1781 sc->rx_ticks = bxe_rx_ticks;
1783 /* Select the PCIe maximum read request size (MRRS). */
1787 sc->mrrs = bxe_mrrs;
1789 /* Check for DCC support. */
1790 if (bxe_dcc_enable == FALSE)
1791 sc->dcc_enable = FALSE;
1793 sc->dcc_enable = TRUE;
1798 * Allocates PCI resources from OS.
1801 * 0 = Success, !0 = Failure
1804 bxe_pci_resources_alloc(struct bxe_softc *sc)
1808 DBENTER(BXE_VERBOSE_LOAD);
1811 * Allocate PCI memory resources for BAR0.
1812 * This includes device registers and internal
1816 sc->bxe_res = bus_alloc_resource_any(sc->dev,
1817 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1818 if (sc->bxe_res == NULL) {
1819 BXE_PRINTF("%s(%d):PCI BAR0 memory allocation failed\n",
1820 __FILE__, __LINE__);
1822 goto bxe_pci_resources_alloc_exit;
1825 /* Get OS resource handles for BAR0 memory. */
1826 sc->bxe_btag = rman_get_bustag(sc->bxe_res);
1827 sc->bxe_bhandle = rman_get_bushandle(sc->bxe_res);
1828 sc->bxe_vhandle = (vm_offset_t) rman_get_virtual(sc->bxe_res);
1831 * Allocate PCI memory resources for BAR2.
1832 * Doorbell (DB) memory.
1835 sc->bxe_db_res = bus_alloc_resource_any(sc->dev,
1836 SYS_RES_MEMORY, &rid, RF_ACTIVE);
1837 if (sc->bxe_db_res == NULL) {
1838 BXE_PRINTF("%s(%d): PCI BAR2 memory allocation failed\n",
1839 __FILE__, __LINE__);
1841 goto bxe_pci_resources_alloc_exit;
1844 /* Get OS resource handles for BAR2 memory. */
1845 sc->bxe_db_btag = rman_get_bustag(sc->bxe_db_res);
1846 sc->bxe_db_bhandle = rman_get_bushandle(sc->bxe_db_res);
1847 sc->bxe_db_vhandle = (vm_offset_t) rman_get_virtual(sc->bxe_db_res);
1849 bxe_pci_resources_alloc_exit:
1850 DBEXIT(BXE_VERBOSE_LOAD);
1856 * Frees PCI resources allocated in bxe_pci_resources_alloc().
1862 bxe_pci_resources_free(struct bxe_softc *sc)
1864 DBENTER(BXE_VERBOSE_UNLOAD);
1866 /* Release the PCIe BAR0 mapped memory. */
1867 if (sc->bxe_res != NULL) {
1868 bus_release_resource(sc->dev, SYS_RES_MEMORY,
1869 PCIR_BAR(0), sc->bxe_res);
1872 /* Release the PCIe BAR2 (doorbell) mapped memory. */
1873 if (sc->bxe_db_res != NULL) {
1874 bus_release_resource(sc->dev, SYS_RES_MEMORY,
1875 PCIR_BAR(2), sc->bxe_db_res);
1878 DBENTER(BXE_VERBOSE_UNLOAD);
1883 * Determines the media reported to the OS by examining
1884 * the installed PHY type.
1887 * 0 = Success, !0 = Failure
1890 bxe_media_detect(struct bxe_softc *sc)
1896 /* Identify supported media based on the PHY type. */
1897 switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
1898 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
1899 DBPRINT(sc, BXE_INFO_LOAD,
1900 "%s(): Found 10GBase-CX4 media.\n", __FUNCTION__);
1901 sc->media = IFM_10G_CX4;
1903 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
1904 /* Technically 10GBase-KR but report as 10GBase-SR*/
1905 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
1906 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
1907 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
1908 DBPRINT(sc, BXE_INFO_LOAD,
1909 "%s(): Found 10GBase-SR media.\n", __FUNCTION__);
1910 sc->media = IFM_10G_SR;
1912 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
1913 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
1914 DBPRINT(sc, BXE_INFO_LOAD,
1915 "%s(): Found 10Gb twinax media.\n", __FUNCTION__);
1916 sc->media = IFM_10G_TWINAX;
1918 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
1919 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
1920 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
1921 DBPRINT(sc, BXE_INFO_LOAD,
1922 "%s(): Found 10GBase-T media.\n", __FUNCTION__);
1923 sc->media = IFM_10G_T;
1925 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
1926 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN:
1937 * Device attach function.
1939 * Allocates device resources, performs secondary chip identification,
1940 * resets and initializes the hardware, and initializes driver instance
1944 * 0 = Success, Positive value on failure.
1947 bxe_attach(device_t dev)
1949 struct bxe_softc *sc;
1953 sc = device_get_softc(dev);
1954 DBENTER(BXE_INFO_LOAD | BXE_INFO_RESET);
1957 sc->bxe_unit = device_get_unit(dev);
1958 sc->bxe_func = pci_get_function(dev);
1960 sc->state = BXE_STATE_CLOSED;
1963 DBPRINT(sc, BXE_FATAL, "%s(): ************************\n",
1965 DBPRINT(sc, BXE_FATAL, "%s(): ** Debug mode enabled **\n",
1967 DBPRINT(sc, BXE_FATAL, "%s(): ************************\n",
1969 DBPRINT(sc, BXE_FATAL, "%s(): sc vaddr = 0x%08X:%08X\n",
1970 __FUNCTION__, (uint32_t) U64_HI(sc), (uint32_t) U64_LO(sc));
1972 /* Get the user configurable values for driver load. */
1973 bxe_tunables_set(sc);
1975 bxe_mutexes_alloc(sc);
1977 /* Prepare tick routine. */
1978 callout_init_mtx(&sc->bxe_tick_callout, &sc->bxe_core_mtx, 0);
1980 /* Enable bus master capability */
1981 pci_enable_busmaster(dev);
1983 /* Enable PCI BAR mapped memory for register access. */
1984 rc = bxe_pci_resources_alloc(sc);
1986 BXE_PRINTF("%s(%d): Error allocating PCI resources!\n",
1987 __FILE__, __LINE__);
1988 goto bxe_attach_fail;
1991 /* Put indirect address registers into a sane state. */
1992 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS,
1993 PCICFG_VENDOR_ID_OFFSET, 4);
1994 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0 + BP_PORT(sc) * 16, 0);
1995 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0 + BP_PORT(sc) * 16, 0);
1996 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0 + BP_PORT(sc) * 16, 0);
1997 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0 + BP_PORT(sc) * 16, 0);
1999 /* Get hardware info from shared memory and validate data. */
2000 rc = bxe_hwinfo_function_get(sc);
2002 DBPRINT(sc, BXE_WARN,
2003 "%s(): Failed to get hardware info!\n", __FUNCTION__);
2004 goto bxe_attach_fail;
2007 /* Setup supported media options. */
2008 rc = bxe_media_detect(sc);
2010 BXE_PRINTF("%s(%d): Unknown media (PHY) type!\n",
2011 __FILE__, __LINE__);
2012 goto bxe_attach_fail;
2015 /* Interface entrypoint for media type/status reporting. */
2016 ifmedia_init(&sc->bxe_ifmedia,
2017 IFM_IMASK, bxe_ifmedia_upd, bxe_ifmedia_status);
2019 /* Default interface values. */
2020 ifmedia_add(&sc->bxe_ifmedia,
2021 IFM_ETHER | sc->media | IFM_FDX, 0, NULL);
2022 ifmedia_add(&sc->bxe_ifmedia,
2023 IFM_ETHER | IFM_AUTO, 0, NULL);
2024 ifmedia_set(&sc->bxe_ifmedia,
2025 IFM_ETHER | IFM_AUTO);
2026 sc->bxe_ifmedia.ifm_media =
2027 sc->bxe_ifmedia.ifm_cur->ifm_media;
2029 /* Setup firmware arrays (firmware load comes later). */
2030 rc = bxe_init_firmware(sc);
2032 BXE_PRINTF("%s(%d): Error preparing firmware load!\n",
2033 __FILE__, __LINE__);
2034 goto bxe_attach_fail;
2038 /* Allocate a memory buffer for grcdump output.*/
2039 sc->grcdump_buffer = malloc(BXE_GRCDUMP_BUF_SIZE, M_TEMP, M_NOWAIT);
2040 if (sc->grcdump_buffer == NULL) {
2041 BXE_PRINTF("%s(%d): Failed to allocate grcdump memory "
2042 "buffer!\n", __FILE__, __LINE__);
2047 /* Check that NVRAM contents are valid.*/
2048 rc = bxe_nvram_test(sc);
2050 BXE_PRINTF("%s(%d): Failed NVRAM test!\n",
2051 __FILE__, __LINE__);
2052 goto bxe_attach_fail;
2055 /* Allocate the appropriate interrupts.*/
2056 rc = bxe_interrupt_alloc(sc);
2058 BXE_PRINTF("%s(%d): Interrupt allocation failed!\n",
2059 __FILE__, __LINE__);
2060 goto bxe_attach_fail;
2063 /* Useful for accessing unconfigured devices (i.e. factory diags).*/
2065 sc->bxe_flags |= BXE_NO_MCP_FLAG;
2067 /* If bootcode is not running only initialize port 0. */
2068 if (nomcp && BP_PORT(sc)) {
2070 "%s(%d): Second device disabled (no bootcode), "
2071 "exiting...\n", __FILE__, __LINE__);
2073 goto bxe_attach_fail;
2076 /* Check if PXE/UNDI is still active and unload it. */
2078 bxe_undi_unload(sc);
2081 * Select the RX and TX ring sizes. The actual
2082 * ring size for TX is complicated by the fact
2083 * that a single TX frame may be broken up into
2084 * many buffer descriptors (tx_start_bd,
2085 * tx_parse_bd, tx_data_bd). In the best case,
2086 * there are always at least two BD's required
2087 * so we'll assume the best case here.
2089 sc->tx_ring_size = (USABLE_TX_BD >> 1);
2090 sc->rx_ring_size = USABLE_RX_BD;
2092 /* Assume receive IP/TCP/UDP checksum is enabled. */
2093 /* ToDo: Change when IOCTL changes checksum offload? */
2099 /* Assume a standard 1500 byte MTU size for mbuf allocations. */
2100 sc->mbuf_alloc_size = MCLBYTES;
2102 /* Allocate DMA memory resources. */
2103 rc = bxe_host_structures_alloc(sc->dev);
2105 BXE_PRINTF("%s(%d): DMA memory allocation failed!\n",
2106 __FILE__, __LINE__);
2107 goto bxe_attach_fail;
2110 /* Allocate a FreeBSD ifnet structure. */
2111 ifp = sc->bxe_ifp = if_alloc(IFT_ETHER);
2113 BXE_PRINTF("%s(%d): Interface allocation failed!\n",
2114 __FILE__, __LINE__);
2116 goto bxe_attach_fail;
2119 /* Initialize the FreeBSD ifnet interface. */
2121 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
2123 /* Written by driver before attach, read-only afterwards. */
2124 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2126 /* Driver entrypoints from the network interface. */
2127 ifp->if_ioctl = bxe_ioctl;
2128 ifp->if_start = bxe_tx_start;
2129 #if __FreeBSD_version >= 800000
2130 ifp->if_transmit = bxe_tx_mq_start;
2131 ifp->if_qflush = bxe_mq_flush;
2138 ifp->if_init = bxe_init;
2139 ifp->if_hwassist = BXE_IF_HWASSIST;
2140 ifp->if_capabilities = BXE_IF_CAPABILITIES;
2141 /* TPA not enabled by default. */
2142 ifp->if_capenable = BXE_IF_CAPABILITIES & ~IFCAP_LRO;
2143 if_initbaudrate(ifp, IF_Gbps(10));
2145 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size;
2147 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
2148 IFQ_SET_READY(&ifp->if_snd);
2150 /* Attach to the Ethernet interface list. */
2151 ether_ifattach(ifp, sc->link_params.mac_addr);
2153 /* Attach the interrupts to the interrupt handlers. */
2154 rc = bxe_interrupt_attach(sc);
2156 BXE_PRINTF("%s(%d): Interrupt allocation failed!\n",
2157 __FILE__, __LINE__);
2158 goto bxe_attach_fail;
2161 /* Print important adapter info for the user. */
2162 bxe_print_adapter_info(sc);
2164 /* Add the supported sysctls to the kernel. */
2165 bxe_add_sysctls(sc);
2171 DBEXIT(BXE_INFO_LOAD | BXE_INFO_RESET);
2177 * Supported link settings.
2179 * Examines hardware configuration present in NVRAM and
2180 * determines the link settings that are supported between
2181 * the external PHY and the switch.
2187 * Sets sc->port.supported
2188 * Sets sc->link_params.phy_addr
2191 bxe_link_settings_supported(struct bxe_softc *sc, uint32_t switch_cfg)
2193 uint32_t ext_phy_type;
2196 DBENTER(BXE_VERBOSE_PHY);
2197 DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): switch_cfg = 0x%08X\n",
2198 __FUNCTION__, switch_cfg);
2201 /* Get the link settings supported by the external PHY. */
2202 switch (switch_cfg) {
2205 SERDES_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
2207 DBPRINT(sc, BXE_VERBOSE_PHY,
2208 "%s(): 1G switch w/ ext_phy_type = "
2209 "0x%08X\n", __FUNCTION__, ext_phy_type);
2211 switch (ext_phy_type) {
2212 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT:
2213 DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): 1G Direct.\n",
2216 sc->port.supported |=
2217 (SUPPORTED_10baseT_Half |
2218 SUPPORTED_10baseT_Full |
2219 SUPPORTED_100baseT_Half |
2220 SUPPORTED_100baseT_Full |
2221 SUPPORTED_1000baseT_Full |
2222 SUPPORTED_2500baseX_Full |
2227 SUPPORTED_Asym_Pause);
2230 case PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482:
2231 DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): 1G 5482\n",
2234 sc->port.supported |=
2235 (SUPPORTED_10baseT_Half |
2236 SUPPORTED_10baseT_Full |
2237 SUPPORTED_100baseT_Half |
2238 SUPPORTED_100baseT_Full |
2239 SUPPORTED_1000baseT_Full |
2244 SUPPORTED_Asym_Pause);
2249 "%s(%d): Bad NVRAM 1Gb PHY configuration data "
2250 "(ext_phy_config=0x%08X).\n",
2252 sc->link_params.ext_phy_config);
2253 goto bxe_link_settings_supported_exit;
2257 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + (port * 0x10));
2259 DBPRINT(sc, BXE_VERBOSE_PHY, "%s(): phy_addr = 0x%08X\n",
2260 __FUNCTION__, sc->port.phy_addr);
2263 case SWITCH_CFG_10G:
2265 XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
2268 sc, BXE_VERBOSE_PHY,
2269 "%s(): 10G switch w/ ext_phy_type = 0x%08X\n",
2270 __FUNCTION__, ext_phy_type);
2272 switch (ext_phy_type) {
2273 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
2274 DBPRINT(sc, BXE_VERBOSE_PHY,
2275 "%s(): 10G switch w/ direct connect.\n",
2278 sc->port.supported |=
2279 (SUPPORTED_10baseT_Half |
2280 SUPPORTED_10baseT_Full |
2281 SUPPORTED_100baseT_Half |
2282 SUPPORTED_100baseT_Full |
2283 SUPPORTED_1000baseT_Full |
2284 SUPPORTED_2500baseX_Full |
2285 SUPPORTED_10000baseT_Full |
2290 SUPPORTED_Asym_Pause);
2293 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
2294 DBPRINT(sc, BXE_VERBOSE_PHY,
2295 "ext_phy_type 0x%x (8072)\n",ext_phy_type);
2297 sc->port.supported |=
2298 (SUPPORTED_10000baseT_Full |
2299 SUPPORTED_1000baseT_Full |
2303 SUPPORTED_Asym_Pause);
2306 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
2308 BXE_VERBOSE_PHY,"ext_phy_type 0x%x (8073)\n",
2311 sc->port.supported |=
2312 (SUPPORTED_10000baseT_Full |
2313 SUPPORTED_2500baseX_Full |
2314 SUPPORTED_1000baseT_Full |
2318 SUPPORTED_Asym_Pause);
2321 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
2322 DBPRINT(sc, BXE_VERBOSE_PHY,
2323 "%s(): 10G switch w/ 8705.\n",__FUNCTION__);
2325 sc->port.supported |=
2326 (SUPPORTED_10000baseT_Full |
2329 SUPPORTED_Asym_Pause);
2332 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
2333 DBPRINT(sc, BXE_VERBOSE_PHY,
2334 "%s(): 10G switch w/ 8706.\n",
2337 sc->port.supported |=
2338 (SUPPORTED_10000baseT_Full |
2339 SUPPORTED_1000baseT_Full |
2342 SUPPORTED_Asym_Pause);
2345 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
2346 DBPRINT(sc, BXE_VERBOSE_PHY,
2347 "%s(): 10G switch w/ 8726.\n",
2350 sc->port.supported |=
2351 (SUPPORTED_10000baseT_Full |
2354 SUPPORTED_Asym_Pause);
2357 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
2358 DBPRINT(sc, BXE_VERBOSE_PHY,"ext_phy_type 0x%x (8727)\n",
2361 sc->port.supported |=
2362 (SUPPORTED_10000baseT_Full |
2363 SUPPORTED_1000baseT_Full |
2367 SUPPORTED_Asym_Pause);
2370 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
2371 DBPRINT(sc, BXE_VERBOSE_PHY,
2372 "%s(): 10G switch w/ SFX7101.\n",
2375 sc->port.supported |=
2376 (SUPPORTED_10000baseT_Full |
2380 SUPPORTED_Asym_Pause);
2383 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
2384 DBPRINT(sc, BXE_VERBOSE_PHY,
2385 "ext_phy_type 0x%x (BCM8481)\n",
2388 sc->port.supported |=
2389 (SUPPORTED_10baseT_Half |
2390 SUPPORTED_10baseT_Full |
2391 SUPPORTED_100baseT_Half |
2392 SUPPORTED_100baseT_Full |
2393 SUPPORTED_1000baseT_Full |
2394 SUPPORTED_10000baseT_Full |
2398 SUPPORTED_Asym_Pause);
2401 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
2402 DBPRINT(sc, BXE_WARN,
2403 "%s(): 10G XGXS PHY failure detected.\n",
2408 "%s(%d): Bad NVRAM 10Gb PHY configuration data "
2409 "(ext_phy_config=0x%08X).\n",
2411 sc->link_params.ext_phy_config);
2412 goto bxe_link_settings_supported_exit;
2416 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR +(port * 0x18));
2420 DBPRINT(sc, BXE_WARN, "%s(): BAD switch configuration "
2421 "(link_config = 0x%08X)\n", __FUNCTION__,
2422 sc->port.link_config);
2423 goto bxe_link_settings_supported_exit;
2426 sc->link_params.phy_addr = sc->port.phy_addr;
2428 /* Mask out unsupported speeds according to NVRAM. */
2429 if ((sc->link_params.speed_cap_mask &
2430 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) == 0)
2431 sc->port.supported &= ~SUPPORTED_10baseT_Half;
2433 if ((sc->link_params.speed_cap_mask &
2434 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) == 0)
2435 sc->port.supported &= ~SUPPORTED_10baseT_Full;
2437 if ((sc->link_params.speed_cap_mask &
2438 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) == 0)
2439 sc->port.supported &= ~SUPPORTED_100baseT_Half;
2441 if ((sc->link_params.speed_cap_mask &
2442 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) == 0)
2443 sc->port.supported &= ~SUPPORTED_100baseT_Full;
2445 if ((sc->link_params.speed_cap_mask &
2446 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) == 0)
2447 sc->port.supported &= ~(SUPPORTED_1000baseT_Half |
2448 SUPPORTED_1000baseT_Full);
2450 if ((sc->link_params.speed_cap_mask &
2451 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) == 0)
2452 sc->port.supported &= ~SUPPORTED_2500baseX_Full;
2454 if ((sc->link_params.speed_cap_mask &
2455 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) == 0)
2456 sc->port.supported &= ~SUPPORTED_10000baseT_Full;
2458 DBPRINT(sc, BXE_VERBOSE_PHY,
2459 "%s(): Supported link settings = 0x%b\n", __FUNCTION__,
2460 sc->port.supported, BXE_SUPPORTED_PRINTFB);
2462 bxe_link_settings_supported_exit:
2464 DBEXIT(BXE_VERBOSE_PHY);
2468 * Requested link settings.
2474 bxe_link_settings_requested(struct bxe_softc *sc)
2476 uint32_t ext_phy_type;
2477 DBENTER(BXE_VERBOSE_PHY);
2479 sc->link_params.req_duplex = MEDIUM_FULL_DUPLEX;
2481 switch (sc->port.link_config & PORT_FEATURE_LINK_SPEED_MASK) {
2483 case PORT_FEATURE_LINK_SPEED_AUTO:
2484 if (sc->port.supported & SUPPORTED_Autoneg) {
2485 sc->link_params.req_line_speed |= SPEED_AUTO_NEG;
2486 sc->port.advertising = sc->port.supported;
2488 ext_phy_type = XGXS_EXT_PHY_TYPE(
2489 sc->link_params.ext_phy_config);
2491 if ((ext_phy_type ==
2492 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705) ||
2494 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706)) {
2495 /* Force 10G, no autonegotiation. */
2496 sc->link_params.req_line_speed = SPEED_10000;
2497 sc->port.advertising =
2498 ADVERTISED_10000baseT_Full |
2503 DBPRINT(sc, BXE_FATAL,
2504 "%s(): NVRAM config error. Invalid "
2505 "link_config (0x%08X) - Autoneg not supported!\n",
2506 __FUNCTION__, sc->port.link_config);
2507 goto bxe_link_settings_requested_exit;
2510 case PORT_FEATURE_LINK_SPEED_10M_FULL:
2511 if (sc->port.supported & SUPPORTED_10baseT_Full) {
2512 sc->link_params.req_line_speed = SPEED_10;
2513 sc->port.advertising = ADVERTISED_10baseT_Full |
2516 DBPRINT(sc, BXE_FATAL,
2517 "%s(): NVRAM config error. Invalid "
2518 "link_config (0x%08X) - speed_cap_mask 0x%08X\n",
2519 __FUNCTION__, sc->port.link_config,
2520 sc->link_params.speed_cap_mask);
2521 goto bxe_link_settings_requested_exit;
2524 case PORT_FEATURE_LINK_SPEED_10M_HALF:
2525 if (sc->port.supported & SUPPORTED_10baseT_Half) {
2526 sc->link_params.req_line_speed = SPEED_10;
2527 sc->link_params.req_duplex = MEDIUM_HALF_DUPLEX;
2528 sc->port.advertising = ADVERTISED_10baseT_Half |
2531 DBPRINT(sc, BXE_FATAL,
2532 "%s(): NVRAM config error. Invalid "
2533 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2534 __FUNCTION__, sc->port.link_config,
2535 sc->link_params.speed_cap_mask);
2536 goto bxe_link_settings_requested_exit;
2539 case PORT_FEATURE_LINK_SPEED_100M_FULL:
2540 if (sc->port.supported & SUPPORTED_100baseT_Full) {
2541 sc->link_params.req_line_speed = SPEED_100;
2542 sc->port.advertising = ADVERTISED_100baseT_Full |
2545 DBPRINT(sc, BXE_FATAL,
2546 "%s(): NVRAM config error. Invalid "
2547 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2548 __FUNCTION__, sc->port.link_config,
2549 sc->link_params.speed_cap_mask);
2550 goto bxe_link_settings_requested_exit;
2553 case PORT_FEATURE_LINK_SPEED_100M_HALF:
2554 if (sc->port.supported & SUPPORTED_100baseT_Half) {
2555 sc->link_params.req_line_speed = SPEED_100;
2556 sc->link_params.req_duplex = MEDIUM_HALF_DUPLEX;
2557 sc->port.advertising = ADVERTISED_100baseT_Half |
2560 DBPRINT(sc, BXE_FATAL,
2561 "%s(): NVRAM config error. Invalid "
2562 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2563 __FUNCTION__, sc->port.link_config,
2564 sc->link_params.speed_cap_mask);
2565 goto bxe_link_settings_requested_exit;
2568 case PORT_FEATURE_LINK_SPEED_1G:
2569 if (sc->port.supported & SUPPORTED_1000baseT_Full) {
2570 sc->link_params.req_line_speed = SPEED_1000;
2571 sc->port.advertising = ADVERTISED_1000baseT_Full |
2574 DBPRINT(sc, BXE_FATAL,
2575 "%s(): NVRAM config error. Invalid "
2576 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2577 __FUNCTION__, sc->port.link_config,
2578 sc->link_params.speed_cap_mask);
2579 goto bxe_link_settings_requested_exit;
2582 case PORT_FEATURE_LINK_SPEED_2_5G:
2583 if (sc->port.supported & SUPPORTED_2500baseX_Full) {
2584 sc->link_params.req_line_speed = SPEED_2500;
2585 sc->port.advertising = ADVERTISED_2500baseX_Full |
2588 DBPRINT(sc, BXE_FATAL,
2589 "%s(): NVRAM config error. Invalid "
2590 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2591 __FUNCTION__, sc->port.link_config,
2592 sc->link_params.speed_cap_mask);
2593 goto bxe_link_settings_requested_exit;
2596 case PORT_FEATURE_LINK_SPEED_10G_CX4:
2597 case PORT_FEATURE_LINK_SPEED_10G_KX4:
2598 case PORT_FEATURE_LINK_SPEED_10G_KR:
2599 if (sc->port.supported & SUPPORTED_10000baseT_Full) {
2600 sc->link_params.req_line_speed = SPEED_10000;
2601 sc->port.advertising = ADVERTISED_10000baseT_Full |
2604 DBPRINT(sc, BXE_FATAL,
2605 "%s(): NVRAM config error. Invalid "
2606 "link_config (0x%08X) - speed_cap_mask = 0x%08X\n",
2607 __FUNCTION__, sc->port.link_config,
2608 sc->link_params.speed_cap_mask);
2609 goto bxe_link_settings_requested_exit;
2613 DBPRINT(sc, BXE_FATAL, "%s(): NVRAM config error. BAD link "
2614 "speed - link_config = 0x%08X\n", __FUNCTION__,
2615 sc->port.link_config);
2616 sc->link_params.req_line_speed = 0;
2617 sc->port.advertising = sc->port.supported;
2621 DBPRINT(sc, BXE_VERBOSE_PHY,
2622 "%s(): req_line_speed = %d, req_duplex = %d\n",
2623 __FUNCTION__, sc->link_params.req_line_speed,
2624 sc->link_params.req_duplex);
2626 sc->link_params.req_flow_ctrl =
2627 sc->port.link_config & PORT_FEATURE_FLOW_CONTROL_MASK;
2629 if ((sc->link_params.req_flow_ctrl == FLOW_CTRL_AUTO) &&
2630 !(sc->port.supported & SUPPORTED_Autoneg))
2631 sc->link_params.req_flow_ctrl = FLOW_CTRL_NONE;
2633 DBPRINT(sc, BXE_VERBOSE_PHY,
2634 "%s(): req_flow_ctrl = 0x%08X, advertising = 0x%08X\n",
2635 __FUNCTION__, sc->link_params.req_flow_ctrl,
2636 sc->port.advertising);
2638 bxe_link_settings_requested_exit:
2640 DBEXIT(BXE_VERBOSE_PHY);
2645 * Get function specific hardware configuration.
2647 * Multiple function devices such as the BCM57711E have configuration
2648 * information that is specific to each PCIe function of the controller.
2649 * The number of PCIe functions is not necessarily the same as the number
2650 * of Ethernet ports supported by the device.
2653 * 0 = Success, !0 = Failure
2656 bxe_hwinfo_function_get(struct bxe_softc *sc)
2658 uint32_t mac_hi, mac_lo, val;
2661 DBENTER(BXE_VERBOSE_LOAD);
2666 /* Get the common hardware configuration first. */
2667 bxe_hwinfo_common_get(sc);
2669 /* Assume no outer VLAN/multi-function support. */
2670 sc->e1hov = sc->e1hmf = 0;
2672 /* Get config info for mf enabled devices. */
2673 if (CHIP_IS_E1H(sc)) {
2674 sc->mf_config[BP_E1HVN(sc)] =
2675 SHMEM_RD(sc, mf_cfg.func_mf_config[func].config);
2676 val = (SHMEM_RD(sc, mf_cfg.func_mf_config[func].e1hov_tag) &
2677 FUNC_MF_CFG_E1HOV_TAG_MASK);
2678 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
2679 sc->e1hov = (uint16_t) val;
2684 goto bxe_hwinfo_function_get_exit;
2690 bxe_hwinfo_port_get(sc);
2691 sc->fw_seq = SHMEM_RD(sc, func_mb[func].drv_mb_header) &
2692 DRV_MSG_SEQ_NUMBER_MASK;
2697 * Fetch the factory configured MAC address for multi function
2698 * devices. If this is not a multi-function device then the MAC
2699 * address was already read in the bxe_hwinfo_port_get() routine.
2700 * The MAC addresses used by the port are not the same as the MAC
2701 * addressed used by the function.
2704 mac_hi = SHMEM_RD(sc, mf_cfg.func_mf_config[func].mac_upper);
2705 mac_lo = SHMEM_RD(sc, mf_cfg.func_mf_config[func].mac_lower);
2707 if ((mac_lo == 0) && (mac_hi == 0)) {
2708 BXE_PRINTF("%s(%d): Invalid Ethernet address!\n",
2709 __FILE__, __LINE__);
2712 sc->link_params.mac_addr[0] = (u_char)(mac_hi >> 8);
2713 sc->link_params.mac_addr[1] = (u_char)(mac_hi);
2714 sc->link_params.mac_addr[2] = (u_char)(mac_lo >> 24);
2715 sc->link_params.mac_addr[3] = (u_char)(mac_lo >> 16);
2716 sc->link_params.mac_addr[4] = (u_char)(mac_lo >> 8);
2717 sc->link_params.mac_addr[5] = (u_char)(mac_lo);
2722 bxe_hwinfo_function_get_exit:
2723 DBEXIT(BXE_VERBOSE_LOAD);
2729 * Get port specific hardware configuration.
2731 * Multiple port devices such as the BCM57710 have configuration
2732 * information that is specific to each Ethernet port of the
2733 * controller. This function reads that configuration
2734 * information from the bootcode's shared memory and saves it
2738 * 0 = Success, !0 = Failure
2741 bxe_hwinfo_port_get(struct bxe_softc *sc)
2744 uint32_t val, mac_hi, mac_lo;
2746 DBENTER(BXE_VERBOSE_LOAD);
2750 sc->link_params.sc = sc;
2751 sc->link_params.port = port;
2753 /* Fetch several configuration values from bootcode shared memory. */
2754 sc->link_params.lane_config =
2755 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config);
2756 sc->link_params.ext_phy_config =
2757 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config);
2759 if (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config) ==
2760 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC) {
2761 sc->link_params.ext_phy_config &=
2762 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
2763 sc->link_params.ext_phy_config |=
2764 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727;
2765 sc->link_params.feature_config_flags |=
2766 FEATURE_CONFIG_BCM8727_NOC;
2769 sc->link_params.speed_cap_mask =
2770 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask);
2771 sc->port.link_config =
2772 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config);
2775 /* Read the XGXS RX/TX preemphasis values. */
2776 for (i = 0; i < 2; i++) {
2778 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]);
2779 sc->link_params.xgxs_config_rx[i << 1] = ((val >> 16) & 0xffff);
2780 sc->link_params.xgxs_config_rx[(i << 1) + 1] = (val & 0xffff);
2783 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]);
2784 sc->link_params.xgxs_config_tx[i << 1] = ((val >> 16) & 0xffff);
2785 sc->link_params.xgxs_config_tx[(i << 1) + 1] = (val & 0xffff);
2788 /* Fetch the device configured link settings. */
2789 sc->link_params.switch_cfg = sc->port.link_config &
2790 PORT_FEATURE_CONNECTED_SWITCH_MASK;
2792 bxe_link_settings_supported(sc, sc->link_params.switch_cfg);
2793 bxe_link_settings_requested(sc);
2795 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper);
2796 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower);
2798 if (mac_lo == 0 && mac_hi == 0) {
2799 BXE_PRINTF("%s(%d): No Ethernet address programmed on the "
2800 "controller!\n", __FILE__, __LINE__);
2803 sc->link_params.mac_addr[0] = (u_char)(mac_hi >> 8);
2804 sc->link_params.mac_addr[1] = (u_char)(mac_hi);
2805 sc->link_params.mac_addr[2] = (u_char)(mac_lo >> 24);
2806 sc->link_params.mac_addr[3] = (u_char)(mac_lo >> 16);
2807 sc->link_params.mac_addr[4] = (u_char)(mac_lo >> 8);
2808 sc->link_params.mac_addr[5] = (u_char)(mac_lo);
2811 DBEXIT(BXE_VERBOSE_LOAD);
2817 * Get common hardware configuration.
2819 * Multiple port devices such as the BCM57710 have configuration
2820 * information that is shared between all ports of the Ethernet
2821 * controller. This function reads that configuration
2822 * information from the bootcode's shared memory and saves it
2826 * 0 = Success, !0 = Failure
2829 bxe_hwinfo_common_get(struct bxe_softc *sc)
2834 DBENTER(BXE_VERBOSE_LOAD);
2837 /* Get the chip revision. */
2838 sc->common.chip_id = sc->link_params.chip_id =
2839 ((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) |
2840 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0x000f) << 12) |
2841 ((REG_RD(sc, MISC_REG_CHIP_METAL) & 0xff) << 4) |
2842 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf));
2844 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): chip_id = 0x%08X.\n",
2845 __FUNCTION__, sc->common.chip_id);
2847 val = (REG_RD(sc, 0x2874) & 0x55);
2848 if ((sc->common.chip_id & 0x1) ||
2849 (CHIP_IS_E1(sc) && val) || (CHIP_IS_E1H(sc) && (val == 0x55))) {
2850 sc->bxe_flags |= BXE_ONE_PORT_FLAG;
2851 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): Single port device.\n",
2855 /* Identify enabled PCI capabilites (PCIe, MSI-X, etc.). */
2856 bxe_probe_pci_caps(sc);
2858 /* Get the NVRAM size. */
2859 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4);
2860 sc->common.flash_size = (NVRAM_1MB_SIZE <<
2861 (val & MCPR_NVM_CFG4_FLASH_SIZE));
2863 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): flash_size = 0x%08x (%dKB)\n",
2864 __FUNCTION__, sc->common.flash_size,(sc->common.flash_size >> 10));
2866 /* Find the shared memory base address. */
2867 sc->common.shmem_base = sc->link_params.shmem_base =
2868 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR);
2869 sc->common.shmem2_base = REG_RD(sc, MISC_REG_GENERIC_CR_0);
2870 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): shmem_base = 0x%08X\n",
2871 __FUNCTION__, sc->common.shmem_base);
2873 /* Make sure the shared memory address is valid. */
2874 if (!sc->common.shmem_base ||
2875 (sc->common.shmem_base < 0xA0000) ||
2876 (sc->common.shmem_base > 0xC0000)) {
2878 BXE_PRINTF("%s(%d): MCP is not active!\n",
2879 __FILE__, __LINE__);
2880 /* ToDo: Remove the NOMCP support. */
2881 sc->bxe_flags |= BXE_NO_MCP_FLAG;
2883 goto bxe_hwinfo_common_get_exit;
2886 /* Make sure the shared memory contents are valid. */
2887 val = SHMEM_RD(sc, validity_map[BP_PORT(sc)]);
2888 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) !=
2889 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) {
2890 BXE_PRINTF("%s(%d): Invalid NVRAM! Bad validity "
2891 "signature.\n", __FILE__, __LINE__);
2893 goto bxe_hwinfo_common_get_exit;
2896 /* Read the device configuration from shared memory. */
2897 sc->common.hw_config =
2898 SHMEM_RD(sc, dev_info.shared_hw_config.config);
2899 sc->link_params.hw_led_mode = ((sc->common.hw_config &
2900 SHARED_HW_CFG_LED_MODE_MASK) >> SHARED_HW_CFG_LED_MODE_SHIFT);
2902 /* Check if we need to override the preemphasis values. */
2903 sc->link_params.feature_config_flags = 0;
2904 val = SHMEM_RD(sc, dev_info.shared_feature_config.config);
2905 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
2906 sc->link_params.feature_config_flags |=
2907 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
2909 sc->link_params.feature_config_flags &=
2910 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
2912 /* In multifunction mode, we can't support WoL on a VN. */
2913 if (BP_E1HVN(sc) == 0) {
2914 val = REG_RD(sc, PCICFG_OFFSET + PCICFG_PM_CAPABILITY);
2915 sc->bxe_flags |= (val & PCICFG_PM_CAPABILITY_PME_IN_D3_COLD) ?
2916 0 : BXE_NO_WOL_FLAG;
2918 sc->bxe_flags |= BXE_NO_WOL_FLAG;
2920 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): %sWoL capable\n", __FUNCTION__,
2921 (sc->bxe_flags & BXE_NO_WOL_FLAG) ? "Not " : "");
2923 /* Check bootcode version */
2924 sc->common.bc_ver = ((SHMEM_RD(sc, dev_info.bc_rev)) >> 8);
2925 if (sc->common.bc_ver < MIN_BXE_BC_VER) {
2926 BXE_PRINTF("%s(%d): Warning: This driver needs bootcode "
2927 "0x%08X but found 0x%08X, please upgrade!\n",
2928 __FILE__, __LINE__, MIN_BXE_BC_VER, sc->common.bc_ver);
2930 goto bxe_hwinfo_common_get_exit;
2933 bxe_hwinfo_common_get_exit:
2934 DBEXIT(BXE_VERBOSE_LOAD);
2940 * Remove traces of PXE boot by forcing UNDI driver unload.
2946 bxe_undi_unload(struct bxe_softc *sc)
2948 uint32_t reset_code, swap_en, swap_val, val;
2951 DBENTER(BXE_VERBOSE_LOAD);
2953 /* Check if there is any driver already loaded */
2954 val = REG_RD(sc, MISC_REG_UNPREPARED);
2957 /* Check if it is the UNDI driver. */
2958 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
2959 val = REG_RD(sc, DORQ_REG_NORM_CID_OFST);
2961 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
2964 DBPRINT(sc, BXE_WARN,
2965 "%s(): UNDI is active! Resetting the device.\n",
2968 /* Clear the UNDI indication. */
2969 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0);
2971 /* Try to unload UNDI on port 0. */
2973 sc->fw_seq = (SHMEM_RD(sc,
2974 func_mb[sc->bxe_func].drv_mb_header) &
2975 DRV_MSG_SEQ_NUMBER_MASK);
2976 reset_code = bxe_fw_command(sc, reset_code);
2978 /* Check if UNDI is active on port 1. */
2979 if (reset_code != FW_MSG_CODE_DRV_UNLOAD_COMMON) {
2981 /* Send "done" for previous unload. */
2982 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
2984 /* Now unload on port 1. */
2986 sc->fw_seq = (SHMEM_RD(sc,
2987 func_mb[sc->bxe_func].drv_mb_header) &
2988 DRV_MSG_SEQ_NUMBER_MASK);
2990 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
2991 bxe_fw_command(sc, reset_code);
2994 /* It's now safe to release the lock. */
2995 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
2997 REG_WR(sc, (BP_PORT(sc) ? HC_REG_CONFIG_1 :
2998 HC_REG_CONFIG_0), 0x1000);
3000 REG_WR(sc, (BP_PORT(sc) ?
3001 NIG_REG_LLH1_BRB1_DRV_MASK :
3002 NIG_REG_LLH0_BRB1_DRV_MASK), 0x0);
3004 REG_WR(sc, (BP_PORT(sc) ?
3005 NIG_REG_LLH1_BRB1_NOT_MCP :
3006 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
3009 REG_WR(sc, (BP_PORT(sc) ?
3010 MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3011 MISC_REG_AEU_MASK_ATTN_FUNC_0), 0);
3015 /* Save NIG port swap information. */
3016 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
3017 swap_en = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
3019 /* Reset the controller. */
3020 REG_WR(sc, GRCBASE_MISC +
3021 MISC_REGISTERS_RESET_REG_1_CLEAR, 0xd3ffffff);
3022 REG_WR(sc, GRCBASE_MISC +
3023 MISC_REGISTERS_RESET_REG_2_CLEAR, 0x00001403);
3025 /* Take the NIG out of reset and restore swap values.*/
3026 REG_WR(sc, GRCBASE_MISC +
3027 MISC_REGISTERS_RESET_REG_1_SET,
3028 MISC_REGISTERS_RESET_REG_1_RST_NIG);
3029 REG_WR(sc, NIG_REG_PORT_SWAP, swap_val);
3030 REG_WR(sc, NIG_REG_STRAP_OVERRIDE, swap_en);
3032 /* Send completion message to the MCP. */
3033 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
3036 * Restore our function and firmware sequence counter.
3038 sc->bxe_func = func;
3039 sc->fw_seq = (SHMEM_RD(sc,
3040 func_mb[sc->bxe_func].drv_mb_header) &
3041 DRV_MSG_SEQ_NUMBER_MASK);
3043 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_UNDI);
3046 DBEXIT(BXE_VERBOSE_LOAD);
3051 * Device detach function.
3053 * Stops the controller, resets the controller, and releases resources.
3056 * 0 on success, !0 = failure.
3059 bxe_detach(device_t dev)
3061 struct bxe_softc *sc;
3065 sc = device_get_softc(dev);
3066 DBENTER(BXE_INFO_UNLOAD);
3071 if (ifp != NULL && ifp->if_vlantrunk != NULL) {
3072 BXE_PRINTF("%s(%d): Cannot detach while VLANs are in use.\n",
3073 __FILE__, __LINE__);
3075 goto bxe_detach_exit;
3078 /* Stop and reset the controller if it was open. */
3079 if (sc->state != BXE_STATE_CLOSED) {
3081 rc = bxe_stop_locked(sc, UNLOAD_CLOSE);
3082 BXE_CORE_UNLOCK(sc);
3086 /* Free memory buffer for grcdump output.*/
3087 if (sc->grcdump_buffer != NULL)
3088 free(sc->grcdump_buffer, M_TEMP);
3091 /* Clean-up any remaining interrupt resources. */
3092 bxe_interrupt_detach(sc);
3093 bxe_interrupt_free(sc);
3095 /* Release the network interface. */
3097 ether_ifdetach(ifp);
3098 ifmedia_removeall(&sc->bxe_ifmedia);
3100 /* Release all remaining resources. */
3101 bxe_release_resources(sc);
3103 /* Free all PCI resources. */
3104 bxe_pci_resources_free(sc);
3105 pci_disable_busmaster(dev);
3107 bxe_mutexes_free(sc);
3110 DBEXIT(BXE_INFO_UNLOAD);
3116 * Setup a leading connection for the controller.
3119 * 0 = Success, !0 = Failure.
3122 bxe_setup_leading(struct bxe_softc *sc)
3126 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
3128 DBPRINT(sc, BXE_VERBOSE_LOAD, "%s(): Setup leading connection "
3129 "on fp[00].\n", __FUNCTION__);
3131 /* Reset IGU state for the leading connection. */
3132 bxe_ack_sb(sc, sc->fp[0].sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
3134 /* Post a PORT_SETUP ramrod and wait for completion. */
3135 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_PORT_SETUP, 0, 0, 0, 0);
3137 /* Wait for the ramrod to complete on the leading connection. */
3138 rc = bxe_wait_ramrod(sc, BXE_STATE_OPEN, 0, &(sc->state), 1);
3140 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
3146 * Stop the leading connection on the controller.
3152 bxe_stop_leading(struct bxe_softc *sc)
3154 uint16_t dsb_sp_prod_idx;
3157 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
3158 BXE_VERBOSE_UNLOAD), "%s(): Stop client connection "
3159 "on fp[00].\n", __FUNCTION__);
3161 /* Send the ETH_HALT ramrod. */
3162 sc->fp[0].state = BXE_FP_STATE_HALTING;
3163 bxe_sp_post(sc,RAMROD_CMD_ID_ETH_HALT, 0, 0, sc->fp[0].cl_id, 0);
3165 /* Poll for the ETH_HALT ramrod on the leading connection. */
3166 rc = bxe_wait_ramrod(sc, BXE_FP_STATE_HALTED,
3167 0, &(sc->fp[0].state), 1);
3169 DBPRINT(sc, BXE_FATAL, "%s(): Timeout waiting for "
3170 "STATE_HALTED ramrod completion!\n", __FUNCTION__);
3171 goto bxe_stop_leading_exit;
3174 /* Get the default status block SP producer index. */
3175 dsb_sp_prod_idx = *sc->dsb_sp_prod;
3177 /* After HALT we send PORT_DELETE ramrod. */
3178 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_PORT_DEL, 0, 0, 0, 1);
3180 /* Be patient but don't wait forever. */
3182 while (dsb_sp_prod_idx == *sc->dsb_sp_prod) {
3184 DBPRINT(sc, BXE_FATAL, "%s(): Timeout waiting for "
3185 "PORT_DEL ramrod completion!\n", __FUNCTION__);
3194 /* Update the adapter and connection states. */
3195 sc->state = BXE_STATE_CLOSING_WAIT4_UNLOAD;
3196 sc->fp[0].state = BXE_FP_STATE_CLOSED;
3198 bxe_stop_leading_exit:
3203 * Setup a client connection when using multi-queue/RSS.
3209 bxe_setup_multi(struct bxe_softc *sc, int index)
3211 struct bxe_fastpath *fp;
3214 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
3215 BXE_VERBOSE_UNLOAD), "%s(): Setup client connection "
3216 "on fp[%02d].\n", __FUNCTION__, index);
3218 fp = &sc->fp[index];
3219 /* Reset IGU state. */
3220 bxe_ack_sb(sc, fp->sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
3222 /* Post a CLIENT_SETUP ramrod. */
3223 fp->state = BXE_FP_STATE_OPENING;
3224 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_CLIENT_SETUP, index, 0, fp->cl_id, 0);
3226 /* Wait for the ramrod to complete. */
3227 rc = bxe_wait_ramrod(sc, BXE_FP_STATE_OPEN, index, &fp->state, 1);
3233 * Stop a client connection.
3235 * Stops an individual client connection on the device. Use
3236 * bxe_stop_leading() for the first/default connection.
3239 * 0 = Success, !0 = Failure.
3242 bxe_stop_multi(struct bxe_softc *sc, int index)
3244 struct bxe_fastpath *fp;
3247 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
3248 BXE_VERBOSE_UNLOAD), "%s(): Stop client connection "
3249 "on fp[%02d].\n", __FUNCTION__, index);
3251 fp = &sc->fp[index];
3253 /* Halt the client connection. */
3254 fp->state = BXE_FP_STATE_HALTING;
3255 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_HALT, index, 0, fp->cl_id, 0);
3257 /* Wait for the HALT ramrod completion. */
3258 rc = bxe_wait_ramrod(sc, BXE_FP_STATE_HALTED, index, &fp->state, 1);
3260 BXE_PRINTF("%s(%d): fp[%02d] client ramrod halt failed!\n",
3261 __FILE__, __LINE__, index);
3262 goto bxe_stop_multi_exit;
3264 /* Delete the CFC entry. */
3265 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_CFC_DEL, index, 0, 0, 1);
3267 /* Poll for the DELETE ramrod completion. */
3268 rc = bxe_wait_ramrod(sc, BXE_FP_STATE_CLOSED, index, &fp->state, 1);
3270 bxe_stop_multi_exit:
3275 * Hardware lock for shared, dual-port PHYs.
3281 bxe_acquire_phy_lock(struct bxe_softc *sc)
3283 uint32_t ext_phy_type;
3285 DBENTER(BXE_VERBOSE_PHY);
3287 ext_phy_type = XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
3288 switch(ext_phy_type){
3289 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3290 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3291 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3292 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
3293 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
3298 DBEXIT(BXE_VERBOSE_PHY);
3302 * Hardware unlock for shared, dual-port PHYs.
3308 bxe_release_phy_lock(struct bxe_softc *sc)
3310 uint32_t ext_phy_type;
3312 DBENTER(BXE_VERBOSE_PHY);
3313 ext_phy_type = XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config);
3314 switch(ext_phy_type){
3315 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
3316 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
3317 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
3318 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
3319 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_MDIO);
3325 DBEXIT(BXE_VERBOSE_PHY);
3334 bxe__link_reset(struct bxe_softc *sc)
3336 DBENTER(BXE_VERBOSE_PHY);
3339 bxe_acquire_phy_lock(sc);
3340 bxe_link_reset(&sc->link_params, &sc->link_vars, 1);
3341 bxe_release_phy_lock(sc);
3343 DBPRINT(sc, BXE_WARN,
3344 "%s(): Bootcode is not running, not resetting link!\n",
3348 DBEXIT(BXE_VERBOSE_PHY);
3352 * Stop the controller.
3355 * 0 = Success, !0 = Failure
3358 bxe_stop_locked(struct bxe_softc *sc, int unload_mode)
3361 struct mac_configuration_cmd *config;
3362 struct bxe_fastpath *fp;
3363 uint32_t reset_code;
3364 uint32_t emac_base, val;
3365 uint8_t entry, *mac_addr;
3366 int count, i, port, rc;
3368 DBENTER(BXE_INFO_LOAD | BXE_INFO_RESET | BXE_INFO_UNLOAD);
3372 rc = reset_code = 0;
3374 BXE_CORE_LOCK_ASSERT(sc);
3376 /* Stop the periodic tick. */
3377 callout_stop(&sc->bxe_tick_callout);
3379 sc->state = BXE_STATE_CLOSING_WAIT4_HALT;
3381 /* Prevent any further RX traffic. */
3382 sc->rx_mode = BXE_RX_MODE_NONE;
3383 bxe_set_storm_rx_mode(sc);
3385 /* Tell the stack the driver is stopped and TX queue is full. */
3387 ifp->if_drv_flags = 0;
3389 /* Tell the bootcode to stop watching for a heartbeat. */
3390 SHMEM_WR(sc, func_mb[BP_FUNC(sc)].drv_pulse_mb,
3391 (DRV_PULSE_ALWAYS_ALIVE | sc->fw_drv_pulse_wr_seq));
3393 /* Stop the statistics updates. */
3394 bxe_stats_handle(sc, STATS_EVENT_STOP);
3396 /* Wait until all TX fastpath tasks have completed. */
3397 for (i = 0; i < sc->num_queues; i++) {
3400 if (fp == NULL || fp->tx_pkt_cons_sb == NULL)
3404 while (bxe_has_tx_work(fp)) {
3410 "%s(%d): Timeout wating for fp[%02d] transmits to complete!\n",
3411 __FILE__, __LINE__, i);
3420 /* Wait until all slowpath tasks have completed. */
3422 while ((sc->spq_left != MAX_SPQ_PENDING) && count--)
3425 /* Disable Interrupts */
3426 bxe_int_disable(sc);
3429 /* Clear the MAC addresses. */
3430 if (CHIP_IS_E1(sc)) {
3431 config = BXE_SP(sc, mcast_config);
3432 bxe_set_mac_addr_e1(sc, 0);
3434 for (i = 0; i < config->hdr.length; i++)
3435 CAM_INVALIDATE(&config->config_table[i]);
3437 config->hdr.length = i;
3438 config->hdr.offset = BXE_MAX_MULTICAST * (1 + port);
3439 config->hdr.client_id = BP_CL_ID(sc);
3440 config->hdr.reserved1 = 0;
3442 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
3443 U64_HI(BXE_SP_MAPPING(sc, mcast_config)),
3444 U64_LO(BXE_SP_MAPPING(sc, mcast_config)), 0);
3446 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 0);
3447 bxe_set_mac_addr_e1h(sc, 0);
3448 for (i = 0; i < MC_HASH_SIZE; i++)
3449 REG_WR(sc, MC_HASH_OFFSET(sc, i), 0);
3450 REG_WR(sc, MISC_REG_E1HMF_MODE, 0);
3453 /* Determine if any WoL settings needed. */
3454 if (unload_mode == UNLOAD_NORMAL)
3455 /* Driver initiatied WoL is disabled. */
3456 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3457 else if (sc->bxe_flags & BXE_NO_WOL_FLAG) {
3458 /* Driver initiated WoL is disabled, use OOB WoL settings. */
3459 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
3460 if (CHIP_IS_E1H(sc))
3461 REG_WR(sc, MISC_REG_E1HMF_MODE, 0);
3462 } else if (sc->wol) {
3463 emac_base = BP_PORT(sc) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3464 mac_addr = sc->link_params.mac_addr;
3465 entry = (BP_E1HVN(sc) + 1) * 8;
3466 val = (mac_addr[0] << 8) | mac_addr[1];
3467 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val);
3468 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
3469 (mac_addr[4] << 8) | mac_addr[5];
3470 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
3471 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
3474 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
3477 /* Stop all non-leading client connections. */
3478 for (i = 1; i < sc->num_queues; i++) {
3479 if (bxe_stop_multi(sc, i)){
3480 goto bxe_stop_locked_exit;
3484 /* Stop the leading client connection. */
3485 rc = bxe_stop_leading(sc);
3488 bxe_stop_locked_exit:
3490 DBPRINT(sc, BXE_INFO,
3491 "%s(): Old No MCP load counts: %d, %d, %d\n",
3492 __FUNCTION__, load_count[0], load_count[1], load_count[2]);
3495 load_count[1 + port]--;
3496 DBPRINT(sc, BXE_INFO,
3497 "%s(): New No MCP load counts: %d, %d, %d\n",
3498 __FUNCTION__, load_count[0], load_count[1], load_count[2]);
3500 if (load_count[0] == 0)
3501 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
3502 else if (load_count[1 + BP_PORT(sc)] == 0)
3503 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
3505 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
3507 /* Tell MCP driver unload is complete. */
3508 reset_code = bxe_fw_command(sc, reset_code);
3511 if ((reset_code == FW_MSG_CODE_DRV_UNLOAD_COMMON) ||
3512 (reset_code == FW_MSG_CODE_DRV_UNLOAD_PORT))
3513 bxe__link_reset(sc);
3517 /* Reset the chip */
3518 bxe_reset_chip(sc, reset_code);
3522 /* Report UNLOAD_DONE to MCP */
3524 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
3527 /* Free RX chains and buffers. */
3528 bxe_clear_rx_chains(sc);
3530 /* Free TX chains and buffers. */
3531 bxe_clear_tx_chains(sc);
3533 sc->state = BXE_STATE_CLOSED;
3537 DBEXIT(BXE_INFO_LOAD | BXE_INFO_RESET |BXE_INFO_UNLOAD);
3542 * Device shutdown function.
3544 * Stops and resets the controller.
3547 * 0 = Success, !0 = Failure
3550 bxe_shutdown(device_t dev)
3552 struct bxe_softc *sc;
3554 sc = device_get_softc(dev);
3555 DBENTER(BXE_INFO_LOAD | BXE_INFO_RESET | BXE_INFO_UNLOAD);
3557 /* Stop the controller, but only if it was ever started.
3558 * Stopping an uninitialized controller can cause
3559 * IPMI bus errors on some systems.
3562 if (sc->state != BXE_STATE_CLOSED) {
3563 bxe_stop_locked(sc, UNLOAD_NORMAL);
3565 BXE_CORE_UNLOCK(sc);
3567 DBEXIT(BXE_INFO_LOAD | BXE_INFO_RESET | BXE_INFO_UNLOAD);
3572 * Prints out link speed and duplex setting to console.
3578 bxe_link_report(struct bxe_softc *sc)
3580 uint32_t line_speed;
3581 uint16_t vn_max_rate;
3583 DBENTER(BXE_VERBOSE_PHY);
3585 if (sc->link_vars.link_up) {
3586 /* Report the link status change to OS. */
3587 if (sc->state == BXE_STATE_OPEN)
3588 if_link_state_change(sc->bxe_ifp, LINK_STATE_UP);
3590 line_speed = sc->link_vars.line_speed;
3593 vn_max_rate = ((sc->mf_config[BP_E1HVN(sc)] &
3594 FUNC_MF_CFG_MAX_BW_MASK) >>
3595 FUNC_MF_CFG_MAX_BW_SHIFT) * 100;
3596 if (vn_max_rate < line_speed)
3597 line_speed = vn_max_rate;
3600 BXE_PRINTF("Link is up, %d Mbps, ", line_speed);
3602 if (sc->link_vars.duplex == MEDIUM_FULL_DUPLEX)
3603 printf("full duplex");
3605 printf("half duplex");
3607 if (sc->link_vars.flow_ctrl) {
3608 if (sc->link_vars.flow_ctrl & FLOW_CTRL_RX) {
3609 printf(", receive ");
3610 if (sc->link_vars.flow_ctrl & FLOW_CTRL_TX)
3611 printf("& transmit ");
3613 printf(", transmit ");
3614 printf("flow control ON");
3618 /* Report the link down */
3619 BXE_PRINTF("Link is down\n");
3620 if_link_state_change(sc->bxe_ifp, LINK_STATE_DOWN);
3623 DBEXIT(BXE_VERBOSE_PHY);
3632 bxe__link_status_update(struct bxe_softc *sc)
3634 DBENTER(BXE_VERBOSE_PHY);
3636 if (sc->stats_enable == FALSE || sc->state != BXE_STATE_OPEN)
3639 bxe_link_status_update(&sc->link_params, &sc->link_vars);
3641 if (sc->link_vars.link_up)
3642 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
3644 bxe_stats_handle(sc, STATS_EVENT_STOP);
3646 bxe_read_mf_cfg(sc);
3648 /* Indicate link status. */
3649 bxe_link_report(sc);
3651 DBEXIT(BXE_VERBOSE_PHY);
3655 * Calculate flow control to advertise during autonegotiation.
3661 bxe_calc_fc_adv(struct bxe_softc *sc)
3663 DBENTER(BXE_EXTREME_PHY);
3665 switch (sc->link_vars.ieee_fc &
3666 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
3668 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
3669 sc->port.advertising &= ~(ADVERTISED_Asym_Pause |
3673 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
3674 sc->port.advertising |= (ADVERTISED_Asym_Pause |
3678 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
3679 sc->port.advertising |= ADVERTISED_Asym_Pause;
3683 sc->port.advertising &= ~(ADVERTISED_Asym_Pause |
3688 DBEXIT(BXE_EXTREME_PHY);
3699 bxe_initial_phy_init(struct bxe_softc *sc)
3703 DBENTER(BXE_VERBOSE_PHY);
3709 * It is recommended to turn off RX flow control for 5771x
3710 * when using jumbo frames for better performance.
3712 if (!IS_E1HMF(sc) && (sc->mbuf_alloc_size > 5000))
3713 sc->link_params.req_fc_auto_adv = FLOW_CTRL_TX;
3715 sc->link_params.req_fc_auto_adv = FLOW_CTRL_BOTH;
3717 bxe_acquire_phy_lock(sc);
3718 rc = bxe_phy_init(&sc->link_params, &sc->link_vars);
3719 bxe_release_phy_lock(sc);
3721 bxe_calc_fc_adv(sc);
3723 if (sc->link_vars.link_up) {
3724 bxe_stats_handle(sc,STATS_EVENT_LINK_UP);
3725 bxe_link_report(sc);
3729 DBPRINT(sc, BXE_FATAL, "%s(): Bootcode is not running, "
3730 "not initializing link!\n", __FUNCTION__);
3734 DBEXIT(BXE_VERBOSE_PHY);
3739 #if __FreeBSD_version >= 800000
3741 * Allocate buffer rings used for multiqueue.
3744 * 0 = Success, !0 = Failure.
3747 bxe_alloc_buf_rings(struct bxe_softc *sc)
3749 struct bxe_fastpath *fp;
3752 DBENTER(BXE_VERBOSE_LOAD);
3755 for (i = 0; i < sc->num_queues; i++) {
3759 fp->br = buf_ring_alloc(BXE_BR_SIZE,
3760 M_DEVBUF, M_NOWAIT, &fp->mtx);
3761 if (fp->br == NULL) {
3763 goto bxe_alloc_buf_rings_exit;
3766 BXE_PRINTF("%s(%d): Bug!\n", __FILE__, __LINE__);
3769 bxe_alloc_buf_rings_exit:
3770 DBEXIT(BXE_VERBOSE_LOAD);
3775 * Releases buffer rings used for multiqueue.
3781 bxe_free_buf_rings(struct bxe_softc *sc)
3783 struct bxe_fastpath *fp;
3786 DBENTER(BXE_VERBOSE_UNLOAD);
3788 for (i = 0; i < sc->num_queues; i++) {
3792 buf_ring_free(fp->br, M_DEVBUF);
3796 DBEXIT(BXE_VERBOSE_UNLOAD);
3802 * Handles controller initialization.
3804 * Must be called from a locked routine. Since this code
3805 * may be called from the OS it does not provide a return
3806 * error value and must clean-up it's own mess.
3812 bxe_init_locked(struct bxe_softc *sc, int load_mode)
3818 DBENTER(BXE_INFO_LOAD | BXE_INFO_RESET);
3820 BXE_CORE_LOCK_ASSERT(sc);
3823 /* Skip if we're in panic mode. */
3825 DBPRINT(sc, BXE_WARN, "%s(): Panic mode enabled, exiting!\n",
3827 goto bxe_init_locked_exit;
3830 /* Check if the driver is still running and bail out if it is. */
3831 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3832 DBPRINT(sc, BXE_WARN,
3833 "%s(): Init called while driver is running!\n",
3835 goto bxe_init_locked_exit;
3839 * Send LOAD_REQUEST command to MCP.
3840 * The MCP will return the type of LOAD
3841 * the driver should perform.
3842 * - If it is the first port to be initialized
3843 * then all common blocks should be initialized.
3844 * - If it is not the first port to be initialized
3845 * then don't do the common block initialization.
3847 sc->state = BXE_STATE_OPENING_WAIT4_LOAD;
3852 DBPRINT(sc, BXE_INFO,
3853 "%s(): Old No MCP load counts: %d, %d, %d\n",
3855 load_count[0], load_count[1], load_count[2]);
3858 load_count[1 + port]++;
3860 DBPRINT(sc, BXE_INFO,
3861 "%s(): New No MCP load counts: %d, %d, %d\n",
3863 load_count[0], load_count[1], load_count[2]);
3865 /* No MCP to tell us what to do. */
3866 if (load_count[0] == 1)
3867 load_code = FW_MSG_CODE_DRV_LOAD_COMMON;
3868 else if (load_count[1 + port] == 1)
3869 load_code = FW_MSG_CODE_DRV_LOAD_PORT;
3871 load_code = FW_MSG_CODE_DRV_LOAD_FUNCTION;
3874 /* Ask the MCP what type of initialization we need to do. */
3875 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ);
3877 if ((load_code == 0) ||
3878 (load_code == FW_MSG_CODE_DRV_LOAD_REFUSED)) {
3879 BXE_PRINTF("%s(%d): Bootcode refused load request.!\n",
3880 __FILE__, __LINE__);
3881 goto bxe_init_locked_failed1;
3885 /* Keep track of whether we are controlling the port. */
3886 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
3887 (load_code == FW_MSG_CODE_DRV_LOAD_PORT))
3892 /* Block any interrupts until we're ready. */
3895 /* Initialize hardware. */
3896 error = bxe_init_hw(sc, load_code);
3898 BXE_PRINTF("%s(%d): Hardware initialization failed, "
3899 "aborting!\n", __FILE__, __LINE__);
3900 goto bxe_init_locked_failed1;
3903 /* Calculate and save the Ethernet MTU size. */
3904 sc->port.ether_mtu = ifp->if_mtu + ETHER_HDR_LEN +
3905 (ETHER_VLAN_ENCAP_LEN * 2) + ETHER_CRC_LEN + 4;
3907 DBPRINT(sc, BXE_INFO, "%s(): Setting MTU = %d\n",
3908 __FUNCTION__, sc->port.ether_mtu);
3910 /* Setup the mbuf allocation size for RX frames. */
3911 if (sc->port.ether_mtu <= MCLBYTES)
3912 sc->mbuf_alloc_size = MCLBYTES;
3913 else if (sc->port.ether_mtu <= PAGE_SIZE)
3914 sc->mbuf_alloc_size = PAGE_SIZE;
3916 sc->mbuf_alloc_size = MJUM9BYTES;
3918 DBPRINT(sc, BXE_INFO, "%s(): mbuf_alloc_size = %d, "
3919 "max_frame_size = %d\n", __FUNCTION__,
3920 sc->mbuf_alloc_size, sc->port.ether_mtu);
3922 /* Setup NIC internals and enable interrupts. */
3923 error = bxe_init_nic(sc, load_code);
3925 BXE_PRINTF("%s(%d): NIC initialization failed, "
3926 "aborting!\n", __FILE__, __LINE__);
3927 goto bxe_init_locked_failed1;
3930 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) &&
3931 (sc->common.shmem2_base)){
3932 if (sc->dcc_enable == TRUE) {
3933 BXE_PRINTF("Enabing DCC support\n");
3934 SHMEM2_WR(sc, dcc_support,
3935 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
3936 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
3940 #if __FreeBSD_version >= 800000
3941 /* Allocate buffer rings for multiqueue operation. */
3942 error = bxe_alloc_buf_rings(sc);
3944 BXE_PRINTF("%s(%d): Buffer ring initialization failed, "
3945 "aborting!\n", __FILE__, __LINE__);
3946 goto bxe_init_locked_failed1;
3950 /* Tell MCP that driver load is done. */
3952 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE);
3954 BXE_PRINTF("%s(%d): Driver load failed! No MCP "
3955 "response to LOAD_DONE!\n", __FILE__, __LINE__);
3956 goto bxe_init_locked_failed2;
3960 sc->state = BXE_STATE_OPENING_WAIT4_PORT;
3962 /* Enable ISR for PORT_SETUP ramrod. */
3965 /* Setup the leading connection for the controller. */
3966 error = bxe_setup_leading(sc);
3968 DBPRINT(sc, BXE_FATAL, "%s(): Initial PORT_SETUP ramrod "
3969 "failed. State is not OPEN!\n", __FUNCTION__);
3970 goto bxe_init_locked_failed3;
3973 if (CHIP_IS_E1H(sc)) {
3974 if (sc->mf_config[BP_E1HVN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) {
3975 BXE_PRINTF("Multi-function mode is disabled\n");
3976 /* sc->state = BXE_STATE_DISABLED; */
3979 /* Setup additional client connections for RSS/multi-queue */
3980 if (sc->state == BXE_STATE_OPEN) {
3981 for (i = 1; i < sc->num_queues; i++) {
3982 if (bxe_setup_multi(sc, i)) {
3983 DBPRINT(sc, BXE_FATAL,
3984 "%s(): fp[%02d] CLIENT_SETUP ramrod failed! State not OPEN!\n",
3986 goto bxe_init_locked_failed4;
3995 /* Initialize statistics. */
3999 /* Load our MAC address. */
4000 bcopy(IF_LLADDR(sc->bxe_ifp), sc->link_params.mac_addr, ETHER_ADDR_LEN);
4003 bxe_set_mac_addr_e1(sc, 1);
4005 bxe_set_mac_addr_e1h(sc, 1);
4009 /* Perform PHY initialization for the primary port. */
4011 bxe_initial_phy_init(sc);
4015 /* Start fastpath. */
4016 switch (load_mode) {
4019 /* Initialize the receive filters. */
4020 bxe_set_rx_mode(sc);
4024 /* Initialize the receive filters. */
4025 bxe_set_rx_mode(sc);
4026 sc->state = BXE_STATE_DIAG;
4030 DBPRINT(sc, BXE_WARN, "%s(): Unknown load mode (%d)!\n",
4031 __FUNCTION__, load_mode);
4036 bxe__link_status_update(sc);
4039 /* Tell the stack the driver is running. */
4040 ifp->if_drv_flags = IFF_DRV_RUNNING;
4042 /* Schedule our periodic timer tick. */
4043 callout_reset(&sc->bxe_tick_callout, hz, bxe_tick, sc);
4044 /* Everything went OK, go ahead and exit. */
4045 goto bxe_init_locked_exit;
4047 bxe_init_locked_failed4:
4048 /* Try and gracefully shutdown the device because of a failure. */
4049 for (i = 1; i < sc->num_queues; i++)
4050 bxe_stop_multi(sc, i);
4052 bxe_init_locked_failed3:
4053 bxe_stop_leading(sc);
4054 bxe_stats_handle(sc, STATS_EVENT_STOP);
4056 bxe_init_locked_failed2:
4057 bxe_int_disable(sc);
4059 bxe_init_locked_failed1:
4061 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE);
4062 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
4063 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE);
4067 #if __FreeBSD_version >= 800000
4068 bxe_free_buf_rings(sc);
4071 DBPRINT(sc, BXE_WARN, "%s(): Initialization failed!\n", __FUNCTION__);
4073 bxe_init_locked_exit:
4074 DBEXIT(BXE_INFO_LOAD | BXE_INFO_RESET);
4078 * Ramrod wait function.
4080 * Waits for a ramrod command to complete.
4083 * 0 = Success, !0 = Failure
4086 bxe_wait_ramrod(struct bxe_softc *sc, int state, int idx, int *state_p,
4091 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
4093 DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): %s for state 0x%08X on "
4094 "fp[%02d], currently 0x%08X.\n", __FUNCTION__,
4095 poll ? "Polling" : "Waiting", state, idx, *state_p);
4101 /* Manually check for the completion. */
4105 * Some commands don't use the leading client
4109 bxe_rxeof(&sc->fp[idx]);
4112 /* State may be changed by bxe_sp_event(). */
4114 if (*state_p == state)
4115 goto bxe_wait_ramrod_exit;
4119 /* Pause 1ms before checking again. */
4123 /* We timed out polling for a completion. */
4124 DBPRINT(sc, BXE_FATAL, "%s(): Timeout %s for state 0x%08X on fp[%02d]. "
4125 "Got 0x%x instead\n", __FUNCTION__, poll ? "polling" : "waiting",
4126 state, idx, *state_p);
4130 bxe_wait_ramrod_exit:
4132 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_RAMROD);
4141 bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
4142 uint32_t addr, uint32_t len)
4144 int dmae_wr_max, offset;
4145 DBENTER(BXE_INSANE_REGS);
4147 dmae_wr_max = DMAE_LEN32_WR_MAX(sc);
4149 while (len > dmae_wr_max) {
4150 bxe_write_dmae(sc, phys_addr + offset, addr + offset,
4152 offset += dmae_wr_max * 4;
4155 bxe_write_dmae(sc, phys_addr + offset, addr + offset, len);
4156 DBEXIT(BXE_INSANE_REGS);
4162 #define INIT_MEM_WR(block, reg, part, hw, data, reg_off, len) \
4163 bxe_init_str_wr(sc, GRCBASE_##block + reg + reg_off * 4, data, len)
4167 * Write a block of data to a range of registers.
4173 bxe_init_str_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
4177 for (i = 0; i < len; i++)
4178 REG_WR(sc, addr + i * 4, data[i]);
4182 * Write a block of data to a range of registers using indirect access.
4188 bxe_init_ind_wr(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
4192 for (i = 0; i < len; i++)
4193 REG_WR_IND(sc, addr + i * 4, data[i]);
4202 bxe_write_big_buf(struct bxe_softc *sc, uint32_t addr, uint32_t len)
4204 DBENTER(BXE_INSANE_REGS);
4207 bxe_write_dmae_phys_len(sc, sc->gz_dma.paddr, addr, len);
4209 bxe_init_str_wr(sc, addr, sc->gz, len);
4211 bxe_init_str_wr(sc, addr, sc->gz, len);
4214 DBEXIT(BXE_INSANE_REGS);
4218 * Fill areas of device memory with the specified value.
4220 * Generally used to clear a small area of device memory prior to writing
4221 * firmware to STORM memory or writing STORM firmware to device memory.
4227 bxe_init_fill(struct bxe_softc *sc, uint32_t addr, int fill, uint32_t len)
4229 uint32_t cur_len, i, leftovers, length;
4231 DBENTER(BXE_VERBOSE_LOAD);
4233 length = (((len * 4) > BXE_FW_BUF_SIZE) ? BXE_FW_BUF_SIZE : (len * 4));
4234 leftovers = length / 4;
4235 memset(sc->gz, fill, length);
4237 for (i = 0; i < len; i += leftovers) {
4238 cur_len = min(leftovers, len - i);
4239 bxe_write_big_buf(sc, addr + i * 4, cur_len);
4242 DBEXIT(BXE_VERBOSE_LOAD);
4251 bxe_init_wr_64(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
4254 uint64_t data64, *pdata;
4255 uint32_t buf_len32, cur_len, len;
4258 DBENTER(BXE_INSANE_REGS);
4260 buf_len32 = BXE_FW_BUF_SIZE / 4;
4262 /* 64 bit value is in a blob: first low DWORD, then high DWORD. */
4263 data64 = HILO_U64((*(data + 1)), (*data));
4264 len64 = min((uint32_t)(BXE_FW_BUF_SIZE / 8), len64);
4265 for (i = 0; i < len64; i++) {
4266 pdata = ((uint64_t *)(sc->gz)) + i;
4270 for (i = 0; i < len; i += buf_len32) {
4271 cur_len = min(buf_len32, len - i);
4272 bxe_write_big_buf(sc, addr + i*4, cur_len);
4275 DBEXIT(BXE_INSANE_REGS);
4280 * There are different blobs for each PRAM section. In addition, each
4281 * blob write operation is divided into multiple, smaller write
4282 * operations in order to decrease the amount of physically contiguous
4283 * buffer memory needed. Thus, when we select a blob, the address may
4284 * be with some offset from the beginning of PRAM section. The same
4285 * holds for the INT_TABLE sections.
4288 #define IF_IS_INT_TABLE_ADDR(base, addr) \
4289 if (((base) <= (addr)) && ((base) + 0x400 >= (addr)))
4291 #define IF_IS_PRAM_ADDR(base, addr) \
4292 if (((base) <= (addr)) && ((base) + 0x40000 >= (addr)))
4300 static const uint8_t *
4301 bxe_sel_blob(struct bxe_softc *sc, uint32_t addr, const uint8_t *data)
4304 IF_IS_INT_TABLE_ADDR(TSEM_REG_INT_TABLE, addr)
4305 data = INIT_TSEM_INT_TABLE_DATA(sc);
4307 IF_IS_INT_TABLE_ADDR(CSEM_REG_INT_TABLE, addr)
4308 data = INIT_CSEM_INT_TABLE_DATA(sc);
4310 IF_IS_INT_TABLE_ADDR(USEM_REG_INT_TABLE, addr)
4311 data = INIT_USEM_INT_TABLE_DATA(sc);
4313 IF_IS_INT_TABLE_ADDR(XSEM_REG_INT_TABLE, addr)
4314 data = INIT_XSEM_INT_TABLE_DATA(sc);
4316 IF_IS_PRAM_ADDR(TSEM_REG_PRAM, addr)
4317 data = INIT_TSEM_PRAM_DATA(sc);
4319 IF_IS_PRAM_ADDR(CSEM_REG_PRAM, addr)
4320 data = INIT_CSEM_PRAM_DATA(sc);
4322 IF_IS_PRAM_ADDR(USEM_REG_PRAM, addr)
4323 data = INIT_USEM_PRAM_DATA(sc);
4325 IF_IS_PRAM_ADDR(XSEM_REG_PRAM, addr)
4326 data = INIT_XSEM_PRAM_DATA(sc);
4333 bxe_write_big_buf_wb(struct bxe_softc *sc, uint32_t addr, uint32_t len)
4336 bxe_write_dmae_phys_len(sc, sc->gz_dma.paddr, addr, len);
4338 bxe_init_ind_wr(sc, addr, sc->gz, len);
4342 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
4344 memcpy(sc->gz, data, (len32)*4); \
4345 bxe_write_big_buf_wb(sc, addr, len32); \
4355 bxe_init_wr_wb(struct bxe_softc *sc, uint32_t addr, const uint32_t *data,
4358 const uint32_t *old_data;
4360 DBENTER(BXE_INSANE_REGS);
4362 data = (const uint32_t *)bxe_sel_blob(sc, addr, (const uint8_t *)data);
4363 if (sc->dmae_ready) {
4364 if (old_data != data)
4365 VIRT_WR_DMAE_LEN(sc, data, addr, len, 1);
4367 VIRT_WR_DMAE_LEN(sc, data, addr, len, 0);
4369 bxe_init_ind_wr(sc, addr, data, len);
4371 DBEXIT(BXE_INSANE_REGS);
4375 bxe_init_wr_zp(struct bxe_softc *sc, uint32_t addr, uint32_t len,
4378 BXE_PRINTF("%s(%d): Compressed FW is not supported yet. "
4379 "ERROR: address:0x%x len:0x%x blob_offset:0x%x\n",
4380 __FILE__, __LINE__, addr, len, blob_off);
4384 * Initialize blocks of the device.
4386 * This routine basically performs bulk register programming for different
4387 * blocks within the controller. The file bxe_init_values.h contains a
4388 * series of register access operations (read, write, fill, etc.) as well
4389 * as a BLOB of data to initialize multiple blocks within the controller.
4390 * Block initialization may be supported by all controllers or by specific
4397 bxe_init_block(struct bxe_softc *sc, uint32_t block, uint32_t stage)
4400 const uint32_t *data, *data_base;
4401 uint32_t i, op_type, addr, len;
4402 uint16_t op_end, op_start;
4405 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
4407 op_start = INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage,
4409 op_end = INIT_OPS_OFFSETS(sc)[BLOCK_OPS_IDX(block, stage, STAGE_END)];
4410 /* If empty block */
4411 if (op_start == op_end)
4416 data_base = INIT_DATA(sc);
4418 for (i = op_start; i < op_end; i++) {
4420 op = (union init_op *)&(INIT_OPS(sc)[i]);
4422 op_type = op->str_wr.op;
4423 addr = op->str_wr.offset;
4424 len = op->str_wr.data_len;
4425 data = data_base + op->str_wr.data_off;
4427 /* HW/EMUL specific */
4428 if ((op_type > OP_WB) && (op_type == hw_wr))
4436 REG_WR(sc, addr, op->write.val);
4439 bxe_init_str_wr(sc, addr, data, len);
4442 bxe_init_wr_wb(sc, addr, data, len);
4445 bxe_init_ind_wr(sc, addr, data, len);
4448 bxe_init_fill(sc, addr, 0, op->zero.len);
4451 bxe_init_wr_zp(sc, addr, len, op->str_wr.data_off);
4454 bxe_init_wr_64(sc, addr, data, len);
4457 /* happens whenever an op is of a diff HW */
4462 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
4466 * Handles controller initialization when called from an unlocked routine.
4467 * ifconfig calls this function.
4475 struct bxe_softc *sc;
4480 bxe_init_locked(sc, LOAD_NORMAL);
4481 BXE_CORE_UNLOCK(sc);
4485 * Release all resources used by the driver.
4487 * Releases all resources acquired by the driver including interrupts,
4488 * interrupt handler, interfaces, mutexes, and DMA memory.
4494 bxe_release_resources(struct bxe_softc *sc)
4498 DBENTER(BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
4502 /* Release the FreeBSD interface. */
4503 if (sc->bxe_ifp != NULL)
4504 if_free(sc->bxe_ifp);
4506 /* Free the DMA resources. */
4507 bxe_host_structures_free(sc);
4509 #if __FreeBSD_version >= 800000
4510 /* Free multiqueue buffer rings. */
4511 bxe_free_buf_rings(sc);
4518 * Indirect register write.
4520 * Writes NetXtreme II registers using an index/data register pair in PCI
4521 * configuration space. Using this mechanism avoids issues with posted
4522 * writes but is much slower than memory-mapped I/O.
4528 bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t offset, uint32_t val)
4530 DBPRINT(sc, BXE_INSANE_REGS, "%s(); offset = 0x%08X, val = 0x%08X\n",
4531 __FUNCTION__, offset, val);
4533 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, offset, 4);
4534 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4);
4536 /* Return to a safe address. */
4537 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS,
4538 PCICFG_VENDOR_ID_OFFSET, 4);
4543 * Indirect register read.
4545 * Reads NetXtreme II registers using an index/data register pair in PCI
4546 * configuration space. Using this mechanism avoids issues with posted
4547 * reads but is much slower than memory-mapped I/O.
4550 * The value of the register.
4553 bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t offset)
4557 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, offset, 4);
4558 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4);
4560 /* Return to a safe address. */
4561 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS,
4562 PCICFG_VENDOR_ID_OFFSET, 4);
4564 DBPRINT(sc, BXE_INSANE_REGS, "%s(); offset = 0x%08X, val = 0x%08X\n",
4565 __FUNCTION__, offset, val);
4571 static uint32_t dmae_reg_go_c[] = {
4572 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
4573 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
4574 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
4575 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
4580 * Copy DMAE command into memory and start the command.
4586 bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx)
4588 uint32_t cmd_offset;
4590 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
4592 for (i = 0; i < (sizeof(struct dmae_command) / 4); i++) {
4593 REG_WR(sc, cmd_offset + i * 4, *(((uint32_t *)dmae) + i));
4594 DBPRINT(sc, BXE_INSANE_REGS, "%s(): DMAE cmd[%d].%d : 0x%08X\n",
4595 __FUNCTION__, idx, i, cmd_offset + i * 4);
4598 /* Kick off the command. */
4599 REG_WR(sc, dmae_reg_go_c[idx], 1);
4604 * Perform a DMAE write to device memory.
4606 * Some of the registers on the 577XX controller are 128bits wide. It is
4607 * required that when accessing those registers that they be written
4608 * atomically and that no intervening bus acceses to the device occur.
4609 * This could be handled by a lock held across all driver instances for
4610 * the device or it can be handled by performing a DMA operation when
4611 * writing to the device. This code implements the latter.
4617 bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, uint32_t dst_addr,
4620 struct dmae_command dmae;
4621 uint32_t *data, *wb_comp;
4624 DBENTER(BXE_INSANE_REGS);
4626 DBPRINT(sc, BXE_EXTREME_REGS,
4627 "%s(): host addr = 0x%jX, device addr = 0x%08X, length = %d.\n",
4628 __FUNCTION__, (uintmax_t)dma_addr, dst_addr, (int)len32);
4630 wb_comp = BXE_SP(sc, wb_comp);
4631 /* Fall back to indirect access if DMAE is not ready. */
4632 if (!sc->dmae_ready) {
4633 data = BXE_SP(sc, wb_data[0]);
4635 DBPRINT(sc, BXE_WARN, "%s(): DMAE not ready, "
4636 "using indirect.\n", __FUNCTION__);
4638 bxe_init_ind_wr(sc, dst_addr, data, len32);
4639 goto bxe_write_dmae_exit;
4642 memset(&dmae, 0, sizeof(struct dmae_command));
4644 dmae.opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
4645 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4646 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4648 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4650 DMAE_CMD_ENDIANITY_DW_SWAP |
4652 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4653 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
4654 dmae.src_addr_lo = U64_LO(dma_addr);
4655 dmae.src_addr_hi = U64_HI(dma_addr);
4656 dmae.dst_addr_lo = dst_addr >> 2;
4657 dmae.dst_addr_hi = 0;
4659 dmae.comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
4660 dmae.comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
4661 dmae.comp_val = BXE_WB_COMP_VAL;
4667 bxe_post_dmae(sc, &dmae, INIT_DMAE_C(sc));
4671 /* Wait up to 200ms. */
4673 while (*wb_comp != BXE_WB_COMP_VAL) {
4675 DBPRINT(sc, BXE_FATAL,
4676 "%s(): DMAE timeout (dst_addr = 0x%08X, len = %d)!\n",
4677 __FUNCTION__, dst_addr, len32);
4684 BXE_DMAE_UNLOCK(sc);
4686 bxe_write_dmae_exit:
4687 DBEXIT(BXE_INSANE_REGS);
4692 * Perform a DMAE read from to device memory.
4694 * Some of the registers on the 577XX controller are 128bits wide. It is
4695 * required that when accessing those registers that they be read
4696 * atomically and that no intervening bus acceses to the device occur.
4697 * This could be handled by a lock held across all driver instances for
4698 * the device or it can be handled by performing a DMA operation when
4699 * reading from the device. This code implements the latter.
4705 bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr,
4708 struct dmae_command dmae;
4709 uint32_t *data, *wb_comp;
4712 DBENTER(BXE_INSANE_REGS);
4714 wb_comp = BXE_SP(sc, wb_comp);
4715 /* Fall back to indirect access if DMAE is not ready. */
4716 if (!sc->dmae_ready) {
4717 data = BXE_SP(sc, wb_data[0]);
4719 DBPRINT(sc, BXE_WARN, "%s(): DMAE not ready, "
4720 "using indirect.\n", __FUNCTION__);
4722 for (i = 0; i < len32; i++)
4723 data[i] = bxe_reg_rd_ind(sc, src_addr + i * 4);
4725 goto bxe_read_dmae_exit;
4728 memset(&dmae, 0, sizeof(struct dmae_command));
4730 dmae.opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
4731 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
4732 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
4734 DMAE_CMD_ENDIANITY_B_DW_SWAP |
4736 DMAE_CMD_ENDIANITY_DW_SWAP |
4738 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
4739 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
4741 dmae.src_addr_lo = src_addr >> 2;
4742 dmae.src_addr_hi = 0;
4743 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data));
4744 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data));
4746 dmae.comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp));
4747 dmae.comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp));
4748 dmae.comp_val = BXE_WB_COMP_VAL;
4752 memset(BXE_SP(sc, wb_data[0]), 0, sizeof(uint32_t) * 4);
4755 bxe_post_dmae(sc, &dmae, INIT_DMAE_C(sc));
4760 while (*wb_comp != BXE_WB_COMP_VAL) {
4762 DBPRINT(sc, BXE_FATAL,
4763 "%s(): DMAE timeout (src_addr = 0x%08X, len = %d)!\n",
4764 __FUNCTION__, src_addr, len32);
4771 BXE_DMAE_UNLOCK(sc);
4774 DBEXIT(BXE_INSANE_REGS);
4778 * DMAE write wrapper.
4784 bxe_wb_wr(struct bxe_softc *sc, int reg, uint32_t val_hi, uint32_t val_lo)
4786 uint32_t wb_write[2];
4788 wb_write[0] = val_hi;
4789 wb_write[1] = val_lo;
4790 REG_WR_DMAE(sc, reg, wb_write, 2);
4796 * Poll a register waiting for a value.
4799 * The last read register value.
4802 uint32_t bxe_reg_poll(struct bxe_softc *sc, uint32_t reg, uint32_t expected,
4808 val = REG_RD(sc, reg);
4809 if (val == expected)
4821 * Microcode assert display.
4823 * This function walks through each STORM processor and prints out a
4824 * listing of all asserts currently in effect. Useful for post-mortem
4828 * The number of asserts detected.
4831 bxe_mc_assert(struct bxe_softc *sc)
4833 uint32_t row0, row1, row2, row3;
4837 DBENTER(BXE_VERBOSE_INTR);
4841 last_idx = REG_RD8(sc, BAR_XSTORM_INTMEM +
4842 XSTORM_ASSERT_LIST_INDEX_OFFSET);
4845 DBPRINT(sc, BXE_FATAL, "DATA XSTORM_ASSERT_LIST_INDEX 0x%x\n",
4848 /* Print the asserts */
4849 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
4851 row0 = REG_RD(sc, BAR_XSTORM_INTMEM +
4852 XSTORM_ASSERT_LIST_OFFSET(i));
4853 row1 = REG_RD(sc, BAR_XSTORM_INTMEM +
4854 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
4855 row2 = REG_RD(sc, BAR_XSTORM_INTMEM +
4856 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
4857 row3 = REG_RD(sc, BAR_XSTORM_INTMEM +
4858 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
4860 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
4861 DBPRINT(sc, BXE_FATAL, "DATA XSTORM_ASSERT_INDEX %d = "
4862 "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
4870 last_idx = REG_RD8(sc, BAR_TSTORM_INTMEM +
4871 TSTORM_ASSERT_LIST_INDEX_OFFSET);
4874 DBPRINT(sc, BXE_FATAL, "DATA TSTORM_ASSERT_LIST_INDEX 0x%x\n",
4877 /* Print the asserts */
4878 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
4880 row0 = REG_RD(sc, BAR_TSTORM_INTMEM +
4881 TSTORM_ASSERT_LIST_OFFSET(i));
4882 row1 = REG_RD(sc, BAR_TSTORM_INTMEM +
4883 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
4884 row2 = REG_RD(sc, BAR_TSTORM_INTMEM +
4885 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
4886 row3 = REG_RD(sc, BAR_TSTORM_INTMEM +
4887 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
4889 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
4890 DBPRINT(sc, BXE_FATAL, "DATA TSTORM_ASSERT_INDEX %d = "
4891 "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
4899 last_idx = REG_RD8(sc, BAR_CSTORM_INTMEM +
4900 CSTORM_ASSERT_LIST_INDEX_OFFSET);
4903 DBPRINT(sc, BXE_FATAL, "DATA CSTORM_ASSERT_LIST_INDEX 0x%x\n",
4906 /* Print the asserts */
4907 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
4909 row0 = REG_RD(sc, BAR_CSTORM_INTMEM +
4910 CSTORM_ASSERT_LIST_OFFSET(i));
4911 row1 = REG_RD(sc, BAR_CSTORM_INTMEM +
4912 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
4913 row2 = REG_RD(sc, BAR_CSTORM_INTMEM +
4914 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
4915 row3 = REG_RD(sc, BAR_CSTORM_INTMEM +
4916 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
4918 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
4919 DBPRINT(sc, BXE_FATAL, "DATA CSTORM_ASSERT_INDEX %d = "
4920 "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
4928 last_idx = REG_RD8(sc, BAR_USTORM_INTMEM +
4929 USTORM_ASSERT_LIST_INDEX_OFFSET);
4932 DBPRINT(sc, BXE_FATAL, "DATA USTORM_ASSERT_LIST_INDEX 0x%x\n",
4935 /* Print the asserts */
4936 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) {
4938 row0 = REG_RD(sc, BAR_USTORM_INTMEM +
4939 USTORM_ASSERT_LIST_OFFSET(i));
4940 row1 = REG_RD(sc, BAR_USTORM_INTMEM +
4941 USTORM_ASSERT_LIST_OFFSET(i) + 4);
4942 row2 = REG_RD(sc, BAR_USTORM_INTMEM +
4943 USTORM_ASSERT_LIST_OFFSET(i) + 8);
4944 row3 = REG_RD(sc, BAR_USTORM_INTMEM +
4945 USTORM_ASSERT_LIST_OFFSET(i) + 12);
4947 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
4948 DBPRINT(sc, BXE_FATAL, "DATA USTORM_ASSERT_INDEX %d = "
4949 "0x%08x 0x%08x 0x%08x 0x%08x\n", i, row3, row2,
4956 DBEXIT(BXE_VERBOSE_INTR);
4962 * Perform a panic dump.
4968 bxe_panic_dump(struct bxe_softc *sc)
4972 sc->stats_state = STATS_STATE_DISABLED;
4974 BXE_PRINTF("---------- Begin crash dump ----------\n");
4976 /* Idle check is run twice to verify the controller has stopped. */
4985 BXE_PRINTF("---------- End crash dump ----------\n");
4992 * Enables interrupt generation.
4998 bxe_int_enable(struct bxe_softc *sc)
5000 uint32_t hc_addr, val;
5003 DBENTER(BXE_VERBOSE_INTR);
5006 hc_addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5007 val = REG_RD(sc, hc_addr);
5008 if (sc->msix_count > 0) {
5009 if (sc->msix_count == 1) {
5011 /* Single interrupt, multiple queues.*/
5012 DBPRINT(sc, BXE_VERBOSE_INTR,
5013 "%s(): Setting host coalescing registers for MSI-X (SIMQ).\n",
5017 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5019 /* Enable single ISR mode, MSI/MSI-X, and attention messages. */
5020 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5021 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5022 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5025 /* Multiple interrupts, multiple queues.*/
5026 DBPRINT(sc, BXE_VERBOSE_INTR,
5027 "%s(): Setting host coalescing registers for MSI-X (MIMQ).\n",
5030 /* Clear single ISR mode and INTx. */
5031 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5032 HC_CONFIG_0_REG_INT_LINE_EN_0);
5034 /* Enable MSI/MSI-X and attention messages. */
5035 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5036 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5039 } else if (sc->msi_count > 0) {
5041 if (sc->msi_count == 1) {
5043 /* Single interrupt, multiple queues.*/
5044 DBPRINT(sc, BXE_VERBOSE_INTR,
5045 "%s(): Setting host coalescing registers for MSI (SIMQ).\n",
5049 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
5051 /* Enable single ISR mode, MSI/MSI-X, and attention
5054 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5055 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5056 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5058 /* Multiple interrupts, multiple queues.*/
5059 DBPRINT(sc, BXE_VERBOSE_INTR,
5060 "%s(): Setting host coalescing registers for"
5064 /* Clear single ISR mode and INTx. */
5065 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5066 HC_CONFIG_0_REG_INT_LINE_EN_0);
5068 /* Enable MSI/MSI-X and attention messages. */
5069 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5070 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5073 /* Single interrupt, single queue. */
5074 DBPRINT(sc, BXE_VERBOSE_INTR,
5075 "%s(): Setting host coalescing registers for INTA#.\n",
5078 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
5079 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5080 HC_CONFIG_0_REG_INT_LINE_EN_0 |
5081 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5082 REG_WR(sc, hc_addr, val);
5084 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
5087 /* Write the interrupt mode to the host coalescing block. */
5088 REG_WR(sc, hc_addr, val);
5090 if (CHIP_IS_E1H(sc)) {
5092 /* Init leading/trailing edge attention generation. */
5094 val = (0xee0f | (1 << (BP_E1HVN(sc) + 4)));
5097 * Check if this driver instance is the port
5101 /* Enable nig & GPIO3 attentions. */
5106 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
5107 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
5110 DBEXIT(BXE_VERBOSE_INTR);
5115 * Disables interrupt generation.
5121 bxe_int_disable(struct bxe_softc *sc)
5123 uint32_t hc_addr, val;
5126 DBENTER(BXE_VERBOSE_INTR | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
5129 hc_addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
5130 val = REG_RD(sc, hc_addr);
5132 val &= ~(HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
5133 HC_CONFIG_0_REG_INT_LINE_EN_0 | HC_CONFIG_0_REG_ATTN_BIT_EN_0);
5135 REG_WR(sc, hc_addr, val);
5137 if (REG_RD(sc, hc_addr)!= val) {
5138 DBPRINT(sc, BXE_WARN, "%s(): BUG! Returned value from IGU "
5139 "doesn't match value written (0x%08X).\n",
5143 DBEXIT(BXE_VERBOSE_INTR | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
5146 #define BXE_CRC32_RESIDUAL 0xdebb20e3
5150 * 0 = Success, !0 = Failure.
5153 bxe_nvram_acquire_lock(struct bxe_softc *sc)
5158 DBENTER(BXE_VERBOSE_NVRAM);
5164 /* Acquire the NVRAM lock. */
5165 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
5166 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
5168 for (i = 0; i < NVRAM_TIMEOUT_COUNT * 10; i++) {
5169 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
5170 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
5176 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
5177 DBPRINT(sc, BXE_WARN, "%s(): Cannot acquire NVRAM lock!\n",
5182 DBEXIT(BXE_VERBOSE_NVRAM);
5188 * 0 = Success, !0 = Failure.
5191 bxe_nvram_release_lock(struct bxe_softc *sc)
5196 DBENTER(BXE_VERBOSE_NVRAM);
5202 /* Release the NVRAM lock. */
5203 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB,
5204 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
5206 for (i = 0; i < NVRAM_TIMEOUT_COUNT * 10; i++) {
5207 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB);
5208 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
5214 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
5215 DBPRINT(sc, BXE_WARN, "%s(): Cannot release NVRAM lock!\n",
5220 DBEXIT(BXE_VERBOSE_NVRAM);
5229 bxe_nvram_enable_access(struct bxe_softc *sc)
5233 DBENTER(BXE_VERBOSE_NVRAM);
5235 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
5237 /* Enable both bits, even on read */
5238 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
5239 (val | MCPR_NVM_ACCESS_ENABLE_EN |
5240 MCPR_NVM_ACCESS_ENABLE_WR_EN));
5242 DBEXIT(BXE_VERBOSE_NVRAM);
5250 bxe_nvram_disable_access(struct bxe_softc *sc)
5254 DBENTER(BXE_VERBOSE_NVRAM);
5256 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
5258 /* Disable both bits, even after read. */
5259 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
5260 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
5261 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
5263 DBEXIT(BXE_VERBOSE_NVRAM);
5268 * 0 = Success, !0 = Failure.
5271 bxe_nvram_read_dword(struct bxe_softc *sc, uint32_t offset, uint32_t *ret_val,
5277 DBENTER(BXE_INSANE_NVRAM);
5279 /* Build the command word. */
5280 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
5282 /* Need to clear DONE bit separately. */
5283 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
5285 /* Address within the NVRAM to read. */
5286 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
5287 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
5289 /* Issue a read command. */
5290 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
5292 /* Wait for completion. */
5295 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
5297 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
5299 if (val & MCPR_NVM_COMMAND_DONE) {
5300 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ);
5308 DBPRINT(sc, BXE_INSANE_NVRAM, "%s(): Read 0x%08X from offset 0x%08X.\n",
5309 __FUNCTION__, *ret_val, offset);
5310 DBEXIT(BXE_INSANE_NVRAM);
5316 * 0 = Success, !0 = Failure.
5319 bxe_nvram_read(struct bxe_softc *sc, uint32_t offset, uint8_t *ret_buf,
5322 uint32_t cmd_flags, val;
5325 DBENTER(BXE_EXTREME_NVRAM);
5327 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
5328 DBPRINT(sc, BXE_WARN, "%s(): Unaligned address or invalid "
5329 "buffer for NVRAM read (offset = 0x%08X, buf_size = %d)!\n",
5330 __FUNCTION__, offset, buf_size);
5332 goto bxe_nvram_read_exit;
5335 if (offset + buf_size > sc->common.flash_size) {
5336 DBPRINT(sc, BXE_WARN, "%s(): Read extends beyond the end of "
5337 "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
5338 "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
5339 sc->common.flash_size);
5341 goto bxe_nvram_read_exit;
5344 rc = bxe_nvram_acquire_lock(sc);
5346 goto bxe_nvram_read_exit;
5348 bxe_nvram_enable_access(sc);
5350 /* Read the first word(s). */
5351 cmd_flags = MCPR_NVM_COMMAND_FIRST;
5352 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) {
5353 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
5354 memcpy(ret_buf, &val, 4);
5356 /* Advance to the next DWORD. */
5357 offset += sizeof(uint32_t);
5358 ret_buf += sizeof(uint32_t);
5359 buf_size -= sizeof(uint32_t);
5363 /* Read the final word. */
5365 cmd_flags |= MCPR_NVM_COMMAND_LAST;
5366 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags);
5367 memcpy(ret_buf, &val, 4);
5370 /* Disable access to NVRAM interface. */
5371 bxe_nvram_disable_access(sc);
5372 bxe_nvram_release_lock(sc);
5374 bxe_nvram_read_exit:
5375 DBEXIT(BXE_EXTREME_NVRAM);
5379 #ifdef BXE_NVRAM_WRITE_SUPPORT
5382 * 0 = Success, !0 = Failure.
5385 bxe_nvram_write_dword(struct bxe_softc *sc, uint32_t offset, uint32_t val,
5390 DBENTER(BXE_VERBOSE_NVRAM);
5392 /* Build the command word. */
5393 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
5395 /* Need to clear DONE bit separately. */
5396 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
5398 /* Write the data. */
5399 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val);
5401 /* Address to write within the NVRAM. */
5402 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR,
5403 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
5405 /* Issue the write command. */
5406 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
5408 /* Wait for completion. */
5410 for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
5412 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND);
5413 if (val & MCPR_NVM_COMMAND_DONE) {
5419 DBEXIT(BXE_VERBOSE_NVRAM);
5423 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
5430 bxe_nvram_write1(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf,
5433 uint32_t align_offset, cmd_flags, val;
5436 DBENTER(BXE_VERBOSE_NVRAM);
5438 if (offset + buf_size > sc->common.flash_size) {
5439 DBPRINT(sc, BXE_WARN, "%s(): Write extends beyond the end of "
5440 "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
5441 "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
5442 sc->common.flash_size);
5444 goto bxe_nvram_write1_exit;
5447 /* request access to nvram interface */
5448 rc = bxe_nvram_acquire_lock(sc);
5450 goto bxe_nvram_write1_exit;
5452 /* Enable access to the NVRAM interface. */
5453 bxe_nvram_enable_access(sc);
5455 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
5456 align_offset = (offset & ~0x03);
5457 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags);
5460 val &= ~(0xff << BYTE_OFFSET(offset));
5461 val |= (*data_buf << BYTE_OFFSET(offset));
5464 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags);
5467 /* Disable access to the NVRAM interface. */
5468 bxe_nvram_disable_access(sc);
5469 bxe_nvram_release_lock(sc);
5471 bxe_nvram_write1_exit:
5472 DBEXIT(BXE_VERBOSE_NVRAM);
5478 * 0 = Success, !0 = Failure.
5481 bxe_nvram_write(struct bxe_softc *sc, uint32_t offset, uint8_t *data_buf,
5484 uint32_t cmd_flags, val, written_so_far;
5490 return (bxe_nvram_write1(sc, offset, data_buf, buf_size));
5492 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
5493 DBPRINT(sc, BXE_WARN, "%s(): Unaligned address or invalid "
5494 "buffer for NVRAM write "
5495 "(offset = 0x%08X, buf_size = %d)!\n", __FUNCTION__,
5498 goto bxe_nvram_write_exit;
5501 if (offset + buf_size > sc->common.flash_size) {
5502 DBPRINT(sc, BXE_WARN, "%s(): Write extends beyond the end of "
5503 "the NVRAM (offset (0x%08X) + buf_size (%d) > flash_size "
5504 "(0x%08X))!\n", __FUNCTION__, offset, buf_size,
5505 sc->common.flash_size);
5507 goto bxe_nvram_write_exit;
5510 /* Request access to NVRAM interface. */
5511 rc = bxe_nvram_acquire_lock(sc);
5513 goto bxe_nvram_write_exit;
5515 /* Enable access to the NVRAM interface. */
5516 bxe_nvram_enable_access(sc);
5519 cmd_flags = MCPR_NVM_COMMAND_FIRST;
5520 while ((written_so_far < buf_size) && (rc == 0)) {
5521 if (written_so_far == (buf_size - sizeof(uint32_t)))
5522 cmd_flags |= MCPR_NVM_COMMAND_LAST;
5523 else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0)
5524 cmd_flags |= MCPR_NVM_COMMAND_LAST;
5525 else if ((offset % NVRAM_PAGE_SIZE) == 0)
5526 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
5528 memcpy(&val, data_buf, 4);
5530 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags);
5532 /* Advance to the next DWORD. */
5533 offset += sizeof(uint32_t);
5534 data_buf += sizeof(uint32_t);
5535 written_so_far += sizeof(uint32_t);
5539 /* Disable access to the NVRAM interface. */
5540 bxe_nvram_disable_access(sc);
5541 bxe_nvram_release_lock(sc);
5543 bxe_nvram_write_exit:
5544 DBEXIT(BXE_VERBOSE_NVRAM);
5550 * This function validates NVRAM content by reading spcific
5551 * regions and validating that the NVRAM checksum matches the
5555 * 0 = Success, !0 = Failure.
5558 bxe_nvram_test(struct bxe_softc *sc)
5560 static const struct {
5564 { 0, 0x14 }, /* bootstrap area*/
5565 { 0x14, 0xec }, /* directory area */
5566 { 0x100, 0x350 }, /* manuf_info */
5567 { 0x450, 0xf0 }, /* feature_info */
5568 { 0x640, 0x64 }, /* upgrade_key_info */
5569 { 0x708, 0x70 }, /* manuf_key_info */
5572 uint32_t magic, csum, buf[0x350 / 4];
5576 DBENTER(BXE_VERBOSE_NVRAM);
5578 data = (uint8_t *) buf;
5580 /* Read the DWORD at offset 0 in NVRAM. */
5581 rc = bxe_nvram_read(sc, 0, data, 4);
5583 BXE_PRINTF("%s(%d): Error (%d) returned reading NVRAM!\n",
5584 __FILE__, __LINE__, rc);
5585 goto bxe_nvram_test_exit;
5588 /* Make sure we found our magic value. */
5589 magic = be32toh(buf[0]);
5590 if (magic != 0x669955aa) {
5591 BXE_PRINTF("%s(%d): Invalid magic value (0x%08x) found!\n",
5592 __FILE__, __LINE__, magic);
5594 goto bxe_nvram_test_exit;
5597 /* Read through each region in NVRAM and validate the checksum. */
5598 for (i = 0; nvram_tbl[i].size; i++) {
5599 DBPRINT(sc, BXE_VERBOSE_NVRAM, "%s(): Testing NVRAM region %d, "
5600 "starting offset = %d, length = %d\n", __FUNCTION__, i,
5601 nvram_tbl[i].offset, nvram_tbl[i].size);
5603 rc = bxe_nvram_read(sc, nvram_tbl[i].offset, data,
5606 BXE_PRINTF("%s(%d): Error (%d) returned reading NVRAM "
5607 "region %d!\n", __FILE__, __LINE__, rc, i);
5608 goto bxe_nvram_test_exit;
5611 csum = ether_crc32_le(data, nvram_tbl[i].size);
5612 if (csum != BXE_CRC32_RESIDUAL) {
5613 BXE_PRINTF("%s(%d): Checksum error (0x%08X) for NVRAM "
5614 "region %d!\n", __FILE__, __LINE__, csum, i);
5616 goto bxe_nvram_test_exit;
5620 bxe_nvram_test_exit:
5621 DBEXIT(BXE_VERBOSE_NVRAM);
5626 * Acknowledge status block and modify interrupt mode.
5631 static __inline void
5632 bxe_ack_sb(struct bxe_softc *sc, uint8_t sb_id, uint8_t storm, uint16_t index,
5633 uint8_t int_mode, uint8_t update)
5635 struct igu_ack_register igu_ack;
5638 hc_addr = (HC_REG_COMMAND_REG + BP_PORT(sc) * 32 + COMMAND_REG_INT_ACK);
5639 igu_ack.status_block_index = index;
5640 igu_ack.sb_id_and_flags =
5641 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
5642 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
5643 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
5644 (int_mode << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
5647 REG_WR(sc, hc_addr, (*(uint32_t *) &igu_ack));
5652 * Update fastpath status block index.
5655 * 0 = Nu completes, 1 = TX completes, 2 = RX completes,
5656 * 3 = RX & TX completes
5658 static __inline uint16_t
5659 bxe_update_fpsb_idx(struct bxe_fastpath *fp)
5661 struct host_status_block *fpsb;
5664 fpsb = fp->status_block;
5669 /* Check for any CSTORM transmit completions. */
5670 if (fp->fp_c_idx != le16toh(fpsb->c_status_block.status_block_index)) {
5671 fp->fp_c_idx = le16toh(fpsb->c_status_block.status_block_index);
5675 /* Check for any USTORM receive completions. */
5676 if (fp->fp_u_idx != le16toh(fpsb->u_status_block.status_block_index)) {
5677 fp->fp_u_idx = le16toh(fpsb->u_status_block.status_block_index);
5685 * Acknowledge interrupt.
5688 * Interrupt value read from IGU.
5691 bxe_ack_int(struct bxe_softc *sc)
5693 uint32_t hc_addr, result;
5695 hc_addr = HC_REG_COMMAND_REG + BP_PORT(sc) * 32 + COMMAND_REG_SIMD_MASK;
5696 result = REG_RD(sc, hc_addr);
5697 DBPRINT(sc, BXE_INSANE_INTR, "%s(): Read 0x%08X from HC addr 0x%08X\n",
5698 __FUNCTION__, result, hc_addr);
5704 * Slowpath event handler.
5706 * Checks that a ramrod completion occurs while the
5707 * controller is in the proper state.
5713 bxe_sp_event(struct bxe_fastpath *fp, union eth_rx_cqe *rr_cqe)
5715 struct bxe_softc *sc;
5719 DBENTER(BXE_VERBOSE_RAMROD);
5721 cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
5722 command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
5723 DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): CID = %d, ramrod command = %d, "
5724 "device state = 0x%08X, fp[%02d].state = 0x%08X, type = %d\n",
5725 __FUNCTION__, cid, command, sc->state, fp->index, fp->state,
5726 rr_cqe->ramrod_cqe.ramrod_type);
5728 /* Free up an entry on the slowpath queue. */
5731 /* Handle ramrod commands that completed on a client connection. */
5733 /* Check for a completion for the current state. */
5734 switch (command | fp->state) {
5735 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP | BXE_FP_STATE_OPENING):
5736 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5737 "%s(): Completed fp[%02d] CLIENT_SETUP Ramrod.\n",
5739 fp->state = BXE_FP_STATE_OPEN;
5741 case (RAMROD_CMD_ID_ETH_HALT | BXE_FP_STATE_HALTING):
5742 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5743 "%s(): Completed fp[%02d] ETH_HALT ramrod\n",
5745 fp->state = BXE_FP_STATE_HALTED;
5748 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5749 "%s(): Unexpected microcode reply (%d) while "
5750 "in state 0x%04X!\n", __FUNCTION__, command,
5754 goto bxe_sp_event_exit;
5757 /* Handle ramrod commands that completed on the leading connection. */
5758 switch (command | sc->state) {
5759 case (RAMROD_CMD_ID_ETH_PORT_SETUP | BXE_STATE_OPENING_WAIT4_PORT):
5760 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5761 "%s(): Completed PORT_SETUP ramrod.\n", __FUNCTION__);
5762 sc->state = BXE_STATE_OPEN;
5764 case (RAMROD_CMD_ID_ETH_HALT | BXE_STATE_CLOSING_WAIT4_HALT):
5765 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5766 "%s(): Completed ETH_HALT ramrod.\n", __FUNCTION__);
5767 sc->state = BXE_STATE_CLOSING_WAIT4_DELETE;
5768 fp->state = BXE_FP_STATE_HALTED;
5770 case (RAMROD_CMD_ID_ETH_CFC_DEL | BXE_STATE_CLOSING_WAIT4_HALT):
5771 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5772 "%s(): Completed fp[%02d] ETH_CFC_DEL ramrod.\n",
5774 sc->fp[cid].state = BXE_FP_STATE_CLOSED;
5776 case (RAMROD_CMD_ID_ETH_SET_MAC | BXE_STATE_OPEN):
5777 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5778 "%s(): Completed ETH_SET_MAC ramrod in STATE_OPEN state.\n",
5781 case (RAMROD_CMD_ID_ETH_SET_MAC | BXE_STATE_CLOSING_WAIT4_HALT):
5782 DBPRINT(sc, BXE_VERBOSE_RAMROD,
5783 "%s(): Completed ETH_SET_MAC ramrod in "
5784 "CLOSING_WAIT4_HALT state.\n", __FUNCTION__);
5787 DBPRINT(sc, BXE_FATAL, "%s(): Unexpected microcode reply (%d)! "
5788 "State is 0x%08X\n", __FUNCTION__, command, sc->state);
5792 /* Force bxe_wait_ramrod() to see the change. */
5794 DBEXIT(BXE_VERBOSE_RAMROD);
5798 * Lock access to a hardware resource using controller arbitration
5802 * 0 = Success, !0 = Failure.
5805 bxe_acquire_hw_lock(struct bxe_softc *sc, uint32_t resource)
5807 uint32_t hw_lock_control_reg, lock_status, resource_bit;
5811 DBENTER(BXE_VERBOSE_MISC);
5812 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Locking resource 0x%08X\n",
5813 __FUNCTION__, resource);
5816 resource_bit = 1 << resource;
5819 hw_lock_control_reg = ((func <= 5) ?
5820 (MISC_REG_DRIVER_CONTROL_1 + func * 8) :
5821 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8));
5823 /* Validating that the resource is within range. */
5824 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5825 DBPRINT(sc, BXE_WARN, "%s(): Resource is out of range! "
5826 "resource(0x%08X) > HW_LOCK_MAX_RESOURCE_VALUE(0x%08X)\n",
5827 __FUNCTION__, resource, HW_LOCK_MAX_RESOURCE_VALUE);
5829 goto bxe_acquire_hw_lock_exit;
5832 /* Validating that the resource is not already taken. */
5833 lock_status = REG_RD(sc, hw_lock_control_reg);
5834 if (lock_status & resource_bit) {
5835 DBPRINT(sc, BXE_WARN, "%s(): Failed to acquire lock! "
5836 "lock_status = 0x%08X, resource_bit = 0x%08X\n",
5837 __FUNCTION__, lock_status, resource_bit);
5839 goto bxe_acquire_hw_lock_exit;
5842 /* Try for 5 seconds every 5ms. */
5843 for (cnt = 0; cnt < 1000; cnt++) {
5844 /* Try to acquire the lock. */
5845 REG_WR(sc, hw_lock_control_reg + 4, resource_bit);
5846 lock_status = REG_RD(sc, hw_lock_control_reg);
5848 if (lock_status & resource_bit)
5849 goto bxe_acquire_hw_lock_exit;
5853 DBPRINT(sc, BXE_WARN, "%s(): Timeout!\n", __FUNCTION__);
5856 bxe_acquire_hw_lock_exit:
5857 DBEXIT(BXE_VERBOSE_MISC);
5862 * Unlock access to a hardware resource using controller arbitration
5866 * 0 = Success, !0 = Failure.
5869 bxe_release_hw_lock(struct bxe_softc *sc, uint32_t resource)
5871 uint32_t hw_lock_control_reg, lock_status, resource_bit;
5875 DBENTER(BXE_VERBOSE_MISC);
5876 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Unlocking resource 0x%08X\n",
5877 __FUNCTION__, resource);
5879 resource_bit = 1 << resource;
5882 /* Validating that the resource is within range */
5883 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
5884 DBPRINT(sc, BXE_WARN, "%s(): Resource is out of range! "
5885 "resource(0x%08X) > HW_LOCK_MAX_RESOURCE_VALUE(0x%08X)\n",
5886 __FUNCTION__, resource, HW_LOCK_MAX_RESOURCE_VALUE);
5888 goto bxe_release_hw_lock_exit;
5891 /* Find the register for the resource lock. */
5892 hw_lock_control_reg = ((func <= 5) ?
5893 (MISC_REG_DRIVER_CONTROL_1 + func * 8) :
5894 (MISC_REG_DRIVER_CONTROL_7 + (func - 6) * 8));
5896 /* Validating that the resource is currently taken */
5897 lock_status = REG_RD(sc, hw_lock_control_reg);
5898 if (!(lock_status & resource_bit)) {
5899 DBPRINT(sc, BXE_WARN, "%s(): The resource is not currently "
5900 "locked! lock_status = 0x%08X, resource_bit = 0x%08X\n",
5901 __FUNCTION__, lock_status, resource_bit);
5903 goto bxe_release_hw_lock_exit;
5906 /* Free the hardware lock. */
5907 REG_WR(sc, hw_lock_control_reg, resource_bit);
5909 bxe_release_hw_lock_exit:
5910 DBEXIT(BXE_VERBOSE_MISC);
5915 bxe_get_gpio(struct bxe_softc *sc, int gpio_num, uint8_t port)
5917 uint32_t gpio_mask, gpio_reg;
5918 int gpio_port, gpio_shift, value;
5920 /* The GPIO should be swapped if swap register is set and active */
5921 gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
5922 NIG_REG_STRAP_OVERRIDE)) ^ port;
5923 gpio_shift = gpio_num +
5924 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
5925 gpio_mask = 1 << gpio_shift;
5927 if (gpio_num > MISC_REGISTERS_GPIO_3) {
5928 DBPRINT(sc, BXE_WARN, "%s(): Invalid GPIO %d\n",
5929 __FUNCTION__, gpio_num);
5933 /* read GPIO value */
5934 gpio_reg = REG_RD(sc, MISC_REG_GPIO);
5936 /* get the requested pin value */
5937 if ((gpio_reg & gpio_mask) == gpio_mask)
5942 DBPRINT(sc, BXE_VERBOSE_PHY, "pin %d value 0x%x\n", gpio_num, value);
5948 * Sets the state of a General Purpose I/O (GPIO).
5954 bxe_set_gpio(struct bxe_softc *sc, int gpio_num, uint32_t mode, uint8_t port)
5956 uint32_t gpio_reg, gpio_mask;
5957 int gpio_port, gpio_shift, rc;
5959 DBENTER(BXE_VERBOSE_MISC);
5961 /* The GPIO should be swapped if swap register is set and active. */
5962 gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
5963 NIG_REG_STRAP_OVERRIDE)) ^ port;
5964 gpio_shift = gpio_num +
5965 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
5966 gpio_mask = (1 << gpio_shift);
5969 if (gpio_num > MISC_REGISTERS_GPIO_3) {
5970 DBPRINT(sc, BXE_FATAL, "%s(): Invalid GPIO (%d)!\n",
5971 __FUNCTION__, gpio_num);
5973 goto bxe_set_gpio_exit;
5976 /* Make sure no one else is trying to use the GPIO. */
5977 rc = bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
5979 DBPRINT(sc, BXE_WARN, "%s(): Can't acquire GPIO lock!\n",
5981 goto bxe_set_gpio_exit;
5984 /* Read GPIO and mask all but the float bits. */
5985 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
5988 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
5989 DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
5990 "output low\n", __FUNCTION__, gpio_num, gpio_shift);
5991 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
5992 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
5994 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
5995 DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
5996 "output high\n", __FUNCTION__, gpio_num, gpio_shift);
5997 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
5998 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
6000 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
6001 DBPRINT(sc, BXE_VERBOSE, "%s(): Set GPIO %d (shift %d) -> "
6002 "input\n", __FUNCTION__, gpio_num, gpio_shift);
6003 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
6006 DBPRINT(sc, BXE_FATAL, "%s(): Unknown GPIO mode (0x%08X)!\n",
6007 __FUNCTION__, mode);
6011 REG_WR(sc, MISC_REG_GPIO, gpio_reg);
6012 rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
6014 DBPRINT(sc, BXE_WARN, "%s(): Can't release GPIO lock!\n",
6019 DBEXIT(BXE_VERBOSE_MISC);
6024 bxe_set_gpio_int(struct bxe_softc *sc, int gpio_num, uint32_t mode,
6027 uint32_t gpio_mask, gpio_reg;
6028 int gpio_port, gpio_shift;
6030 /* The GPIO should be swapped if swap register is set and active */
6031 gpio_port = (REG_RD(sc, NIG_REG_PORT_SWAP) && REG_RD(sc,
6032 NIG_REG_STRAP_OVERRIDE)) ^ port;
6033 gpio_shift = gpio_num +
6034 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
6035 gpio_mask = (1 << gpio_shift);
6036 if (gpio_num > MISC_REGISTERS_GPIO_3) {
6037 DBPRINT(sc, BXE_WARN, "%s(): Invalid GPIO %d\n",
6038 __FUNCTION__, gpio_num);
6042 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
6044 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT);
6047 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
6048 DBPRINT(sc, BXE_VERBOSE_PHY, "Clear GPIO INT %d (shift %d) -> "
6049 "output low\n", gpio_num, gpio_shift);
6050 /* clear SET and set CLR */
6051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
6052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
6054 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
6055 DBPRINT(sc, BXE_VERBOSE_PHY, "Set GPIO INT %d (shift %d) -> "
6056 "output high\n", gpio_num, gpio_shift);
6057 /* clear CLR and set SET */
6058 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
6059 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
6065 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg);
6066 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO);
6072 * Sets the state of a Shared Purpose I/O (SPIO).
6075 * 0 = Success, !0 = Failure.
6078 bxe_set_spio(struct bxe_softc *sc, int spio_num, uint32_t mode)
6080 uint32_t spio_reg, spio_mask;
6084 spio_mask = 1 << spio_num;
6086 /* Validate the SPIO. */
6087 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
6088 (spio_num > MISC_REGISTERS_SPIO_7)) {
6089 DBPRINT(sc, BXE_WARN, "%s(): Invalid SPIO (%d)!\n",
6090 __FUNCTION__, spio_num);
6092 goto bxe_set_spio_exit;
6095 rc = bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
6097 DBPRINT(sc, BXE_WARN, "%s(): Can't acquire SPIO lock!\n",
6099 goto bxe_set_spio_exit;
6102 /* Read SPIO and mask all but the float bits. */
6103 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
6106 case MISC_REGISTERS_SPIO_OUTPUT_LOW :
6107 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Set SPIO %d -> "
6108 "output low\n", __FUNCTION__, spio_num);
6109 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
6110 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
6112 case MISC_REGISTERS_SPIO_OUTPUT_HIGH :
6113 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Set SPIO %d -> "
6114 "output high\n", __FUNCTION__, spio_num);
6115 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
6116 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
6118 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
6119 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Set SPIO %d -> "
6120 "input\n", __FUNCTION__, spio_num);
6121 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
6124 DBPRINT(sc, BXE_WARN, "%s(): Unknown SPIO mode (0x%08X)!\n",
6125 __FUNCTION__, mode);
6129 REG_WR(sc, MISC_REG_SPIO, spio_reg);
6130 rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO);
6132 DBPRINT(sc, BXE_WARN, "%s(): Can't release SPIO lock!\n",
6141 * When the 57711E is operating in multi-function mode, the controller
6142 * must be configured to arbitrate TX between multiple VNICs.
6148 bxe_init_port_minmax(struct bxe_softc *sc)
6150 uint32_t fair_periodic_timeout_usec, r_param, t_fair;
6152 DBENTER(BXE_VERBOSE_MISC);
6154 r_param = sc->link_vars.line_speed / 8;
6156 memset(&(sc->cmng.rs_vars), 0,
6157 sizeof(struct rate_shaping_vars_per_port));
6158 memset(&(sc->cmng.fair_vars), 0, sizeof(struct fairness_vars_per_port));
6160 /* 100 usec in SDM ticks = 25 since each tick is 4 usec. */
6161 sc->cmng.rs_vars.rs_periodic_timeout = RS_PERIODIC_TIMEOUT_USEC / 4;
6163 * This is the threshold below which no timer arming will occur.
6164 * We use a coefficient of 1, 25 so that the threshold is a
6165 * little bigger that real time to compensate for timer
6168 sc->cmng.rs_vars.rs_threshold = (RS_PERIODIC_TIMEOUT_USEC *
6170 /* Resolution of fairness timer. */
6171 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param;
6173 /* For 10G it is 1000us, for 1G it is 10000us. */
6174 t_fair = T_FAIR_COEF / sc->link_vars.line_speed;
6175 /* This is the threshold where we won't arm the timer
6177 sc->cmng.fair_vars.fair_threshold = QM_ARB_BYTES;
6179 * Multiply by 1e3/8 to get bytes/msec. We don't want the
6180 * credits to pass a credit of the T_FAIR*FAIR_MEM (algorithm
6183 sc->cmng.fair_vars.upper_bound = r_param * t_fair * FAIR_MEM;
6184 /* Since each tick is 4 us. */
6185 sc->cmng.fair_vars.fairness_timeout = fair_periodic_timeout_usec / 4;
6187 DBEXIT(BXE_VERBOSE_MISC);
6192 * This function is called when a link interrupt is generated
6193 * and configures the controller for the new link state.
6199 bxe_link_attn(struct bxe_softc *sc)
6201 struct host_port_stats *pstats;
6202 uint32_t pause_enabled;
6203 int func, i, port, vn;
6205 DBENTER(BXE_VERBOSE_PHY);
6207 /* Make sure that we are synced with the current statistics. */
6208 bxe_stats_handle(sc, STATS_EVENT_STOP);
6210 bxe_link_update(&sc->link_params, &sc->link_vars);
6212 if (sc->link_vars.link_up) {
6213 if (CHIP_IS_E1H(sc)) {
6217 if (sc->link_vars.flow_ctrl & FLOW_CTRL_TX)
6220 REG_WR(sc, BAR_USTORM_INTMEM +
6221 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
6225 if (sc->link_vars.mac_type == MAC_TYPE_BMAC) {
6226 pstats = BXE_SP(sc, port_stats);
6227 /* Reset old BMAC statistics. */
6228 memset(&(pstats->mac_stx[0]), 0,
6229 sizeof(struct mac_stx));
6232 if ((sc->state == BXE_STATE_OPEN) ||
6233 (sc->state == BXE_STATE_DISABLED))
6234 bxe_stats_handle(sc, STATS_EVENT_LINK_UP);
6237 /* Need additional handling for multi-function devices. */
6240 if (sc->link_vars.link_up) {
6241 if (sc->dcc_enable == TRUE) {
6242 bxe_congestionmgmt(sc, TRUE);
6243 /* Store in internal memory. */
6245 sizeof(struct cmng_struct_per_port) / 4;
6247 REG_WR(sc, BAR_XSTORM_INTMEM +
6248 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + (i*4),
6249 ((uint32_t *)(&sc->cmng))[i]);
6253 for (vn = VN_0; vn < E1HVN_MAX; vn++) {
6254 /* Don't send an attention to ourselves. */
6255 if (vn == BP_E1HVN(sc))
6257 func = ((vn << 1) | port);
6259 * Send an attention to other drivers on the same port.
6261 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_0 +
6262 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func) * 4, 1);
6266 DBEXIT(BXE_VERBOSE_PHY);
6270 * Sets the driver instance as the port management function (PMF).
6272 * This is only used on "multi-function" capable devices such as the
6273 * 57711E and initializes the controller so that the PMF driver instance
6274 * can interact with other driver instances that may be operating on
6275 * the same Ethernet port.
6281 bxe_pmf_update(struct bxe_softc *sc)
6286 /* Record that this driver instance is managing the port. */
6288 DBPRINT(sc, BXE_INFO, "%s(): Enabling this port as PMF.\n",
6291 /* Enable NIG attention. */
6293 val = (0xff0f | (1 << (BP_E1HVN(sc) + 4)));
6294 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, val);
6295 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, val);
6297 bxe_stats_handle(sc, STATS_EVENT_PMF);
6300 /* 8073 Download definitions */
6301 /* spi Parameters.*/
6302 #define SPI_CTRL_1_L 0xC000
6303 #define SPI_CTRL_1_H 0xC002
6304 #define SPI_CTRL_2_L 0xC400
6305 #define SPI_CTRL_2_H 0xC402
6306 #define SPI_TXFIFO 0xD000
6307 #define SPI_RXFIFO 0xD400
6309 /* Input Command Messages.*/
6311 * Write CPU/SPI Control Regs, followed by Count And CPU/SPI Controller
6312 * Reg add/data pairs.
6314 #define WR_CPU_CTRL_REGS 0x11
6316 * Read CPU/SPI Control Regs, followed by Count and CPU/SPI Controller
6319 #define RD_CPU_CTRL_REGS 0xEE
6321 * Write CPU/SPI Control Regs Continously, followed by Count and
6322 * CPU/SPI Controller Reg addr and data's.
6324 #define WR_CPU_CTRL_FIFO 0x66
6325 /* Output Command Messages.*/
6328 /* SPI Controller Commands (known As messages).*/
6329 #define MSGTYPE_HWR 0x40
6330 #define MSGTYPE_HRD 0x80
6331 #define WRSR_OPCODE 0x01
6332 #define WR_OPCODE 0x02
6333 #define RD_OPCODE 0x03
6334 #define WRDI_OPCODE 0x04
6335 #define RDSR_OPCODE 0x05
6336 #define WREN_OPCODE 0x06
6337 #define WR_BLOCK_SIZE 0x40 /* Maximum 64 Bytes Writes.*/
6340 * Post a slowpath command.
6342 * A slowpath command is used to propogate a configuration change through
6343 * the controller in a controlled manner, allowing each STORM processor and
6344 * other H/W blocks to phase in the change. The commands sent on the
6345 * slowpath are referred to as ramrods. Depending on the ramrod used the
6346 * completion of the ramrod will occur in different ways. Here's a
6347 * breakdown of ramrods and how they complete:
6349 * RAMROD_CMD_ID_ETH_PORT_SETUP
6350 * Used to setup the leading connection on a port. Completes on the
6351 * Receive Completion Queue (RCQ) of that port (typically fp[0]).
6353 * RAMROD_CMD_ID_ETH_CLIENT_SETUP
6354 * Used to setup an additional connection on a port. Completes on the
6355 * RCQ of the multi-queue/RSS connection being initialized.
6357 * RAMROD_CMD_ID_ETH_STAT_QUERY
6358 * Used to force the storm processors to update the statistics database
6359 * in host memory. This ramrod is send on the leading connection CID and
6360 * completes as an index increment of the CSTORM on the default status
6363 * RAMROD_CMD_ID_ETH_UPDATE
6364 * Used to update the state of the leading connection, usually to udpate
6365 * the RSS indirection table. Completes on the RCQ of the leading
6366 * connection. (Not currently used under FreeBSD until OS support becomes
6369 * RAMROD_CMD_ID_ETH_HALT
6370 * Used when tearing down a connection prior to driver unload. Completes
6371 * on the RCQ of the multi-queue/RSS connection being torn down. Don't
6372 * use this on the leading connection.
6374 * RAMROD_CMD_ID_ETH_SET_MAC
6375 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on
6376 * the RCQ of the leading connection.
6378 * RAMROD_CMD_ID_ETH_CFC_DEL
6379 * Used when tearing down a conneciton prior to driver unload. Completes
6380 * on the RCQ of the leading connection (since the current connection
6381 * has been completely removed from controller memory).
6383 * RAMROD_CMD_ID_ETH_PORT_DEL
6384 * Used to tear down the leading connection prior to driver unload,
6385 * typically fp[0]. Completes as an index increment of the CSTORM on the
6386 * default status block.
6388 * RAMROD_CMD_ID_ETH_FORWARD_SETUP
6389 * Used for connection offload. Completes on the RCQ of the multi-queue
6390 * RSS connection that is being offloaded. (Not currently used under
6393 * There can only be one command pending per function.
6396 * 0 = Success, !0 = Failure.
6399 bxe_sp_post(struct bxe_softc *sc, int command, int cid, uint32_t data_hi,
6400 uint32_t data_lo, int common)
6404 DBRUNMSG((BXE_EXTREME_LOAD | BXE_EXTREME_RESET |
6405 BXE_EXTREME_UNLOAD | BXE_EXTREME_RAMROD),
6406 bxe_decode_ramrod_cmd(sc, command));
6408 DBPRINT(sc, BXE_VERBOSE_RAMROD, "%s(): cid = %d, data_hi = 0x%08X, "
6409 "data_low = 0x%08X, remaining spq entries = %d\n", __FUNCTION__,
6410 cid, data_hi, data_lo, sc->spq_left);
6413 /* Skip all slowpath commands if the driver has panic'd. */
6416 goto bxe_sp_post_exit;
6421 /* We are limited to 8 slowpath commands. */
6422 if (!sc->spq_left) {
6423 BXE_PRINTF("%s(%d): Slowpath queue is full!\n",
6424 __FILE__, __LINE__);
6427 goto bxe_sp_post_exit;
6430 /* Encode the CID with the command. */
6431 sc->spq_prod_bd->hdr.conn_and_cmd_data =
6432 htole32(((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid)));
6433 sc->spq_prod_bd->hdr.type = htole16(ETH_CONNECTION_TYPE);
6436 sc->spq_prod_bd->hdr.type |=
6437 htole16((1 << SPE_HDR_COMMON_RAMROD_SHIFT));
6439 /* Point the hardware at the new configuration data. */
6440 sc->spq_prod_bd->data.mac_config_addr.hi = htole32(data_hi);
6441 sc->spq_prod_bd->data.mac_config_addr.lo = htole32(data_lo);
6443 /* Reduce the number of available slots for slowpath commands. */
6446 /* Manage the end of the ring. */
6447 if (sc->spq_prod_bd == sc->spq_last_bd) {
6448 sc->spq_prod_bd = sc->spq;
6449 sc->spq_prod_idx = 0;
6450 DBPRINT(sc, BXE_VERBOSE, "%s(): End of slowpath queue.\n",
6458 /* Kick off the slowpath command. */
6459 REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
6469 * Acquire the MCP access lock.
6472 * 0 = Success, !0 = Failure.
6475 bxe_acquire_alr(struct bxe_softc *sc)
6480 DBENTER(BXE_VERBOSE_MISC);
6484 /* Acquire lock using mcpr_access_lock SPLIT register. */
6485 for (i = 0; i < retries * 10; i++) {
6487 REG_WR(sc, GRCBASE_MCP + 0x9c, val);
6488 val = REG_RD(sc, GRCBASE_MCP + 0x9c);
6490 if (val & (1L << 31))
6496 if (!(val & (1L << 31))) {
6497 DBPRINT(sc, BXE_WARN,
6498 "%s(): Cannot acquire MCP split access lock.\n",
6503 DBEXIT(BXE_VERBOSE_MISC);
6509 * Release the MCP access lock.
6515 bxe_release_alr(struct bxe_softc* sc)
6518 DBENTER(BXE_VERBOSE_MISC);
6520 REG_WR(sc, GRCBASE_MCP + 0x9c, 0);
6522 DBEXIT(BXE_VERBOSE_MISC);
6526 * Update driver's copies of the values in the host default status block.
6529 * Bitmap indicating changes to the block.
6531 static __inline uint16_t
6532 bxe_update_dsb_idx(struct bxe_softc *sc)
6534 struct host_def_status_block *dsb;
6539 /* Read memory barrier since block is written by hardware. */
6542 if (sc->def_att_idx !=
6543 le16toh(dsb->atten_status_block.attn_bits_index)) {
6545 le16toh(dsb->atten_status_block.attn_bits_index);
6549 if (sc->def_c_idx !=
6550 le16toh(dsb->c_def_status_block.status_block_index)) {
6552 le16toh(dsb->c_def_status_block.status_block_index);
6556 if (sc->def_u_idx !=
6557 le16toh(dsb->u_def_status_block.status_block_index)) {
6559 le16toh(dsb->u_def_status_block.status_block_index);
6563 if (sc->def_x_idx !=
6564 le16toh(dsb->x_def_status_block.status_block_index)) {
6566 le16toh(dsb->x_def_status_block.status_block_index);
6570 if (sc->def_t_idx !=
6571 le16toh(dsb->t_def_status_block.status_block_index)) {
6573 le16toh(dsb->t_def_status_block.status_block_index);
6581 * Handle any attentions that have been newly asserted.
6587 bxe_attn_int_asserted(struct bxe_softc *sc, uint32_t asserted)
6589 uint32_t aeu_addr, hc_addr, nig_int_mask_addr;
6590 uint32_t aeu_mask, nig_mask;
6593 DBENTER(BXE_VERBOSE_INTR);
6596 hc_addr = (HC_REG_COMMAND_REG + port * 32 + COMMAND_REG_ATTN_BITS_SET);
6597 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
6598 MISC_REG_AEU_MASK_ATTN_FUNC_0;
6599 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
6600 NIG_REG_MASK_INTERRUPT_PORT0;
6603 if (sc->attn_state & asserted)
6604 BXE_PRINTF("%s(%d): IGU attention ERROR!\n",
6605 __FILE__, __LINE__);
6607 rc = bxe_acquire_hw_lock(sc,
6608 HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
6610 DBPRINT(sc, BXE_WARN,
6611 "%s(): Failed to acquire attention lock for port %d!\n",
6612 __FUNCTION__, port);
6613 goto bxe_attn_int_asserted_exit;
6616 aeu_mask = REG_RD(sc, aeu_addr);
6617 DBPRINT(sc, BXE_VERBOSE_INTR,
6618 "%s(): aeu_mask = 0x%08X, newly asserted = 0x%08X\n", __FUNCTION__,
6619 aeu_mask, asserted);
6621 aeu_mask &= ~(asserted & 0xff);
6622 DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): new mask = 0x%08X\n", __FUNCTION__,
6624 REG_WR(sc, aeu_addr, aeu_mask);
6626 rc = bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
6628 DBPRINT(sc, BXE_WARN,
6629 "%s(): Failed to release attention lock!\n", __FUNCTION__);
6630 goto bxe_attn_int_asserted_exit;
6633 DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): attn_state = 0x%08X\n",
6634 __FUNCTION__, sc->attn_state);
6636 sc->attn_state |= asserted;
6637 DBPRINT(sc, BXE_VERBOSE_INTR, "%s(): new attn_state = 0x%08X\n",
6638 __FUNCTION__, sc->attn_state);
6640 if (asserted & ATTN_HARD_WIRED_MASK) {
6641 if (asserted & ATTN_NIG_FOR_FUNC) {
6642 bxe_acquire_phy_lock(sc);
6644 /* Save NIG interrupt mask. */
6645 nig_mask = REG_RD(sc, nig_int_mask_addr);
6646 REG_WR(sc, nig_int_mask_addr, 0);
6651 if (asserted & ATTN_SW_TIMER_4_FUNC)
6652 DBPRINT(sc, BXE_WARN, "%s(): ATTN_SW_TIMER_4_FUNC!\n",
6655 if (asserted & GPIO_2_FUNC)
6656 DBPRINT(sc, BXE_WARN, "%s(): GPIO_2_FUNC!\n",
6659 if (asserted & GPIO_3_FUNC)
6660 DBPRINT(sc, BXE_WARN, "%s(): GPIO_3_FUNC!\n",
6663 if (asserted & GPIO_4_FUNC)
6664 DBPRINT(sc, BXE_WARN, "%s(): GPIO_4_FUNC!\n",
6668 if (asserted & ATTN_GENERAL_ATTN_1) {
6669 DBPRINT(sc, BXE_WARN,
6670 "%s(): ATTN_GENERAL_ATTN_1!\n",
6672 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
6675 if (asserted & ATTN_GENERAL_ATTN_2) {
6676 DBPRINT(sc, BXE_WARN,
6677 "%s(): ATTN_GENERAL_ATTN_2!\n",
6679 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
6682 if (asserted & ATTN_GENERAL_ATTN_3) {
6683 DBPRINT(sc, BXE_WARN,
6684 "%s(): ATTN_GENERAL_ATTN_3!\n",
6686 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
6689 if (asserted & ATTN_GENERAL_ATTN_4) {
6690 DBPRINT(sc, BXE_WARN,
6691 "%s(): ATTN_GENERAL_ATTN_4!\n",
6693 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
6696 if (asserted & ATTN_GENERAL_ATTN_5) {
6697 DBPRINT(sc, BXE_WARN,
6698 "%s(): ATTN_GENERAL_ATTN_5!\n",
6700 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
6702 if (asserted & ATTN_GENERAL_ATTN_6) {
6703 DBPRINT(sc, BXE_WARN,
6704 "%s(): ATTN_GENERAL_ATTN_6!\n",
6706 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
6711 DBPRINT(sc, BXE_VERBOSE_INTR,
6712 "%s(): Writing 0x%08X to HC addr 0x%08X\n", __FUNCTION__,
6714 REG_WR(sc, hc_addr, asserted);
6716 /* Now set back the NIG mask. */
6717 if (asserted & ATTN_NIG_FOR_FUNC) {
6718 REG_WR(sc, nig_int_mask_addr, nig_mask);
6719 bxe_release_phy_lock(sc);
6722 bxe_attn_int_asserted_exit:
6723 DBEXIT(BXE_VERBOSE_INTR);
6727 * Handle any attentions that have been newly deasserted.
6732 static __inline void
6733 bxe_attn_int_deasserted0(struct bxe_softc *sc, uint32_t attn)
6735 uint32_t val, swap_val, swap_override;
6736 int port, reg_offset;
6738 DBENTER(BXE_VERBOSE_INTR);
6741 reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6742 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
6744 /* Handle SPIO5 attention. */
6745 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
6746 val = REG_RD(sc, reg_offset);
6747 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
6748 REG_WR(sc, reg_offset, val);
6750 DBPRINT(sc, BXE_FATAL, "%s(): SPIO5 H/W attention!\n",
6752 /* Fan failure attention */
6753 switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
6754 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
6756 * SPIO5 is used on A1022G boards to indicate
6757 * fan failure. Shutdown the controller and
6758 * associated PHY to avoid damage.
6761 /* Low power mode is controled by GPIO 2. */
6762 bxe_set_gpio(sc, MISC_REGISTERS_GPIO_2,
6763 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6764 /* PHY reset is controled by GPIO 1. */
6765 bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
6766 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6768 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
6769 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
6771 * The PHY reset is controlled by GPIO 1.
6772 * Fake the port number to cancel the swap done in
6775 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
6776 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
6777 port = (swap_val && swap_override) ^ 1;
6778 bxe_set_gpio(sc, MISC_REGISTERS_GPIO_1,
6779 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
6785 /* Mark the failure. */
6786 sc->link_params.ext_phy_config &=
6787 ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
6788 sc->link_params.ext_phy_config |=
6789 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
6790 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config,
6791 sc->link_params.ext_phy_config);
6792 /* Log the failure */
6793 BXE_PRINTF("A fan failure has caused the driver to "
6794 "shutdown the device to prevent permanent damage.\n");
6797 if (attn & (AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 |
6798 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1)) {
6799 bxe_acquire_phy_lock(sc);
6800 bxe_handle_module_detect_int(&sc->link_params);
6801 bxe_release_phy_lock(sc);
6804 /* Checking for an assert on the zero block */
6805 if (attn & HW_INTERRUT_ASSERT_SET_0) {
6806 val = REG_RD(sc, reg_offset);
6807 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
6808 REG_WR(sc, reg_offset, val);
6810 BXE_PRINTF("%s(%d): FATAL hardware block attention "
6811 "(set0 = 0x%08X)!\n", __FILE__, __LINE__,
6812 (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_0));
6817 DBEXIT(BXE_VERBOSE_INTR);
6821 * Handle any attentions that have been newly deasserted.
6826 static __inline void
6827 bxe_attn_int_deasserted1(struct bxe_softc *sc, uint32_t attn)
6830 int port, reg_offset;
6832 DBENTER(BXE_VERBOSE_INTR);
6834 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
6835 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR);
6837 DBPRINT(sc, BXE_FATAL,
6838 "%s(): Doorbell hardware attention (0x%08X).\n",
6841 /* DORQ discard attention */
6843 DBPRINT(sc, BXE_FATAL,
6844 "%s(): FATAL doorbell queue error!\n",
6848 if (attn & HW_INTERRUT_ASSERT_SET_1) {
6850 reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
6851 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1;
6853 val = REG_RD(sc, reg_offset);
6854 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
6855 REG_WR(sc, reg_offset, val);
6857 BXE_PRINTF("%s(%d): FATAL hardware block attention "
6858 "(set1 = 0x%08X)!\n", __FILE__, __LINE__,
6859 (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_1));
6864 DBEXIT(BXE_VERBOSE_INTR);
6868 * Handle any attentions that have been newly deasserted.
6873 static __inline void
6874 bxe_attn_int_deasserted2(struct bxe_softc *sc, uint32_t attn)
6877 int port, reg_offset;
6879 DBENTER(BXE_VERBOSE_INTR);
6881 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
6882 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR);
6884 DBPRINT(sc, BXE_FATAL,
6885 "%s(): CFC hardware attention (0x%08X).\n", __FUNCTION__,
6888 /* CFC error attention. */
6890 DBPRINT(sc, BXE_FATAL, "%s(): FATAL CFC error!\n",
6894 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
6895 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0);
6897 DBPRINT(sc, BXE_FATAL,
6898 "%s(): PXP hardware attention (0x%08X).\n", __FUNCTION__,
6901 /* RQ_USDMDP_FIFO_OVERFLOW */
6903 DBPRINT(sc, BXE_FATAL, "%s(): FATAL PXP error!\n",
6907 if (attn & HW_INTERRUT_ASSERT_SET_2) {
6909 reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
6910 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2;
6912 val = REG_RD(sc, reg_offset);
6913 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
6914 REG_WR(sc, reg_offset, val);
6916 BXE_PRINTF("%s(%d): FATAL hardware block attention (set2 = "
6917 "0x%08X)! port=%d, val written=0x%x attn=0x%x\n", __FILE__,
6918 __LINE__, (attn & (uint32_t)HW_INTERRUT_ASSERT_SET_2),
6924 DBEXIT(BXE_VERBOSE_INTR);
6928 * Handle any attentions that have been newly deasserted.
6933 static __inline void
6934 bxe_attn_int_deasserted3(struct bxe_softc *sc, uint32_t attn)
6939 DBENTER(BXE_VERBOSE_INTR);
6941 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
6942 /* Look for any port assertions. */
6943 if (attn & BXE_PMF_LINK_ASSERT) {
6945 * We received a message from the driver instance
6946 * that is managing the Ethernet port (link up/down).
6947 * Go ahead and handle it.
6951 DBPRINT(sc, BXE_INFO,
6952 "%s(): Received link attention from PMF.\n",
6955 /* Clear the attention. */
6956 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
6957 sc->mf_config[BP_E1HVN(sc)] =
6959 mf_cfg.func_mf_config[(sc->bxe_func & 1)].config);
6960 val = SHMEM_RD(sc, func_mb[func].drv_status);
6961 if (sc->dcc_enable == TRUE) {
6962 if (val & DRV_STATUS_DCC_EVENT_MASK)
6964 val & DRV_STATUS_DCC_EVENT_MASK);
6966 bxe__link_status_update(sc);
6968 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF))
6970 /* Look for any microcode assertions. */
6971 } else if (attn & BXE_MC_ASSERT_BITS) {
6972 DBPRINT(sc, BXE_FATAL, "%s(): Microcode assert!\n",
6975 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0);
6976 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0);
6977 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0);
6978 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0);
6982 /* Look for any bootcode assertions. */
6983 } else if (attn & BXE_MCP_ASSERT) {
6984 DBPRINT(sc, BXE_FATAL, "%s(): Bootcode assert!\n",
6987 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0);
6989 DBRUN(bxe_dump_fw(sc));
6991 DBPRINT(sc, BXE_FATAL,
6992 "%s(): Unknown hardware assertion "
6993 "(attn = 0x%08X)!\n", __FUNCTION__, attn);
6996 /* Look for any hardware latched attentions. */
6997 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
6998 DBPRINT(sc, BXE_FATAL,
6999 "%s(): Latched attention 0x%08X (masked)!\n", __FUNCTION__,
7002 /* Check if a GRC register access timeout occurred. */
7003 if (attn & BXE_GRC_TIMEOUT) {
7004 val = CHIP_IS_E1H(sc) ? REG_RD(sc,
7005 MISC_REG_GRC_TIMEOUT_ATTN) : 0;
7007 DBPRINT(sc, BXE_WARN,
7008 "%s(): GRC timeout for register 0x%08X!\n",
7012 /* Check if a GRC reserved register was accessed. */
7013 if (attn & BXE_GRC_RSV) {
7014 val = CHIP_IS_E1H(sc) ? REG_RD(sc,
7015 MISC_REG_GRC_RSV_ATTN) : 0;
7017 DBPRINT(sc, BXE_WARN,
7018 "%s(): GRC register 0x%08X is reserved!\n",
7022 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
7025 DBEXIT(BXE_VERBOSE_INTR);
7029 * Handle any attentions that have been newly deasserted.
7035 bxe_attn_int_deasserted(struct bxe_softc *sc, uint32_t deasserted)
7037 struct attn_route attn;
7038 struct attn_route group_mask;
7039 uint32_t val, reg_addr, aeu_mask;
7042 DBENTER(BXE_VERBOSE_INTR);
7045 * Need to take HW lock because MCP or other port might also try
7046 * to handle this event.
7048 bxe_acquire_alr(sc);
7051 /* Get the current attention signal bits. */
7052 attn.sig[0] = REG_RD(sc,
7053 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port * 4);
7054 attn.sig[1] = REG_RD(sc,
7055 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port * 4);
7056 attn.sig[2] = REG_RD(sc,
7057 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port * 4);
7058 attn.sig[3] = REG_RD(sc,
7059 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port * 4);
7061 DBPRINT(sc, BXE_EXTREME_INTR,
7062 "%s(): attention = 0x%08X 0x%08X 0x%08X 0x%08X\n", __FUNCTION__,
7063 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3]);
7066 * Compare the current attention bits to each attention group
7067 * to see if anyone has registered this attention.
7069 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
7070 if (deasserted & (1 << index)) {
7071 group_mask = sc->attn_group[index];
7073 DBPRINT(sc, BXE_EXTREME_INTR,
7074 "%s(): group[%02d] = 0x%08X 0x%08X 0x%08x 0X%08x\n",
7075 __FUNCTION__, index, group_mask.sig[0],
7076 group_mask.sig[1], group_mask.sig[2],
7079 /* Handle any registered attentions. */
7080 bxe_attn_int_deasserted3(sc,
7081 attn.sig[3] & group_mask.sig[3]);
7082 bxe_attn_int_deasserted1(sc,
7083 attn.sig[1] & group_mask.sig[1]);
7084 bxe_attn_int_deasserted2(sc,
7085 attn.sig[2] & group_mask.sig[2]);
7086 bxe_attn_int_deasserted0(sc,
7087 attn.sig[0] & group_mask.sig[0]);
7089 if ((attn.sig[0] & group_mask.sig[0] &
7090 HW_PRTY_ASSERT_SET_0) ||
7091 (attn.sig[1] & group_mask.sig[1] &
7092 HW_PRTY_ASSERT_SET_1) ||
7093 (attn.sig[2] & group_mask.sig[2] &
7094 HW_PRTY_ASSERT_SET_2))
7095 BXE_PRINTF("%s(%d): FATAL hardware block "
7096 "parity attention!\n", __FILE__, __LINE__);
7100 bxe_release_alr(sc);
7102 reg_addr = (HC_REG_COMMAND_REG +
7103 port * 32 + COMMAND_REG_ATTN_BITS_CLR);
7106 DBPRINT(sc, BXE_EXTREME_INTR,
7107 "%s(): About to mask 0x%08X at HC addr 0x%08X\n", __FUNCTION__,
7108 deasserted, reg_addr);
7109 REG_WR(sc, reg_addr, val);
7111 if (~sc->attn_state & deasserted)
7112 DBPRINT(sc, BXE_FATAL, "%s(): IGU Bug!\n", __FUNCTION__);
7114 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
7115 MISC_REG_AEU_MASK_ATTN_FUNC_0;
7117 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7118 aeu_mask = REG_RD(sc, reg_addr);
7120 DBPRINT(sc, BXE_EXTREME_INTR,
7121 "%s(): Current aeu_mask = 0x%08X, newly deasserted = 0x%08X\n",
7122 __FUNCTION__, aeu_mask, deasserted);
7123 aeu_mask |= (deasserted & 0xff);
7125 DBPRINT(sc, BXE_EXTREME_INTR, "%s(): New aeu_mask = 0x%08X\n",
7126 __FUNCTION__, aeu_mask);
7128 REG_WR(sc, reg_addr, aeu_mask);
7129 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
7131 DBPRINT(sc, BXE_EXTREME_INTR, "%s(): Current attn_state = 0x%08X\n",
7132 __FUNCTION__, sc->attn_state);
7134 sc->attn_state &= ~deasserted;
7135 DBPRINT(sc, BXE_EXTREME_INTR, "%s(): New attn_state = 0x%08X\n",
7136 __FUNCTION__, sc->attn_state);
7138 DBEXIT(BXE_VERBOSE_INTR);
7142 * Handle interrupts caused by internal attentions (everything else other
7143 * than RX, TX, and link state changes).
7149 bxe_attn_int(struct bxe_softc* sc)
7151 uint32_t attn_ack, attn_bits, attn_state;
7152 uint32_t asserted, deasserted;
7154 DBENTER(BXE_VERBOSE_INTR);
7156 attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits);
7158 le32toh(sc->def_sb->atten_status_block.attn_bits_ack);
7159 attn_state = sc->attn_state;
7160 asserted = attn_bits & ~attn_ack & ~attn_state;
7161 deasserted = ~attn_bits & attn_ack & attn_state;
7163 /* Make sure we're in a sane state. */
7164 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
7165 BXE_PRINTF("%s(%d): Bad attention state!\n",
7166 __FILE__, __LINE__);
7168 /* Handle any attentions that are newly asserted. */
7170 DBPRINT(sc, BXE_VERBOSE_INTR,
7171 "%s(): attn_state = 0x%08X, attn_bits = 0x%08X, "
7172 "attn_ack = 0x%08X, asserted = 0x%08X\n", __FUNCTION__,
7173 attn_state, attn_bits, attn_ack, asserted);
7174 bxe_attn_int_asserted(sc, asserted);
7177 /* Handle any attentions that are newly deasserted. */
7179 DBPRINT(sc, BXE_VERBOSE_INTR,
7180 "%s(): attn_state = 0x%08X, attn_bits = 0x%08X, "
7181 "attn_ack = 0x%08X, deasserted = 0x%08X\n", __FUNCTION__,
7182 attn_state, attn_bits, attn_ack, deasserted);
7183 bxe_attn_int_deasserted(sc, deasserted);
7186 DBEXIT(BXE_VERBOSE_INTR);
7189 /* sum[hi:lo] += add[hi:lo] */
7190 #define ADD_64(s_hi, a_hi, s_lo, a_lo) do { \
7192 s_hi += a_hi + ((s_lo < a_lo) ? 1 : 0); \
7195 /* Subtraction = minuend -= subtrahend */
7196 #define SUB_64(m_hi, s_hi, m_lo, s_lo) \
7198 DIFF_64(m_hi, m_hi, s_hi, m_lo, m_lo, s_lo); \
7202 /* difference = minuend - subtrahend */
7203 #define DIFF_64(d_hi, m_hi, s_hi, d_lo, m_lo, s_lo) do { \
7204 if (m_lo < s_lo) { \
7206 d_hi = m_hi - s_hi; \
7208 /* we can 'loan' 1 */ \
7210 d_lo = m_lo + (UINT_MAX - s_lo) + 1; \
7212 /* m_hi <= s_hi */ \
7217 /* m_lo >= s_lo */ \
7218 if (m_hi < s_hi) { \
7222 /* m_hi >= s_hi */ \
7223 d_hi = m_hi - s_hi; \
7224 d_lo = m_lo - s_lo; \
7229 #define UPDATE_STAT64(s, t) do { \
7230 DIFF_64(diff.hi, new->s##_hi, pstats->mac_stx[0].t##_hi,\
7231 diff.lo, new->s##_lo, pstats->mac_stx[0].t##_lo); \
7232 pstats->mac_stx[0].t##_hi = new->s##_hi; \
7233 pstats->mac_stx[0].t##_lo = new->s##_lo; \
7234 ADD_64(pstats->mac_stx[1].t##_hi, diff.hi, \
7235 pstats->mac_stx[1].t##_lo, diff.lo); \
7238 #define UPDATE_STAT64_NIG(s, t) do { \
7239 DIFF_64(diff.hi, new->s##_hi, old->s##_hi, \
7240 diff.lo, new->s##_lo, old->s##_lo); \
7241 ADD_64(estats->t##_hi, diff.hi, \
7242 estats->t##_lo, diff.lo); \
7245 /* sum[hi:lo] += add */
7246 #define ADD_EXTEND_64(s_hi, s_lo, a) do { \
7248 s_hi += (s_lo < a) ? 1 : 0; \
7251 #define UPDATE_EXTEND_STAT(s) do { \
7252 ADD_EXTEND_64(pstats->mac_stx[1].s##_hi, \
7253 pstats->mac_stx[1].s##_lo, new->s); \
7256 #define UPDATE_EXTEND_TSTAT(s, t) do { \
7257 diff = (tclient->s) - (old_tclient->s); \
7258 old_tclient->s = (tclient->s); \
7259 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
7262 #define UPDATE_EXTEND_XSTAT(s, t) do { \
7263 diff = xclient->s - old_xclient->s; \
7264 old_xclient->s = xclient->s; \
7265 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
7268 #define UPDATE_EXTEND_USTAT(s, t) do { \
7269 diff = uclient->s - old_uclient->s; \
7270 old_uclient->s = uclient->s; \
7271 ADD_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
7274 #define SUB_EXTEND_64(m_hi, m_lo, s)do { \
7275 SUB_64(m_hi, 0, m_lo, s); \
7278 #define SUB_EXTEND_USTAT(s, t)do { \
7279 diff = (uclient->s) - (old_uclient->s); \
7280 SUB_EXTEND_64(qstats->t##_hi, qstats->t##_lo, diff); \
7287 #define BITS_PER_LONG 32
7289 #define BITS_PER_LONG 64
7292 static __inline long
7293 bxe_hilo(uint32_t *hiref)
7298 #if (BITS_PER_LONG == 64)
7299 uint32_t hi = *hiref;
7300 return (HILO_U64(hi, lo));
7307 * Request the STORM statistics by posting a slowpath ramrod.
7313 bxe_stats_storm_post(struct bxe_softc *sc)
7315 struct eth_query_ramrod_data ramrod_data = {0};
7318 DBENTER(BXE_INSANE_STATS);
7320 if (!sc->stats_pending) {
7321 ramrod_data.drv_counter = sc->stats_counter++;
7322 ramrod_data.collect_port = sc->port.pmf ? 1 : 0;
7323 for (i = 0; i < sc->num_queues; i++)
7324 ramrod_data.ctr_id_vector |= (1 << sc->fp[i].cl_id);
7326 rc = bxe_sp_post(sc, RAMROD_CMD_ID_ETH_STAT_QUERY, 0,
7327 ((uint32_t *)&ramrod_data)[1],
7328 ((uint32_t *)&ramrod_data)[0], 0);
7330 /* Stats ramrod has it's own slot on the SPQ. */
7332 sc->stats_pending = 1;
7336 DBEXIT(BXE_INSANE_STATS);
7340 * Setup the adrress used by the driver to report port-based statistics
7341 * back to the controller.
7347 bxe_stats_port_base_init(struct bxe_softc *sc)
7349 uint32_t *stats_comp;
7350 struct dmae_command *dmae;
7352 DBENTER(BXE_VERBOSE_STATS);
7354 /* Only the port management function (PMF) does this work. */
7355 if ((sc->port.pmf == 0) || !sc->port.port_stx) {
7356 BXE_PRINTF("%s(%d): Invalid statistcs port setup!\n",
7357 __FILE__, __LINE__);
7358 goto bxe_stats_port_base_init_exit;
7361 stats_comp = BXE_SP(sc, stats_comp);
7362 sc->executer_idx = 0;
7364 /* DMA the address of the drivers port statistics block. */
7365 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7366 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
7367 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
7368 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7370 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7372 DMAE_CMD_ENDIANITY_DW_SWAP |
7374 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7375 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
7376 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
7377 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
7378 dmae->dst_addr_lo = sc->port.port_stx >> 2;
7379 dmae->dst_addr_hi = 0;
7380 dmae->len = sizeof(struct host_port_stats) >> 2;
7381 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
7382 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
7383 dmae->comp_val = DMAE_COMP_VAL;
7386 bxe_stats_hw_post(sc);
7389 bxe_stats_port_base_init_exit:
7390 DBEXIT(BXE_VERBOSE_STATS);
7394 * Setup the adrress used by the driver to report function-based statistics
7395 * back to the controller.
7401 bxe_stats_func_base_init(struct bxe_softc *sc)
7407 DBENTER(BXE_VERBOSE_STATS);
7409 /* Only the port management function (PMF) does this work. */
7410 if ((sc->port.pmf == 0) || !sc->func_stx) {
7411 BXE_PRINTF("%s(%d): Invalid statistcs function setup!\n",
7412 __FILE__, __LINE__);
7413 goto bxe_stats_func_base_init_exit;
7417 func_stx = sc->func_stx;
7418 vn_max = IS_E1HMF(sc) ? E1HVN_MAX : E1VN_MAX;
7420 /* Initialize each function individually. */
7421 for (vn = VN_0; vn < vn_max; vn++) {
7422 func = 2 * vn + port;
7423 sc->func_stx = SHMEM_RD(sc, func_mb[func].fw_mb_param);
7424 bxe_stats_func_init(sc);
7425 bxe_stats_hw_post(sc);
7429 sc->func_stx = func_stx;
7431 bxe_stats_func_base_init_exit:
7432 DBEXIT(BXE_VERBOSE_STATS);
7436 * DMA the function-based statistics to the controller.
7442 bxe_stats_func_base_update(struct bxe_softc *sc)
7444 uint32_t *stats_comp;
7445 struct dmae_command *dmae;
7447 DBENTER(BXE_VERBOSE_STATS);
7449 /* Only the port management function (PMF) does this work. */
7450 if ((sc->port.pmf == 0) || !sc->func_stx) {
7451 BXE_PRINTF("%s(%d): Invalid statistcs function update!\n",
7452 __FILE__, __LINE__);
7453 goto bxe_stats_func_base_update_exit;
7456 dmae = &sc->stats_dmae;
7457 stats_comp = BXE_SP(sc, stats_comp);
7458 sc->executer_idx = 0;
7459 memset(dmae, 0, sizeof(struct dmae_command));
7461 /* DMA the function statistics from the driver to the H/W. */
7462 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
7463 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
7464 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7466 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7468 DMAE_CMD_ENDIANITY_DW_SWAP |
7470 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7471 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
7472 dmae->src_addr_lo = sc->func_stx >> 2;
7473 dmae->src_addr_hi = 0;
7474 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats_base));
7475 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats_base));
7476 dmae->len = sizeof(struct host_func_stats) >> 2;
7477 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
7478 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
7479 dmae->comp_val = DMAE_COMP_VAL;
7482 bxe_stats_hw_post(sc);
7485 bxe_stats_func_base_update_exit:
7486 DBEXIT(BXE_VERBOSE_STATS);
7491 * Initialize statistics.
7497 bxe_stats_init(struct bxe_softc *sc)
7499 struct bxe_fastpath *fp;
7502 DBENTER(BXE_VERBOSE_STATS);
7504 if (sc->stats_enable == FALSE)
7505 goto bxe_stats_init_exit;
7509 sc->executer_idx = 0;
7510 sc->stats_counter = 0;
7511 sc->stats_pending = 0;
7513 /* Fetch the offset of port & function statistics in shared memory. */
7515 sc->port.port_stx = 0;
7518 sc->port.port_stx = SHMEM_RD(sc, port_mb[port].port_stx);
7519 sc->func_stx = SHMEM_RD(sc, func_mb[func].fw_mb_param);
7522 DBPRINT(sc, BXE_VERBOSE_STATS, "%s(): sc->port.port_stx = 0x%08X\n",
7523 __FUNCTION__, sc->port.port_stx);
7524 DBPRINT(sc, BXE_VERBOSE_STATS, "%s(): sc->func_stx = 0x%08X\n",
7525 __FUNCTION__, sc->func_stx);
7527 /* Port statistics. */
7528 memset(&(sc->port.old_nig_stats), 0, sizeof(struct nig_stats));
7529 sc->port.old_nig_stats.brb_discard = REG_RD(sc,
7530 NIG_REG_STAT0_BRB_DISCARD + port * 0x38);
7531 sc->port.old_nig_stats.brb_truncate = REG_RD(sc,
7532 NIG_REG_STAT0_BRB_TRUNCATE + port * 0x38);
7533 REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port * 0x50,
7534 &(sc->port.old_nig_stats.egress_mac_pkt0_lo), 2);
7535 REG_RD_DMAE(sc, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port * 0x50,
7536 &(sc->port.old_nig_stats.egress_mac_pkt1_lo), 2);
7538 /* Function statistics. */
7539 for (i = 0; i < sc->num_queues; i++) {
7542 /* Clear all per-queue statistics. */
7543 memset(&fp->old_tclient, 0,
7544 sizeof(struct tstorm_per_client_stats));
7545 memset(&fp->old_uclient, 0,
7546 sizeof(struct ustorm_per_client_stats));
7547 memset(&fp->old_xclient, 0,
7548 sizeof(struct xstorm_per_client_stats));
7549 memset(&fp->eth_q_stats, 0,
7550 sizeof(struct bxe_q_stats));
7553 /* ToDo: Clear any driver specific statistics? */
7555 sc->stats_state = STATS_STATE_DISABLED;
7557 if (sc->port.pmf == 1) {
7558 /* Init port & function stats if we're PMF. */
7559 if (sc->port.port_stx)
7560 bxe_stats_port_base_init(sc);
7562 bxe_stats_func_base_init(sc);
7563 } else if (sc->func_stx)
7564 /* Update function stats if we're not PMF. */
7565 bxe_stats_func_base_update(sc);
7567 bxe_stats_init_exit:
7568 DBEXIT(BXE_VERBOSE_STATS);
7577 bxe_stats_hw_post(struct bxe_softc *sc)
7579 struct dmae_command *dmae;
7580 uint32_t *stats_comp;
7583 DBENTER(BXE_INSANE_STATS);
7585 dmae = &sc->stats_dmae;
7586 stats_comp = BXE_SP(sc, stats_comp);
7587 *stats_comp = DMAE_COMP_VAL;
7589 if (sc->executer_idx) {
7590 loader_idx = PMF_DMAE_C(sc);
7592 memset(dmae, 0, sizeof(struct dmae_command));
7594 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
7595 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
7596 DMAE_CMD_DST_RESET |
7598 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7600 DMAE_CMD_ENDIANITY_DW_SWAP |
7602 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7603 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
7605 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, dmae[0]));
7606 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, dmae[0]));
7607 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
7608 sizeof(struct dmae_command) * (loader_idx + 1)) >> 2;
7609 dmae->dst_addr_hi = 0;
7610 dmae->len = sizeof(struct dmae_command) >> 2;
7615 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
7616 dmae->comp_addr_hi = 0;
7620 bxe_post_dmae(sc, dmae, loader_idx);
7622 } else if (sc->func_stx) {
7624 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc));
7627 DBEXIT(BXE_INSANE_STATS);
7631 * Delay routine which polls for the DMA engine to complete.
7634 * 0 = Failure, !0 = Success
7637 bxe_stats_comp(struct bxe_softc *sc)
7639 uint32_t *stats_comp;
7642 DBENTER(BXE_VERBOSE_STATS);
7644 stats_comp = BXE_SP(sc, stats_comp);
7647 while (*stats_comp != DMAE_COMP_VAL) {
7649 BXE_PRINTF("%s(%d): Timeout waiting for statistics "
7650 "completions.\n", __FILE__, __LINE__);
7657 DBEXIT(BXE_VERBOSE_STATS);
7658 /* ToDo: Shouldn't this return the value of cnt? */
7663 * DMA port statistcs from controller to driver.
7669 bxe_stats_pmf_update(struct bxe_softc *sc)
7671 struct dmae_command *dmae;
7672 uint32_t opcode, *stats_comp;
7675 DBENTER(BXE_VERBOSE_STATS);
7677 stats_comp = BXE_SP(sc, stats_comp);
7678 loader_idx = PMF_DMAE_C(sc);
7680 /* We shouldn't be here if any of the following are false. */
7681 if (!IS_E1HMF(sc) || (sc->port.pmf == 0) || !sc->port.port_stx) {
7682 BXE_PRINTF("%s(%d): Statistics bug!\n", __FILE__, __LINE__);
7683 goto bxe_stats_pmf_update_exit;
7686 sc->executer_idx = 0;
7688 /* Instruct DMA engine to copy port statistics from H/W to driver. */
7689 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
7690 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
7691 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7693 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7695 DMAE_CMD_ENDIANITY_DW_SWAP |
7697 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7698 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
7700 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7701 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
7702 dmae->src_addr_lo = sc->port.port_stx >> 2;
7703 dmae->src_addr_hi = 0;
7704 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
7705 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
7706 dmae->len = DMAE_LEN32_RD_MAX;
7707 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7708 dmae->comp_addr_hi = 0;
7711 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7712 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
7713 dmae->src_addr_lo = (sc->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
7714 dmae->src_addr_hi = 0;
7715 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats) +
7716 DMAE_LEN32_RD_MAX * 4);
7717 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats) +
7718 DMAE_LEN32_RD_MAX * 4);
7719 dmae->len = (sizeof(struct host_port_stats) >> 2) -
7721 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
7722 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
7723 dmae->comp_val = DMAE_COMP_VAL;
7725 /* Start the DMA and wait for the result. */
7727 bxe_stats_hw_post(sc);
7730 bxe_stats_pmf_update_exit:
7731 DBEXIT(BXE_VERBOSE_STATS);
7735 * Prepare the DMAE parameters required for all statistics.
7737 * This function should only be called by the driver instance
7738 * that is designated as the port management function (PMF).
7744 bxe_stats_port_init(struct bxe_softc *sc)
7746 struct dmae_command *dmae;
7747 uint32_t mac_addr, opcode, *stats_comp;
7748 int loader_idx, port, vn;
7750 DBENTER(BXE_VERBOSE_STATS);
7754 loader_idx = PMF_DMAE_C(sc);
7755 stats_comp = BXE_SP(sc, stats_comp);
7757 /* Only the port management function (PMF) does this work. */
7758 if (!sc->link_vars.link_up || (sc->port.pmf == 0)) {
7759 BXE_PRINTF("%s(%d): Invalid statistics port setup!\n",
7760 __FILE__, __LINE__);
7761 goto bxe_stats_port_init_exit;
7764 sc->executer_idx = 0;
7766 /* The same opcde is used for multiple DMA operations. */
7767 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
7768 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
7769 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7771 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7773 DMAE_CMD_ENDIANITY_DW_SWAP |
7775 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7776 (vn << DMAE_CMD_E1HVN_SHIFT));
7778 /* Setup the DMA for port statistics. */
7779 if (sc->port.port_stx) {
7780 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7781 dmae->opcode = opcode;
7782 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
7783 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
7784 dmae->dst_addr_lo = sc->port.port_stx >> 2;
7785 dmae->dst_addr_hi = 0;
7786 dmae->len = sizeof(struct host_port_stats) >> 2;
7787 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7788 dmae->comp_addr_hi = 0;
7792 /* Setup the DMA for function statistics. */
7794 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7795 dmae->opcode = opcode;
7796 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
7797 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
7798 dmae->dst_addr_lo = sc->func_stx >> 2;
7799 dmae->dst_addr_hi = 0;
7800 dmae->len = sizeof(struct host_func_stats) >> 2;
7801 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7802 dmae->comp_addr_hi = 0;
7806 /* Setup statistics reporting for the MAC. */
7807 opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
7808 DMAE_CMD_C_DST_GRC | DMAE_CMD_C_ENABLE |
7809 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7811 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7813 DMAE_CMD_ENDIANITY_DW_SWAP |
7815 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7816 (vn << DMAE_CMD_E1HVN_SHIFT));
7818 if (sc->link_vars.mac_type == MAC_TYPE_BMAC) {
7819 /* Enable statistics for the 10Gb BMAC. */
7821 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
7822 NIG_REG_INGRESS_BMAC0_MEM);
7824 /* Setup BMAC TX statistics (TX_STAT_GTPKT .. TX_STAT_GTBYT). */
7825 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7826 dmae->opcode = opcode;
7827 dmae->src_addr_lo = (mac_addr +
7828 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
7829 dmae->src_addr_hi = 0;
7830 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats));
7831 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats));
7832 dmae->len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
7833 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
7834 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7835 dmae->comp_addr_hi = 0;
7838 /* Setup BMAC RX statistcs (RX_STAT_GR64 .. RX_STAT_GRIPJ). */
7839 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7840 dmae->opcode = opcode;
7841 dmae->src_addr_lo = (mac_addr +
7842 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
7843 dmae->src_addr_hi = 0;
7844 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
7845 offsetof(struct bmac_stats, rx_stat_gr64_lo));
7846 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
7847 offsetof(struct bmac_stats, rx_stat_gr64_lo));
7848 dmae->len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
7849 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
7850 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7851 dmae->comp_addr_hi = 0;
7854 } else if (sc->link_vars.mac_type == MAC_TYPE_EMAC) {
7855 /* Enable statistics for the 1Gb EMAC. */
7857 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
7859 /* Setup EMAC RX statistics. */
7860 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7861 dmae->opcode = opcode;
7862 dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_RX_STAT_AC) >> 2;
7863 dmae->src_addr_hi = 0;
7864 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats));
7865 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats));
7866 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
7867 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7868 dmae->comp_addr_hi = 0;
7871 /* Setup additional EMAC RX statistics. */
7872 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7873 dmae->opcode = opcode;
7874 dmae->src_addr_lo = (mac_addr +
7875 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
7876 dmae->src_addr_hi = 0;
7877 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
7878 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
7879 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
7880 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
7882 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7883 dmae->comp_addr_hi = 0;
7886 /* Setup EMAC TX statistics. */
7887 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7888 dmae->opcode = opcode;
7889 dmae->src_addr_lo = (mac_addr + EMAC_REG_EMAC_TX_STAT_AC) >> 2;
7890 dmae->src_addr_hi = 0;
7891 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, mac_stats) +
7892 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
7893 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, mac_stats) +
7894 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
7895 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
7896 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7897 dmae->comp_addr_hi = 0;
7900 DBPRINT(sc, BXE_WARN, "%s(): Undefined MAC type.\n",
7904 /* Enable NIG statistics. */
7905 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7906 dmae->opcode = opcode;
7907 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
7908 NIG_REG_STAT0_BRB_DISCARD) >> 2;
7909 dmae->src_addr_hi = 0;
7910 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats));
7911 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats));
7912 dmae->len = (sizeof(struct nig_stats) - 4 * sizeof(uint32_t)) >> 2;
7913 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7914 dmae->comp_addr_hi = 0;
7917 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7918 dmae->opcode = opcode;
7919 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
7920 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
7921 dmae->src_addr_hi = 0;
7922 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats) +
7923 offsetof(struct nig_stats, egress_mac_pkt0_lo));
7924 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats) +
7925 offsetof(struct nig_stats, egress_mac_pkt0_lo));
7926 dmae->len = (2 * sizeof(uint32_t)) >> 2;
7927 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
7928 dmae->comp_addr_hi = 0;
7931 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
7932 dmae->opcode = (DMAE_CMD_SRC_GRC | DMAE_CMD_DST_PCI |
7933 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
7934 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7936 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7938 DMAE_CMD_ENDIANITY_DW_SWAP |
7940 (port ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7941 (vn << DMAE_CMD_E1HVN_SHIFT));
7942 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
7943 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
7944 dmae->src_addr_hi = 0;
7945 dmae->dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, nig_stats) +
7946 offsetof(struct nig_stats, egress_mac_pkt1_lo));
7947 dmae->dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, nig_stats) +
7948 offsetof(struct nig_stats, egress_mac_pkt1_lo));
7949 dmae->len = (2 * sizeof(uint32_t)) >> 2;
7950 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
7951 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
7952 dmae->comp_val = DMAE_COMP_VAL;
7954 /* Clear the statistics completion value. */
7957 bxe_stats_port_init_exit:
7958 DBEXIT(BXE_VERBOSE_STATS);
7962 * Prepare the DMAE parameters required for function statistics.
7964 * This function is called by all driver instances.
7970 bxe_stats_func_init(struct bxe_softc *sc)
7972 struct dmae_command *dmae;
7973 uint32_t *stats_comp;
7975 DBENTER(BXE_VERBOSE_STATS);
7977 if (!sc->func_stx) {
7978 BXE_PRINTF("%s(%d): Invalid statistics function setup!\n",
7979 __FILE__, __LINE__);
7980 goto bxe_stats_func_init_exit;
7983 dmae = &sc->stats_dmae;
7984 stats_comp = BXE_SP(sc, stats_comp);
7985 sc->executer_idx = 0;
7986 memset(dmae, 0, sizeof(struct dmae_command));
7988 /* Setup the DMA for function statistics. */
7989 dmae->opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
7990 DMAE_CMD_C_DST_PCI | DMAE_CMD_C_ENABLE |
7991 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
7993 DMAE_CMD_ENDIANITY_B_DW_SWAP |
7995 DMAE_CMD_ENDIANITY_DW_SWAP |
7997 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
7998 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
8000 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
8001 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
8002 dmae->dst_addr_lo = sc->func_stx >> 2;
8003 dmae->dst_addr_hi = 0;
8004 dmae->len = sizeof(struct host_func_stats) >> 2;
8005 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
8006 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
8007 dmae->comp_val = DMAE_COMP_VAL;
8011 bxe_stats_func_init_exit:
8012 DBEXIT(BXE_VERBOSE_STATS);
8016 * Starts a statistics update DMA and waits for completion.
8022 bxe_stats_start(struct bxe_softc *sc)
8025 DBENTER(BXE_VERBOSE_STATS);
8027 if (sc->port.pmf == 1)
8028 bxe_stats_port_init(sc);
8029 else if (sc->func_stx)
8030 bxe_stats_func_init(sc);
8032 bxe_stats_hw_post(sc);
8033 bxe_stats_storm_post(sc);
8035 DBEXIT(BXE_VERBOSE_STATS);
8043 bxe_stats_pmf_start(struct bxe_softc *sc)
8045 DBENTER(BXE_VERBOSE_STATS);
8048 bxe_stats_pmf_update(sc);
8049 bxe_stats_start(sc);
8051 DBEXIT(BXE_VERBOSE_STATS);
8059 bxe_stats_restart(struct bxe_softc *sc)
8062 DBENTER(BXE_VERBOSE_STATS);
8065 bxe_stats_start(sc);
8067 DBEXIT(BXE_VERBOSE_STATS);
8071 * Update the Big MAC (10Gb BMAC) statistics.
8077 bxe_stats_bmac_update(struct bxe_softc *sc)
8079 struct bmac_stats *new;
8080 struct host_port_stats *pstats;
8081 struct bxe_port_stats *estats;
8082 struct regpair diff;
8084 DBENTER(BXE_INSANE_STATS);
8086 new = BXE_SP(sc, mac_stats.bmac_stats);
8087 pstats = BXE_SP(sc, port_stats);
8088 estats = &sc->eth_stats;
8090 UPDATE_STAT64(rx_stat_grerb,
8091 rx_stat_ifhcinbadoctets);
8092 UPDATE_STAT64(rx_stat_grfcs,
8093 rx_stat_dot3statsfcserrors);
8094 UPDATE_STAT64(rx_stat_grund,
8095 rx_stat_etherstatsundersizepkts);
8096 UPDATE_STAT64(rx_stat_grovr,
8097 rx_stat_dot3statsframestoolong);
8098 UPDATE_STAT64(rx_stat_grfrg,
8099 rx_stat_etherstatsfragments);
8100 UPDATE_STAT64(rx_stat_grjbr,
8101 rx_stat_etherstatsjabbers);
8102 UPDATE_STAT64(rx_stat_grxcf,
8103 rx_stat_maccontrolframesreceived);
8104 UPDATE_STAT64(rx_stat_grxpf,
8105 rx_stat_xoffstateentered);
8106 UPDATE_STAT64(rx_stat_grxpf,
8108 UPDATE_STAT64(tx_stat_gtxpf,
8109 tx_stat_outxoffsent);
8110 UPDATE_STAT64(tx_stat_gtxpf,
8111 tx_stat_flowcontroldone);
8112 UPDATE_STAT64(tx_stat_gt64,
8113 tx_stat_etherstatspkts64octets);
8114 UPDATE_STAT64(tx_stat_gt127,
8115 tx_stat_etherstatspkts65octetsto127octets);
8116 UPDATE_STAT64(tx_stat_gt255,
8117 tx_stat_etherstatspkts128octetsto255octets);
8118 UPDATE_STAT64(tx_stat_gt511,
8119 tx_stat_etherstatspkts256octetsto511octets);
8120 UPDATE_STAT64(tx_stat_gt1023,
8121 tx_stat_etherstatspkts512octetsto1023octets);
8122 UPDATE_STAT64(tx_stat_gt1518,
8123 tx_stat_etherstatspkts1024octetsto1522octets);
8124 UPDATE_STAT64(tx_stat_gt2047,
8126 UPDATE_STAT64(tx_stat_gt4095,
8128 UPDATE_STAT64(tx_stat_gt9216,
8130 UPDATE_STAT64(tx_stat_gt16383,
8131 tx_stat_bmac_16383);
8132 UPDATE_STAT64(tx_stat_gterr,
8133 tx_stat_dot3statsinternalmactransmiterrors);
8134 UPDATE_STAT64(tx_stat_gtufl,
8137 estats->pause_frames_received_hi =
8138 pstats->mac_stx[1].rx_stat_bmac_xpf_hi;
8139 estats->pause_frames_received_lo =
8140 pstats->mac_stx[1].rx_stat_bmac_xpf_lo;
8141 estats->pause_frames_sent_hi =
8142 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
8143 estats->pause_frames_sent_lo =
8144 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
8146 DBEXIT(BXE_INSANE_STATS);
8150 * Update the Ethernet MAC (1Gb EMAC) statistics.
8156 bxe_stats_emac_update(struct bxe_softc *sc)
8158 struct emac_stats *new;
8159 struct host_port_stats *pstats;
8160 struct bxe_port_stats *estats;
8162 DBENTER(BXE_INSANE_STATS);
8164 new = BXE_SP(sc, mac_stats.emac_stats);
8165 pstats = BXE_SP(sc, port_stats);
8166 estats = &sc->eth_stats;
8168 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
8169 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
8170 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
8171 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
8172 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
8173 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
8174 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
8175 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
8176 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
8177 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
8178 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
8179 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
8180 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
8181 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
8182 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
8183 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
8184 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
8185 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
8186 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
8187 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
8188 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
8189 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
8190 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
8191 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
8192 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
8193 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
8194 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
8195 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
8196 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
8197 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
8198 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
8200 estats->pause_frames_received_hi =
8201 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
8202 estats->pause_frames_received_lo =
8203 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
8204 ADD_64(estats->pause_frames_received_hi,
8205 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
8206 estats->pause_frames_received_lo,
8207 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
8209 estats->pause_frames_sent_hi =
8210 pstats->mac_stx[1].tx_stat_outxonsent_hi;
8211 estats->pause_frames_sent_lo =
8212 pstats->mac_stx[1].tx_stat_outxonsent_lo;
8213 ADD_64(estats->pause_frames_sent_hi,
8214 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
8215 estats->pause_frames_sent_lo,
8216 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
8218 DBEXIT(BXE_INSANE_STATS);
8223 * 0 = Success, !0 = Failure.
8226 bxe_stats_hw_update(struct bxe_softc *sc)
8228 struct nig_stats *new, *old;
8229 struct host_port_stats *pstats;
8230 struct bxe_port_stats *estats;
8231 struct regpair diff;
8232 uint32_t nig_timer_max;
8235 DBENTER(BXE_INSANE_STATS);
8238 new = BXE_SP(sc, nig_stats);
8239 old = &(sc->port.old_nig_stats);
8240 pstats = BXE_SP(sc, port_stats);
8241 estats = &sc->eth_stats;
8243 /* Update statistics for the active MAC. */
8244 if (sc->link_vars.mac_type == MAC_TYPE_BMAC)
8245 bxe_stats_bmac_update(sc);
8246 else if (sc->link_vars.mac_type == MAC_TYPE_EMAC)
8247 bxe_stats_emac_update(sc);
8249 DBPRINT(sc, BXE_WARN,
8250 "%s(): Statistics updated by DMAE but no MAC is active!\n",
8253 goto bxe_stats_hw_update_exit;
8256 /* Now update the hardware (NIG) statistics. */
8257 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
8258 new->brb_discard - old->brb_discard);
8259 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
8260 new->brb_truncate - old->brb_truncate);
8262 UPDATE_STAT64_NIG(egress_mac_pkt0,
8263 etherstatspkts1024octetsto1522octets);
8264 UPDATE_STAT64_NIG(egress_mac_pkt1, etherstatspktsover1522octets);
8266 memcpy(old, new, sizeof(struct nig_stats));
8268 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
8269 sizeof(struct mac_stx));
8270 estats->brb_drop_hi = pstats->brb_drop_hi;
8271 estats->brb_drop_lo = pstats->brb_drop_lo;
8273 pstats->host_port_stats_start = ++pstats->host_port_stats_end;
8277 SHMEM_RD(sc, port_mb[BP_PORT(sc)].stat_nig_timer);
8278 if (nig_timer_max != estats->nig_timer_max) {
8279 estats->nig_timer_max = nig_timer_max;
8280 DBPRINT(sc, BXE_WARN,
8281 "%s(): NIG timer reached max value (%u)!\n",
8282 __FUNCTION__, estats->nig_timer_max);
8286 bxe_stats_hw_update_exit:
8287 DBEXIT(BXE_INSANE_STATS);
8293 * 0 = Success, !0 = Failure.
8297 bxe_stats_storm_update(struct bxe_softc *sc)
8300 struct eth_stats_query *stats;
8301 struct bxe_port_stats *estats;
8302 struct host_func_stats *fstats;
8303 struct bxe_q_stats *qstats;
8304 struct tstorm_per_port_stats *tport;
8305 struct tstorm_per_client_stats *tclient;
8306 struct ustorm_per_client_stats *uclient;
8307 struct xstorm_per_client_stats *xclient;
8308 struct tstorm_per_client_stats *old_tclient;
8309 struct ustorm_per_client_stats *old_uclient;
8310 struct xstorm_per_client_stats *old_xclient;
8311 struct bxe_fastpath * fp;
8314 DBENTER(BXE_INSANE_STATS);
8318 stats = BXE_SP(sc, fw_stats);
8319 tport = &stats->tstorm_common.port_statistics;
8320 fstats = BXE_SP(sc, func_stats);
8322 memcpy(&(fstats->total_bytes_received_hi),
8323 &(BXE_SP(sc, func_stats_base)->total_bytes_received_hi),
8324 sizeof(struct host_func_stats) - 2 * sizeof(uint32_t));
8326 estats = &sc->eth_stats;
8327 estats->no_buff_discard_hi = 0;
8328 estats->no_buff_discard_lo = 0;
8329 estats->error_bytes_received_hi = 0;
8330 estats->error_bytes_received_lo = 0;
8331 estats->etherstatsoverrsizepkts_hi = 0;
8332 estats->etherstatsoverrsizepkts_lo = 0;
8334 for (i = 0; i < sc->num_queues; i++) {
8337 tclient = &stats->tstorm_common.client_statistics[cl_id];
8338 old_tclient = &fp->old_tclient;
8339 uclient = &stats->ustorm_common.client_statistics[cl_id];
8340 old_uclient = &fp->old_uclient;
8341 xclient = &stats->xstorm_common.client_statistics[cl_id];
8342 old_xclient = &fp->old_xclient;
8343 qstats = &fp->eth_q_stats;
8345 /* Are TSTORM statistics valid? */
8346 if ((uint16_t)(le16toh(tclient->stats_counter) + 1) !=
8347 sc->stats_counter) {
8348 DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by TSTORM "
8349 "(tstorm counter (%d) != stats_counter (%d))!\n",
8350 __FUNCTION__, tclient->stats_counter, sc->stats_counter);
8352 goto bxe_stats_storm_update_exit;
8355 /* Are USTORM statistics valid? */
8356 if ((uint16_t)(le16toh(uclient->stats_counter) + 1) !=
8357 sc->stats_counter) {
8358 DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by USTORM "
8359 "(ustorm counter (%d) != stats_counter (%d))!\n",
8360 __FUNCTION__, uclient->stats_counter, sc->stats_counter);
8362 goto bxe_stats_storm_update_exit;
8365 /* Are XSTORM statistics valid? */
8366 if ((uint16_t)(le16toh(xclient->stats_counter) + 1) !=
8367 sc->stats_counter) {
8368 DBPRINT(sc, BXE_WARN, "%s(): Stats not updated by XSTORM "
8369 "(xstorm counter (%d) != stats_counter (%d))!\n",
8370 __FUNCTION__, xclient->stats_counter, sc->stats_counter);
8372 goto bxe_stats_storm_update_exit;
8375 qstats->total_bytes_received_hi =
8376 (tclient->rcv_broadcast_bytes.hi);
8377 qstats->total_bytes_received_lo =
8378 le32toh(tclient->rcv_broadcast_bytes.lo);
8380 ADD_64(qstats->total_bytes_received_hi,
8381 le32toh(tclient->rcv_multicast_bytes.hi),
8382 qstats->total_bytes_received_lo,
8383 le32toh(tclient->rcv_multicast_bytes.lo));
8385 ADD_64(qstats->total_bytes_received_hi,
8386 le32toh(tclient->rcv_unicast_bytes.hi),
8387 qstats->total_bytes_received_lo,
8388 le32toh(tclient->rcv_unicast_bytes.lo));
8390 SUB_64(qstats->total_bytes_received_hi,
8391 le32toh(uclient->bcast_no_buff_bytes.hi),
8392 qstats->total_bytes_received_lo,
8393 le32toh(uclient->bcast_no_buff_bytes.lo));
8395 SUB_64(qstats->total_bytes_received_hi,
8396 le32toh(uclient->mcast_no_buff_bytes.hi),
8397 qstats->total_bytes_received_lo,
8398 le32toh(uclient->mcast_no_buff_bytes.lo));
8400 SUB_64(qstats->total_bytes_received_hi,
8401 le32toh(uclient->ucast_no_buff_bytes.hi),
8402 qstats->total_bytes_received_lo,
8403 le32toh(uclient->ucast_no_buff_bytes.lo));
8405 qstats->valid_bytes_received_hi =
8406 qstats->total_bytes_received_hi;
8407 qstats->valid_bytes_received_lo =
8408 qstats->total_bytes_received_lo;
8410 qstats->error_bytes_received_hi =
8411 le32toh(tclient->rcv_error_bytes.hi);
8412 qstats->error_bytes_received_lo =
8413 le32toh(tclient->rcv_error_bytes.lo);
8415 ADD_64(qstats->total_bytes_received_hi,
8416 qstats->error_bytes_received_hi,
8417 qstats->total_bytes_received_lo,
8418 qstats->error_bytes_received_lo);
8420 UPDATE_EXTEND_TSTAT(rcv_unicast_pkts,
8421 total_unicast_packets_received);
8422 UPDATE_EXTEND_TSTAT(rcv_multicast_pkts,
8423 total_multicast_packets_received);
8424 UPDATE_EXTEND_TSTAT(rcv_broadcast_pkts,
8425 total_broadcast_packets_received);
8426 UPDATE_EXTEND_TSTAT(packets_too_big_discard,
8427 etherstatsoverrsizepkts);
8428 UPDATE_EXTEND_TSTAT(no_buff_discard, no_buff_discard);
8430 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
8431 total_unicast_packets_received);
8432 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
8433 total_multicast_packets_received);
8434 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
8435 total_broadcast_packets_received);
8436 UPDATE_EXTEND_USTAT(ucast_no_buff_pkts, no_buff_discard);
8437 UPDATE_EXTEND_USTAT(mcast_no_buff_pkts, no_buff_discard);
8438 UPDATE_EXTEND_USTAT(bcast_no_buff_pkts, no_buff_discard);
8440 qstats->total_bytes_transmitted_hi =
8441 le32toh(xclient->unicast_bytes_sent.hi);
8442 qstats->total_bytes_transmitted_lo =
8443 le32toh(xclient->unicast_bytes_sent.lo);
8445 ADD_64(qstats->total_bytes_transmitted_hi,
8446 le32toh(xclient->multicast_bytes_sent.hi),
8447 qstats->total_bytes_transmitted_lo,
8448 le32toh(xclient->multicast_bytes_sent.lo));
8450 ADD_64(qstats->total_bytes_transmitted_hi,
8451 le32toh(xclient->broadcast_bytes_sent.hi),
8452 qstats->total_bytes_transmitted_lo,
8453 le32toh(xclient->broadcast_bytes_sent.lo));
8455 UPDATE_EXTEND_XSTAT(unicast_pkts_sent,
8456 total_unicast_packets_transmitted);
8458 UPDATE_EXTEND_XSTAT(multicast_pkts_sent,
8459 total_multicast_packets_transmitted);
8461 UPDATE_EXTEND_XSTAT(broadcast_pkts_sent,
8462 total_broadcast_packets_transmitted);
8464 old_tclient->checksum_discard = tclient->checksum_discard;
8465 old_tclient->ttl0_discard = tclient->ttl0_discard;
8467 ADD_64(fstats->total_bytes_received_hi,
8468 qstats->total_bytes_received_hi,
8469 fstats->total_bytes_received_lo,
8470 qstats->total_bytes_received_lo);
8471 ADD_64(fstats->total_bytes_transmitted_hi,
8472 qstats->total_bytes_transmitted_hi,
8473 fstats->total_bytes_transmitted_lo,
8474 qstats->total_bytes_transmitted_lo);
8475 ADD_64(fstats->total_unicast_packets_received_hi,
8476 qstats->total_unicast_packets_received_hi,
8477 fstats->total_unicast_packets_received_lo,
8478 qstats->total_unicast_packets_received_lo);
8479 ADD_64(fstats->total_multicast_packets_received_hi,
8480 qstats->total_multicast_packets_received_hi,
8481 fstats->total_multicast_packets_received_lo,
8482 qstats->total_multicast_packets_received_lo);
8483 ADD_64(fstats->total_broadcast_packets_received_hi,
8484 qstats->total_broadcast_packets_received_hi,
8485 fstats->total_broadcast_packets_received_lo,
8486 qstats->total_broadcast_packets_received_lo);
8487 ADD_64(fstats->total_unicast_packets_transmitted_hi,
8488 qstats->total_unicast_packets_transmitted_hi,
8489 fstats->total_unicast_packets_transmitted_lo,
8490 qstats->total_unicast_packets_transmitted_lo);
8491 ADD_64(fstats->total_multicast_packets_transmitted_hi,
8492 qstats->total_multicast_packets_transmitted_hi,
8493 fstats->total_multicast_packets_transmitted_lo,
8494 qstats->total_multicast_packets_transmitted_lo);
8495 ADD_64(fstats->total_broadcast_packets_transmitted_hi,
8496 qstats->total_broadcast_packets_transmitted_hi,
8497 fstats->total_broadcast_packets_transmitted_lo,
8498 qstats->total_broadcast_packets_transmitted_lo);
8499 ADD_64(fstats->valid_bytes_received_hi,
8500 qstats->valid_bytes_received_hi,
8501 fstats->valid_bytes_received_lo,
8502 qstats->valid_bytes_received_lo);
8504 ADD_64(estats->error_bytes_received_hi,
8505 qstats->error_bytes_received_hi,
8506 estats->error_bytes_received_lo,
8507 qstats->error_bytes_received_lo);
8508 ADD_64(estats->etherstatsoverrsizepkts_hi,
8509 qstats->etherstatsoverrsizepkts_hi,
8510 estats->etherstatsoverrsizepkts_lo,
8511 qstats->etherstatsoverrsizepkts_lo);
8512 ADD_64(estats->no_buff_discard_hi,
8513 qstats->no_buff_discard_hi,
8514 estats->no_buff_discard_lo,
8515 qstats->no_buff_discard_lo);
8518 ADD_64(fstats->total_bytes_received_hi,
8519 estats->rx_stat_ifhcinbadoctets_hi,
8520 fstats->total_bytes_received_lo,
8521 estats->rx_stat_ifhcinbadoctets_lo);
8523 memcpy(estats, &(fstats->total_bytes_received_hi),
8524 sizeof(struct host_func_stats) - 2 * sizeof(uint32_t));
8526 ADD_64(estats->etherstatsoverrsizepkts_hi,
8527 estats->rx_stat_dot3statsframestoolong_hi,
8528 estats->etherstatsoverrsizepkts_lo,
8529 estats->rx_stat_dot3statsframestoolong_lo);
8530 ADD_64(estats->error_bytes_received_hi,
8531 estats->rx_stat_ifhcinbadoctets_hi,
8532 estats->error_bytes_received_lo,
8533 estats->rx_stat_ifhcinbadoctets_lo);
8536 estats->mac_filter_discard =
8537 le32toh(tport->mac_filter_discard);
8538 estats->xxoverflow_discard =
8539 le32toh(tport->xxoverflow_discard);
8540 estats->brb_truncate_discard =
8541 le32toh(tport->brb_truncate_discard);
8542 estats->mac_discard = le32toh(tport->mac_discard);
8545 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
8547 sc->stats_pending = 0;
8549 bxe_stats_storm_update_exit:
8551 DBEXIT(BXE_INSANE_STATS);
8556 * Copy the controller maintained statistics over to the OS.
8562 bxe_stats_net_update(struct bxe_softc *sc)
8564 struct tstorm_per_client_stats *old_tclient;
8565 struct bxe_port_stats *estats;
8568 DBENTER(BXE_INSANE_STATS);
8570 old_tclient = &sc->fp[0].old_tclient;
8571 estats = &sc->eth_stats;
8575 * Update the OS interface statistics from
8576 * the hardware statistics.
8579 ifp->if_collisions =
8580 (u_long) estats->tx_stat_dot3statssinglecollisionframes_lo +
8581 (u_long) estats->tx_stat_dot3statsmultiplecollisionframes_lo +
8582 (u_long) estats->tx_stat_dot3statslatecollisions_lo +
8583 (u_long) estats->tx_stat_dot3statsexcessivecollisions_lo;
8586 (u_long) old_tclient->checksum_discard +
8587 (u_long) estats->no_buff_discard_lo +
8588 (u_long) estats->mac_discard +
8589 (u_long) estats->rx_stat_etherstatsundersizepkts_lo +
8590 (u_long) estats->brb_drop_lo +
8591 (u_long) estats->brb_truncate_discard +
8592 (u_long) estats->rx_stat_dot3statsfcserrors_lo +
8593 (u_long) estats->rx_stat_dot3statsalignmenterrors_lo +
8594 (u_long) estats->xxoverflow_discard;
8597 (u_long) estats->tx_stat_dot3statslatecollisions_lo +
8598 (u_long) estats->tx_stat_dot3statsexcessivecollisions_lo +
8599 (u_long) estats->tx_stat_dot3statsinternalmactransmiterrors_lo;
8602 bxe_hilo(&estats->total_unicast_packets_received_hi) +
8603 bxe_hilo(&estats->total_multicast_packets_received_hi) +
8604 bxe_hilo(&estats->total_broadcast_packets_received_hi);
8607 bxe_hilo(&estats->total_unicast_packets_transmitted_hi) +
8608 bxe_hilo(&estats->total_multicast_packets_transmitted_hi) +
8609 bxe_hilo(&estats->total_broadcast_packets_transmitted_hi);
8611 DBEXIT(BXE_INSANE_STATS);
8620 bxe_stats_update(struct bxe_softc *sc)
8622 uint32_t *stats_comp;
8625 DBENTER(BXE_INSANE_STATS);
8627 stats_comp = BXE_SP(sc, stats_comp);
8630 /* Make sure the statistics DMAE update has completed. */
8631 if (*stats_comp != DMAE_COMP_VAL)
8632 goto bxe_stats_update_exit;
8634 /* Check for any hardware statistics updates. */
8635 if (sc->port.pmf == 1)
8636 update = (bxe_stats_hw_update(sc) == 0);
8638 /* Check for any STORM statistics updates. */
8639 update |= (bxe_stats_storm_update(sc) == 0);
8641 /* If we got updated hardware statistics then update the OS. */
8643 bxe_stats_net_update(sc);
8645 /* Check if any statistics updates are pending. */
8646 if (sc->stats_pending) {
8647 /* The update hasn't completed, keep waiting. */
8648 sc->stats_pending++;
8650 /* Have we been waiting for too long? */
8651 if (sc->stats_pending >= 3) {
8653 "%s(%d): Failed to get statistics after "
8654 "3 tries!\n", __FILE__, __LINE__);
8656 goto bxe_stats_update_exit;
8661 /* Kickoff the next statistics request. */
8662 bxe_stats_hw_post(sc);
8663 bxe_stats_storm_post(sc);
8665 bxe_stats_update_exit:
8666 DBEXIT(BXE_INSANE_STATS);
8675 bxe_stats_port_stop(struct bxe_softc *sc)
8677 struct dmae_command *dmae;
8678 uint32_t opcode, *stats_comp;
8681 DBENTER(BXE_VERBOSE_STATS);
8683 stats_comp = BXE_SP(sc, stats_comp);
8684 loader_idx = PMF_DMAE_C(sc);
8685 sc->executer_idx = 0;
8687 opcode = (DMAE_CMD_SRC_PCI | DMAE_CMD_DST_GRC |
8689 DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET |
8691 DMAE_CMD_ENDIANITY_B_DW_SWAP |
8693 DMAE_CMD_ENDIANITY_DW_SWAP |
8695 (BP_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0) |
8696 (BP_E1HVN(sc) << DMAE_CMD_E1HVN_SHIFT));
8698 if (sc->port.port_stx) {
8699 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
8702 dmae->opcode = (opcode | DMAE_CMD_C_DST_GRC);
8704 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
8706 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, port_stats));
8707 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, port_stats));
8708 dmae->dst_addr_lo = sc->port.port_stx >> 2;
8709 dmae->dst_addr_hi = 0;
8710 dmae->len = sizeof(struct host_port_stats) >> 2;
8713 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
8714 dmae->comp_addr_hi = 0;
8717 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc,
8719 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc,
8721 dmae->comp_val = DMAE_COMP_VAL;
8728 dmae = BXE_SP(sc, dmae[sc->executer_idx++]);
8729 dmae->opcode = (opcode | DMAE_CMD_C_DST_PCI);
8730 dmae->src_addr_lo = U64_LO(BXE_SP_MAPPING(sc, func_stats));
8731 dmae->src_addr_hi = U64_HI(BXE_SP_MAPPING(sc, func_stats));
8732 dmae->dst_addr_lo = sc->func_stx >> 2;
8733 dmae->dst_addr_hi = 0;
8734 dmae->len = sizeof(struct host_func_stats) >> 2;
8735 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, stats_comp));
8736 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, stats_comp));
8737 dmae->comp_val = DMAE_COMP_VAL;
8742 DBEXIT(BXE_VERBOSE_STATS);
8750 bxe_stats_stop(struct bxe_softc *sc)
8754 DBENTER(BXE_VERBOSE_STATS);
8758 /* Wait for any pending completions. */
8761 if (sc->port.pmf == 1)
8762 update = (bxe_stats_hw_update(sc) == 0);
8764 update |= (bxe_stats_storm_update(sc) == 0);
8767 bxe_stats_net_update(sc);
8769 if (sc->port.pmf == 1)
8770 bxe_stats_port_stop(sc);
8772 bxe_stats_hw_post(sc);
8776 DBEXIT(BXE_VERBOSE_STATS);
8780 * A dummy function to fill in the statistics state transition table.
8786 bxe_stats_do_nothing(struct bxe_softc *sc)
8788 DBENTER(BXE_VERBOSE_STATS);
8789 DBEXIT(BXE_VERBOSE_STATS);
8792 static const struct {
8793 void (*action)(struct bxe_softc *sc);
8794 enum bxe_stats_state next_state;
8795 } bxe_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
8798 /* DISABLED PMF */ {bxe_stats_pmf_update, STATS_STATE_DISABLED},
8799 /* LINK_UP */ {bxe_stats_start, STATS_STATE_ENABLED},
8800 /* UPDATE */ {bxe_stats_do_nothing, STATS_STATE_DISABLED},
8801 /* STOP */ {bxe_stats_do_nothing, STATS_STATE_DISABLED}
8805 /* ENABLED PMF */ {bxe_stats_pmf_start, STATS_STATE_ENABLED},
8806 /* LINK_UP */ {bxe_stats_restart, STATS_STATE_ENABLED},
8807 /* UPDATE */ {bxe_stats_update, STATS_STATE_ENABLED},
8808 /* STOP */ {bxe_stats_stop, STATS_STATE_DISABLED}
8813 * Move to the next state of the statistics state machine.
8819 bxe_stats_handle(struct bxe_softc *sc, enum bxe_stats_event event)
8821 enum bxe_stats_state state;
8823 DBENTER(BXE_EXTREME_STATS);
8825 state = sc->stats_state;
8828 if (event != STATS_EVENT_UPDATE)
8829 DBPRINT(sc, BXE_VERBOSE_STATS,
8830 "%s(): Current state = %d, event = %d.\n", __FUNCTION__,
8834 bxe_stats_stm[state][event].action(sc);
8835 sc->stats_state = bxe_stats_stm[state][event].next_state;
8838 if (event != STATS_EVENT_UPDATE)
8839 DBPRINT(sc, BXE_VERBOSE_STATS, "%s(): New state = %d.\n",
8840 __FUNCTION__, sc->stats_state);
8843 DBEXIT(BXE_EXTREME_STATS);
8847 * bxe_chktso_window()
8848 * Checks to ensure the 13 bd sliding window is >= MSS for TSO.
8849 * Check that (13 total bds - 3bds) = 10 bd window >= MSS.
8850 * The window: 3 bds are = 1 (for headers BD) + 2 (for PBD and last BD)
8851 * The headers comes in a seperate bd in FreeBSD. So 13-3=10.
8854 * 0 if OK to send, 1 if packet needs further defragmentation.
8857 bxe_chktso_window(struct bxe_softc* sc, int nsegs, bus_dma_segment_t *segs,
8860 uint32_t num_wnds, wnd_size, wnd_sum;
8861 int32_t frag_idx, wnd_idx;
8862 unsigned short lso_mss;
8868 num_wnds = nsegs - wnd_size;
8869 lso_mss = htole16(m0->m_pkthdr.tso_segsz);
8872 * Total Header lengths Eth+IP+TCP in 1st FreeBSD mbuf so
8873 * calculate the first window sum of data skip the first
8874 * assuming it is the header in FreeBSD.
8876 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++)
8877 wnd_sum += htole16(segs[frag_idx].ds_len);
8879 /* Chk the first 10 bd window size */
8880 if (wnd_sum < lso_mss)
8881 return (defrag = 1);
8883 /* Run through the windows */
8884 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) {
8885 /* Subtract the 1st mbuf->m_len of the last wndw(-header). */
8886 wnd_sum -= htole16(segs[wnd_idx+1].ds_len);
8887 /* Add the next mbuf len to the len of our new window. */
8888 wnd_sum += htole16(segs[frag_idx].ds_len);
8889 if (wnd_sum < lso_mss) {
8900 * Encapsultes an mbuf cluster into the tx_bd chain structure and
8901 * makes the memory visible to the controller.
8903 * If an mbuf is submitted to this routine and cannot be given to the
8904 * controller (e.g. it has too many fragments) then the function may free
8905 * the mbuf and return to the caller.
8908 * 0 = Success, !0 = Failure
8909 * Note the side effect that an mbuf may be freed if it causes a problem.
8912 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head)
8914 bus_dma_segment_t segs[32];
8917 struct eth_tx_parse_bd *tx_parse_bd;
8918 struct eth_tx_bd *tx_data_bd;
8919 struct eth_tx_bd *tx_total_pkt_size_bd;
8920 struct eth_tx_start_bd *tx_start_bd;
8921 uint16_t etype, sw_tx_bd_prod, sw_pkt_prod, total_pkt_size;
8922 // uint16_t bd_index, pkt_index;
8924 int i, defragged, e_hlen, error, nsegs, rc, nbds, vlan_off, ovlan;
8925 struct bxe_softc *sc;
8928 DBENTER(BXE_VERBOSE_SEND);
8930 DBRUN(M_ASSERTPKTHDR(*m_head));
8933 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0;
8937 tx_total_pkt_size_bd = NULL;
8939 /* Get the H/W pointer (0 to 65535) for packets and BD's. */
8940 sw_pkt_prod = fp->tx_pkt_prod;
8941 sw_tx_bd_prod = fp->tx_bd_prod;
8943 /* Create the S/W index (0 to MAX_TX_BD) for packets and BD's. */
8944 // pkt_index = TX_BD(sw_pkt_prod);
8945 // bd_index = TX_BD(sw_tx_bd_prod);
8947 mac_type = UNICAST_ADDRESS;
8949 /* Map the mbuf into the next open DMAable memory. */
8950 map = fp->tx_mbuf_map[TX_BD(sw_pkt_prod)];
8951 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, map, m0,
8952 segs, &nsegs, BUS_DMA_NOWAIT);
8954 /* Handle any mapping errors. */
8955 if(__predict_false(error != 0)){
8956 fp->tx_dma_mapping_failure++;
8957 if (error == ENOMEM) {
8958 /* Resource issue, try again later. */
8960 } else if (error == EFBIG) {
8961 /* Possibly recoverable with defragmentation. */
8962 fp->mbuf_defrag_attempts++;
8963 m0 = m_defrag(*m_head, M_NOWAIT);
8965 fp->mbuf_defrag_failures++;
8968 /* Defrag successful, try mapping again.*/
8970 error = bus_dmamap_load_mbuf_sg(
8971 fp->tx_mbuf_tag, map, m0,
8972 segs, &nsegs, BUS_DMA_NOWAIT);
8974 fp->tx_dma_mapping_failure++;
8979 /* Unknown, unrecoverable mapping error. */
8980 DBPRINT(sc, BXE_WARN_SEND,
8981 "%s(): Unknown TX mapping error! "
8982 "rc = %d.\n", __FUNCTION__, error);
8983 DBRUN(bxe_dump_mbuf(sc, m0));
8987 goto bxe_tx_encap_continue;
8990 /* Make sure there's enough room in the send queue. */
8991 if (__predict_false((nsegs + 2) >
8992 (USABLE_TX_BD - fp->tx_bd_used))) {
8993 /* Recoverable, try again later. */
8994 fp->tx_hw_queue_full++;
8995 bus_dmamap_unload(fp->tx_mbuf_tag, map);
8997 goto bxe_tx_encap_continue;
9000 /* Capture the current H/W TX chain high watermark. */
9001 if (__predict_false(fp->tx_hw_max_queue_depth <
9003 fp->tx_hw_max_queue_depth = fp->tx_bd_used;
9005 /* Now make sure it fits in the packet window. */
9006 if (__predict_false(nsegs > 12)) {
9008 * The mbuf may be to big for the controller
9009 * to handle. If the frame is a TSO frame
9010 * we'll need to do an additional check.
9012 if(m0->m_pkthdr.csum_flags & CSUM_TSO){
9013 if (bxe_chktso_window(sc,nsegs,segs,m0) == 0)
9015 goto bxe_tx_encap_continue;
9017 fp->tx_window_violation_tso++;
9019 fp->tx_window_violation_std++;
9021 /* No sense trying to defrag again, we'll drop the frame. */
9026 bxe_tx_encap_continue:
9027 /* Check for errors */
9030 /* Recoverable try again later */
9032 fp->tx_soft_errors++;
9033 fp->tx_mbuf_alloc--;
9037 goto bxe_tx_encap_exit;
9040 /* Save the mbuf and mapping. */
9041 fp->tx_mbuf_ptr[TX_BD(sw_pkt_prod)] = m0;
9042 fp->tx_mbuf_map[TX_BD(sw_pkt_prod)] = map;
9044 /* Set flag according to packet type (UNICAST_ADDRESS is default). */
9045 if (m0->m_flags & M_BCAST)
9046 mac_type = BROADCAST_ADDRESS;
9047 else if (m0->m_flags & M_MCAST)
9048 mac_type = MULTICAST_ADDRESS;
9050 /* Prepare the first transmit (Start) BD for the mbuf. */
9051 tx_start_bd = &fp->tx_chain[TX_BD(sw_tx_bd_prod)].start_bd;
9053 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
9054 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
9055 tx_start_bd->nbytes = htole16(segs[0].ds_len);
9056 total_pkt_size += tx_start_bd->nbytes;
9057 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
9058 tx_start_bd->general_data =
9059 (mac_type << ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
9061 tx_start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
9063 /* All frames have at least Start BD + Parsing BD. */
9065 tx_start_bd->nbd = htole16(nbds);
9067 if (m0->m_flags & M_VLANTAG) {
9068 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_VLAN_TAG;
9069 tx_start_bd->vlan = htole16(m0->m_pkthdr.ether_vtag);
9072 * In cases where the VLAN tag is not used the firmware
9073 * expects to see a packet counter in the VLAN tag field
9074 * Failure to do so will cause an assertion which will
9075 * stop the controller.
9077 tx_start_bd->vlan = htole16(fp->tx_pkt_prod);
9080 * Add a parsing BD from the chain. The parsing BD is always added,
9081 * however, it is only used for TSO & chksum.
9083 sw_tx_bd_prod = NEXT_TX_BD(sw_tx_bd_prod);
9084 tx_parse_bd = (struct eth_tx_parse_bd *)
9085 &fp->tx_chain[TX_BD(sw_tx_bd_prod)].parse_bd;
9086 memset(tx_parse_bd, 0, sizeof(struct eth_tx_parse_bd));
9088 /* Gather all info about the packet and add to tx_parse_bd */
9089 if (m0->m_pkthdr.csum_flags) {
9090 struct ether_vlan_header *eh;
9091 struct ip *ip = NULL;
9092 struct tcphdr *th = NULL;
9094 struct udphdr *uh = NULL;
9096 /* Map Ethernet header to find type & header length. */
9097 eh = mtod(m0, struct ether_vlan_header *);
9099 /* Handle VLAN encapsulation if present. */
9100 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9101 etype = ntohs(eh->evl_proto);
9102 e_hlen = ETHER_HDR_LEN + vlan_off;
9104 etype = ntohs(eh->evl_encap_proto);
9105 e_hlen = ETHER_HDR_LEN;
9108 /* Set the Ethernet header length in 16 bit words. */
9109 tx_parse_bd->global_data = (e_hlen + ovlan) >> 1;
9110 tx_parse_bd->global_data |= ((m0->m_flags & M_VLANTAG) <<
9111 ETH_TX_PARSE_BD_LLC_SNAP_EN_SHIFT);
9115 /* If mbuf len < 20bytes, IP header is in next mbuf. */
9116 if (m0->m_len < sizeof(struct ip))
9117 ip = (struct ip *) m0->m_next->m_data;
9119 ip = (struct ip *) (m0->m_data + e_hlen);
9121 /* Calculate IP header length (16 bit words). */
9122 tx_parse_bd->ip_hlen = (ip->ip_hl << 1);
9124 /* Calculate enet + IP header length (16 bit words). */
9125 tx_parse_bd->total_hlen = tx_parse_bd->ip_hlen +
9128 if (m0->m_pkthdr.csum_flags & CSUM_IP) {
9129 fp->tx_offload_frames_csum_ip++;
9130 flags |= ETH_TX_BD_FLAGS_IP_CSUM;
9133 /* Handle any checksums requested by the stack. */
9134 if ((m0->m_pkthdr.csum_flags & CSUM_TCP)||
9135 (m0->m_pkthdr.csum_flags & CSUM_TSO)){
9137 /* Get the TCP header. */
9138 th = (struct tcphdr *)((caddr_t)ip +
9141 /* Add the TCP checksum offload flag. */
9142 flags |= ETH_TX_BD_FLAGS_L4_CSUM;
9143 fp->tx_offload_frames_csum_tcp++;
9145 /* Update the enet + IP + TCP header length. */
9146 tx_parse_bd->total_hlen +=
9147 (uint16_t)(th->th_off << 1);
9149 /* Get the pseudo header checksum. */
9150 tx_parse_bd->tcp_pseudo_csum =
9153 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) {
9155 * The hardware doesn't actually support UDP
9156 * checksum offload but we can fake it by
9157 * doing TCP checksum offload and factoring
9158 * out the extra bytes that are different
9159 * between the TCP header and the UDP header.
9161 * Calculation will begin 10 bytes before the
9162 * actual start of the UDP header. To work
9163 * around this we need to calculate the
9164 * checksum of the 10 bytes before the UDP
9165 * header and factor that out of the UDP
9166 * pseudo header checksum before asking the
9167 * H/W to calculate the full UDP checksum.
9172 /* This value is 10. */
9173 uint8_t fix = (uint8_t) (offsetof(struct tcphdr, th_sum) -
9174 (int) offsetof(struct udphdr, uh_sum));
9177 * Add the TCP checksum offload flag for
9180 flags |= ETH_TX_BD_FLAGS_L4_CSUM;
9181 fp->tx_offload_frames_csum_udp++;
9182 tx_parse_bd->global_data |=
9183 ETH_TX_PARSE_BD_UDP_CS_FLG;
9185 /* Get a pointer to the UDP header. */
9186 uh = (struct udphdr *)((caddr_t)ip +
9189 /* Set pointer 10 bytes before UDP header. */
9190 tmp_uh = (uint32_t *)((uint8_t *)uh -
9194 * Calculate a pseudo header checksum over
9195 * the 10 bytes before the UDP header.
9197 tmp_csum = in_pseudo(ntohl(*tmp_uh),
9198 ntohl(*(tmp_uh + 1)),
9199 ntohl((*(tmp_uh + 2)) & 0x0000FFFF));
9201 /* Update the enet + IP + UDP header length. */
9202 tx_parse_bd->total_hlen +=
9203 (sizeof(struct udphdr) >> 1);
9204 tx_parse_bd->tcp_pseudo_csum =
9205 ~in_addword(uh->uh_sum, ~tmp_csum);
9208 /* Update the offload flags. */
9209 tx_start_bd->bd_flags.as_bitfield |= flags;
9212 case ETHERTYPE_IPV6:
9213 fp->tx_unsupported_tso_request_ipv6++;
9214 /* ToDo: Add IPv6 support. */
9218 fp->tx_unsupported_tso_request_not_tcp++;
9219 /* ToDo - How to handle this error? */
9222 /* Setup the Parsing BD with TSO specific info */
9223 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
9224 uint16_t hdr_len = tx_parse_bd->total_hlen << 1;
9226 tx_start_bd->bd_flags.as_bitfield |=
9227 ETH_TX_BD_FLAGS_SW_LSO;
9228 fp->tx_offload_frames_tso++;
9230 /* ToDo: Does this really help? */
9231 if (__predict_false(tx_start_bd->nbytes > hdr_len)) {
9232 fp->tx_header_splits++;
9234 * Split the first BD into 2 BDs to make the
9235 * firmwares job easy...
9238 DBPRINT(sc, BXE_EXTREME_SEND,
9239 "%s(): TSO split headr size is %d (%x:%x) nbds %d\n",
9240 __FUNCTION__, tx_start_bd->nbytes,
9241 tx_start_bd->addr_hi,
9242 tx_start_bd->addr_lo, nbds);
9244 sw_tx_bd_prod = NEXT_TX_BD(sw_tx_bd_prod);
9246 /* New transmit BD (after the tx_parse_bd). */
9248 &fp->tx_chain[TX_BD(sw_tx_bd_prod)].reg_bd;
9249 tx_data_bd->addr_hi =
9250 htole32(U64_HI(segs[0].ds_addr + hdr_len));
9251 tx_data_bd->addr_lo =
9252 htole32(U64_LO(segs[0].ds_addr + hdr_len));
9253 tx_data_bd->nbytes =
9254 htole16(segs[0].ds_len) - hdr_len;
9255 if (tx_total_pkt_size_bd == NULL)
9256 tx_total_pkt_size_bd = tx_data_bd;
9260 * The controller needs the following info for TSO:
9261 * MSS, tcp_send_seq, ip_id, and tcp_pseudo_csum.
9263 tx_parse_bd->lso_mss = htole16(m0->m_pkthdr.tso_segsz);
9264 tx_parse_bd->tcp_send_seq = ntohl(th->th_seq);
9265 tx_parse_bd->tcp_flags = th->th_flags;
9266 tx_parse_bd->ip_id = ntohs(ip->ip_id);
9268 tx_parse_bd->tcp_pseudo_csum =
9269 ntohs(in_pseudo(ip->ip_src.s_addr,
9270 ip->ip_dst.s_addr, htons(IPPROTO_TCP)));
9272 tx_parse_bd->global_data |=
9273 ETH_TX_PARSE_BD_PSEUDO_CS_WITHOUT_LEN;
9277 /* Prepare remaining BDs. Start_tx_bd contains first seg (frag). */
9278 for (i = 1; i < nsegs ; i++) {
9279 sw_tx_bd_prod = NEXT_TX_BD(sw_tx_bd_prod);
9280 tx_data_bd = &fp->tx_chain[TX_BD(sw_tx_bd_prod)].reg_bd;
9281 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr));
9282 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr));
9283 tx_data_bd->nbytes = htole16(segs[i].ds_len);
9284 if (tx_total_pkt_size_bd == NULL)
9285 tx_total_pkt_size_bd = tx_data_bd;
9286 total_pkt_size += tx_data_bd->nbytes;
9289 if(tx_total_pkt_size_bd != NULL)
9290 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size;
9292 /* Update TX BD producer index value for next TX */
9293 sw_tx_bd_prod = NEXT_TX_BD(sw_tx_bd_prod);
9295 /* Update the used TX BD counter. */
9296 fp->tx_bd_used += nbds;
9299 * If the chain of tx_bd's describing this frame
9300 * is adjacent to or spans an eth_tx_next_bd element
9301 * then we need to increment the nbds value.
9303 if(TX_IDX(sw_tx_bd_prod) < nbds)
9306 /* Don't allow reordering of writes for nbd and packets. */
9308 fp->tx_db.data.prod += nbds;
9310 /* Producer points to the next free tx_bd at this point. */
9312 fp->tx_bd_prod = sw_tx_bd_prod;
9314 DOORBELL(sc, fp->index, fp->tx_db.raw);
9318 /* Prevent speculative reads from getting ahead of the status block. */
9319 bus_space_barrier(sc->bxe_btag, sc->bxe_bhandle,
9320 0, 0, BUS_SPACE_BARRIER_READ);
9322 /* Prevent speculative reads from getting ahead of the doorbell. */
9323 bus_space_barrier(sc->bxe_db_btag, sc->bxe_db_bhandle,
9324 0, 0, BUS_SPACE_BARRIER_READ);
9327 DBEXIT(BXE_VERBOSE_SEND);
9333 * Legacy (non-RSS) dispatch routine.
9339 bxe_tx_start(struct ifnet *ifp)
9341 struct bxe_softc *sc;
9342 struct bxe_fastpath *fp;
9345 DBENTER(BXE_EXTREME_SEND);
9347 /* Exit if the transmit queue is full or link down. */
9348 if (((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
9349 IFF_DRV_RUNNING) || !sc->link_vars.link_up) {
9350 DBPRINT(sc, BXE_WARN,
9351 "%s(): No link or TX queue full, ignoring "
9352 "transmit request.\n", __FUNCTION__);
9353 goto bxe_tx_start_exit;
9356 /* Set the TX queue for the frame. */
9360 bxe_tx_start_locked(ifp, fp);
9364 DBEXIT(BXE_EXTREME_SEND);
9369 * Legacy (non-RSS) transmit routine.
9375 bxe_tx_start_locked(struct ifnet *ifp, struct bxe_fastpath *fp)
9377 struct bxe_softc *sc;
9378 struct mbuf *m = NULL;
9382 DBENTER(BXE_EXTREME_SEND);
9384 BXE_FP_LOCK_ASSERT(fp);
9386 /* Keep adding entries while there are frames to send. */
9387 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
9389 /* Check for any frames to send. */
9390 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
9391 if (__predict_false(m == NULL))
9394 /* The transmit mbuf now belongs to us, keep track of it. */
9395 fp->tx_mbuf_alloc++;
9398 * Pack the data into the transmit ring. If we
9399 * don't have room, place the mbuf back at the
9400 * head of the TX queue, set the OACTIVE flag,
9401 * and wait for the NIC to drain the chain.
9403 if (__predict_false(bxe_tx_encap(fp, &m))) {
9404 fp->tx_encap_failures++;
9405 /* Very Bad Frames(tm) may have been dropped. */
9408 * Mark the TX queue as full and return
9411 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
9412 IFQ_DRV_PREPEND(&ifp->if_snd, m);
9413 fp->tx_mbuf_alloc--;
9414 fp->tx_queue_xoff++;
9419 /* Stop looking for more work. */
9423 /* The transmit frame was enqueued successfully. */
9426 /* Send a copy of the frame to any BPF listeners. */
9430 /* No TX packets were dequeued. */
9432 /* Reset the TX watchdog timeout timer. */
9433 fp->watchdog_timer = BXE_TX_TIMEOUT;
9435 DBEXIT(BXE_EXTREME_SEND);
9438 #if __FreeBSD_version >= 800000
9440 * Multiqueue (RSS) dispatch routine.
9443 * 0 if transmit succeeds, !0 otherwise.
9446 bxe_tx_mq_start(struct ifnet *ifp, struct mbuf *m)
9448 struct bxe_softc *sc;
9449 struct bxe_fastpath *fp;
9453 DBENTER(BXE_EXTREME_SEND);
9457 /* If using flow ID, assign the TX queue based on the flow ID. */
9458 if ((m->m_flags & M_FLOWID) != 0)
9459 fp_index = m->m_pkthdr.flowid % sc->num_queues;
9461 /* Select the fastpath TX queue for the frame. */
9462 fp = &sc->fp[fp_index];
9464 /* Skip H/W enqueue if transmit queue is full or link down. */
9465 if (((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
9466 IFF_DRV_RUNNING) || !sc->link_vars.link_up) {
9467 /* Stash the mbuf if we can. */
9468 rc = drbr_enqueue(ifp, fp->br, m);
9469 goto bxe_tx_mq_start_exit;
9473 rc = bxe_tx_mq_start_locked(ifp, fp, m);
9476 bxe_tx_mq_start_exit:
9477 DBEXIT(BXE_EXTREME_SEND);
9483 * Multiqueue (TSS) transmit routine. This routine is responsible
9484 * for adding a frame to the hardware's transmit queue.
9487 * 0 if transmit succeeds, !0 otherwise.
9490 bxe_tx_mq_start_locked(struct ifnet *ifp,
9491 struct bxe_fastpath *fp, struct mbuf *m)
9493 struct bxe_softc *sc;
9495 int depth, rc, tx_count;
9498 DBENTER(BXE_EXTREME_SEND);
9502 /* Fetch the depth of the driver queue. */
9503 depth = drbr_inuse(ifp, fp->br);
9504 if (depth > fp->tx_max_drbr_queue_depth)
9505 fp->tx_max_drbr_queue_depth = depth;
9507 BXE_FP_LOCK_ASSERT(fp);
9510 rc = drbr_enqueue(ifp, fp->br, m);
9512 fp->tx_soft_errors++;
9513 goto bxe_tx_mq_start_locked_exit;
9516 /* Keep adding entries while there are frames to send. */
9517 while ((next = drbr_peek(ifp, fp->br)) != NULL) {
9518 /* The transmit mbuf now belongs to us, keep track of it. */
9519 fp->tx_mbuf_alloc++;
9522 * Pack the data into the transmit ring. If we
9523 * don't have room, place the mbuf back at the
9524 * head of the TX queue, set the OACTIVE flag,
9525 * and wait for the NIC to drain the chain.
9527 rc = bxe_tx_encap(fp, &next);
9528 if (__predict_false(rc != 0)) {
9529 fp->tx_encap_failures++;
9530 /* Very Bad Frames(tm) may have been dropped. */
9532 drbr_advance(ifp, fp->br);
9534 drbr_putback(ifp, fp->br, next);
9536 * Mark the TX queue as full and save
9539 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
9540 fp->tx_frame_deferred++;
9541 fp->tx_mbuf_alloc--;
9543 /* Stop looking for more work. */
9546 drbr_advance(ifp, fp->br);
9547 /* The transmit frame was enqueued successfully. */
9551 ifp->if_obytes += next->m_pkthdr.len;
9552 if (next->m_flags & M_MCAST)
9555 /* Send a copy of the frame to any BPF listeners. */
9556 BPF_MTAP(ifp, next);
9558 /* Handle any completions if we're running low. */
9559 if (fp->tx_bd_used >= BXE_TX_CLEANUP_THRESHOLD)
9562 /* Close TX since there's so little room left. */
9563 if (fp->tx_bd_used >= BXE_TX_CLEANUP_THRESHOLD) {
9564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
9569 /* No TX packets were dequeued. */
9571 /* Reset the TX watchdog timeout timer. */
9572 fp->watchdog_timer = BXE_TX_TIMEOUT;
9574 bxe_tx_mq_start_locked_exit:
9575 DBEXIT(BXE_EXTREME_SEND);
9581 bxe_mq_flush(struct ifnet *ifp)
9583 struct bxe_softc *sc;
9584 struct bxe_fastpath *fp;
9590 DBENTER(BXE_VERBOSE_UNLOAD);
9592 for (i = 0; i < sc->num_queues; i++) {
9595 if (fp->br != NULL) {
9596 DBPRINT(sc, BXE_VERBOSE_UNLOAD,
9597 "%s(): Clearing fp[%02d]...\n",
9598 __FUNCTION__, fp->index);
9601 while ((m = buf_ring_dequeue_sc(fp->br)) != NULL)
9609 DBEXIT(BXE_VERBOSE_UNLOAD);
9611 #endif /* FreeBSD_version >= 800000 */
9615 * Handles any IOCTL calls from the operating system.
9618 * 0 for success, positive value for failure.
9621 bxe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
9623 struct bxe_softc *sc;
9625 int error, mask, reinit;
9628 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_MISC);
9630 ifr = (struct ifreq *)data;
9637 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Received SIOCSIFMTU\n",
9640 /* Check that the MTU setting is supported. */
9641 if ((ifr->ifr_mtu < BXE_MIN_MTU) ||
9642 (ifr->ifr_mtu > BXE_JUMBO_MTU)) {
9648 ifp->if_mtu = ifr->ifr_mtu;
9649 BXE_CORE_UNLOCK(sc);
9654 /* Toggle the interface state up or down. */
9655 DBPRINT(sc, BXE_VERBOSE_MISC, "%s(): Received SIOCSIFFLAGS\n",
9659 /* Check if the interface is up. */
9660 if (ifp->if_flags & IFF_UP) {
9661 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
9662 /* Set promiscuous/multicast flags. */
9663 bxe_set_rx_mode(sc);
9666 bxe_init_locked(sc, LOAD_NORMAL);
9669 /* Bring down the interface. */
9670 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
9671 bxe_stop_locked(sc, UNLOAD_NORMAL);
9673 BXE_CORE_UNLOCK(sc);
9678 /* Add/Delete multicast addresses. */
9679 DBPRINT(sc, BXE_VERBOSE_MISC,
9680 "%s(): Received SIOCADDMULTI/SIOCDELMULTI\n", __FUNCTION__);
9683 /* Check if the interface is up. */
9684 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
9685 /* Set receive mode flags. */
9686 bxe_set_rx_mode(sc);
9687 BXE_CORE_UNLOCK(sc);
9692 /* Set/Get Interface media */
9693 DBPRINT(sc, BXE_VERBOSE_MISC,
9694 "%s(): Received SIOCSIFMEDIA/SIOCGIFMEDIA\n", __FUNCTION__);
9696 error = ifmedia_ioctl(ifp, ifr, &sc->bxe_ifmedia, command);
9699 /* Set interface capability */
9701 /* Find out which capabilities have changed. */
9702 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
9703 DBPRINT(sc, BXE_VERBOSE_MISC,
9704 "%s(): Received SIOCSIFCAP (mask = 0x%08X)\n", __FUNCTION__,
9709 /* Toggle the LRO capabilites enable flag. */
9710 if (mask & IFCAP_LRO) {
9711 ifp->if_capenable ^= IFCAP_LRO;
9712 sc->bxe_flags ^= BXE_TPA_ENABLE_FLAG;
9713 DBPRINT(sc, BXE_INFO_MISC,
9714 "%s(): Toggling LRO (bxe_flags = "
9715 "0x%08X).\n", __FUNCTION__, sc->bxe_flags);
9717 /* LRO requires different buffer setup. */
9721 /* Toggle the TX checksum capabilites enable flag. */
9722 if (mask & IFCAP_TXCSUM) {
9723 DBPRINT(sc, BXE_VERBOSE_MISC,
9724 "%s(): Toggling IFCAP_TXCSUM.\n", __FUNCTION__);
9726 ifp->if_capenable ^= IFCAP_TXCSUM;
9728 if (IFCAP_TXCSUM & ifp->if_capenable)
9729 ifp->if_hwassist = BXE_IF_HWASSIST;
9731 ifp->if_hwassist = 0;
9734 /* Toggle the RX checksum capabilities enable flag. */
9735 if (mask & IFCAP_RXCSUM) {
9736 DBPRINT(sc, BXE_VERBOSE_MISC,
9737 "%s(): Toggling IFCAP_RXCSUM.\n", __FUNCTION__);
9739 ifp->if_capenable ^= IFCAP_RXCSUM;
9741 if (IFCAP_RXCSUM & ifp->if_capenable)
9742 ifp->if_hwassist = BXE_IF_HWASSIST;
9744 ifp->if_hwassist = 0;
9747 /* Toggle VLAN_MTU capabilities enable flag. */
9748 if (mask & IFCAP_VLAN_MTU) {
9749 /* ToDo: Is this really true? */
9750 BXE_PRINTF("%s(%d): Changing VLAN_MTU not supported.\n",
9751 __FILE__, __LINE__);
9755 /* Toggle VLANHWTAG capabilities enabled flag. */
9756 if (mask & IFCAP_VLAN_HWTAGGING) {
9757 /* ToDo: Is this really true? */
9759 "%s(%d): Changing VLAN_HWTAGGING not supported!\n",
9760 __FILE__, __LINE__);
9764 /* Toggle TSO4 capabilities enabled flag. */
9765 if (mask & IFCAP_TSO4) {
9766 DBPRINT(sc, BXE_VERBOSE_MISC,
9767 "%s(): Toggling IFCAP_TSO4.\n", __FUNCTION__);
9769 ifp->if_capenable ^= IFCAP_TSO4;
9772 /* Toggle TSO6 capabilities enabled flag. */
9773 if (mask & IFCAP_TSO6) {
9774 /* ToDo: Add TSO6 support. */
9776 "%s(%d): Changing TSO6 not supported!\n",
9777 __FILE__, __LINE__);
9779 BXE_CORE_UNLOCK(sc);
9782 * ToDo: Look into supporting:
9787 * WOL[_UCAST|_MCAST|_MAGIC]
9792 /* We don't know how to handle the IOCTL, pass it on. */
9793 error = ether_ioctl(ifp, command, data);
9797 /* Restart the controller with the new capabilities. */
9798 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) && (reinit != 0)) {
9800 bxe_stop_locked(sc, UNLOAD_NORMAL);
9801 bxe_init_locked(sc, LOAD_NORMAL);
9802 BXE_CORE_UNLOCK(sc);
9805 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_MISC);
9811 * Gets the current value of the RX Completion Consumer index
9812 * from the fastpath status block, updates it as necessary if
9813 * it is pointing to a "Next Page" entry, and returns it to the
9817 * The adjusted value of *fp->rx_cons_sb.
9819 static __inline uint16_t
9820 bxe_rx_cq_cons(struct bxe_fastpath *fp)
9822 volatile uint16_t rx_cq_cons_sb = 0;
9825 rx_cq_cons_sb = (volatile uint16_t) le16toh(*fp->rx_cq_cons_sb);
9828 * It is valid for the hardware's copy of the completion
9829 * consumer index to be pointing at a "Next Page" entry in
9830 * the completion chain but the driver prefers to assume
9831 * that it is pointing at the next available CQE so we
9832 * need to adjust the value accordingly.
9834 if ((rx_cq_cons_sb & USABLE_RCQ_ENTRIES_PER_PAGE) ==
9835 USABLE_RCQ_ENTRIES_PER_PAGE)
9838 return (rx_cq_cons_sb);
9842 bxe_has_tx_work(struct bxe_fastpath *fp)
9846 return (((fp->tx_pkt_prod != le16toh(*fp->tx_pkt_cons_sb)) || \
9847 (fp->tx_pkt_prod != fp->tx_pkt_cons)));
9851 * Checks if there are any received frames to process on the
9855 * 0 = No received frames pending, !0 = Received frames
9859 bxe_has_rx_work(struct bxe_fastpath *fp)
9863 return (bxe_rx_cq_cons(fp) != fp->rx_cq_cons);
9867 * Slowpath task entry point.
9873 bxe_task_sp(void *xsc, int pending)
9875 struct bxe_softc *sc;
9880 DBPRINT(sc, BXE_EXTREME_INTR, "%s(): pending = %d.\n", __FUNCTION__,
9883 /* Check for the source of the interrupt. */
9884 sp_status = bxe_update_dsb_idx(sc);
9886 /* Handle any hardware attentions. */
9887 if (sp_status & 0x1) {
9892 /* CSTORM event asserted (query_stats, port delete ramrod, etc.). */
9893 if (sp_status & 0x2) {
9894 sc->stats_pending = 0;
9898 /* Check for other weirdness. */
9899 if (sp_status != 0) {
9900 DBPRINT(sc, BXE_WARN, "%s(): Unexpected slowpath interrupt "
9901 "(sp_status = 0x%04X)!\n", __FUNCTION__, sp_status);
9904 /* Acknowledge the xSTORM tags and enable slowpath interrupts. */
9905 bxe_ack_sb(sc, DEF_SB_ID, ATTENTION_ID, le16toh(sc->def_att_idx),
9907 bxe_ack_sb(sc, DEF_SB_ID, USTORM_ID, le16toh(sc->def_u_idx),
9909 bxe_ack_sb(sc, DEF_SB_ID, CSTORM_ID, le16toh(sc->def_c_idx),
9911 bxe_ack_sb(sc, DEF_SB_ID, XSTORM_ID, le16toh(sc->def_x_idx),
9913 bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, le16toh(sc->def_t_idx),
9919 * Legacy interrupt entry point.
9921 * Verifies that the controller generated the interrupt and
9922 * then calls a separate routine to handle the various
9923 * interrupt causes: link, RX, and TX.
9929 bxe_intr_legacy(void *xsc)
9931 struct bxe_softc *sc;
9932 struct bxe_fastpath *fp;
9933 uint32_t mask, fp_status;
9938 /* Don't handle any interrupts if we're not ready. */
9939 if (__predict_false(sc->intr_sem != 0))
9940 goto bxe_intr_legacy_exit;
9942 /* Bail out if the interrupt wasn't generated by our hardware. */
9943 fp_status = bxe_ack_int(sc);
9945 goto bxe_intr_legacy_exit;
9947 /* Handle the fastpath interrupt. */
9949 * sb_id = 0 for ustorm, 1 for cstorm.
9950 * The bits returned from ack_int() are 0-15,
9951 * bit 0=attention status block
9952 * bit 1=fast path status block
9953 * A mask of 0x2 or more = tx/rx event
9954 * A mask of 1 = slow path event
9957 mask = (0x2 << fp->sb_id);
9958 DBPRINT(sc, BXE_INSANE_INTR, "%s(): fp_status = 0x%08X, mask = "
9959 "0x%08X\n", __FUNCTION__, fp_status, mask);
9961 /* CSTORM event means fastpath completion. */
9962 if (fp_status & mask) {
9963 /* This interrupt must be ours, disable further interrupts. */
9964 bxe_ack_sb(sc, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
9966 taskqueue_enqueue(fp->tq, &fp->task);
9968 bxe_task_fp((void *)fp, 0);
9970 /* Clear this event from the status flags. */
9974 /* Handle all slow path interrupts and attentions */
9975 if (fp_status & 0x1) {
9976 /* Acknowledge and disable further slowpath interrupts. */
9977 bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
9979 /* Schedule the slowpath task. */
9980 taskqueue_enqueue(sc->tq, &sc->task);
9982 bxe_task_sp(xsc, 0);
9984 /* Clear this event from the status flags. */
9990 DBPRINT(sc, BXE_WARN,
9991 "%s(): Unexpected fastpath status (fp_status = 0x%08X)!\n",
9992 __FUNCTION__, fp_status);
9996 DBEXIT(BXE_EXTREME_INTR);
9998 bxe_intr_legacy_exit:
10003 * Slowpath interrupt entry point.
10005 * Acknowledge the interrupt and schedule a slowpath task.
10011 bxe_intr_sp(void *xsc)
10013 struct bxe_softc *sc;
10017 DBPRINT(sc, BXE_INSANE_INTR, "%s(%d): Slowpath interrupt.\n",
10018 __FUNCTION__, curcpu);
10020 /* Don't handle any interrupts if we're not ready. */
10021 if (__predict_false(sc->intr_sem != 0))
10022 goto bxe_intr_sp_exit;
10024 /* Acknowledge and disable further slowpath interrupts. */
10025 bxe_ack_sb(sc, DEF_SB_ID, TSTORM_ID, 0, IGU_INT_DISABLE, 0);
10028 /* Schedule the slowpath task. */
10029 taskqueue_enqueue(sc->tq, &sc->task);
10031 bxe_task_sp(xsc, 0);
10039 * Fastpath interrupt entry point.
10041 * Acknowledge the interrupt and schedule a fastpath task.
10047 bxe_intr_fp (void *xfp)
10049 struct bxe_fastpath *fp;
10050 struct bxe_softc *sc;
10055 DBPRINT(sc, BXE_INSANE_INTR,
10056 "%s(%d): fp[%02d].sb_id = %d interrupt.\n",
10057 __FUNCTION__, curcpu, fp->index, fp->sb_id);
10059 /* Don't handle any interrupts if we're not ready. */
10060 if (__predict_false(sc->intr_sem != 0))
10061 goto bxe_intr_fp_exit;
10063 /* Disable further interrupts. */
10064 bxe_ack_sb(sc, fp->sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
10066 taskqueue_enqueue(fp->tq, &fp->task);
10068 bxe_task_fp (xfp, 0);
10076 * Fastpath task entry point.
10078 * Handle any pending transmit or receive events.
10084 bxe_task_fp (void *xfp, int pending)
10086 struct bxe_fastpath *fp;
10087 struct bxe_softc *sc;
10092 DBPRINT(sc, BXE_EXTREME_INTR, "%s(%d): Fastpath task on fp[%02d]"
10093 ".sb_id = %d\n", __FUNCTION__, curcpu, fp->index, fp->sb_id);
10095 /* Update the fast path indices */
10096 bxe_update_fpsb_idx(fp);
10098 /* Service any completed TX frames. */
10099 if (bxe_has_tx_work(fp)) {
10105 /* Service any completed RX frames. */
10109 /* Acknowledge the fastpath status block indices. */
10110 bxe_ack_sb(sc, fp->sb_id, USTORM_ID, fp->fp_u_idx, IGU_INT_NOP, 1);
10111 bxe_ack_sb(sc, fp->sb_id, CSTORM_ID, fp->fp_c_idx, IGU_INT_ENABLE, 1);
10115 * Clears the fastpath (per-queue) status block.
10121 bxe_zero_sb(struct bxe_softc *sc, int sb_id)
10125 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10126 port = BP_PORT(sc);
10129 bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
10130 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), 0,
10131 CSTORM_SB_STATUS_BLOCK_U_SIZE / 4);
10132 bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
10133 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), 0,
10134 CSTORM_SB_STATUS_BLOCK_C_SIZE / 4);
10136 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10140 * Initialize the fastpath (per queue) status block.
10146 bxe_init_sb(struct bxe_softc *sc, struct host_status_block *sb,
10147 bus_addr_t mapping, int sb_id)
10150 int func, index, port;
10152 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10154 port = BP_PORT(sc);
10155 func = BP_FUNC(sc);
10157 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
10158 "%s(): Initializing sb_id = %d on port %d, function %d.\n",
10159 __FUNCTION__, sb_id, port, func);
10161 /* Setup the USTORM status block. */
10162 section = ((uint64_t)mapping) + offsetof(struct host_status_block,
10164 sb->u_status_block.status_block_id = sb_id;
10166 REG_WR(sc, BAR_CSTORM_INTMEM +
10167 CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id), U64_LO(section));
10168 REG_WR(sc, BAR_CSTORM_INTMEM +
10169 ((CSTORM_SB_HOST_SB_ADDR_U_OFFSET(port, sb_id)) + 4),
10171 REG_WR8(sc, BAR_CSTORM_INTMEM + FP_USB_FUNC_OFF +
10172 CSTORM_SB_HOST_STATUS_BLOCK_U_OFFSET(port, sb_id), func);
10174 for (index = 0; index < HC_USTORM_SB_NUM_INDICES; index++)
10175 REG_WR16(sc, BAR_CSTORM_INTMEM +
10176 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id, index), 0x1);
10178 /* Setup the CSTORM status block. */
10179 section = ((uint64_t)mapping) + offsetof(struct host_status_block,
10181 sb->c_status_block.status_block_id = sb_id;
10183 /* Write the status block address to CSTORM. Order is important! */
10184 REG_WR(sc, BAR_CSTORM_INTMEM +
10185 CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id), U64_LO(section));
10186 REG_WR(sc, BAR_CSTORM_INTMEM +
10187 ((CSTORM_SB_HOST_SB_ADDR_C_OFFSET(port, sb_id)) + 4),
10189 REG_WR8(sc, BAR_CSTORM_INTMEM + FP_CSB_FUNC_OFF +
10190 CSTORM_SB_HOST_STATUS_BLOCK_C_OFFSET(port, sb_id), func);
10192 for (index = 0; index < HC_CSTORM_SB_NUM_INDICES; index++)
10193 REG_WR16(sc, BAR_CSTORM_INTMEM +
10194 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id, index), 0x1);
10196 /* Enable interrupts. */
10197 bxe_ack_sb(sc, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
10199 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10203 * Clears the default status block.
10209 bxe_zero_def_sb(struct bxe_softc *sc)
10213 func = BP_FUNC(sc);
10215 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10216 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
10217 "%s(): Clearing default status block on function %d.\n",
10218 __FUNCTION__, func);
10220 /* Fill the STORM's copy of the default status block with 0. */
10221 bxe_init_fill(sc, TSEM_REG_FAST_MEMORY +
10222 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
10223 sizeof(struct tstorm_def_status_block) / 4);
10224 bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
10225 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), 0,
10226 sizeof(struct cstorm_def_status_block_u) / 4);
10227 bxe_init_fill(sc, CSEM_REG_FAST_MEMORY +
10228 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), 0,
10229 sizeof(struct cstorm_def_status_block_c) / 4);
10230 bxe_init_fill(sc, XSEM_REG_FAST_MEMORY +
10231 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), 0,
10232 sizeof(struct xstorm_def_status_block) / 4);
10234 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10238 * Initialize default status block.
10244 bxe_init_def_sb(struct bxe_softc *sc, struct host_def_status_block *def_sb,
10245 bus_addr_t mapping, int sb_id)
10248 int func, index, port, reg_offset, val;
10250 port = BP_PORT(sc);
10251 func = BP_FUNC(sc);
10253 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10254 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR),
10255 "%s(): Initializing default status block on port %d, function %d.\n",
10256 __FUNCTION__, port, func);
10258 /* Setup the default status block (DSB). */
10259 section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
10260 atten_status_block);
10261 def_sb->atten_status_block.status_block_id = sb_id;
10262 sc->attn_state = 0;
10263 sc->def_att_idx = 0;
10266 * Read routing configuration for attn signal
10267 * output of groups. Currently, only groups
10268 * 0 through 3 are wired.
10270 reg_offset = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
10271 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
10273 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
10274 sc->attn_group[index].sig[0] = REG_RD(sc, reg_offset +
10276 sc->attn_group[index].sig[1] = REG_RD(sc, reg_offset +
10277 0x10 * index + 0x4);
10278 sc->attn_group[index].sig[2] = REG_RD(sc, reg_offset +
10279 0x10 * index + 0x8);
10280 sc->attn_group[index].sig[3] = REG_RD(sc, reg_offset +
10281 0x10 * index + 0xc);
10283 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET |
10285 "%s(): attn_group[%d] = 0x%08X 0x%08X 0x%08x 0X%08x\n",
10286 __FUNCTION__, index, sc->attn_group[index].sig[0],
10287 sc->attn_group[index].sig[1], sc->attn_group[index].sig[2],
10288 sc->attn_group[index].sig[3]);
10291 reg_offset = port ? HC_REG_ATTN_MSG1_ADDR_L : HC_REG_ATTN_MSG0_ADDR_L;
10293 REG_WR(sc, reg_offset, U64_LO(section));
10294 REG_WR(sc, reg_offset + 4, U64_HI(section));
10296 reg_offset = port ? HC_REG_ATTN_NUM_P1 : HC_REG_ATTN_NUM_P0;
10298 val = REG_RD(sc, reg_offset);
10300 REG_WR(sc, reg_offset, val);
10303 section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
10304 u_def_status_block);
10305 def_sb->u_def_status_block.status_block_id = sb_id;
10308 REG_WR(sc, BAR_CSTORM_INTMEM +
10309 CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func), U64_LO(section));
10310 REG_WR(sc, BAR_CSTORM_INTMEM +
10311 ((CSTORM_DEF_SB_HOST_SB_ADDR_U_OFFSET(func)) + 4), U64_HI(section));
10312 REG_WR8(sc, BAR_CSTORM_INTMEM + DEF_USB_FUNC_OFF +
10313 CSTORM_DEF_SB_HOST_STATUS_BLOCK_U_OFFSET(func), func);
10315 for (index = 0; index < HC_USTORM_DEF_SB_NUM_INDICES; index++)
10316 REG_WR16(sc, BAR_CSTORM_INTMEM +
10317 CSTORM_DEF_SB_HC_DISABLE_U_OFFSET(func, index), 1);
10320 section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
10321 c_def_status_block);
10322 def_sb->c_def_status_block.status_block_id = sb_id;
10325 REG_WR(sc, BAR_CSTORM_INTMEM +
10326 CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func), U64_LO(section));
10327 REG_WR(sc, BAR_CSTORM_INTMEM +
10328 ((CSTORM_DEF_SB_HOST_SB_ADDR_C_OFFSET(func)) + 4), U64_HI(section));
10329 REG_WR8(sc, BAR_CSTORM_INTMEM + DEF_CSB_FUNC_OFF +
10330 CSTORM_DEF_SB_HOST_STATUS_BLOCK_C_OFFSET(func), func);
10332 for (index = 0; index < HC_CSTORM_DEF_SB_NUM_INDICES; index++)
10333 REG_WR16(sc, BAR_CSTORM_INTMEM +
10334 CSTORM_DEF_SB_HC_DISABLE_C_OFFSET(func, index), 1);
10337 section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
10338 t_def_status_block);
10339 def_sb->t_def_status_block.status_block_id = sb_id;
10342 REG_WR(sc, BAR_TSTORM_INTMEM +
10343 TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
10344 REG_WR(sc, BAR_TSTORM_INTMEM +
10345 ((TSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section));
10346 REG_WR8(sc, BAR_TSTORM_INTMEM + DEF_TSB_FUNC_OFF +
10347 TSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
10349 for (index = 0; index < HC_TSTORM_DEF_SB_NUM_INDICES; index++)
10350 REG_WR16(sc, BAR_TSTORM_INTMEM +
10351 TSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
10354 section = ((uint64_t)mapping) + offsetof(struct host_def_status_block,
10355 x_def_status_block);
10356 def_sb->x_def_status_block.status_block_id = sb_id;
10359 REG_WR(sc, BAR_XSTORM_INTMEM +
10360 XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func), U64_LO(section));
10361 REG_WR(sc, BAR_XSTORM_INTMEM +
10362 ((XSTORM_DEF_SB_HOST_SB_ADDR_OFFSET(func)) + 4), U64_HI(section));
10363 REG_WR8(sc, BAR_XSTORM_INTMEM + DEF_XSB_FUNC_OFF +
10364 XSTORM_DEF_SB_HOST_STATUS_BLOCK_OFFSET(func), func);
10366 for (index = 0; index < HC_XSTORM_DEF_SB_NUM_INDICES; index++)
10367 REG_WR16(sc, BAR_XSTORM_INTMEM +
10368 XSTORM_DEF_SB_HC_DISABLE_OFFSET(func, index), 1);
10370 sc->stats_pending = 0;
10371 sc->set_mac_pending = 0;
10373 bxe_ack_sb(sc, sb_id, CSTORM_ID, 0, IGU_INT_ENABLE, 0);
10375 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_INTR);
10379 * Update interrupt coalescing parameters.
10385 bxe_update_coalesce(struct bxe_softc *sc)
10387 int i, port, sb_id;
10389 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10391 port = BP_PORT(sc);
10392 /* Cycle through each fastpath queue and set the coalescing values. */
10393 for (i = 0; i < sc->num_queues; i++) {
10394 sb_id = sc->fp[i].sb_id;
10396 /* Receive interrupt coalescing is done on USTORM. */
10397 REG_WR8(sc, BAR_CSTORM_INTMEM +
10398 CSTORM_SB_HC_TIMEOUT_U_OFFSET(port, sb_id,
10399 U_SB_ETH_RX_CQ_INDEX), sc->rx_ticks / (BXE_BTR * 4));
10401 REG_WR16(sc, BAR_CSTORM_INTMEM +
10402 CSTORM_SB_HC_DISABLE_U_OFFSET(port, sb_id,
10403 U_SB_ETH_RX_CQ_INDEX),
10404 (sc->rx_ticks / (BXE_BTR * 4)) ? 0 : 1);
10406 /* Transmit interrupt coalescing is done on CSTORM. */
10407 REG_WR8(sc, BAR_CSTORM_INTMEM +
10408 CSTORM_SB_HC_TIMEOUT_C_OFFSET(port, sb_id,
10409 C_SB_ETH_TX_CQ_INDEX), sc->tx_ticks / (BXE_BTR * 4));
10410 REG_WR16(sc, BAR_CSTORM_INTMEM +
10411 CSTORM_SB_HC_DISABLE_C_OFFSET(port, sb_id,
10412 C_SB_ETH_TX_CQ_INDEX),
10413 (sc->tx_ticks / (BXE_BTR * 4)) ? 0 : 1);
10416 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10420 * Allocate an mbuf and assign it to the TPA pool.
10423 * 0 = Success, !0 = Failure
10426 * fp->tpa_mbuf_ptr[queue]
10427 * fp->tpa_mbuf_map[queue]
10428 * fp->tpa_mbuf_segs[queue]
10431 bxe_alloc_tpa_mbuf(struct bxe_fastpath *fp, int queue)
10433 struct bxe_softc *sc;
10434 bus_dma_segment_t segs[1];
10440 DBENTER(BXE_INSANE_TPA);
10443 DBRUNIF((fp->disable_tpa == TRUE),
10444 BXE_PRINTF("%s(): fp[%02d] TPA disabled!\n",
10445 __FUNCTION__, fp->index));
10448 /* Simulate an mbuf allocation failure. */
10449 if (DB_RANDOMTRUE(bxe_debug_mbuf_allocation_failure)) {
10450 sc->debug_sim_mbuf_alloc_failed++;
10451 fp->mbuf_tpa_alloc_failed++;
10453 goto bxe_alloc_tpa_mbuf_exit;
10457 /* Allocate the new TPA mbuf. */
10458 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->mbuf_alloc_size);
10459 if (__predict_false(m == NULL)) {
10460 fp->mbuf_tpa_alloc_failed++;
10462 goto bxe_alloc_tpa_mbuf_exit;
10465 DBRUN(fp->tpa_mbuf_alloc++);
10467 /* Initialize the mbuf buffer length. */
10468 m->m_pkthdr.len = m->m_len = sc->mbuf_alloc_size;
10471 /* Simulate an mbuf mapping failure. */
10472 if (DB_RANDOMTRUE(bxe_debug_dma_map_addr_failure)) {
10473 sc->debug_sim_mbuf_map_failed++;
10474 fp->mbuf_tpa_mapping_failed++;
10476 DBRUN(fp->tpa_mbuf_alloc--);
10478 goto bxe_alloc_tpa_mbuf_exit;
10482 /* Map the TPA mbuf into non-paged pool. */
10483 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
10484 fp->tpa_mbuf_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT);
10485 if (__predict_false(rc != 0)) {
10486 fp->mbuf_tpa_mapping_failed++;
10488 DBRUN(fp->tpa_mbuf_alloc--);
10489 goto bxe_alloc_tpa_mbuf_exit;
10492 /* All mubfs must map to a single segment. */
10493 KASSERT(nsegs == 1, ("%s(): Too many segments (%d) returned!",
10494 __FUNCTION__, nsegs));
10496 /* Release any existing TPA mbuf mapping. */
10497 if (fp->tpa_mbuf_map[queue] != NULL) {
10498 bus_dmamap_sync(fp->rx_mbuf_tag,
10499 fp->tpa_mbuf_map[queue], BUS_DMASYNC_POSTREAD);
10500 bus_dmamap_unload(fp->rx_mbuf_tag,
10501 fp->tpa_mbuf_map[queue]);
10504 /* Save the mbuf and mapping info for the TPA mbuf. */
10505 map = fp->tpa_mbuf_map[queue];
10506 fp->tpa_mbuf_map[queue] = fp->tpa_mbuf_spare_map;
10507 fp->tpa_mbuf_spare_map = map;
10508 bus_dmamap_sync(fp->rx_mbuf_tag,
10509 fp->tpa_mbuf_map[queue], BUS_DMASYNC_PREREAD);
10510 fp->tpa_mbuf_ptr[queue] = m;
10511 fp->tpa_mbuf_segs[queue] = segs[0];
10513 bxe_alloc_tpa_mbuf_exit:
10514 DBEXIT(BXE_INSANE_TPA);
10519 * Allocate mbufs for a fastpath TPA pool.
10522 * 0 = Success, !0 = Failure.
10529 bxe_fill_tpa_pool(struct bxe_fastpath *fp)
10531 struct bxe_softc *sc;
10532 int max_agg_queues, queue, rc;
10535 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10538 if (!TPA_ENABLED(sc)) {
10539 fp->disable_tpa = TRUE;
10540 goto bxe_fill_tpa_pool_exit;
10543 max_agg_queues = CHIP_IS_E1(sc) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
10544 ETH_MAX_AGGREGATION_QUEUES_E1H;
10546 /* Assume the fill operation worked. */
10547 fp->disable_tpa = FALSE;
10549 /* Fill the TPA pool. */
10550 for (queue = 0; queue < max_agg_queues; queue++) {
10551 rc = bxe_alloc_tpa_mbuf(fp, queue);
10554 "%s(%d): fp[%02d] TPA disabled!\n",
10555 __FILE__, __LINE__, fp->index);
10556 fp->disable_tpa = TRUE;
10559 fp->tpa_state[queue] = BXE_TPA_STATE_STOP;
10562 bxe_fill_tpa_pool_exit:
10563 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10568 * Free all mbufs from a fastpath TPA pool.
10574 * fp->tpa_mbuf_ptr[]
10575 * fp->tpa_mbuf_map[]
10576 * fp->tpa_mbuf_alloc
10579 bxe_free_tpa_pool(struct bxe_fastpath *fp)
10581 struct bxe_softc *sc;
10582 int i, max_agg_queues;
10585 DBENTER(BXE_INSANE_LOAD | BXE_INSANE_UNLOAD | BXE_INSANE_TPA);
10587 if (fp->rx_mbuf_tag == NULL)
10588 goto bxe_free_tpa_pool_exit;
10590 max_agg_queues = CHIP_IS_E1H(sc) ?
10591 ETH_MAX_AGGREGATION_QUEUES_E1H :
10592 ETH_MAX_AGGREGATION_QUEUES_E1;
10594 /* Release all mbufs and and all DMA maps in the TPA pool. */
10595 for (i = 0; i < max_agg_queues; i++) {
10596 if (fp->tpa_mbuf_map[i] != NULL) {
10597 bus_dmamap_sync(fp->rx_mbuf_tag, fp->tpa_mbuf_map[i],
10598 BUS_DMASYNC_POSTREAD);
10599 bus_dmamap_unload(fp->rx_mbuf_tag, fp->tpa_mbuf_map[i]);
10602 if (fp->tpa_mbuf_ptr[i] != NULL) {
10603 m_freem(fp->tpa_mbuf_ptr[i]);
10604 DBRUN(fp->tpa_mbuf_alloc--);
10605 fp->tpa_mbuf_ptr[i] = NULL;
10609 bxe_free_tpa_pool_exit:
10610 DBEXIT(BXE_INSANE_LOAD | BXE_INSANE_UNLOAD | BXE_INSANE_TPA);
10614 * Allocate an mbuf and assign it to the receive scatter gather chain.
10615 * The caller must take care to save a copy of the existing mbuf in the
10619 * 0 = Success, !0= Failure.
10622 * fp->sg_chain[index]
10623 * fp->rx_sge_buf_ptr[index]
10624 * fp->rx_sge_buf_map[index]
10625 * fp->rx_sge_spare_map
10628 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, uint16_t index)
10630 struct bxe_softc *sc;
10631 struct eth_rx_sge *sge;
10632 bus_dma_segment_t segs[1];
10638 DBENTER(BXE_INSANE_TPA);
10642 /* Simulate an mbuf allocation failure. */
10643 if (DB_RANDOMTRUE(bxe_debug_mbuf_allocation_failure)) {
10644 sc->debug_sim_mbuf_alloc_failed++;
10645 fp->mbuf_sge_alloc_failed++;
10647 goto bxe_alloc_rx_sge_mbuf_exit;
10651 /* Allocate a new SGE mbuf. */
10652 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE);
10653 if (__predict_false(m == NULL)) {
10654 fp->mbuf_sge_alloc_failed++;
10656 goto bxe_alloc_rx_sge_mbuf_exit;
10659 DBRUN(fp->sge_mbuf_alloc++);
10661 /* Initialize the mbuf buffer length. */
10662 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE;
10665 /* Simulate an mbuf mapping failure. */
10666 if (DB_RANDOMTRUE(bxe_debug_dma_map_addr_failure)) {
10667 sc->debug_sim_mbuf_map_failed++;
10668 fp->mbuf_sge_mapping_failed++;
10670 DBRUN(fp->sge_mbuf_alloc--);
10672 goto bxe_alloc_rx_sge_mbuf_exit;
10676 /* Map the SGE mbuf into non-paged pool. */
10677 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_buf_tag,
10678 fp->rx_sge_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT);
10679 if (__predict_false(rc != 0)) {
10680 fp->mbuf_sge_mapping_failed++;
10682 DBRUN(fp->sge_mbuf_alloc--);
10683 goto bxe_alloc_rx_sge_mbuf_exit;
10686 /* All mubfs must map to a single segment. */
10687 KASSERT(nsegs == 1, ("%s(): Too many segments (%d) returned!",
10688 __FUNCTION__, nsegs));
10690 /* Unload any existing SGE mbuf mapping. */
10691 if (fp->rx_sge_buf_map[index] != NULL) {
10692 bus_dmamap_sync(fp->rx_sge_buf_tag,
10693 fp->rx_sge_buf_map[index], BUS_DMASYNC_POSTREAD);
10694 bus_dmamap_unload(fp->rx_sge_buf_tag,
10695 fp->rx_sge_buf_map[index]);
10698 /* Add the new SGE mbuf to the SGE ring. */
10699 map = fp->rx_sge_buf_map[index];
10700 fp->rx_sge_buf_map[index] = fp->rx_sge_spare_map;
10701 fp->rx_sge_spare_map = map;
10702 bus_dmamap_sync(fp->rx_sge_buf_tag,
10703 fp->rx_sge_buf_map[index], BUS_DMASYNC_PREREAD);
10704 fp->rx_sge_buf_ptr[index] = m;
10705 sge = &fp->sg_chain[index];
10706 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr));
10707 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr));
10709 bxe_alloc_rx_sge_mbuf_exit:
10710 DBEXIT(BXE_INSANE_TPA);
10715 * Allocate mbufs for a SGE chain.
10718 * 0 = Success, !0 = Failure.
10725 bxe_fill_sg_chain(struct bxe_fastpath *fp)
10727 struct bxe_softc *sc;
10733 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10736 if (!TPA_ENABLED(sc)) {
10737 fp->disable_tpa = TRUE;
10738 goto bxe_fill_sg_chain_exit;
10741 /* Assume the fill operation works. */
10742 fp->disable_tpa = FALSE;
10744 /* Fill the RX SGE chain. */
10746 for (i = 0; i < USABLE_RX_SGE; i++) {
10747 rc = bxe_alloc_rx_sge_mbuf(fp, index);
10750 "%s(%d): fp[%02d] SGE memory allocation failure!\n",
10751 __FILE__, __LINE__, fp->index);
10753 fp->disable_tpa = TRUE;
10756 index = NEXT_SGE_IDX(index);
10759 /* Update the driver's copy of the RX SGE producer index. */
10760 fp->rx_sge_prod = index;
10762 bxe_fill_sg_chain_exit:
10763 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10768 * Free all elements from the receive scatter gather chain.
10774 * fp->rx_sge_buf_ptr[]
10775 * fp->rx_sge_buf_map[]
10776 * fp->sge_mbuf_alloc
10779 bxe_free_sg_chain(struct bxe_fastpath *fp)
10781 struct bxe_softc *sc;
10785 DBENTER(BXE_INSANE_TPA);
10787 if (fp->rx_sge_buf_tag == NULL)
10788 goto bxe_free_sg_chain_exit;
10790 /* Free all mbufs and unload all maps. */
10791 for (i = 0; i < TOTAL_RX_SGE; i++) {
10792 /* Free the map and the mbuf if they're allocated. */
10793 if (fp->rx_sge_buf_map[i] != NULL) {
10794 bus_dmamap_sync(fp->rx_sge_buf_tag,
10795 fp->rx_sge_buf_map[i], BUS_DMASYNC_POSTREAD);
10796 bus_dmamap_unload(fp->rx_sge_buf_tag,
10797 fp->rx_sge_buf_map[i]);
10800 if (fp->rx_sge_buf_ptr[i] != NULL) {
10801 m_freem(fp->rx_sge_buf_ptr[i]);
10802 DBRUN(fp->sge_mbuf_alloc--);
10803 fp->rx_sge_buf_ptr[i] = NULL;
10807 bxe_free_sg_chain_exit:
10808 DBEXIT(BXE_INSANE_TPA);
10812 * Allocate an mbuf, if necessary, and add it to the receive chain.
10815 * 0 = Success, !0 = Failure.
10818 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, uint16_t index)
10820 struct bxe_softc *sc;
10821 struct eth_rx_bd *rx_bd;
10822 bus_dma_segment_t segs[1];
10828 DBENTER(BXE_INSANE_LOAD | BXE_INSANE_RESET | BXE_INSANE_RECV);
10832 /* Simulate an mbuf allocation failure. */
10833 if (DB_RANDOMTRUE(bxe_debug_mbuf_allocation_failure)) {
10834 sc->debug_sim_mbuf_alloc_failed++;
10835 fp->mbuf_rx_bd_alloc_failed++;
10837 goto bxe_alloc_rx_bd_mbuf_exit;
10841 /* Allocate the new RX BD mbuf. */
10842 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, sc->mbuf_alloc_size);
10843 if (__predict_false(m == NULL)) {
10844 fp->mbuf_rx_bd_alloc_failed++;
10846 goto bxe_alloc_rx_bd_mbuf_exit;
10849 DBRUN(fp->rx_mbuf_alloc++);
10851 /* Initialize the mbuf buffer length. */
10852 m->m_pkthdr.len = m->m_len = sc->mbuf_alloc_size;
10855 /* Simulate an mbuf mapping failure. */
10856 if (DB_RANDOMTRUE(bxe_debug_dma_map_addr_failure)) {
10857 sc->debug_sim_mbuf_map_failed++;
10858 fp->mbuf_rx_bd_mapping_failed++;
10860 DBRUN(fp->rx_mbuf_alloc--);
10862 goto bxe_alloc_rx_bd_mbuf_exit;
10866 /* Map the TPA mbuf into non-paged pool. */
10867 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag,
10868 fp->rx_mbuf_spare_map, m, segs, &nsegs, BUS_DMA_NOWAIT);
10869 if (__predict_false(rc != 0)) {
10870 fp->mbuf_rx_bd_mapping_failed++;
10872 DBRUN(fp->rx_mbuf_alloc--);
10873 goto bxe_alloc_rx_bd_mbuf_exit;
10876 /* All mubfs must map to a single segment. */
10877 KASSERT(nsegs == 1, ("%s(): Too many segments (%d) returned!",
10878 __FUNCTION__, nsegs));
10880 /* Release any existing RX BD mbuf mapping. */
10881 if (fp->rx_mbuf_map[index] != NULL) {
10882 bus_dmamap_sync(fp->rx_mbuf_tag,
10883 fp->rx_mbuf_map[index], BUS_DMASYNC_POSTREAD);
10884 bus_dmamap_unload(fp->rx_mbuf_tag,
10885 fp->rx_mbuf_map[index]);
10888 /* Save the mbuf and mapping info. */
10889 map = fp->rx_mbuf_map[index];
10890 fp->rx_mbuf_map[index] = fp->rx_mbuf_spare_map;
10891 fp->rx_mbuf_spare_map = map;
10892 bus_dmamap_sync(fp->rx_mbuf_tag,
10893 fp->rx_mbuf_map[index], BUS_DMASYNC_PREREAD);
10894 fp->rx_mbuf_ptr[index] = m;
10895 rx_bd = &fp->rx_chain[index];
10896 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr));
10897 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr));
10899 bxe_alloc_rx_bd_mbuf_exit:
10900 DBEXIT(BXE_INSANE_LOAD | BXE_INSANE_RESET | BXE_INSANE_RECV);
10907 * Allocate mbufs for a receive chain.
10910 * 0 = Success, !0 = Failure.
10916 bxe_fill_rx_bd_chain(struct bxe_fastpath *fp)
10918 struct bxe_softc *sc;
10923 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10926 /* Allocate buffers for all the RX BDs in RX BD Chain. */
10927 for (i = 0; i < USABLE_RX_BD; i++) {
10928 rc = bxe_alloc_rx_bd_mbuf(fp, index);
10931 "%s(%d): Memory allocation failure! Cannot fill fp[%02d] RX chain.\n",
10932 __FILE__, __LINE__, fp->index);
10936 index = NEXT_RX_BD(index);
10939 fp->rx_bd_prod = index;
10940 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10945 * Free all buffers from the receive chain.
10951 * fp->rx_mbuf_ptr[]
10952 * fp->rx_mbuf_map[]
10953 * fp->rx_mbuf_alloc
10956 bxe_free_rx_bd_chain(struct bxe_fastpath *fp)
10958 struct bxe_softc *sc;
10962 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10964 if (fp->rx_mbuf_tag == NULL)
10965 goto bxe_free_rx_bd_chain_exit;
10967 /* Free all mbufs and unload all maps. */
10968 for (i = 0; i < TOTAL_RX_BD; i++) {
10969 if (fp->rx_mbuf_map[i] != NULL) {
10970 bus_dmamap_sync(fp->rx_mbuf_tag, fp->rx_mbuf_map[i],
10971 BUS_DMASYNC_POSTREAD);
10972 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_map[i]);
10975 if (fp->rx_mbuf_ptr[i] != NULL) {
10976 m_freem(fp->rx_mbuf_ptr[i]);
10977 DBRUN(fp->rx_mbuf_alloc--);
10978 fp->rx_mbuf_ptr[i] = NULL;
10982 bxe_free_rx_bd_chain_exit:
10983 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
10987 * Setup mutexes used by the driver.
10993 bxe_mutexes_alloc(struct bxe_softc *sc)
10995 struct bxe_fastpath *fp;
10998 DBENTER(BXE_VERBOSE_LOAD);
11000 BXE_CORE_LOCK_INIT(sc, device_get_nameunit(sc->dev));
11001 BXE_SP_LOCK_INIT(sc, "bxe_sp_lock");
11002 BXE_DMAE_LOCK_INIT(sc, "bxe_dmae_lock");
11003 BXE_PHY_LOCK_INIT(sc, "bxe_phy_lock");
11004 BXE_FWMB_LOCK_INIT(sc, "bxe_fwmb_lock");
11005 BXE_PRINT_LOCK_INIT(sc, "bxe_print_lock");
11007 /* Allocate one mutex for each fastpath structure. */
11008 for (i = 0; i < sc->num_queues; i++ ) {
11011 /* Allocate per fastpath mutexes. */
11012 snprintf(fp->mtx_name, sizeof(fp->mtx_name), "%s:fp[%02d]",
11013 device_get_nameunit(sc->dev), fp->index);
11014 mtx_init(&fp->mtx, fp->mtx_name, NULL, MTX_DEF);
11017 DBEXIT(BXE_VERBOSE_LOAD);
11021 * Free mutexes used by the driver.
11027 bxe_mutexes_free(struct bxe_softc *sc)
11029 struct bxe_fastpath *fp;
11032 DBENTER(BXE_VERBOSE_UNLOAD);
11034 for (i = 0; i < sc->num_queues; i++ ) {
11037 /* Release per fastpath mutexes. */
11038 if (mtx_initialized(&fp->mtx))
11039 mtx_destroy(&fp->mtx);
11042 BXE_PRINT_LOCK_DESTROY(sc);
11043 BXE_FWMB_LOCK_DESTROY(sc);
11044 BXE_PHY_LOCK_DESTROY(sc);
11045 BXE_DMAE_LOCK_DESTROY(sc);
11046 BXE_SP_LOCK_DESTROY(sc);
11047 BXE_CORE_LOCK_DESTROY(sc);
11049 DBEXIT(BXE_VERBOSE_UNLOAD);
11054 * Free memory and clear the RX data structures.
11060 bxe_clear_rx_chains(struct bxe_softc *sc)
11062 struct bxe_fastpath *fp;
11065 DBENTER(BXE_VERBOSE_RESET);
11067 for (i = 0; i < sc->num_queues; i++) {
11070 /* Free all RX buffers. */
11071 bxe_free_rx_bd_chain(fp);
11072 bxe_free_tpa_pool(fp);
11073 bxe_free_sg_chain(fp);
11075 /* Check if any mbufs lost in the process. */
11076 DBRUNIF((fp->tpa_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
11077 "%s(): Memory leak! Lost %d mbufs from fp[%02d] TPA pool!\n",
11078 __FUNCTION__, fp->tpa_mbuf_alloc, fp->index));
11079 DBRUNIF((fp->sge_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
11080 "%s(): Memory leak! Lost %d mbufs from fp[%02d] SGE chain!\n",
11081 __FUNCTION__, fp->sge_mbuf_alloc, fp->index));
11082 DBRUNIF((fp->rx_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
11083 "%s(): Memory leak! Lost %d mbufs from fp[%02d] RX chain!\n",
11084 __FUNCTION__, fp->rx_mbuf_alloc, fp->index));
11087 DBEXIT(BXE_VERBOSE_RESET);
11091 * Initialize the receive rings.
11097 bxe_init_rx_chains(struct bxe_softc *sc)
11099 struct bxe_fastpath *fp;
11102 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11104 func = BP_FUNC(sc);
11106 /* Allocate memory for RX and CQ chains. */
11107 for (i = 0; i < sc->num_queues; i++) {
11109 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
11110 "%s(): Initializing fp[%02d] RX chain.\n", __FUNCTION__, i);
11112 fp->rx_bd_cons = fp->rx_bd_prod = 0;
11113 fp->rx_cq_cons = fp->rx_cq_prod = 0;
11115 /* Pointer to status block's CQ consumer index. */
11116 fp->rx_cq_cons_sb = &fp->status_block->
11117 u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS];
11119 /* Pointer to status block's receive consumer index. */
11120 fp->rx_bd_cons_sb = &fp->status_block->
11121 u_status_block.index_values[HC_INDEX_U_ETH_RX_BD_CONS];
11123 fp->rx_cq_prod = TOTAL_RCQ_ENTRIES;
11124 fp->rx_pkts = fp->rx_tpa_pkts = fp->rx_soft_errors = 0;
11126 /* Allocate memory for the receive chain. */
11127 rc = bxe_fill_rx_bd_chain(fp);
11129 goto bxe_init_rx_chains_exit;
11131 /* Allocate memory for TPA pool. */
11132 rc = bxe_fill_tpa_pool(fp);
11134 goto bxe_init_rx_chains_exit;
11136 /* Allocate memory for scatter-gather chain. */
11137 rc = bxe_fill_sg_chain(fp);
11139 goto bxe_init_rx_chains_exit;
11141 /* Prepare the receive BD and CQ buffers for DMA access. */
11142 bus_dmamap_sync(fp->rx_dma.tag, fp->rx_dma.map,
11143 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
11145 bus_dmamap_sync(fp->rcq_dma.tag, fp->rcq_dma.map,
11146 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
11149 * Tell the controller that we have rx_bd's and CQE's
11150 * available. Warning! this will generate an interrupt
11151 * (to the TSTORM). This must only be done when the
11152 * controller is initialized.
11154 bxe_update_rx_prod(sc, fp, fp->rx_bd_prod,
11155 fp->rx_cq_prod, fp->rx_sge_prod);
11157 /* ToDo - Move to dma_alloc(). */
11159 * Tell controller where the receive CQ
11160 * chains start in physical memory.
11163 REG_WR(sc, BAR_USTORM_INTMEM +
11164 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
11165 U64_LO(fp->rcq_dma.paddr));
11166 REG_WR(sc, BAR_USTORM_INTMEM +
11167 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
11168 U64_HI(fp->rcq_dma.paddr));
11172 bxe_init_rx_chains_exit:
11173 /* Release memory if an error occurred. */
11175 bxe_clear_rx_chains(sc);
11177 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11182 * Free memory and clear the TX data structures.
11188 bxe_clear_tx_chains(struct bxe_softc *sc)
11190 struct bxe_fastpath *fp;
11193 DBENTER(BXE_VERBOSE_RESET);
11195 for (i = 0; i < sc->num_queues; i++) {
11198 /* Free all mbufs and unload all maps. */
11199 if (fp->tx_mbuf_tag) {
11200 for (j = 0; j < TOTAL_TX_BD; j++) {
11201 if (fp->tx_mbuf_ptr[j] != NULL) {
11202 bus_dmamap_sync(fp->tx_mbuf_tag,
11203 fp->tx_mbuf_map[j],
11204 BUS_DMASYNC_POSTWRITE);
11205 bus_dmamap_unload(fp->tx_mbuf_tag,
11206 fp->tx_mbuf_map[j]);
11207 m_freem(fp->tx_mbuf_ptr[j]);
11208 fp->tx_mbuf_alloc--;
11209 fp->tx_mbuf_ptr[j] = NULL;
11214 /* Check if we lost any mbufs in the process. */
11215 DBRUNIF((fp->tx_mbuf_alloc), DBPRINT(sc, BXE_FATAL,
11216 "%s(): Memory leak! Lost %d mbufs from fp[%02d] TX chain!\n",
11217 __FUNCTION__, fp->tx_mbuf_alloc, fp->index));
11220 DBEXIT(BXE_VERBOSE_RESET);
11224 * Initialize the transmit chain.
11230 bxe_init_tx_chains(struct bxe_softc *sc)
11232 struct bxe_fastpath *fp;
11235 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11237 for (i = 0; i < sc->num_queues; i++) {
11240 /* Initialize transmit doorbell. */
11241 fp->tx_db.data.header.header = DOORBELL_HDR_DB_TYPE;
11242 fp->tx_db.data.zero_fill1 = 0;
11243 fp->tx_db.data.prod = 0;
11245 /* Initialize tranmsit producer/consumer indices. */
11246 fp->tx_pkt_prod = fp->tx_pkt_cons = 0;
11247 fp->tx_bd_prod = fp->tx_bd_cons = 0;
11248 fp->tx_bd_used = 0;
11250 /* Pointer to TX packet consumer in status block. */
11251 fp->tx_pkt_cons_sb =
11252 &fp->status_block->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX];
11254 /* Soft TX counters. */
11256 fp->tx_soft_errors = 0;
11257 fp->tx_offload_frames_csum_ip = 0;
11258 fp->tx_offload_frames_csum_tcp = 0;
11259 fp->tx_offload_frames_csum_udp = 0;
11260 fp->tx_offload_frames_tso = 0;
11261 fp->tx_header_splits = 0;
11262 fp->tx_encap_failures = 0;
11263 fp->tx_hw_queue_full = 0;
11264 fp->tx_hw_max_queue_depth = 0;
11265 fp->tx_dma_mapping_failure = 0;
11266 fp->tx_max_drbr_queue_depth = 0;
11267 fp->tx_window_violation_std = 0;
11268 fp->tx_window_violation_tso = 0;
11269 fp->tx_unsupported_tso_request_ipv6 = 0;
11270 fp->tx_unsupported_tso_request_not_tcp = 0;
11271 fp->tx_chain_lost_mbuf = 0;
11272 fp->tx_frame_deferred = 0;
11273 fp->tx_queue_xoff = 0;
11275 /* Clear all TX mbuf pointers. */
11276 for (j = 0; j < TOTAL_TX_BD; j++) {
11277 fp->tx_mbuf_ptr[j] = NULL;
11281 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11285 * Initialize the slowpath ring.
11291 bxe_init_sp_ring(struct bxe_softc *sc)
11295 func = BP_FUNC(sc);
11297 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11299 bzero((char *)sc->slowpath, BXE_SLOWPATH_SZ);
11301 /* When the producer equals the consumer the chain is empty. */
11302 sc->spq_left = MAX_SPQ_PENDING;
11303 sc->spq_prod_idx = 0;
11304 sc->dsb_sp_prod = BXE_SP_DSB_INDEX;
11305 sc->spq_prod_bd = sc->spq;
11306 sc->spq_last_bd = sc->spq_prod_bd + MAX_SP_DESC_CNT;
11308 /* Tell the controller the address of the slowpath ring. */
11309 REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func),
11310 U64_LO(sc->spq_dma.paddr));
11311 REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PAGE_BASE_OFFSET(func) + 4,
11312 U64_HI(sc->spq_dma.paddr));
11313 REG_WR(sc, XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(func),
11316 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11320 * Initialize STORM processor context.
11326 bxe_init_context(struct bxe_softc *sc)
11328 struct eth_context *context;
11329 struct bxe_fastpath *fp;
11334 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11336 for (i = 0; i < sc->num_queues; i++) {
11337 context = BXE_SP(sc, context[i].eth);
11342 /* Update the USTORM context. */
11343 context->ustorm_st_context.common.sb_index_numbers =
11344 BXE_RX_SB_INDEX_NUM;
11345 context->ustorm_st_context.common.clientId = cl_id;
11346 context->ustorm_st_context.common.status_block_id = sb_id;
11347 /* Enable packet alignment/pad and statistics. */
11348 context->ustorm_st_context.common.flags =
11349 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_MC_ALIGNMENT;
11350 if (sc->stats_enable == TRUE)
11351 context->ustorm_st_context.common.flags |=
11352 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_STATISTICS;
11353 context->ustorm_st_context.common.statistics_counter_id=cl_id;
11355 * Set packet alignment boundary.
11356 * (Must be >= 4 (i.e. 16 bytes).)
11358 context->ustorm_st_context.common.mc_alignment_log_size = 8;
11359 /* Set the size of the receive buffers. */
11360 context->ustorm_st_context.common.bd_buff_size =
11361 sc->mbuf_alloc_size;
11363 /* Set the address of the receive chain base page. */
11364 context->ustorm_st_context.common.bd_page_base_hi =
11365 U64_HI(fp->rx_dma.paddr);
11366 context->ustorm_st_context.common.bd_page_base_lo =
11367 U64_LO(fp->rx_dma.paddr);
11369 if (TPA_ENABLED(sc) && (fp->disable_tpa == FALSE)) {
11370 /* Enable TPA and SGE chain support. */
11371 context->ustorm_st_context.common.flags |=
11372 USTORM_ETH_ST_CONTEXT_CONFIG_ENABLE_TPA;
11374 /* Set the size of the SGE buffer. */
11375 context->ustorm_st_context.common.sge_buff_size =
11376 (uint16_t) (SGE_PAGE_SIZE * PAGES_PER_SGE);
11378 /* Set the address of the SGE chain base page. */
11379 context->ustorm_st_context.common.sge_page_base_hi =
11380 U64_HI(fp->sg_dma.paddr);
11381 context->ustorm_st_context.common.sge_page_base_lo =
11382 U64_LO(fp->sg_dma.paddr);
11384 DBPRINT(sc, BXE_VERBOSE_TPA, "%s(): MTU = %d\n",
11385 __FUNCTION__, (int) sc->bxe_ifp->if_mtu);
11387 /* Describe MTU to SGE alignment. */
11388 context->ustorm_st_context.common.max_sges_for_packet =
11389 SGE_PAGE_ALIGN(sc->bxe_ifp->if_mtu) >>
11391 context->ustorm_st_context.common.max_sges_for_packet =
11392 ((context->ustorm_st_context.common.
11393 max_sges_for_packet + PAGES_PER_SGE - 1) &
11394 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT;
11396 DBPRINT(sc, BXE_VERBOSE_TPA,
11397 "%s(): max_sges_for_packet = %d\n", __FUNCTION__,
11398 context->ustorm_st_context.common.max_sges_for_packet);
11401 /* Update USTORM context. */
11402 context->ustorm_ag_context.cdu_usage =
11403 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, i),
11404 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
11406 /* Update XSTORM context. */
11407 context->xstorm_ag_context.cdu_reserved =
11408 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, i),
11409 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
11411 /* Set the address of the transmit chain base page. */
11412 context->xstorm_st_context.tx_bd_page_base_hi =
11413 U64_HI(fp->tx_dma.paddr);
11414 context->xstorm_st_context.tx_bd_page_base_lo =
11415 U64_LO(fp->tx_dma.paddr);
11417 /* Enable XSTORM statistics. */
11418 context->xstorm_st_context.statistics_data = (cl_id |
11419 XSTORM_ETH_ST_CONTEXT_STATISTICS_ENABLE);
11421 /* Update CSTORM status block configuration. */
11422 context->cstorm_st_context.sb_index_number =
11423 C_SB_ETH_TX_CQ_INDEX;
11424 context->cstorm_st_context.status_block_id = sb_id;
11427 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11431 * Initialize indirection table.
11437 bxe_init_ind_table(struct bxe_softc *sc)
11441 func = BP_FUNC(sc);
11443 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11445 if (sc->multi_mode == ETH_RSS_MODE_DISABLED)
11448 /* Initialize the indirection table. */
11449 for (i = 0; i < TSTORM_INDIRECTION_TABLE_SIZE; i++)
11450 REG_WR8(sc, BAR_TSTORM_INTMEM +
11451 TSTORM_INDIRECTION_TABLE_OFFSET(func) + i,
11452 sc->fp->cl_id + (i % sc->num_queues));
11454 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11458 * Set client configuration.
11464 bxe_set_client_config(struct bxe_softc *sc)
11466 struct tstorm_eth_client_config tstorm_client = {0};
11469 port = BP_PORT(sc);
11471 DBENTER(BXE_VERBOSE_MISC);
11473 tstorm_client.mtu = sc->bxe_ifp->if_mtu; /* ETHERMTU */
11474 tstorm_client.config_flags =
11475 (TSTORM_ETH_CLIENT_CONFIG_STATSITICS_ENABLE |
11476 TSTORM_ETH_CLIENT_CONFIG_E1HOV_REM_ENABLE);
11478 /* Unconditionally enable VLAN tag stripping. */
11480 tstorm_client.config_flags |=
11481 TSTORM_ETH_CLIENT_CONFIG_VLAN_REM_ENABLE;
11482 DBPRINT(sc, BXE_VERBOSE, "%s(): VLAN tag stripping enabled.\n",
11486 /* Initialize the receive mode for each receive queue. */
11487 for (i = 0; i < sc->num_queues; i++) {
11488 tstorm_client.statistics_counter_id = sc->fp[i].cl_id;
11490 REG_WR(sc, BAR_TSTORM_INTMEM +
11491 TSTORM_CLIENT_CONFIG_OFFSET(port, sc->fp[i].cl_id),
11492 ((uint32_t *) &tstorm_client)[0]);
11493 REG_WR(sc, BAR_TSTORM_INTMEM +
11494 TSTORM_CLIENT_CONFIG_OFFSET(port, sc->fp[i].cl_id) + 4,
11495 ((uint32_t *) &tstorm_client)[1]);
11498 DBEXIT(BXE_VERBOSE_MISC);
11502 * Set receive mode.
11504 * Programs the MAC according to the type of unicast/broadcast/multicast
11505 * packets it should receive.
11511 bxe_set_storm_rx_mode(struct bxe_softc *sc)
11513 struct tstorm_eth_mac_filter_config tstorm_mac_filter = {0};
11516 int func, i , port;
11518 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11520 mode = sc->rx_mode;
11521 mask = 1 << BP_L_ID(sc);
11522 func = BP_FUNC(sc);
11523 port = BP_PORT(sc);
11525 /* All but management unicast packets should pass to the host as well */
11526 llh_mask = NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_BRCST |
11527 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_MLCST |
11528 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_VLAN |
11529 NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_NO_VLAN;
11531 /* Set the individual accept/drop flags based on the receive mode. */
11533 case BXE_RX_MODE_NONE:
11534 /* Drop everything. */
11535 DBPRINT(sc, BXE_VERBOSE,
11536 "%s(): Setting RX_MODE_NONE for function %d.\n",
11537 __FUNCTION__, func);
11538 tstorm_mac_filter.ucast_drop_all = mask;
11539 tstorm_mac_filter.mcast_drop_all = mask;
11540 tstorm_mac_filter.bcast_drop_all = mask;
11542 case BXE_RX_MODE_NORMAL:
11543 /* Accept all broadcast frames. */
11544 DBPRINT(sc, BXE_VERBOSE,
11545 "%s(): Setting RX_MODE_NORMAL for function %d.\n",
11546 __FUNCTION__, func);
11547 tstorm_mac_filter.bcast_accept_all = mask;
11549 case BXE_RX_MODE_ALLMULTI:
11550 /* Accept all broadcast and multicast frames. */
11551 DBPRINT(sc, BXE_VERBOSE,
11552 "%s(): Setting RX_MODE_ALLMULTI for function %d.\n",
11553 __FUNCTION__, func);
11554 tstorm_mac_filter.mcast_accept_all = mask;
11555 tstorm_mac_filter.bcast_accept_all = mask;
11557 case BXE_RX_MODE_PROMISC:
11558 /* Accept all frames (promiscuous mode). */
11559 DBPRINT(sc, BXE_VERBOSE,
11560 "%s(): Setting RX_MODE_PROMISC for function %d.\n",
11561 __FUNCTION__, func);
11562 tstorm_mac_filter.ucast_accept_all = mask;
11563 tstorm_mac_filter.mcast_accept_all = mask;
11564 tstorm_mac_filter.bcast_accept_all = mask;
11565 llh_mask |= NIG_LLH0_BRB1_DRV_MASK_REG_LLH0_BRB1_DRV_MASK_UNCST;
11570 "%s(%d): Tried to set unknown receive mode (0x%08X)!\n",
11571 __FILE__, __LINE__, mode);
11574 REG_WR(sc, port ? NIG_REG_LLH1_BRB1_DRV_MASK :
11575 NIG_REG_LLH0_BRB1_DRV_MASK, llh_mask);
11577 /* Write the RX mode filter to the TSTORM. */
11578 for (i = 0; i < sizeof(struct tstorm_eth_mac_filter_config) / 4; i++)
11579 REG_WR(sc, BAR_TSTORM_INTMEM +
11580 TSTORM_MAC_FILTER_CONFIG_OFFSET(func) + (i * 4),
11581 ((uint32_t *) &tstorm_mac_filter)[i]);
11583 if (mode != BXE_RX_MODE_NONE)
11584 bxe_set_client_config(sc);
11586 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11590 * Initialize common internal resources. (Applies to both ports and
11597 bxe_init_internal_common(struct bxe_softc *sc)
11601 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11604 * Zero this manually as its initialization is currently not
11605 * handled through block initialization.
11607 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
11608 REG_WR(sc, BAR_USTORM_INTMEM + USTORM_AGG_DATA_OFFSET + i * 4,
11611 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11615 * Initialize port specific internal resources.
11621 bxe_init_internal_port(struct bxe_softc *sc)
11623 int port = BP_PORT(sc);
11625 port = BP_PORT(sc);
11627 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11628 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
11629 "%s(): Port %d internal initialization.\n", __FUNCTION__, port);
11632 * Each SDM timer tick is 4us. Configure host coalescing
11633 * basic timer resolution (BTR) to 12us (3 * 4us).
11635 REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_HC_BTR_U_OFFSET(port), BXE_BTR);
11636 REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_HC_BTR_C_OFFSET(port), BXE_BTR);
11637 REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_HC_BTR_OFFSET(port), BXE_BTR);
11638 REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_HC_BTR_OFFSET(port), BXE_BTR);
11640 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11644 * Initialize function specific internal resources.
11650 bxe_init_internal_func(struct bxe_softc *sc)
11652 struct tstorm_eth_function_common_config tstorm_config = {0};
11653 struct stats_indication_flags stats_flags = {0};
11654 struct ustorm_eth_rx_pause_data_e1h rx_pause = {0};
11655 struct bxe_fastpath *fp;
11656 struct eth_rx_cqe_next_page *nextpg;
11657 uint32_t offset, size;
11658 uint16_t max_agg_size;
11660 int func, i, j, port;
11662 port = BP_PORT(sc);
11663 func = BP_FUNC(sc);
11665 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11666 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
11667 "%s(): Port %d, function %d internal initialization.\n",
11668 __FUNCTION__, port, func);
11671 * Configure which fields the controller looks at when
11672 * distributing incoming frames for RSS/multi-queue operation.
11674 if (sc->num_queues > 1) {
11675 tstorm_config.config_flags = MULTI_FLAGS(sc);
11676 tstorm_config.rss_result_mask = MULTI_MASK;
11679 /* Enable TPA if needed */
11680 if (TPA_ENABLED(sc))
11681 tstorm_config.config_flags |=
11682 TSTORM_ETH_FUNCTION_COMMON_CONFIG_ENABLE_TPA;
11685 tstorm_config.config_flags |=
11686 TSTORM_ETH_FUNCTION_COMMON_CONFIG_E1HOV_IN_CAM;
11688 tstorm_config.leading_client_id = BP_L_ID(sc);
11690 REG_WR(sc, BAR_TSTORM_INTMEM +
11691 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(func),
11692 (*(uint32_t *)&tstorm_config));
11694 /* Don't receive anything until the link is up. */
11695 sc->rx_mode = BXE_RX_MODE_NONE;
11696 sc->rx_mode_cl_mask = (1 << BP_L_ID(sc));
11697 bxe_set_storm_rx_mode(sc);
11699 for (i = 0; i < sc->num_queues; i++) {
11700 cl_id = sc->fp[i].cl_id;
11701 /* Reset XSTORM per client statistics. */
11702 size = sizeof(struct xstorm_per_client_stats) / 4;
11703 offset = BAR_XSTORM_INTMEM +
11704 XSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
11705 for (j = 0; j < size; j++)
11706 REG_WR(sc, offset +(j * 4), 0);
11708 /* Reset TSTORM per client statistics. */
11709 size = sizeof(struct tstorm_per_client_stats) / 4;
11710 offset = BAR_TSTORM_INTMEM +
11711 TSTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
11712 for (j = 0; j < size; j++)
11713 REG_WR(sc, offset + (j * 4), 0);
11715 /* Reset USTORM per client statistics. */
11716 size = sizeof(struct ustorm_per_client_stats) / 4;
11717 offset = BAR_USTORM_INTMEM +
11718 USTORM_PER_COUNTER_ID_STATS_OFFSET(port, cl_id);
11719 for (j = 0; j < size; j++)
11720 REG_WR(sc, offset + (j * 4), 0);
11723 /* Initialize statistics related context. */
11724 stats_flags.collect_eth = 1;
11726 REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func),
11727 ((uint32_t *)&stats_flags)[0]);
11728 REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_STATS_FLAGS_OFFSET(func) + 4,
11729 ((uint32_t *)&stats_flags)[1]);
11731 REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func),
11732 ((uint32_t *)&stats_flags)[0]);
11733 REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_STATS_FLAGS_OFFSET(func) + 4,
11734 ((uint32_t *)&stats_flags)[1]);
11736 REG_WR(sc, BAR_USTORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func),
11737 ((uint32_t *)&stats_flags)[0]);
11738 REG_WR(sc, BAR_USTORM_INTMEM + USTORM_STATS_FLAGS_OFFSET(func) + 4,
11739 ((uint32_t *)&stats_flags)[1]);
11741 REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func),
11742 ((uint32_t *)&stats_flags)[0]);
11743 REG_WR(sc, BAR_CSTORM_INTMEM + CSTORM_STATS_FLAGS_OFFSET(func) + 4,
11744 ((uint32_t *)&stats_flags)[1]);
11746 REG_WR(sc, BAR_XSTORM_INTMEM + XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
11747 U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
11748 REG_WR(sc, BAR_XSTORM_INTMEM +
11749 XSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
11750 U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
11752 REG_WR(sc, BAR_TSTORM_INTMEM + TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
11753 U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
11754 REG_WR(sc, BAR_TSTORM_INTMEM +
11755 TSTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
11756 U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
11758 REG_WR(sc, BAR_USTORM_INTMEM + USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func),
11759 U64_LO(BXE_SP_MAPPING(sc, fw_stats)));
11760 REG_WR(sc, BAR_USTORM_INTMEM +
11761 USTORM_ETH_STATS_QUERY_ADDR_OFFSET(func) + 4,
11762 U64_HI(BXE_SP_MAPPING(sc, fw_stats)));
11764 /* Additional initialization for 57711/57711E. */
11765 if (CHIP_IS_E1H(sc)) {
11766 REG_WR8(sc, BAR_XSTORM_INTMEM + XSTORM_FUNCTION_MODE_OFFSET,
11768 REG_WR8(sc, BAR_TSTORM_INTMEM + TSTORM_FUNCTION_MODE_OFFSET,
11770 REG_WR8(sc, BAR_CSTORM_INTMEM + CSTORM_FUNCTION_MODE_OFFSET,
11772 REG_WR8(sc, BAR_USTORM_INTMEM + USTORM_FUNCTION_MODE_OFFSET,
11775 /* Set the outer VLAN tag. */
11776 REG_WR16(sc, BAR_XSTORM_INTMEM + XSTORM_E1HOV_OFFSET(func),
11780 /* Init completion queue mapping and TPA aggregation size. */
11781 max_agg_size = min((uint32_t)(sc->mbuf_alloc_size +
11782 (8 * BCM_PAGE_SIZE * PAGES_PER_SGE)), (uint32_t)0xffff);
11784 DBPRINT(sc, BXE_VERBOSE_TPA, "%s(): max_agg_size = 0x%08X\n",
11785 __FUNCTION__, max_agg_size);
11787 for (i = 0; i < sc->num_queues; i++) {
11789 nextpg = (struct eth_rx_cqe_next_page *)
11790 &fp->rcq_chain[USABLE_RCQ_ENTRIES_PER_PAGE];
11792 /* Program the completion queue address. */
11793 REG_WR(sc, BAR_USTORM_INTMEM +
11794 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id),
11795 U64_LO(fp->rcq_dma.paddr));
11796 REG_WR(sc, BAR_USTORM_INTMEM +
11797 USTORM_CQE_PAGE_BASE_OFFSET(port, fp->cl_id) + 4,
11798 U64_HI(fp->rcq_dma.paddr));
11800 /* Program the first CQ next page address. */
11801 REG_WR(sc, BAR_USTORM_INTMEM +
11802 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id),
11804 REG_WR(sc, BAR_USTORM_INTMEM +
11805 USTORM_CQE_PAGE_NEXT_OFFSET(port, fp->cl_id) + 4,
11808 /* Set the maximum TPA aggregation size. */
11809 REG_WR16(sc, BAR_USTORM_INTMEM +
11810 USTORM_MAX_AGG_SIZE_OFFSET(port, fp->cl_id),
11814 /* Configure lossless flow control. */
11815 if (CHIP_IS_E1H(sc)) {
11816 rx_pause.bd_thr_low = 250;
11817 rx_pause.cqe_thr_low = 250;
11819 rx_pause.sge_thr_low = 0;
11820 rx_pause.bd_thr_high = 350;
11821 rx_pause.cqe_thr_high = 350;
11822 rx_pause.sge_thr_high = 0;
11824 for (i = 0; i < sc->num_queues; i++) {
11826 if (fp->disable_tpa == FALSE) {
11827 rx_pause.sge_thr_low = 150;
11828 rx_pause.sge_thr_high = 250;
11831 offset = BAR_USTORM_INTMEM +
11832 USTORM_ETH_RING_PAUSE_DATA_OFFSET(port, fp->cl_id);
11835 sizeof(struct ustorm_eth_rx_pause_data_e1h) / 4;
11837 REG_WR(sc, offset + (j * 4),
11838 ((uint32_t *)&rx_pause)[j]);
11842 memset(&(sc->cmng), 0, sizeof(struct cmng_struct_per_port));
11843 if (IS_E1HMF(sc)) {
11845 * During init there is no active link.
11846 * Until link is up, assume link rate @ 10Gbps
11848 bxe_read_mf_cfg(sc);
11851 DBPRINT(sc, BXE_VERBOSE_MISC,
11852 "%s(): All MIN values are zeroes, "
11853 "fairness will be disabled.\n", __FUNCTION__);
11856 /* Store it to internal memory */
11857 if (sc->port.pmf) {
11858 for (i = 0; i < sizeof(struct cmng_struct_per_port) / 4; i++)
11859 REG_WR(sc, BAR_XSTORM_INTMEM +
11860 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port) + i * 4,
11861 ((uint32_t *)(&sc->cmng))[i]);
11864 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11868 * Initialize internal resources.
11874 bxe_init_internal(struct bxe_softc *sc, uint32_t load_code)
11877 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11879 switch (load_code) {
11880 case FW_MSG_CODE_DRV_LOAD_COMMON:
11881 bxe_init_internal_common(sc);
11884 case FW_MSG_CODE_DRV_LOAD_PORT:
11885 bxe_init_internal_port(sc);
11888 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
11889 bxe_init_internal_func(sc);
11894 "%s(%d): Unknown load_code (0x%08X) from MCP!\n",
11895 __FILE__, __LINE__, load_code);
11899 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11904 * Perform driver instance specific initialization.
11910 bxe_init_nic(struct bxe_softc *sc, uint32_t load_code)
11912 struct bxe_fastpath *fp;
11915 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11917 /* Intialize fastpath structures and the status block. */
11918 for (i = 0; i < sc->num_queues; i++) {
11920 fp->disable_tpa = TRUE;
11922 bzero((char *)fp->status_block, BXE_STATUS_BLK_SZ);
11926 /* Set a pointer back to the driver instance. */
11929 /* Set the fastpath starting state as closed. */
11930 fp->state = BXE_FP_STATE_CLOSED;
11932 /* Self-reference to this fastpath's instance. */
11935 /* Set the client ID beginning with the leading id. */
11936 fp->cl_id = BP_L_ID(sc) + i;
11938 /* Set the status block ID for this fastpath instance. */
11939 fp->sb_id = fp->cl_id;
11941 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
11942 "%s(): fp[%02d]: cl_id = %d, sb_id = %d\n",
11943 __FUNCTION__, fp->index, fp->cl_id, fp->sb_id);
11945 /* Initialize the fastpath status block. */
11946 bxe_init_sb(sc, fp->status_block, fp->sb_dma.paddr,
11948 bxe_update_fpsb_idx(fp);
11953 bzero((char *)sc->def_sb, BXE_DEF_STATUS_BLK_SZ);
11955 /* Initialize the Default Status Block. */
11956 bxe_init_def_sb(sc, sc->def_sb, sc->def_sb_dma.paddr, DEF_SB_ID);
11957 bxe_update_dsb_idx(sc);
11959 /* Initialize the coalescence parameters. */
11960 bxe_update_coalesce(sc);
11962 /* Initialize receive chains. */
11963 rc = bxe_init_rx_chains(sc);
11965 goto bxe_init_nic_exit;
11968 /* Initialize the Transmit BD Chain. */
11969 bxe_init_tx_chains(sc);
11971 /* Initialize the Slow Path Chain. */
11972 bxe_init_sp_ring(sc);
11974 /* Initialize STORM processor context/configuration. */
11975 bxe_init_context(sc);
11977 /* Initialize the Context. */
11978 bxe_init_internal(sc, load_code);
11980 /* Enable indirection table for multi-queue operation. */
11981 bxe_init_ind_table(sc);
11985 /* Disable the interrupts from device until init is complete.*/
11986 bxe_int_disable(sc);
11989 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
11994 * Send a loopback packet through the Network Interface Glue (NIG) block.
12000 bxe_lb_pckt(struct bxe_softc *sc)
12002 #ifdef BXE_USE_DMAE
12003 uint32_t wb_write[3];
12006 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12008 /* Ethernet source and destination addresses. */
12009 #ifdef BXE_USE_DMAE
12010 wb_write[0] = 0x55555555;
12011 wb_write[1] = 0x55555555;
12012 wb_write[2] = 0x20; /* SOP */
12013 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
12015 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB, 0x55555555);
12016 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
12017 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 8, 0x20);
12020 /* NON-IP protocol. */
12021 #ifdef BXE_USE_DMAE
12022 wb_write[0] = 0x09000000;
12023 wb_write[1] = 0x55555555;
12024 wb_write[2] = 0x10; /* EOP */
12025 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
12027 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB, 0x09000000);
12028 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 4, 0x55555555);
12029 REG_WR_IND(sc, NIG_REG_DEBUG_PACKET_LB + 8, 0x10);
12032 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12036 * Perform an internal memory test.
12038 * Some internal memories are not accessible through the PCIe interface so
12039 * we send some debug packets for the test.
12042 * 0 = Success, !0 = Failure.
12045 bxe_int_mem_test(struct bxe_softc *sc)
12053 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12055 /* Perform a single debug packet test. */
12057 /* Disable inputs of parser neighbor blocks. */
12058 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
12059 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
12060 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
12061 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
12063 /* Write 0 to parser credits for CFC search request. */
12064 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
12066 /* Send an Ethernet packet. */
12069 /* Wait until NIG register shows 1 packet of size 0x10. */
12072 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
12073 val = *BXE_SP(sc, wb_data[0]);
12082 DBPRINT(sc, BXE_FATAL,
12083 "%s(): NIG loopback test 1 timeout (val = 0x%08X)!\n",
12084 __FUNCTION__, val);
12086 goto bxe_int_mem_test_exit;
12089 /* Wait until PRS register shows 1 packet */
12092 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
12102 DBPRINT(sc, BXE_FATAL,
12103 "%s(): PRS loopback test 1 timeout (val = 0x%08X)!\n",
12104 __FUNCTION__, val);
12106 goto bxe_int_mem_test_exit;
12109 /* Reset and init BRB, PRS. */
12110 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x3);
12112 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x3);
12114 bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
12115 bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
12117 /* Perform the test again, this time with 10 packets. */
12119 /* Disable inputs of parser neighbor blocks. */
12120 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0);
12121 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0);
12122 REG_WR(sc, CFC_REG_DEBUG0, 0x1);
12123 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0);
12125 /* Write 0 to parser credits for CFC search request. */
12126 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
12128 /* Send 10 Ethernet packets. */
12129 for (i = 0; i < 10; i++)
12132 /* Wait until NIG shows 10 + 1 packets of size 11 * 0x10 = 0xb0. */
12135 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
12136 val = *BXE_SP(sc, wb_data[0]);
12145 DBPRINT(sc, BXE_FATAL,
12146 "%s(): NIG loopback test 2 timeout (val = 0x%08X)!\n",
12147 __FUNCTION__, val);
12149 goto bxe_int_mem_test_exit;
12152 /* Wait until PRS register shows 2 packets. */
12153 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
12155 DBPRINT(sc, BXE_FATAL,
12156 "%s(): PRS loopback test 2 timeout (val = 0x%x)!\n",
12157 __FUNCTION__, val);
12159 goto bxe_int_mem_test_exit;
12162 /* Write 1 to parser credits for CFC search request. */
12163 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
12165 /* Wait until PRS register shows 3 packets. */
12168 /* Wait until NIG register shows 1 packet of size 0x10. */
12169 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS);
12171 DBPRINT(sc, BXE_FATAL,
12172 "%s(): PRS loopback test 3 timeout (val = 0x%08X)!\n",
12173 __FUNCTION__, val);
12175 goto bxe_int_mem_test_exit;
12178 /* Clear NIG end-of-packet FIFO. */
12179 for (i = 0; i < 11; i++)
12180 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO);
12182 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY);
12184 DBPRINT(sc, BXE_INFO, "%s(): Unable to clear NIG!\n",
12187 goto bxe_int_mem_test_exit;
12190 /* Reset and init BRB, PRS, NIG. */
12191 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
12193 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
12195 bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
12196 bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
12198 /* Set NIC mode. */
12199 REG_WR(sc, PRS_REG_NIC_MODE, 1);
12201 /* Enable inputs of parser neighbor blocks. */
12202 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff);
12203 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1);
12204 REG_WR(sc, CFC_REG_DEBUG0, 0x0);
12205 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1);
12207 bxe_int_mem_test_exit:
12208 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12213 * Enable attentions from various blocks.
12219 bxe_enable_blocks_attention(struct bxe_softc *sc)
12222 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12224 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
12225 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0);
12226 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
12227 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
12228 REG_WR(sc, QM_REG_QM_INT_MASK, 0);
12229 REG_WR(sc, TM_REG_TM_INT_MASK, 0);
12230 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0);
12231 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0);
12232 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0);
12234 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0);
12235 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0);
12236 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0);
12238 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
12239 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0);
12240 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0);
12241 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0);
12243 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
12245 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0);
12246 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0);
12247 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0);
12249 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0);
12250 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0);
12251 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0X18);
12253 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12261 * This code configures the PCI read/write arbiter
12262 * which implements a weighted round robin
12263 * between the virtual queues in the chip.
12265 * The values were derived for each PCI max payload and max request size.
12266 * since max payload and max request size are only known at run time,
12267 * this is done as a separate init stage.
12270 #define NUM_WR_Q 13
12271 #define NUM_RD_Q 29
12272 #define MAX_RD_ORD 3
12273 #define MAX_WR_ORD 2
12275 /* Configuration for one arbiter queue. */
12282 /* Derived configuration for each read queue for each max request size. */
12283 static const struct arb_line read_arb_data[NUM_RD_Q][MAX_RD_ORD + 1] = {
12284 /* 1 */ { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
12285 { {4, 8, 4}, {4, 8, 4}, {4, 8, 4}, {4, 8, 4} },
12286 { {4, 3, 3}, {4, 3, 3}, {4, 3, 3}, {4, 3, 3} },
12287 { {8, 3, 6}, {16, 3, 11}, {16, 3, 11}, {16, 3, 11} },
12288 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25}, {64, 64, 41} },
12289 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
12290 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
12291 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
12292 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {64, 3, 41} },
12293 /* 10 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12294 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12295 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12296 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12297 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12298 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12299 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12300 { {8, 64, 6}, {16, 64, 11}, {32, 64, 21}, {32, 64, 21} },
12301 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12302 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12303 /* 20 */{ {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12304 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12305 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12306 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12307 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12308 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12309 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12310 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12311 { {8, 3, 6}, {16, 3, 11}, {32, 3, 21}, {32, 3, 21} },
12312 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81}, {64, 64, 120} }
12315 /* Derived configuration for each write queue for each max request size. */
12316 static const struct arb_line write_arb_data[NUM_WR_Q][MAX_WR_ORD + 1] = {
12317 /* 1 */ { {4, 6, 3}, {4, 6, 3}, {4, 6, 3} },
12318 { {4, 2, 3}, {4, 2, 3}, {4, 2, 3} },
12319 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
12320 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
12321 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
12322 { {8, 2, 6}, {16, 2, 11}, {32, 2, 21} },
12323 { {8, 64, 25}, {16, 64, 25}, {32, 64, 25} },
12324 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
12325 { {8, 2, 6}, {16, 2, 11}, {16, 2, 11} },
12326 /* 10 */{ {8, 9, 6}, {16, 9, 11}, {32, 9, 21} },
12327 { {8, 47, 19}, {16, 47, 19}, {32, 47, 21} },
12328 { {8, 9, 6}, {16, 9, 11}, {16, 9, 11} },
12329 { {8, 64, 25}, {16, 64, 41}, {32, 64, 81} }
12332 /* Register addresses for read queues. */
12333 static const struct arb_line read_arb_addr[NUM_RD_Q-1] = {
12334 /* 1 */ {PXP2_REG_RQ_BW_RD_L0, PXP2_REG_RQ_BW_RD_ADD0,
12335 PXP2_REG_RQ_BW_RD_UBOUND0},
12336 {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
12337 PXP2_REG_PSWRQ_BW_UB1},
12338 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
12339 PXP2_REG_PSWRQ_BW_UB2},
12340 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
12341 PXP2_REG_PSWRQ_BW_UB3},
12342 {PXP2_REG_RQ_BW_RD_L4, PXP2_REG_RQ_BW_RD_ADD4,
12343 PXP2_REG_RQ_BW_RD_UBOUND4},
12344 {PXP2_REG_RQ_BW_RD_L5, PXP2_REG_RQ_BW_RD_ADD5,
12345 PXP2_REG_RQ_BW_RD_UBOUND5},
12346 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
12347 PXP2_REG_PSWRQ_BW_UB6},
12348 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
12349 PXP2_REG_PSWRQ_BW_UB7},
12350 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
12351 PXP2_REG_PSWRQ_BW_UB8},
12352 /* 10 */{PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
12353 PXP2_REG_PSWRQ_BW_UB9},
12354 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
12355 PXP2_REG_PSWRQ_BW_UB10},
12356 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
12357 PXP2_REG_PSWRQ_BW_UB11},
12358 {PXP2_REG_RQ_BW_RD_L12, PXP2_REG_RQ_BW_RD_ADD12,
12359 PXP2_REG_RQ_BW_RD_UBOUND12},
12360 {PXP2_REG_RQ_BW_RD_L13, PXP2_REG_RQ_BW_RD_ADD13,
12361 PXP2_REG_RQ_BW_RD_UBOUND13},
12362 {PXP2_REG_RQ_BW_RD_L14, PXP2_REG_RQ_BW_RD_ADD14,
12363 PXP2_REG_RQ_BW_RD_UBOUND14},
12364 {PXP2_REG_RQ_BW_RD_L15, PXP2_REG_RQ_BW_RD_ADD15,
12365 PXP2_REG_RQ_BW_RD_UBOUND15},
12366 {PXP2_REG_RQ_BW_RD_L16, PXP2_REG_RQ_BW_RD_ADD16,
12367 PXP2_REG_RQ_BW_RD_UBOUND16},
12368 {PXP2_REG_RQ_BW_RD_L17, PXP2_REG_RQ_BW_RD_ADD17,
12369 PXP2_REG_RQ_BW_RD_UBOUND17},
12370 {PXP2_REG_RQ_BW_RD_L18, PXP2_REG_RQ_BW_RD_ADD18,
12371 PXP2_REG_RQ_BW_RD_UBOUND18},
12372 /* 20 */{PXP2_REG_RQ_BW_RD_L19, PXP2_REG_RQ_BW_RD_ADD19,
12373 PXP2_REG_RQ_BW_RD_UBOUND19},
12374 {PXP2_REG_RQ_BW_RD_L20, PXP2_REG_RQ_BW_RD_ADD20,
12375 PXP2_REG_RQ_BW_RD_UBOUND20},
12376 {PXP2_REG_RQ_BW_RD_L22, PXP2_REG_RQ_BW_RD_ADD22,
12377 PXP2_REG_RQ_BW_RD_UBOUND22},
12378 {PXP2_REG_RQ_BW_RD_L23, PXP2_REG_RQ_BW_RD_ADD23,
12379 PXP2_REG_RQ_BW_RD_UBOUND23},
12380 {PXP2_REG_RQ_BW_RD_L24, PXP2_REG_RQ_BW_RD_ADD24,
12381 PXP2_REG_RQ_BW_RD_UBOUND24},
12382 {PXP2_REG_RQ_BW_RD_L25, PXP2_REG_RQ_BW_RD_ADD25,
12383 PXP2_REG_RQ_BW_RD_UBOUND25},
12384 {PXP2_REG_RQ_BW_RD_L26, PXP2_REG_RQ_BW_RD_ADD26,
12385 PXP2_REG_RQ_BW_RD_UBOUND26},
12386 {PXP2_REG_RQ_BW_RD_L27, PXP2_REG_RQ_BW_RD_ADD27,
12387 PXP2_REG_RQ_BW_RD_UBOUND27},
12388 {PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
12389 PXP2_REG_PSWRQ_BW_UB28}
12392 /* Register addresses for write queues. */
12393 static const struct arb_line write_arb_addr[NUM_WR_Q-1] = {
12394 /* 1 */ {PXP2_REG_PSWRQ_BW_L1, PXP2_REG_PSWRQ_BW_ADD1,
12395 PXP2_REG_PSWRQ_BW_UB1},
12396 {PXP2_REG_PSWRQ_BW_L2, PXP2_REG_PSWRQ_BW_ADD2,
12397 PXP2_REG_PSWRQ_BW_UB2},
12398 {PXP2_REG_PSWRQ_BW_L3, PXP2_REG_PSWRQ_BW_ADD3,
12399 PXP2_REG_PSWRQ_BW_UB3},
12400 {PXP2_REG_PSWRQ_BW_L6, PXP2_REG_PSWRQ_BW_ADD6,
12401 PXP2_REG_PSWRQ_BW_UB6},
12402 {PXP2_REG_PSWRQ_BW_L7, PXP2_REG_PSWRQ_BW_ADD7,
12403 PXP2_REG_PSWRQ_BW_UB7},
12404 {PXP2_REG_PSWRQ_BW_L8, PXP2_REG_PSWRQ_BW_ADD8,
12405 PXP2_REG_PSWRQ_BW_UB8},
12406 {PXP2_REG_PSWRQ_BW_L9, PXP2_REG_PSWRQ_BW_ADD9,
12407 PXP2_REG_PSWRQ_BW_UB9},
12408 {PXP2_REG_PSWRQ_BW_L10, PXP2_REG_PSWRQ_BW_ADD10,
12409 PXP2_REG_PSWRQ_BW_UB10},
12410 {PXP2_REG_PSWRQ_BW_L11, PXP2_REG_PSWRQ_BW_ADD11,
12411 PXP2_REG_PSWRQ_BW_UB11},
12412 /* 10 */{PXP2_REG_PSWRQ_BW_L28, PXP2_REG_PSWRQ_BW_ADD28,
12413 PXP2_REG_PSWRQ_BW_UB28},
12414 {PXP2_REG_RQ_BW_WR_L29, PXP2_REG_RQ_BW_WR_ADD29,
12415 PXP2_REG_RQ_BW_WR_UBOUND29},
12416 {PXP2_REG_RQ_BW_WR_L30, PXP2_REG_RQ_BW_WR_ADD30,
12417 PXP2_REG_RQ_BW_WR_UBOUND30}
12421 bxe_init_pxp_arb(struct bxe_softc *sc, int r_order, int w_order)
12425 if (r_order > MAX_RD_ORD) {
12426 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12427 "%s(): Read order of %d order adjusted to %d\n",
12428 __FUNCTION__, r_order, MAX_RD_ORD);
12429 r_order = MAX_RD_ORD;
12431 if (w_order > MAX_WR_ORD) {
12432 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12433 "%s(): Write order of %d order adjusted to %d\n",
12434 __FUNCTION__, w_order, MAX_WR_ORD);
12435 w_order = MAX_WR_ORD;
12438 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12439 "%s(): Read order %d, write order %d\n",
12440 __FUNCTION__, r_order, w_order);
12442 for (i = 0; i < NUM_RD_Q - 1; i++) {
12443 REG_WR(sc, read_arb_addr[i].l,
12444 read_arb_data[i][r_order].l);
12445 REG_WR(sc, read_arb_addr[i].add,
12446 read_arb_data[i][r_order].add);
12447 REG_WR(sc, read_arb_addr[i].ubound,
12448 read_arb_data[i][r_order].ubound);
12451 for (i = 0; i < NUM_WR_Q - 1; i++) {
12452 if ((write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L29) ||
12453 (write_arb_addr[i].l == PXP2_REG_RQ_BW_WR_L30)) {
12455 REG_WR(sc, write_arb_addr[i].l,
12456 write_arb_data[i][w_order].l);
12458 REG_WR(sc, write_arb_addr[i].add,
12459 write_arb_data[i][w_order].add);
12461 REG_WR(sc, write_arb_addr[i].ubound,
12462 write_arb_data[i][w_order].ubound);
12465 val = REG_RD(sc, write_arb_addr[i].l);
12466 REG_WR(sc, write_arb_addr[i].l, val |
12467 (write_arb_data[i][w_order].l << 10));
12469 val = REG_RD(sc, write_arb_addr[i].add);
12470 REG_WR(sc, write_arb_addr[i].add, val |
12471 (write_arb_data[i][w_order].add << 10));
12473 val = REG_RD(sc, write_arb_addr[i].ubound);
12474 REG_WR(sc, write_arb_addr[i].ubound, val |
12475 (write_arb_data[i][w_order].ubound << 7));
12479 val = write_arb_data[NUM_WR_Q - 1][w_order].add;
12480 val += write_arb_data[NUM_WR_Q - 1][w_order].ubound << 10;
12481 val += write_arb_data[NUM_WR_Q - 1][w_order].l << 17;
12482 REG_WR(sc, PXP2_REG_PSWRQ_BW_RD, val);
12484 val = read_arb_data[NUM_RD_Q - 1][r_order].add;
12485 val += read_arb_data[NUM_RD_Q - 1][r_order].ubound << 10;
12486 val += read_arb_data[NUM_RD_Q - 1][r_order].l << 17;
12487 REG_WR(sc, PXP2_REG_PSWRQ_BW_WR, val);
12489 REG_WR(sc, PXP2_REG_RQ_WR_MBS0, w_order);
12490 REG_WR(sc, PXP2_REG_RQ_WR_MBS1, w_order);
12491 REG_WR(sc, PXP2_REG_RQ_RD_MBS0, r_order);
12492 REG_WR(sc, PXP2_REG_RQ_RD_MBS1, r_order);
12494 if (r_order == MAX_RD_ORD)
12495 REG_WR(sc, PXP2_REG_RQ_PDR_LIMIT, 0xe00);
12497 REG_WR(sc, PXP2_REG_WR_USDMDP_TH, (0x18 << w_order));
12499 if (CHIP_IS_E1H(sc)) {
12500 /* MPS w_order optimal TH presently TH
12505 val = ((w_order == 0) ? 2 : 3);
12506 REG_WR(sc, PXP2_REG_WR_HC_MPS, val);
12507 REG_WR(sc, PXP2_REG_WR_USDM_MPS, val);
12508 REG_WR(sc, PXP2_REG_WR_CSDM_MPS, val);
12509 REG_WR(sc, PXP2_REG_WR_TSDM_MPS, val);
12510 REG_WR(sc, PXP2_REG_WR_XSDM_MPS, val);
12511 REG_WR(sc, PXP2_REG_WR_QM_MPS, val);
12512 REG_WR(sc, PXP2_REG_WR_TM_MPS, val);
12513 REG_WR(sc, PXP2_REG_WR_SRC_MPS, val);
12514 REG_WR(sc, PXP2_REG_WR_DBG_MPS, val);
12515 REG_WR(sc, PXP2_REG_WR_DMAE_MPS, 2); /* DMAE is special */
12516 REG_WR(sc, PXP2_REG_WR_CDU_MPS, val);
12521 bxe_init_pxp(struct bxe_softc *sc)
12524 int r_order, w_order;
12526 devctl = pci_read_config(sc->dev,
12527 sc->pcie_cap + PCI_EXP_DEVCTL, 2);
12528 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12529 "%s(): Read 0x%x from devctl\n", __FUNCTION__, devctl);
12530 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
12531 if (sc->mrrs == -1)
12532 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
12534 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12535 "%s(): Force MRRS read order to %d\n",
12536 __FUNCTION__, sc->mrrs);
12537 r_order = sc->mrrs;
12540 bxe_init_pxp_arb(sc, r_order, w_order);
12544 bxe_setup_fan_failure_detection(struct bxe_softc *sc)
12546 uint32_t phy_type, val;
12547 int is_required, port;
12553 val = SHMEM_RD(sc, dev_info.shared_hw_config.config2) &
12554 SHARED_HW_CFG_FAN_FAILURE_MASK;
12556 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
12560 * The fan failure mechanism is usually related to the PHY type since
12561 * the power consumption of the board is affected by the PHY. Currently,
12562 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
12564 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
12565 for (port = PORT_0; port < PORT_MAX; port++) {
12566 phy_type = SHMEM_RD(sc,
12567 dev_info.port_hw_config[port].external_phy_config) &
12568 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
12570 ((phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) ||
12571 (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
12572 (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481));
12575 if (is_required == 0)
12578 /* Fan failure is indicated by SPIO 5. */
12579 bxe_set_spio(sc, MISC_REGISTERS_SPIO_5, MISC_REGISTERS_SPIO_INPUT_HI_Z);
12581 /* Set to active low mode. */
12582 val = REG_RD(sc, MISC_REG_SPIO_INT);
12583 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
12584 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
12585 REG_WR(sc, MISC_REG_SPIO_INT, val);
12587 /* Enable interrupt to signal the IGU. */
12588 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN);
12589 val |= (1 << MISC_REGISTERS_SPIO_5);
12590 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val);
12594 * Common initialization.
12597 * 0 = Success, !0 = Failure.
12600 bxe_init_common(struct bxe_softc *sc)
12606 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12608 /* Reset all blocks within the chip except the BMAC. */
12609 bxe_reset_common(sc);
12611 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
12612 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 0xfffc);
12615 bxe_init_block(sc, MISC_BLOCK, COMMON_STAGE);
12616 if (CHIP_IS_E1H(sc))
12617 REG_WR(sc, MISC_REG_E1HMF_MODE, IS_E1HMF(sc));
12619 REG_WR(sc, MISC_REG_LCPLL_CTRL_REG_2, 0x100);
12621 REG_WR(sc, MISC_REG_LCPLL_CTRL_REG_2, 0x0);
12623 bxe_init_block(sc, PXP_BLOCK, COMMON_STAGE);
12624 if (CHIP_IS_E1(sc)) {
12626 * Enable HW interrupt from PXP on USDM overflow
12627 * bit 16 on INT_MASK_0.
12629 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0);
12632 bxe_init_block(sc, PXP2_BLOCK, COMMON_STAGE);
12635 #ifdef __BIG_ENDIAN
12636 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1);
12637 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1);
12638 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
12639 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
12640 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
12641 /* Make sure this value is 0. */
12642 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0);
12644 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1);
12645 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1);
12646 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1);
12647 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
12650 REG_WR(sc, PXP2_REG_RQ_CDU_P_SIZE, 2);
12652 /* Let the HW do it's magic ... */
12654 /* Finish the PXP initialization. */
12655 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE);
12657 BXE_PRINTF("%s(%d): PXP2 CFG failed!\n", __FILE__, __LINE__);
12659 goto bxe_init_common_exit;
12662 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE);
12664 BXE_PRINTF("%s(%d): PXP2 RD_INIT failed!\n", __FILE__,
12667 goto bxe_init_common_exit;
12670 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0);
12671 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0);
12673 bxe_init_block(sc, DMAE_BLOCK, COMMON_STAGE);
12675 sc->dmae_ready = 1;
12676 bxe_init_fill(sc, TSEM_REG_PRAM, 0, 8);
12678 bxe_init_block(sc, TCM_BLOCK, COMMON_STAGE);
12679 bxe_init_block(sc, UCM_BLOCK, COMMON_STAGE);
12680 bxe_init_block(sc, CCM_BLOCK, COMMON_STAGE);
12681 bxe_init_block(sc, XCM_BLOCK, COMMON_STAGE);
12683 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3);
12684 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3);
12685 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3);
12686 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3);
12688 bxe_init_block(sc, QM_BLOCK, COMMON_STAGE);
12690 /* Soft reset pulse. */
12691 REG_WR(sc, QM_REG_SOFT_RESET, 1);
12692 REG_WR(sc, QM_REG_SOFT_RESET, 0);
12694 bxe_init_block(sc, DQ_BLOCK, COMMON_STAGE);
12695 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BCM_PAGE_SHIFT);
12697 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0);
12699 bxe_init_block(sc, BRB1_BLOCK, COMMON_STAGE);
12700 bxe_init_block(sc, PRS_BLOCK, COMMON_STAGE);
12701 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf);
12703 if (CHIP_IS_E1H(sc))
12704 REG_WR(sc, PRS_REG_E1HOV_MODE, IS_E1HMF(sc));
12706 bxe_init_block(sc, TSDM_BLOCK, COMMON_STAGE);
12707 bxe_init_block(sc, CSDM_BLOCK, COMMON_STAGE);
12708 bxe_init_block(sc, USDM_BLOCK, COMMON_STAGE);
12709 bxe_init_block(sc, XSDM_BLOCK, COMMON_STAGE);
12710 /* Clear STORM processor memory. */
12711 bxe_init_fill(sc, TSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
12712 bxe_init_fill(sc, USEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
12713 bxe_init_fill(sc, CSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
12714 bxe_init_fill(sc, XSEM_REG_FAST_MEMORY, 0, STORM_INTMEM_SIZE(sc));
12716 bxe_init_block(sc, TSEM_BLOCK, COMMON_STAGE);
12717 bxe_init_block(sc, USEM_BLOCK, COMMON_STAGE);
12718 bxe_init_block(sc, CSEM_BLOCK, COMMON_STAGE);
12719 bxe_init_block(sc, XSEM_BLOCK, COMMON_STAGE);
12721 /* Sync semi rtc. */
12722 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x80000000);
12723 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x80000000);
12725 bxe_init_block(sc, UPB_BLOCK, COMMON_STAGE);
12726 bxe_init_block(sc, XPB_BLOCK, COMMON_STAGE);
12727 bxe_init_block(sc, PBF_BLOCK, COMMON_STAGE);
12729 REG_WR(sc, SRC_REG_SOFT_RST, 1);
12730 /* Setup RSS/multi-queue hasking keys. */
12731 for (i = SRC_REG_KEYRSS0_0; i <= SRC_REG_KEYRSS1_9; i += 4)
12732 REG_WR(sc, i, 0xc0cac01a);
12734 bxe_init_block(sc, SRCH_BLOCK, COMMON_STAGE);
12736 REG_WR(sc, SRC_REG_SOFT_RST, 0);
12738 /* Make sure the cdu_context structure has the right size. */
12739 if (sizeof(union cdu_context) != 1024) {
12740 BXE_PRINTF("%s(%d): Invalid size for context (%ld != 1024)!\n",
12741 __FILE__, __LINE__, (long)sizeof(union cdu_context));
12743 goto bxe_init_common_exit;
12746 bxe_init_block(sc, CDU_BLOCK, COMMON_STAGE);
12749 * val = (num_context_in_page << 24) +
12750 * (context_waste_size << 12) +
12751 * context_line_size.
12754 val = (4 << 24) + (0 << 12) + 1024;
12755 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val);
12757 bxe_init_block(sc, CFC_BLOCK, COMMON_STAGE);
12758 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF);
12759 /* Enable context validation interrupt from CFC. */
12760 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0);
12762 /* Set the thresholds to prevent CFC/CDU race. */
12763 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000);
12765 bxe_init_block(sc, HC_BLOCK, COMMON_STAGE);
12766 bxe_init_block(sc, MISC_AEU_BLOCK, COMMON_STAGE);
12768 bxe_init_block(sc, PXPCS_BLOCK, COMMON_STAGE);
12769 /* Clear PCIe block debug status bits. */
12770 REG_WR(sc, 0x2814, 0xffffffff);
12771 REG_WR(sc, 0x3820, 0xffffffff);
12773 bxe_init_block(sc, EMAC0_BLOCK, COMMON_STAGE);
12774 bxe_init_block(sc, EMAC1_BLOCK, COMMON_STAGE);
12775 bxe_init_block(sc, DBU_BLOCK, COMMON_STAGE);
12776 bxe_init_block(sc, DBG_BLOCK, COMMON_STAGE);
12778 bxe_init_block(sc, NIG_BLOCK, COMMON_STAGE);
12779 if (CHIP_IS_E1H(sc)) {
12780 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_E1HMF(sc));
12781 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_E1HOV(sc));
12784 /* Finish CFC initialization. */
12785 val = bxe_reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10);
12787 BXE_PRINTF("%s(%d): CFC LL_INIT failed!\n",
12788 __FILE__, __LINE__);
12790 goto bxe_init_common_exit;
12793 val = bxe_reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10);
12795 BXE_PRINTF("%s(%d): CFC AC_INIT failed!\n",
12796 __FILE__, __LINE__);
12798 goto bxe_init_common_exit;
12801 val = bxe_reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
12803 BXE_PRINTF("%s(%d): CFC CAM_INIT failed!\n",
12804 __FILE__, __LINE__);
12806 goto bxe_init_common_exit;
12809 REG_WR(sc, CFC_REG_DEBUG0, 0);
12811 /* Read NIG statistic and check for first load since powerup. */
12812 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2);
12813 val = *BXE_SP(sc, wb_data[0]);
12815 /* Do internal memory self test only after a full power cycle. */
12816 if ((CHIP_IS_E1(sc)) && (val == 0) && bxe_int_mem_test(sc)) {
12817 BXE_PRINTF("%s(%d): Internal memory self-test failed!\n",
12818 __FILE__, __LINE__);
12820 goto bxe_init_common_exit;
12823 /* Handle any board specific initialization. */
12824 switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
12825 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072:
12826 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
12827 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12828 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
12835 bxe_setup_fan_failure_detection(sc);
12837 /* Clear PXP2 attentions. */
12838 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0);
12840 bxe_enable_blocks_attention(sc);
12843 bxe_acquire_phy_lock(sc);
12844 bxe_common_init_phy(sc, sc->common.shmem_base);
12845 bxe_release_phy_lock(sc);
12848 "%s(%d): Bootcode is missing - cannot initialize PHY!\n",
12849 __FILE__, __LINE__);
12851 bxe_init_common_exit:
12852 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12857 * Port initialization.
12860 * 0 = Success, !0 = Failure.
12863 bxe_init_port(struct bxe_softc *sc)
12865 uint32_t val, low, high;
12866 uint32_t swap_val, swap_override, aeu_gpio_mask, offset;
12868 int init_stage, port;
12870 port = BP_PORT(sc);
12871 init_stage = port ? PORT1_STAGE : PORT0_STAGE;
12873 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
12875 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
12876 "%s(): Initializing port %d.\n", __FUNCTION__, port);
12878 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
12880 bxe_init_block(sc, PXP_BLOCK, init_stage);
12881 bxe_init_block(sc, PXP2_BLOCK, init_stage);
12883 bxe_init_block(sc, TCM_BLOCK, init_stage);
12884 bxe_init_block(sc, UCM_BLOCK, init_stage);
12885 bxe_init_block(sc, CCM_BLOCK, init_stage);
12886 bxe_init_block(sc, XCM_BLOCK, init_stage);
12888 bxe_init_block(sc, DQ_BLOCK, init_stage);
12890 bxe_init_block(sc, BRB1_BLOCK, init_stage);
12892 /* Determine the pause threshold for the BRB */
12894 low = (sc->bxe_flags & BXE_ONE_PORT_FLAG) ? 160 : 246;
12895 else if (sc->bxe_ifp->if_mtu > 4096) {
12896 if (sc->bxe_flags & BXE_ONE_PORT_FLAG)
12899 val = sc->bxe_ifp->if_mtu;
12900 /* (24*1024 + val*4)/256 */
12901 low = 96 + (val/64) + ((val % 64) ? 1 : 0);
12904 low = (sc->bxe_flags & BXE_ONE_PORT_FLAG) ? 80 : 160;
12905 high = low + 56; /* 14 * 1024 / 256 */
12907 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port * 4, low);
12908 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port * 4, high);
12910 /* Port PRS comes here. */
12911 bxe_init_block(sc, PRS_BLOCK, init_stage);
12913 bxe_init_block(sc, TSDM_BLOCK, init_stage);
12914 bxe_init_block(sc, CSDM_BLOCK, init_stage);
12915 bxe_init_block(sc, USDM_BLOCK, init_stage);
12916 bxe_init_block(sc, XSDM_BLOCK, init_stage);
12918 bxe_init_block(sc, TSEM_BLOCK, init_stage);
12919 bxe_init_block(sc, USEM_BLOCK, init_stage);
12920 bxe_init_block(sc, CSEM_BLOCK, init_stage);
12921 bxe_init_block(sc, XSEM_BLOCK, init_stage);
12923 bxe_init_block(sc, UPB_BLOCK, init_stage);
12924 bxe_init_block(sc, XPB_BLOCK, init_stage);
12926 bxe_init_block(sc, PBF_BLOCK, init_stage);
12928 /* Configure PBF to work without pause for MTU = 9000. */
12929 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port * 4, 0);
12931 /* Update threshold. */
12932 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port * 4, (9040/16));
12933 /* Update initial credit. */
12934 REG_WR(sc, PBF_REG_P0_INIT_CRD + port * 4, (9040/16) + 553 - 22);
12936 /* Probe changes. */
12937 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 1);
12939 REG_WR(sc, PBF_REG_INIT_P0 + port * 4, 0);
12941 bxe_init_block(sc, CDU_BLOCK, init_stage);
12942 bxe_init_block(sc, CFC_BLOCK, init_stage);
12944 if (CHIP_IS_E1(sc)) {
12945 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
12946 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
12949 bxe_init_block(sc, HC_BLOCK, init_stage);
12951 bxe_init_block(sc, MISC_AEU_BLOCK, init_stage);
12953 * init aeu_mask_attn_func_0/1:
12954 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
12955 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
12956 * bits 4-7 are used for "per vn group attention"
12958 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4,
12959 (IS_E1HMF(sc) ? 0xF7 : 0x7));
12961 bxe_init_block(sc, PXPCS_BLOCK, init_stage);
12962 bxe_init_block(sc, EMAC0_BLOCK, init_stage);
12963 bxe_init_block(sc, EMAC1_BLOCK, init_stage);
12964 bxe_init_block(sc, DBU_BLOCK, init_stage);
12965 bxe_init_block(sc, DBG_BLOCK, init_stage);
12967 bxe_init_block(sc, NIG_BLOCK, init_stage);
12969 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port * 4, 1);
12971 if (CHIP_IS_E1H(sc)) {
12972 /* Enable outer VLAN support if required. */
12973 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port * 4,
12974 (IS_E1HOV(sc) ? 0x1 : 0x2));
12977 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port * 4, 0);
12978 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port * 4, 0);
12979 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port * 4, 1);
12981 bxe_init_block(sc, MCP_BLOCK, init_stage);
12982 bxe_init_block(sc, DMAE_BLOCK, init_stage);
12984 switch (XGXS_EXT_PHY_TYPE(sc->link_params.ext_phy_config)) {
12985 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
12986 bxe_set_gpio(sc, MISC_REGISTERS_GPIO_3,
12987 MISC_REGISTERS_GPIO_INPUT_HI_Z, port);
12990 * The GPIO should be swapped if the swap register is
12993 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
12994 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
12996 /* Select function upon port-swap configuration. */
12998 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
12999 aeu_gpio_mask = (swap_val && swap_override) ?
13000 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1 :
13001 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0;
13003 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
13004 aeu_gpio_mask = (swap_val && swap_override) ?
13005 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_0 :
13006 AEU_INPUTS_ATTN_BITS_GPIO3_FUNCTION_1;
13008 val = REG_RD(sc, offset);
13009 /* Add GPIO3 to group. */
13010 val |= aeu_gpio_mask;
13011 REG_WR(sc, offset, val);
13013 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
13014 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13015 /* Add SPIO 5 to group 0. */
13016 reg_addr = port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
13017 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
13018 val = REG_RD(sc, reg_addr);
13019 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
13020 REG_WR(sc, reg_addr, val);
13026 bxe__link_reset(sc);
13028 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13033 #define ILT_PER_FUNC (768/2)
13034 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
13036 * The phys address is shifted right 12 bits and has an added 1=valid
13037 * bit added to the 53rd bit (bit 52) then since this is a wide
13038 * register(TM) we split it into two 32 bit writes.
13040 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
13041 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
13042 #define PXP_ONE_ILT(x) (((x) << 10) | x)
13043 #define PXP_ILT_RANGE(f, l) (((l) << 10) | f)
13044 #define CNIC_ILT_LINES 0
13053 bxe_ilt_wr(struct bxe_softc *sc, uint32_t index, bus_addr_t addr)
13057 DBENTER(BXE_INSANE_LOAD | BXE_INSANE_RESET);
13059 if (CHIP_IS_E1H(sc))
13060 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index * 8;
13062 reg = PXP2_REG_RQ_ONCHIP_AT + index * 8;
13064 bxe_wb_wr(sc, reg, ONCHIP_ADDR1(addr), ONCHIP_ADDR2(addr));
13066 DBEXIT(BXE_INSANE_LOAD | BXE_INSANE_RESET);
13070 * Initialize a function.
13073 * 0 = Success, !0 = Failure.
13076 bxe_init_func(struct bxe_softc *sc)
13078 uint32_t addr, val;
13081 port = BP_PORT(sc);
13082 func = BP_FUNC(sc);
13084 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13086 DBPRINT(sc, (BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET),
13087 "%s(): Initializing port %d, function %d.\n", __FUNCTION__, port,
13090 /* Set MSI reconfigure capability. */
13091 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
13092 val = REG_RD(sc, addr);
13093 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
13094 REG_WR(sc, addr, val);
13096 i = FUNC_ILT_BASE(func);
13098 bxe_ilt_wr(sc, i, BXE_SP_MAPPING(sc, context));
13100 if (CHIP_IS_E1H(sc)) {
13101 REG_WR(sc, PXP2_REG_RQ_CDU_FIRST_ILT, i);
13102 REG_WR(sc, PXP2_REG_RQ_CDU_LAST_ILT, i + CNIC_ILT_LINES);
13104 REG_WR(sc, PXP2_REG_PSWRQ_CDU0_L2P + func * 4,
13105 PXP_ILT_RANGE(i, i + CNIC_ILT_LINES));
13107 if (CHIP_IS_E1H(sc)) {
13108 bxe_init_block(sc, MISC_BLOCK, FUNC0_STAGE + func);
13109 bxe_init_block(sc, TCM_BLOCK, FUNC0_STAGE + func);
13110 bxe_init_block(sc, UCM_BLOCK, FUNC0_STAGE + func);
13111 bxe_init_block(sc, CCM_BLOCK, FUNC0_STAGE + func);
13112 bxe_init_block(sc, XCM_BLOCK, FUNC0_STAGE + func);
13113 bxe_init_block(sc, TSEM_BLOCK, FUNC0_STAGE + func);
13114 bxe_init_block(sc, USEM_BLOCK, FUNC0_STAGE + func);
13115 bxe_init_block(sc, CSEM_BLOCK, FUNC0_STAGE + func);
13116 bxe_init_block(sc, XSEM_BLOCK, FUNC0_STAGE + func);
13118 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port * 8, 1);
13119 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port * 8, sc->e1hov);
13122 /* Host Coalescing initialization per function. */
13123 if (CHIP_IS_E1H(sc)) {
13124 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func * 4, 0);
13125 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
13126 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
13129 bxe_init_block(sc, HC_BLOCK, FUNC0_STAGE + func);
13131 /* Reset PCIe block debug values. */
13132 REG_WR(sc, 0x2114, 0xffffffff);
13133 REG_WR(sc, 0x2120, 0xffffffff);
13135 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13143 * 0 = Failure, !0 = Failure.
13146 bxe_init_hw(struct bxe_softc *sc, uint32_t load_code)
13151 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13153 sc->dmae_ready = 0;
13154 switch (load_code) {
13155 case FW_MSG_CODE_DRV_LOAD_COMMON:
13156 rc = bxe_init_common(sc);
13158 goto bxe_init_hw_exit;
13160 case FW_MSG_CODE_DRV_LOAD_PORT:
13161 sc->dmae_ready = 1;
13162 rc = bxe_init_port(sc);
13164 goto bxe_init_hw_exit;
13166 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
13167 sc->dmae_ready = 1;
13168 rc = bxe_init_func(sc);
13170 goto bxe_init_hw_exit;
13173 DBPRINT(sc, BXE_WARN,
13174 "%s(): Unknown load_code (0x%08X) from MCP!\n",
13175 __FUNCTION__, load_code);
13179 /* Fetch additional config data if the bootcode is running. */
13181 func = BP_FUNC(sc);
13182 /* Fetch the pulse sequence number. */
13183 sc->fw_drv_pulse_wr_seq = (SHMEM_RD(sc,
13184 func_mb[func].drv_pulse_mb) & DRV_PULSE_SEQ_MASK);
13187 /* Clear the default status block. */
13188 bxe_zero_def_sb(sc);
13189 for (i = 0; i < sc->num_queues; i++)
13190 bxe_zero_sb(sc, BP_L_ID(sc) + i);
13193 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13199 * Send a firmware command and wait for the response.
13201 * Post a command to shared memory for the bootcode running on the MCP and
13202 * stall until the bootcode responds or a timeout occurs.
13205 * 0 = Failure, otherwise firmware response code (FW_MSG_CODE_*).
13208 bxe_fw_command(struct bxe_softc *sc, uint32_t command)
13210 uint32_t cnt, rc, seq;
13213 func = BP_FUNC(sc);
13214 seq = ++sc->fw_seq;
13218 DBRUNMSG(BXE_VERBOSE, bxe_decode_mb_msgs(sc, (command | seq), 0));
13222 /* Write the command to the shared memory mailbox. */
13223 SHMEM_WR(sc, func_mb[func].drv_mb_header, (command | seq));
13225 /* Wait up to 2 seconds for a response. */
13227 /* Wait 10ms for a response. */
13230 /* Pickup the response. */
13231 rc = SHMEM_RD(sc, func_mb[func].fw_mb_header);
13232 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 400));
13234 DBRUNMSG(BXE_VERBOSE, bxe_decode_mb_msgs(sc, 0, rc));
13236 /* Make sure we read the right response. */
13237 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK ))
13238 rc &= FW_MSG_CODE_MASK;
13240 BXE_PRINTF("%s(%d): Bootcode failed to respond!\n",
13241 __FILE__, __LINE__);
13242 DBRUN(bxe_dump_fw(sc));
13246 BXE_FWMB_UNLOCK(sc);
13251 * Allocate a block of memory and map it for DMA. No partial
13252 * completions allowed, release any resources acquired if we
13253 * can't acquire all resources.
13256 * 0 = Success, !0 = Failure
13267 bxe_dma_malloc(struct bxe_softc *sc, bus_size_t size,
13268 struct bxe_dma *dma, int mapflags, const char *msg)
13272 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13274 DBRUNIF(dma->size > 0,
13275 BXE_PRINTF("%s(): Called for %s with size > 0 (%05d)!\n",
13276 __FUNCTION__, msg, (int) dma->size));
13278 rc = bus_dma_tag_create(
13279 sc->parent_tag, /* parent */
13280 BCM_PAGE_SIZE, /* alignment for segs */
13281 BXE_DMA_BOUNDARY, /* cannot cross */
13282 BUS_SPACE_MAXADDR, /* restricted low */
13283 BUS_SPACE_MAXADDR, /* restricted hi */
13284 NULL, NULL, /* filter f(), arg */
13285 size, /* max size for this tag */
13286 1, /* # of discontinuities */
13287 size, /* max seg size */
13288 BUS_DMA_ALLOCNOW, /* flags */
13289 NULL, NULL, /* lock f(), arg */
13293 BXE_PRINTF("%s(%d): bus_dma_tag_create() "
13294 "failed (rc = %d) for %s!\n",
13295 __FILE__, __LINE__, rc, msg);
13296 goto bxe_dma_malloc_fail_create;
13299 rc = bus_dmamem_alloc(dma->tag, (void **)&dma->vaddr,
13300 BUS_DMA_NOWAIT, &dma->map);
13302 BXE_PRINTF("%s(%d): bus_dmamem_alloc() "
13303 "failed (rc = %d) for %s!\n",
13304 __FILE__, __LINE__, rc, msg);
13305 goto bxe_dma_malloc_fail_alloc;
13308 rc = bus_dmamap_load(dma->tag, dma->map, dma->vaddr, size,
13309 bxe_dma_map_addr, &dma->paddr, mapflags | BUS_DMA_NOWAIT);
13311 BXE_PRINTF("%s(%d): bus_dmamap_load() "
13312 "failed (rc = %d) for %s!\n",
13313 __FILE__, __LINE__, rc, msg);
13314 goto bxe_dma_malloc_fail_load;
13319 DBPRINT(sc, BXE_VERBOSE, "%s(): size=%06d, vaddr=0x%p, "
13320 "paddr=0x%jX - %s\n", __FUNCTION__, (int) dma->size,
13321 dma->vaddr, (uintmax_t) dma->paddr, msg);
13323 goto bxe_dma_malloc_exit;
13325 bxe_dma_malloc_fail_load:
13326 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
13328 bxe_dma_malloc_fail_alloc:
13329 bus_dma_tag_destroy(dma->tag);
13332 bxe_dma_malloc_fail_create:
13337 bxe_dma_malloc_exit:
13338 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
13343 * Release a block of DMA memory associated tag/map.
13349 bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma)
13351 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_UNLOAD);
13353 if (dma->size > 0) {
13354 bus_dmamap_sync(dma->tag, dma->map,
13355 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
13356 bus_dmamap_unload(dma->tag, dma->map);
13357 bus_dmamem_free(dma->tag, dma->vaddr, dma->map);
13358 bus_dma_tag_destroy(dma->tag);
13362 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_UNLOAD);
13366 * Free any DMA memory owned by the driver.
13368 * Scans through each data structre that requires DMA memory and frees
13369 * the memory if allocated.
13375 bxe_host_structures_free(struct bxe_softc *sc)
13377 struct bxe_fastpath *fp;
13378 int i, j, max_agg_queues;
13380 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
13381 max_agg_queues = CHIP_IS_E1H(sc) ?
13382 ETH_MAX_AGGREGATION_QUEUES_E1H :
13383 ETH_MAX_AGGREGATION_QUEUES_E1;
13385 if (sc->parent_tag == NULL)
13386 goto bxe_host_structures_free_exit;
13388 for (i = 0; i < sc->num_queues; i++) {
13391 /* Trust no one! */
13395 /* Status block. */
13396 bxe_dma_free(sc, &fp->sb_dma);
13399 bxe_dma_free(sc, &fp->tx_dma);
13400 fp->tx_chain = NULL;
13403 bxe_dma_free(sc, &fp->rx_dma);
13404 fp->rx_chain = NULL;
13407 bxe_dma_free(sc, &fp->rcq_dma);
13408 fp->rcq_chain = NULL;
13411 bxe_dma_free(sc, &fp->sg_dma);
13412 fp->sg_chain = NULL;
13414 /* Unload and destroy the TX mbuf maps. */
13415 if (fp->tx_mbuf_tag != NULL) {
13416 for (j = 0; j < TOTAL_TX_BD; j++) {
13417 if (fp->tx_mbuf_map[j] != NULL) {
13420 fp->tx_mbuf_map[j]);
13421 bus_dmamap_destroy(
13423 fp->tx_mbuf_map[j]);
13427 bus_dma_tag_destroy(fp->tx_mbuf_tag);
13430 /* Unload and destroy the TPA pool mbuf maps. */
13431 if (fp->rx_mbuf_tag != NULL) {
13432 if (fp->tpa_mbuf_spare_map != NULL) {
13435 fp->tpa_mbuf_spare_map);
13436 bus_dmamap_destroy(
13438 fp->tpa_mbuf_spare_map);
13441 for (j = 0; j < max_agg_queues; j++) {
13442 if (fp->tpa_mbuf_map[j] != NULL) {
13445 fp->tpa_mbuf_map[j]);
13446 bus_dmamap_destroy(
13448 fp->tpa_mbuf_map[j]);
13453 /* Unload and destroy the SGE Buf maps. */
13454 if (fp->rx_sge_buf_tag != NULL) {
13455 if (fp->rx_sge_spare_map != NULL) {
13457 fp->rx_sge_buf_tag,
13458 fp->rx_sge_spare_map);
13459 bus_dmamap_destroy(
13460 fp->rx_sge_buf_tag,
13461 fp->rx_sge_spare_map);
13464 for (j = 0; j < TOTAL_RX_SGE; j++) {
13465 if (fp->rx_sge_buf_map[j] != NULL) {
13467 fp->rx_sge_buf_tag,
13468 fp->rx_sge_buf_map[j]);
13469 bus_dmamap_destroy(
13470 fp->rx_sge_buf_tag,
13471 fp->rx_sge_buf_map[j]);
13475 bus_dma_tag_destroy(fp->rx_sge_buf_tag);
13478 /* Unload and destroy the RX mbuf maps. */
13479 if (fp->rx_mbuf_tag != NULL) {
13480 if (fp->rx_mbuf_spare_map != NULL) {
13481 bus_dmamap_unload(fp->rx_mbuf_tag,
13482 fp->rx_mbuf_spare_map);
13483 bus_dmamap_destroy(fp->rx_mbuf_tag,
13484 fp->rx_mbuf_spare_map);
13487 for (j = 0; j < TOTAL_RX_BD; j++) {
13488 if (fp->rx_mbuf_map[j] != NULL) {
13491 fp->rx_mbuf_map[j]);
13492 bus_dmamap_destroy(
13494 fp->rx_mbuf_map[j]);
13498 bus_dma_tag_destroy(fp->rx_mbuf_tag);
13502 /* Destroy the default status block */
13503 bxe_dma_free(sc, &sc->def_sb_dma);
13506 /* Destroy the statistics block */
13507 bxe_dma_free(sc, &sc->stats_dma);
13510 /* Destroy the slowpath block. */
13511 bxe_dma_free(sc, &sc->slowpath_dma);
13512 sc->slowpath = NULL;
13514 /* Destroy the slowpath queue. */
13515 bxe_dma_free(sc, &sc->spq_dma);
13518 /* Destroy the slowpath queue. */
13519 bxe_dma_free(sc, &sc->gz_dma);
13521 free(sc->strm, M_DEVBUF);
13524 bxe_host_structures_free_exit:
13525 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
13529 * Get DMA memory from the OS.
13531 * Validates that the OS has provided DMA buffers in response to a
13532 * bus_dmamap_load call and saves the physical address of those buffers.
13533 * When the callback is used the OS will return 0 for the mapping function
13534 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any
13535 * failures back to the caller.
13541 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
13543 bus_addr_t *busaddr;
13546 /* Check for an error and signal the caller that an error occurred. */
13549 "bxe %s(%d): DMA mapping error (error = %d, nseg = %d)!\n",
13550 __FILE__, __LINE__, error, nseg);
13555 *busaddr = segs->ds_addr;
13559 * Allocate any non-paged DMA memory needed by the driver.
13562 * 0 = Success, !0 = Failure.
13565 bxe_host_structures_alloc(device_t dev)
13567 struct bxe_softc *sc;
13568 struct bxe_fastpath *fp;
13570 bus_addr_t busaddr;
13571 bus_size_t max_size, max_seg_size;
13572 int i, j, max_segments;
13574 sc = device_get_softc(dev);
13575 DBENTER(BXE_VERBOSE_RESET);
13577 int max_agg_queues = CHIP_IS_E1H(sc) ?
13578 ETH_MAX_AGGREGATION_QUEUES_E1H :
13579 ETH_MAX_AGGREGATION_QUEUES_E1;
13582 * Allocate the parent bus DMA tag appropriate for PCI.
13584 rc = bus_dma_tag_create(
13585 bus_get_dma_tag(dev), /* PCI parent tag */
13586 1, /* alignment for segs */
13587 BXE_DMA_BOUNDARY, /* cannot cross */
13588 BUS_SPACE_MAXADDR, /* restricted low */
13589 BUS_SPACE_MAXADDR, /* restricted hi */
13590 NULL, /* filter f() */
13591 NULL, /* filter f() arg */
13592 MAXBSIZE, /* max map for this tag */
13593 BUS_SPACE_UNRESTRICTED, /* # of discontinuities */
13594 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */
13596 NULL, /* lock f() */
13597 NULL, /* lock f() arg */
13598 &sc->parent_tag); /* dma tag */
13600 BXE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
13601 __FILE__, __LINE__);
13603 goto bxe_host_structures_alloc_exit;
13606 /* Allocate DMA memory for each fastpath structure. */
13607 for (i = 0; i < sc->num_queues; i++) {
13611 * Allocate status block*
13613 rc = bxe_dma_malloc(sc, BXE_STATUS_BLK_SZ,
13614 &fp->sb_dma, BUS_DMA_NOWAIT, "fp status block");
13615 /* ToDo: Only using 32 bytes out of 4KB allocation! */
13617 goto bxe_host_structures_alloc_exit;
13619 (struct host_status_block *) fp->sb_dma.vaddr;
13622 * Allocate TX chain.
13624 rc = bxe_dma_malloc(sc, BXE_TX_CHAIN_PAGE_SZ *
13625 NUM_TX_PAGES, &fp->tx_dma, BUS_DMA_NOWAIT,
13628 goto bxe_host_structures_alloc_exit;
13629 fp->tx_chain = (union eth_tx_bd_types *) fp->tx_dma.vaddr;
13631 /* Link the TX chain pages. */
13632 for (j = 1; j <= NUM_TX_PAGES; j++) {
13633 struct eth_tx_next_bd *tx_n_bd =
13634 &fp->tx_chain[TOTAL_TX_BD_PER_PAGE * j - 1].next_bd;
13636 busaddr = fp->tx_dma.paddr +
13637 BCM_PAGE_SIZE * (j % NUM_TX_PAGES);
13638 tx_n_bd->addr_hi = htole32(U64_HI(busaddr));
13639 tx_n_bd->addr_lo = htole32(U64_LO(busaddr));
13643 * Allocate RX chain.
13645 rc = bxe_dma_malloc(sc, BXE_RX_CHAIN_PAGE_SZ *
13646 NUM_RX_PAGES, &fp->rx_dma, BUS_DMA_NOWAIT,
13649 goto bxe_host_structures_alloc_exit;
13650 fp->rx_chain = (struct eth_rx_bd *) fp->rx_dma.vaddr;
13652 /* Link the RX chain pages. */
13653 for (j = 1; j <= NUM_RX_PAGES; j++) {
13654 struct eth_rx_bd *rx_bd =
13655 &fp->rx_chain[TOTAL_RX_BD_PER_PAGE * j - 2];
13657 busaddr = fp->rx_dma.paddr +
13658 BCM_PAGE_SIZE * (j % NUM_RX_PAGES);
13659 rx_bd->addr_hi = htole32(U64_HI(busaddr));
13660 rx_bd->addr_lo = htole32(U64_LO(busaddr));
13664 * Allocate CQ chain.
13666 rc = bxe_dma_malloc(sc, BXE_RX_CHAIN_PAGE_SZ *
13667 NUM_RCQ_PAGES, &fp->rcq_dma, BUS_DMA_NOWAIT,
13668 "rcq chain pages");
13670 goto bxe_host_structures_alloc_exit;
13671 fp->rcq_chain = (union eth_rx_cqe *) fp->rcq_dma.vaddr;
13673 /* Link the CQ chain pages. */
13674 for (j = 1; j <= NUM_RCQ_PAGES; j++) {
13675 struct eth_rx_cqe_next_page *nextpg =
13676 (struct eth_rx_cqe_next_page *)
13677 &fp->rcq_chain[TOTAL_RCQ_ENTRIES_PER_PAGE * j - 1];
13679 busaddr = fp->rcq_dma.paddr +
13680 BCM_PAGE_SIZE * (j % NUM_RCQ_PAGES);
13681 nextpg->addr_hi = htole32(U64_HI(busaddr));
13682 nextpg->addr_lo = htole32(U64_LO(busaddr));
13686 * Allocate SG chain.
13688 rc = bxe_dma_malloc(sc, BXE_RX_CHAIN_PAGE_SZ *
13689 NUM_RX_SGE_PAGES, &fp->sg_dma, BUS_DMA_NOWAIT,
13692 goto bxe_host_structures_alloc_exit;
13693 fp->sg_chain = (struct eth_rx_sge *) fp->sg_dma.vaddr;
13695 /* Link the SG chain pages. */
13696 for (j = 1; j <= NUM_RX_SGE_PAGES; j++) {
13697 struct eth_rx_sge *nextpg =
13698 &fp->sg_chain[TOTAL_RX_SGE_PER_PAGE * j - 2];
13700 busaddr = fp->sg_dma.paddr +
13701 BCM_PAGE_SIZE * (j % NUM_RX_SGE_PAGES);
13702 nextpg->addr_hi = htole32(U64_HI(busaddr));
13703 nextpg->addr_lo = htole32(U64_LO(busaddr));
13707 * Check required size before mapping to conserve resources.
13709 if (sc->tso_enable == TRUE) {
13710 max_size = BXE_TSO_MAX_SIZE;
13711 max_segments = BXE_TSO_MAX_SEGMENTS;
13712 max_seg_size = BXE_TSO_MAX_SEG_SIZE;
13714 max_size = MCLBYTES * BXE_MAX_SEGMENTS;
13715 max_segments = BXE_MAX_SEGMENTS;
13716 max_seg_size = MCLBYTES;
13719 /* Create a DMA tag for TX mbufs. */
13720 if (bus_dma_tag_create(sc->parent_tag,
13721 1, /* alignment for segs */
13722 BXE_DMA_BOUNDARY, /* cannot cross */
13723 BUS_SPACE_MAXADDR, /* restricted low */
13724 BUS_SPACE_MAXADDR, /* restricted hi */
13725 NULL, /* filter f() */
13726 NULL, /* filter f() arg */
13727 max_size, /* max map for this tag */
13728 max_segments, /* # of discontinuities */
13729 max_seg_size, /* max seg size */
13731 NULL, /* lock f() */
13732 NULL, /* lock f() arg */
13733 &fp->tx_mbuf_tag)) {
13735 "%s(%d): Could not allocate fp[%d] "
13736 "TX mbuf DMA tag!\n",
13737 __FILE__, __LINE__, i);
13739 goto bxe_host_structures_alloc_exit;
13742 /* Create DMA maps for each the TX mbuf cluster(ext buf). */
13743 for (j = 0; j < TOTAL_TX_BD; j++) {
13744 if (bus_dmamap_create(fp->tx_mbuf_tag,
13746 &fp->tx_mbuf_map[j])) {
13748 "%s(%d): Unable to create fp[%02d]."
13749 "tx_mbuf_map[%d] DMA map!\n",
13750 __FILE__, __LINE__, i, j);
13752 goto bxe_host_structures_alloc_exit;
13757 * Create a DMA tag for RX mbufs.
13759 if (bus_dma_tag_create(sc->parent_tag,
13760 1, /* alignment for segs */
13761 BXE_DMA_BOUNDARY, /* cannot cross */
13762 BUS_SPACE_MAXADDR, /* restricted low */
13763 BUS_SPACE_MAXADDR, /* restricted hi */
13764 NULL, /* filter f() */
13765 NULL, /* filter f() arg */
13766 MJUM9BYTES, /* max map for this tag */
13767 1, /* # of discontinuities */
13768 MJUM9BYTES, /* max seg size */
13770 NULL, /* lock f() */
13771 NULL, /* lock f() arg */
13772 &fp->rx_mbuf_tag)) {
13774 "%s(%d): Could not allocate fp[%02d] "
13775 "RX mbuf DMA tag!\n",
13776 __FILE__, __LINE__, i);
13778 goto bxe_host_structures_alloc_exit;
13781 /* Create DMA maps for the RX mbuf clusters. */
13782 if (bus_dmamap_create(fp->rx_mbuf_tag,
13783 BUS_DMA_NOWAIT, &fp->rx_mbuf_spare_map)) {
13785 "%s(%d): Unable to create fp[%02d]."
13786 "rx_mbuf_spare_map DMA map!\n",
13787 __FILE__, __LINE__, i);
13789 goto bxe_host_structures_alloc_exit;
13792 for (j = 0; j < TOTAL_RX_BD; j++) {
13793 if (bus_dmamap_create(fp->rx_mbuf_tag,
13794 BUS_DMA_NOWAIT, &fp->rx_mbuf_map[j])) {
13796 "%s(%d): Unable to create fp[%02d]."
13797 "rx_mbuf_map[%d] DMA map!\n",
13798 __FILE__, __LINE__, i, j);
13800 goto bxe_host_structures_alloc_exit;
13805 * Create a DMA tag for RX SGE bufs.
13807 if (bus_dma_tag_create(sc->parent_tag, 1,
13808 BXE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
13809 BUS_SPACE_MAXADDR, NULL, NULL, PAGE_SIZE, 1,
13810 PAGE_SIZE, 0, NULL, NULL, &fp->rx_sge_buf_tag)) {
13812 "%s(%d): Could not allocate fp[%02d] "
13813 "RX SGE mbuf DMA tag!\n",
13814 __FILE__, __LINE__, i);
13816 goto bxe_host_structures_alloc_exit;
13819 /* Create DMA maps for the SGE mbuf clusters. */
13820 if (bus_dmamap_create(fp->rx_sge_buf_tag,
13821 BUS_DMA_NOWAIT, &fp->rx_sge_spare_map)) {
13823 "%s(%d): Unable to create fp[%02d]."
13824 "rx_sge_spare_map DMA map!\n",
13825 __FILE__, __LINE__, i);
13827 goto bxe_host_structures_alloc_exit;
13830 for (j = 0; j < TOTAL_RX_SGE; j++) {
13831 if (bus_dmamap_create(fp->rx_sge_buf_tag,
13832 BUS_DMA_NOWAIT, &fp->rx_sge_buf_map[j])) {
13834 "%s(%d): Unable to create fp[%02d]."
13835 "rx_sge_buf_map[%d] DMA map!\n",
13836 __FILE__, __LINE__, i, j);
13838 goto bxe_host_structures_alloc_exit;
13842 /* Create DMA maps for the TPA pool mbufs. */
13843 if (bus_dmamap_create(fp->rx_mbuf_tag,
13844 BUS_DMA_NOWAIT, &fp->tpa_mbuf_spare_map)) {
13846 "%s(%d): Unable to create fp[%02d]."
13847 "tpa_mbuf_spare_map DMA map!\n",
13848 __FILE__, __LINE__, i);
13850 goto bxe_host_structures_alloc_exit;
13853 for (j = 0; j < max_agg_queues; j++) {
13854 if (bus_dmamap_create(fp->rx_mbuf_tag,
13855 BUS_DMA_NOWAIT, &fp->tpa_mbuf_map[j])) {
13857 "%s(%d): Unable to create fp[%02d]."
13858 "tpa_mbuf_map[%d] DMA map!\n",
13859 __FILE__, __LINE__, i, j);
13861 goto bxe_host_structures_alloc_exit;
13865 bxe_init_sge_ring_bit_mask(fp);
13869 * Allocate default status block.
13871 rc = bxe_dma_malloc(sc, BXE_DEF_STATUS_BLK_SZ, &sc->def_sb_dma,
13872 BUS_DMA_NOWAIT, "default status block");
13874 goto bxe_host_structures_alloc_exit;
13875 sc->def_sb = (struct host_def_status_block *) sc->def_sb_dma.vaddr;
13878 * Allocate statistics block.
13880 rc = bxe_dma_malloc(sc, BXE_STATS_BLK_SZ, &sc->stats_dma,
13881 BUS_DMA_NOWAIT, "statistics block");
13883 goto bxe_host_structures_alloc_exit;
13884 sc->stats = (struct statistics_block *) sc->stats_dma.vaddr;
13887 * Allocate slowpath block.
13889 rc = bxe_dma_malloc(sc, BXE_SLOWPATH_SZ, &sc->slowpath_dma,
13890 BUS_DMA_NOWAIT, "slowpath block");
13892 goto bxe_host_structures_alloc_exit;
13893 sc->slowpath = (struct bxe_slowpath *) sc->slowpath_dma.vaddr;
13896 * Allocate slowpath queue.
13898 rc = bxe_dma_malloc(sc, BXE_SPQ_SZ, &sc->spq_dma,
13899 BUS_DMA_NOWAIT, "slowpath queue");
13901 goto bxe_host_structures_alloc_exit;
13902 sc->spq = (struct eth_spe *) sc->spq_dma.vaddr;
13905 * Allocate firmware decompression buffer.
13907 rc = bxe_dma_malloc(sc, BXE_FW_BUF_SIZE, &sc->gz_dma,
13908 BUS_DMA_NOWAIT, "gunzip buffer");
13910 goto bxe_host_structures_alloc_exit;
13911 sc->gz = sc->gz_dma.vaddr;
13912 if (sc->strm == NULL) {
13913 goto bxe_host_structures_alloc_exit;
13916 sc->strm = malloc(sizeof(*sc->strm), M_DEVBUF, M_NOWAIT);
13918 bxe_host_structures_alloc_exit:
13919 DBEXIT(BXE_VERBOSE_RESET);
13924 * Program the MAC address for 57710 controllers.
13930 bxe_set_mac_addr_e1(struct bxe_softc *sc, int set)
13932 struct mac_configuration_cmd *config;
13933 struct mac_configuration_entry *config_table;
13937 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
13939 config = BXE_SP(sc, mac_config);
13940 port = BP_PORT(sc);
13943 * Port 0 Unicast Addresses: 32 Perfect Match Filters (31-0)
13944 * Port 1 Unicast Addresses: 32 Perfect Match Filters (63-32)
13945 * Port 0 Multicast Addresses: 128 Hashes (127-64)
13946 * Port 1 Multicast Addresses: 128 Hashes (191-128)
13949 config->hdr.length = 2;
13950 config->hdr.offset = port ? 32 : 0;
13951 config->hdr.client_id = BP_CL_ID(sc);
13952 config->hdr.reserved1 = 0;
13954 /* Program the primary MAC address. */
13955 config_table = &config->config_table[0];
13956 eaddr = sc->link_params.mac_addr;
13957 config_table->cam_entry.msb_mac_addr = eaddr[0] << 8 | eaddr[1];
13958 config_table->cam_entry.middle_mac_addr = eaddr[2] << 8 | eaddr[3];
13959 config_table->cam_entry.lsb_mac_addr = eaddr[4] << 8 | eaddr[5];
13960 config_table->cam_entry.flags = htole16(port);
13963 config_table->target_table_entry.flags = 0;
13965 CAM_INVALIDATE(config_table);
13967 config_table->target_table_entry.vlan_id = 0;
13969 DBPRINT(sc, BXE_VERBOSE, "%s(): %s MAC (%04x:%04x:%04x)\n",
13970 __FUNCTION__, (set ? "Setting" : "Clearing"),
13971 config_table->cam_entry.msb_mac_addr,
13972 config_table->cam_entry.middle_mac_addr,
13973 config_table->cam_entry.lsb_mac_addr);
13975 /* Program the broadcast MAC address. */
13976 config_table = &config->config_table[1];
13977 config_table->cam_entry.msb_mac_addr = 0xffff;
13978 config_table->cam_entry.middle_mac_addr = 0xffff;
13979 config_table->cam_entry.lsb_mac_addr = 0xffff;
13980 config_table->cam_entry.flags = htole16(port);
13983 config_table->target_table_entry.flags =
13984 TSTORM_CAM_TARGET_TABLE_ENTRY_BROADCAST;
13986 CAM_INVALIDATE(config_table);
13988 config_table->target_table_entry.vlan_id = 0;
13990 /* Post the command to slow path queue. */
13991 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
13992 U64_HI(BXE_SP_MAPPING(sc, mac_config)),
13993 U64_LO(BXE_SP_MAPPING(sc, mac_config)), 0);
13995 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
13999 * Program the MAC address for 57711/57711E controllers.
14005 bxe_set_mac_addr_e1h(struct bxe_softc *sc, int set)
14007 struct mac_configuration_cmd_e1h *config;
14008 struct mac_configuration_entry_e1h *config_table;
14012 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14014 config = (struct mac_configuration_cmd_e1h *)BXE_SP(sc, mac_config);
14015 port = BP_PORT(sc);
14016 func = BP_FUNC(sc);
14018 if (set && (sc->state != BXE_STATE_OPEN)) {
14019 DBPRINT(sc, BXE_VERBOSE,
14020 "%s(): Can't set E1H MAC in state 0x%08X!\n", __FUNCTION__,
14022 goto bxe_set_mac_addr_e1h_exit;
14027 * Function 0-7 Unicast Addresses: 8 Perfect Match Filters
14028 * Multicast Addresses: 20 + FUNC * 20, 20 each (???)
14030 config->hdr.length = 1;
14031 config->hdr.offset = func;
14032 config->hdr.client_id = 0xff;
14033 config->hdr.reserved1 = 0;
14035 /* Program the primary MAC address. */
14036 config_table = &config->config_table[0];
14037 eaddr = sc->link_params.mac_addr;
14038 config_table->msb_mac_addr = eaddr[0] << 8 | eaddr[1];
14039 config_table->middle_mac_addr = eaddr[2] << 8 | eaddr[3];
14040 config_table->lsb_mac_addr = eaddr[4] << 8 | eaddr[5];
14041 config_table->clients_bit_vector = htole32(1 << sc->fp->cl_id);
14043 config_table->vlan_id = 0;
14044 config_table->e1hov_id = htole16(sc->e1hov);
14047 config_table->flags = port;
14049 config_table->flags =
14050 MAC_CONFIGURATION_ENTRY_E1H_ACTION_TYPE;
14052 DBPRINT(sc, BXE_VERBOSE,
14053 "%s(): %s MAC (%04x:%04x:%04x), E1HOV = %d, CLID = %d\n",
14054 __FUNCTION__, (set ? "Setting" : "Clearing"),
14055 config_table->msb_mac_addr, config_table->middle_mac_addr,
14056 config_table->lsb_mac_addr, sc->e1hov, BP_L_ID(sc));
14058 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
14059 U64_HI(BXE_SP_MAPPING(sc, mac_config)),
14060 U64_LO(BXE_SP_MAPPING(sc, mac_config)), 0);
14062 bxe_set_mac_addr_e1h_exit:
14063 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14067 * Programs the various packet receive modes (broadcast and multicast).
14074 bxe_set_rx_mode(struct bxe_softc *sc)
14077 struct ifmultiaddr *ifma;
14078 struct mac_configuration_cmd *config;
14079 struct mac_configuration_entry *config_table;
14080 uint32_t mc_filter[MC_HASH_SIZE];
14082 uint32_t crc, bit, regidx, rx_mode;
14083 int i, old, offset, port;
14085 BXE_CORE_LOCK_ASSERT(sc);
14087 rx_mode = BXE_RX_MODE_NORMAL;
14088 port = BP_PORT(sc);
14090 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
14092 if (sc->state != BXE_STATE_OPEN) {
14093 DBPRINT(sc, BXE_WARN, "%s(): State (0x%08X) is not open!\n",
14094 __FUNCTION__, sc->state);
14095 goto bxe_set_rx_mode_exit;
14101 * Check for promiscuous, all multicast, or selected
14102 * multicast address filtering.
14104 if (ifp->if_flags & IFF_PROMISC) {
14105 /* Enable promiscuous mode. */
14106 rx_mode = BXE_RX_MODE_PROMISC;
14107 } else if (ifp->if_flags & IFF_ALLMULTI ||
14108 ifp->if_amcount > BXE_MAX_MULTICAST) {
14109 /* Enable all multicast addresses. */
14110 rx_mode = BXE_RX_MODE_ALLMULTI;
14112 /* Enable selective multicast mode. */
14113 if (CHIP_IS_E1(sc)) {
14115 config = BXE_SP(sc, mcast_config);
14117 if_maddr_rlock(ifp);
14119 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
14120 if (ifma->ifma_addr->sa_family != AF_LINK)
14122 maddr = (uint8_t *)LLADDR(
14123 (struct sockaddr_dl *)ifma->ifma_addr);
14124 config_table = &config->config_table[i];
14125 config_table->cam_entry.msb_mac_addr =
14126 maddr[0] << 8 | maddr[1];
14127 config_table->cam_entry.middle_mac_addr =
14128 maddr[2] << 8 | maddr[3];
14129 config_table->cam_entry.lsb_mac_addr =
14130 maddr[4] << 8 | maddr[5];
14131 config_table->cam_entry.flags = htole16(port);
14132 config_table->target_table_entry.flags = 0;
14133 config_table->target_table_entry.
14134 clients_bit_vector =
14135 htole32(1 << BP_L_ID(sc));
14136 config_table->target_table_entry.vlan_id = 0;
14138 DBPRINT(sc, BXE_INFO,
14139 "%s(): Setting MCAST[%d] (%04X:%04X:%04X)\n",
14141 config_table->cam_entry.msb_mac_addr,
14142 config_table->cam_entry.middle_mac_addr,
14143 config_table->cam_entry.lsb_mac_addr);
14146 if_maddr_runlock(ifp);
14148 old = config->hdr.length;
14150 /* Invalidate any extra MC entries in the CAM. */
14152 for (; i < old; i++) {
14153 config_table = &config->config_table[i];
14154 if (CAM_IS_INVALID(config_table))
14157 CAM_INVALIDATE(config_table);
14161 offset = BXE_MAX_MULTICAST * (1 + port);
14162 config->hdr.length = i;
14163 config->hdr.offset = offset;
14164 config->hdr.client_id = sc->fp->cl_id;
14165 config->hdr.reserved1 = 0;
14167 bxe_sp_post(sc, RAMROD_CMD_ID_ETH_SET_MAC, 0,
14168 U64_HI(BXE_SP_MAPPING(sc, mcast_config)),
14169 U64_LO(BXE_SP_MAPPING(sc, mcast_config)), 0);
14171 /* Accept one or more multicasts */
14172 memset(mc_filter, 0, 4 * MC_HASH_SIZE);
14174 if_maddr_rlock(ifp);
14176 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
14177 if (ifma->ifma_addr->sa_family != AF_LINK)
14179 crc = ether_crc32_le(ifma->ifma_addr->sa_data,
14181 bit = (crc >> 24) & 0xff;
14184 mc_filter[regidx] |= (1 << bit);
14186 if_maddr_runlock(ifp);
14188 for (i = 0; i < MC_HASH_SIZE; i++)
14189 REG_WR(sc, MC_HASH_OFFSET(sc, i), mc_filter[i]);
14193 DBPRINT(sc, BXE_VERBOSE, "%s(): Enabling new receive mode: 0x%08X\n",
14194 __FUNCTION__, rx_mode);
14196 sc->rx_mode = rx_mode;
14197 bxe_set_storm_rx_mode(sc);
14199 bxe_set_rx_mode_exit:
14200 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET);
14204 * Function specific controller reset.
14210 bxe_reset_func(struct bxe_softc *sc)
14212 int base, func, i, port;
14214 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14216 port = BP_PORT(sc);
14217 func = BP_FUNC(sc);
14219 /* Configure IGU. */
14220 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port * 8, 0);
14221 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port * 8, 0);
14222 REG_WR(sc, HC_REG_CONFIG_0 + (port * 4), 0x1000);
14225 base = FUNC_ILT_BASE(func);
14226 for (i = base; i < base + ILT_PER_FUNC; i++)
14227 bxe_ilt_wr(sc, i, 0);
14229 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14233 * Port specific controller reset.
14239 bxe_reset_port(struct bxe_softc *sc)
14244 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14246 port = BP_PORT(sc);
14247 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port * 4, 0);
14249 /* Do not receive packets to BRB. */
14250 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port * 4, 0x0);
14252 /* Do not direct receive packets that are not for MCP to the BRB. */
14253 REG_WR(sc, port ? NIG_REG_LLH1_BRB1_NOT_MCP :
14254 NIG_REG_LLH0_BRB1_NOT_MCP, 0x0);
14256 /* Configure AEU. */
14257 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port * 4, 0);
14261 /* Check for BRB port occupancy. */
14262 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port * 4);
14264 DBPRINT(sc, BXE_VERBOSE,
14265 "%s(): BRB1 is not empty (%d blocks are occupied)!\n",
14266 __FUNCTION__, val);
14268 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14272 * Common controller reset.
14278 bxe_reset_common(struct bxe_softc *sc)
14281 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14283 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
14285 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
14288 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14292 * Reset the controller.
14298 bxe_reset_chip(struct bxe_softc *sc, uint32_t reset_code)
14301 DBENTER(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14303 switch (reset_code) {
14304 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
14305 bxe_reset_port(sc);
14306 bxe_reset_func(sc);
14307 bxe_reset_common(sc);
14309 case FW_MSG_CODE_DRV_UNLOAD_PORT:
14310 bxe_reset_port(sc);
14311 bxe_reset_func(sc);
14313 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
14314 bxe_reset_func(sc);
14317 BXE_PRINTF("%s(%d): Unknown reset code (0x%08X) from MCP!\n",
14318 __FILE__, __LINE__, reset_code);
14322 DBEXIT(BXE_VERBOSE_LOAD | BXE_VERBOSE_RESET | BXE_VERBOSE_UNLOAD);
14326 * Called by the OS to set media options (link, speed, etc.)
14327 * when the user specifies "ifconfig bxe media XXX" or
14328 * "ifconfig bxe mediaopt XXX".
14331 * 0 = Success, !0 = Failure
14334 bxe_ifmedia_upd(struct ifnet *ifp)
14336 struct bxe_softc *sc;
14337 struct ifmedia *ifm;
14340 sc = ifp->if_softc;
14341 DBENTER(BXE_VERBOSE_PHY);
14343 ifm = &sc->bxe_ifmedia;
14346 /* We only support Ethernet media type. */
14347 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) {
14349 goto bxe_ifmedia_upd_exit;
14352 switch (IFM_SUBTYPE(ifm->ifm_media)) {
14354 /* ToDo: What to do here? */
14355 /* Doing nothing translates to success here. */
14363 case IFM_10G_TWINAX:
14366 /* We don't support channging the media type. */
14367 DBPRINT(sc, BXE_WARN, "%s(): Invalid media type!\n",
14372 bxe_ifmedia_upd_exit:
14373 DBENTER(BXE_VERBOSE_PHY);
14378 * Called by the OS to report current media status
14379 * (link, speed, etc.).
14385 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr)
14387 struct bxe_softc *sc;
14389 sc = ifp->if_softc;
14390 DBENTER(BXE_EXTREME_LOAD | BXE_EXTREME_RESET);
14392 /* Report link down if the driver isn't running. */
14393 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
14394 ifmr->ifm_active |= IFM_NONE;
14395 goto bxe_ifmedia_status_exit;
14398 /* Setup the default interface info. */
14399 ifmr->ifm_status = IFM_AVALID;
14400 ifmr->ifm_active = IFM_ETHER;
14402 if (sc->link_vars.link_up)
14403 ifmr->ifm_status |= IFM_ACTIVE;
14405 ifmr->ifm_active |= IFM_NONE;
14406 goto bxe_ifmedia_status_exit;
14409 ifmr->ifm_active |= sc->media;
14411 if (sc->link_vars.duplex == MEDIUM_FULL_DUPLEX)
14412 ifmr->ifm_active |= IFM_FDX;
14414 ifmr->ifm_active |= IFM_HDX;
14416 bxe_ifmedia_status_exit:
14417 DBEXIT(BXE_EXTREME_LOAD | BXE_EXTREME_RESET);
14422 * Update last maximum scatter gather entry.
14427 static __inline void
14428 bxe_update_last_max_sge(struct bxe_fastpath *fp, uint16_t index)
14432 last_max = fp->last_max_sge;
14433 if (SUB_S16(index, last_max) > 0)
14434 fp->last_max_sge = index;
14438 * Clear scatter gather mask next elements.
14444 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp)
14448 for (i = 0; i < NUM_RX_SGE_PAGES; i++) {
14449 index = i * TOTAL_RX_SGE_PER_PAGE + USABLE_RX_SGE_PER_PAGE;
14450 for (j = 0; j < 2; j++) {
14451 SGE_MASK_CLEAR_BIT(fp, index);
14458 * Update SGE producer.
14464 bxe_update_sge_prod(struct bxe_fastpath *fp,
14465 struct eth_fast_path_rx_cqe *fp_cqe)
14467 struct bxe_softc *sc;
14468 uint16_t delta, first_elem, last_max, last_elem, sge_len;
14472 DBENTER(BXE_EXTREME_RECV);
14475 sge_len = SGE_PAGE_ALIGN(le16toh(fp_cqe->pkt_len) -
14476 le16toh(fp_cqe->len_on_bd)) >> SGE_PAGE_SHIFT;
14478 goto bxe_update_sge_prod_exit;
14480 /* First mark all used pages. */
14481 for (i = 0; i < sge_len; i++)
14482 SGE_MASK_CLEAR_BIT(fp, RX_SGE(le16toh(fp_cqe->sgl[i])));
14484 /* Assume that the last SGE index is the biggest. */
14485 bxe_update_last_max_sge(fp, le16toh(fp_cqe->sgl[sge_len - 1]));
14487 last_max = RX_SGE(fp->last_max_sge);
14488 last_elem = last_max >> RX_SGE_MASK_ELEM_SHIFT;
14489 first_elem = RX_SGE(fp->rx_sge_prod) >> RX_SGE_MASK_ELEM_SHIFT;
14491 /* If ring is not full. */
14492 if (last_elem + 1 != first_elem)
14495 /* Now update the producer index. */
14496 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
14497 if (fp->rx_sge_mask[i])
14500 fp->rx_sge_mask[i] = RX_SGE_MASK_ELEM_ONE_MASK;
14501 delta += RX_SGE_MASK_ELEM_SZ;
14505 fp->rx_sge_prod += delta;
14506 /* clear page-end entries */
14507 bxe_clear_sge_mask_next_elems(fp);
14510 bxe_update_sge_prod_exit:
14511 DBEXIT(BXE_EXTREME_RECV);
14515 * Initialize scatter gather ring bitmask.
14517 * Each entry in the SGE is associated with an aggregation in process.
14518 * Since there is no guarantee that all Ethernet frames associated with
14519 * a partciular TCP flow will arrive at the adapter and be placed into
14520 * the SGE chain contiguously, we maintain a bitmask for each SGE element
14521 * that identifies which aggregation an Ethernet frame belongs to.
14526 static __inline void
14527 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp)
14530 /* Set the mask to all 1s, it's faster to compare to 0 than to 0xf. */
14531 memset(fp->rx_sge_mask, 0xff,
14532 (TOTAL_RX_SGE >> RX_SGE_MASK_ELEM_SHIFT) * sizeof(uint64_t));
14535 * The SGE chain is formatted just like the RX chain.
14536 * The last two elements are reserved as a "next page pointer"
14537 * to the next page of SGE elements. Clear the last two
14538 * elements in each SGE chain page since they will never be
14539 * used to track an aggregation.
14541 bxe_clear_sge_mask_next_elems(fp);
14545 * The current mbuf is part of an aggregation. Swap the mbuf into the TPA
14546 * aggregation queue, swap an empty mbuf back onto the receive chain, and
14547 * mark the current aggregation queue as in-progress.
14553 bxe_tpa_start(struct bxe_fastpath *fp, uint16_t queue, uint16_t cons,
14556 struct bxe_softc *sc;
14557 struct mbuf *m_temp;
14558 struct eth_rx_bd *rx_bd;
14559 bus_dmamap_t map_temp;
14560 int max_agg_queues;
14563 DBENTER(BXE_INSANE_RECV | BXE_INSANE_TPA);
14567 DBPRINT(sc, BXE_EXTREME_TPA,
14568 "%s(): fp[%02d].tpa[%02d], cons=0x%04X, prod=0x%04X\n",
14569 __FUNCTION__, fp->index, queue, cons, prod);
14571 max_agg_queues = CHIP_IS_E1(sc) ? ETH_MAX_AGGREGATION_QUEUES_E1 :
14572 ETH_MAX_AGGREGATION_QUEUES_E1H;
14574 DBRUNIF((queue > max_agg_queues),
14575 BXE_PRINTF("%s(): fp[%02d] illegal aggregation (%d > %d)!\n",
14576 __FUNCTION__, fp->index, queue, max_agg_queues));
14578 DBRUNIF((fp->tpa_state[queue] != BXE_TPA_STATE_STOP),
14579 BXE_PRINTF("%s(): Starting aggregation on "
14580 "fp[%02d].tpa[%02d] even though queue is not in the "
14581 "TPA_STOP state!\n", __FUNCTION__, fp->index, queue));
14583 /* Remove the existing mbuf and mapping from the TPA pool. */
14584 m_temp = fp->tpa_mbuf_ptr[queue];
14585 map_temp = fp->tpa_mbuf_map[queue];
14587 /* Only the paranoid survive! */
14588 if(m_temp == NULL) {
14589 BXE_PRINTF("%s(%d): fp[%02d].tpa[%02d] not allocated!\n",
14590 __FILE__, __LINE__, fp->index, queue);
14591 /* ToDo: Additional error handling! */
14592 goto bxe_tpa_start_exit;
14595 /* Move received mbuf and mapping to TPA pool. */
14596 fp->tpa_mbuf_ptr[queue] = fp->rx_mbuf_ptr[cons];
14597 fp->tpa_mbuf_map[queue] = fp->rx_mbuf_map[cons];
14599 /* Place the TPA bin into the START state. */
14600 fp->tpa_state[queue] = BXE_TPA_STATE_START;
14601 DBRUN(fp->tpa_queue_used |= (1 << queue));
14603 /* Get the rx_bd for the next open entry on the receive chain. */
14604 rx_bd = &fp->rx_chain[prod];
14606 /* Update the rx_bd with the empty mbuf from the TPA pool. */
14607 rx_bd->addr_hi = htole32(U64_HI(fp->tpa_mbuf_segs[queue].ds_addr));
14608 rx_bd->addr_lo = htole32(U64_LO(fp->tpa_mbuf_segs[queue].ds_addr));
14609 fp->rx_mbuf_ptr[prod] = m_temp;
14610 fp->rx_mbuf_map[prod] = map_temp;
14612 bxe_tpa_start_exit:
14613 DBEXIT(BXE_INSANE_RECV | BXE_INSANE_TPA);
14617 * When a TPA aggregation is completed, loop through the individual mbufs
14618 * of the aggregation, combining them into a single mbuf which will be sent
14619 * up the stack. Refill all freed SGEs with mbufs as we go along.
14622 * 0 = Success, !0 = Failure.
14625 bxe_fill_frag_mbuf(struct bxe_softc *sc, struct bxe_fastpath *fp,
14626 struct mbuf *m, struct eth_fast_path_rx_cqe *fp_cqe, uint16_t cqe_idx)
14628 struct mbuf *m_frag;
14629 uint32_t frag_len, frag_size, pages, i;
14630 uint16_t sge_idx, len_on_bd;
14633 DBENTER(BXE_EXTREME_RECV | BXE_EXTREME_TPA);
14636 len_on_bd = le16toh(fp_cqe->len_on_bd);
14637 frag_size = le16toh(fp_cqe->pkt_len) - len_on_bd;
14638 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT;
14640 DBPRINT(sc, BXE_VERBOSE_TPA,
14641 "%s(): len_on_bd=%d, frag_size=%d, pages=%d\n",
14642 __FUNCTION__, len_on_bd, frag_size, pages);
14644 /* Make sure the aggregated frame is not too big to handle. */
14645 if (pages > 8 * PAGES_PER_SGE) {
14646 DBPRINT(sc, BXE_FATAL,
14647 "%s(): fp[%02d].rx_sge[0x%04X] has too many pages (%d)!\n",
14648 __FUNCTION__, fp->index, cqe_idx, pages);
14649 DBPRINT(sc, BXE_FATAL,
14650 "%s(): fp_cqe->pkt_len = %d fp_cqe->len_on_bd = %d\n",
14651 __FUNCTION__, le16toh(fp_cqe->pkt_len), len_on_bd);
14652 bxe_panic_dump(sc);
14654 goto bxe_fill_frag_mbuf_exit;
14658 * Scan through the scatter gather list, pulling individual
14659 * mbufs into a single mbuf for the host stack.
14661 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
14662 sge_idx = RX_SGE(le16toh(fp_cqe->sgl[j]));
14665 * Firmware gives the indices of the SGE as if the ring is an
14666 * array (meaning that the "next" element will consume 2
14669 frag_len = min(frag_size, (uint32_t)(BCM_PAGE_SIZE *
14672 DBPRINT(sc, BXE_VERBOSE_TPA,
14673 "%s(): i=%d, j=%d, frag_size=%d, frag_len=%d\n",
14674 __FUNCTION__, i, j, frag_size, frag_len);
14676 m_frag = fp->rx_sge_buf_ptr[sge_idx];
14678 /* Allocate a new mbuf for the SGE. */
14679 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx);
14682 * Leave all remaining SGEs in the ring.
14684 goto bxe_fill_frag_mbuf_exit;
14687 /* Update the fragment its length. */
14688 m_frag->m_len = frag_len;
14690 /* Concatenate the fragment to the head mbuf. */
14692 DBRUN(fp->sge_mbuf_alloc--);
14694 /* Update TPA mbuf size and remaining fragment size. */
14695 m->m_pkthdr.len += frag_len;
14696 frag_size -= frag_len;
14699 bxe_fill_frag_mbuf_exit:
14700 DBPRINT(sc, BXE_VERBOSE_TPA,
14701 "%s(): frag_size=%d\n", __FUNCTION__, frag_size);
14702 DBEXIT(BXE_EXTREME_RECV | BXE_EXTREME_TPA);
14707 * The aggregation on the current TPA queue has completed. Pull the
14708 * individual mbuf fragments together into a single mbuf, perform all
14709 * necessary checksum calculations, and send the resuting mbuf to the stack.
14715 bxe_tpa_stop(struct bxe_softc *sc, struct bxe_fastpath *fp, uint16_t queue,
14716 int pad, int len, union eth_rx_cqe *cqe, uint16_t cqe_idx)
14722 DBENTER(BXE_INSANE_RECV | BXE_INSANE_TPA);
14723 DBPRINT(sc, (BXE_EXTREME_RECV | BXE_EXTREME_TPA),
14724 "%s(): fp[%02d].tpa[%02d], len=%d, pad=%d\n",
14725 __FUNCTION__, fp->index, queue, len, pad);
14729 m = fp->tpa_mbuf_ptr[queue];
14731 /* Allocate a replacement before modifying existing mbuf. */
14732 rc = bxe_alloc_tpa_mbuf(fp, queue);
14734 /* Drop the frame and log a soft error. */
14735 fp->rx_soft_errors++;
14736 goto bxe_tpa_stop_exit;
14739 /* We have a replacement, fixup the current mbuf. */
14741 m->m_pkthdr.len = m->m_len = len;
14743 /* Mark the checksums valid (taken care of by firmware). */
14744 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID |
14745 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
14746 m->m_pkthdr.csum_data = 0xffff;
14748 /* Aggregate all of the SGEs into a single mbuf. */
14749 rc = bxe_fill_frag_mbuf(sc, fp, m, &cqe->fast_path_cqe, cqe_idx);
14751 /* Drop the packet and log an error. */
14752 fp->rx_soft_errors++;
14755 /* Find VLAN tag and send frame up to the stack. */
14756 if ((le16toh(cqe->fast_path_cqe.pars_flags.flags) &
14757 PARSING_FLAGS_VLAN)) {
14758 m->m_pkthdr.ether_vtag =
14759 cqe->fast_path_cqe.vlan_tag;
14760 m->m_flags |= M_VLANTAG;
14763 /* Assign packet to the appropriate interface. */
14764 m->m_pkthdr.rcvif = ifp;
14766 /* Update packet statistics. */
14768 ifp->if_ipackets++;
14770 /* ToDo: Any potential locking issues here? */
14771 /* Pass the frame to the stack. */
14772 (*ifp->if_input)(ifp, m);
14775 /* We passed mbuf up the stack or dropped the frame. */
14776 DBRUN(fp->tpa_mbuf_alloc--);
14779 fp->tpa_state[queue] = BXE_TPA_STATE_STOP;
14780 DBRUN(fp->tpa_queue_used &= ~(1 << queue));
14781 DBEXIT(BXE_INSANE_RECV | BXE_INSANE_TPA);
14785 * Notify the controller that the RX producer indices have been updated for
14786 * a fastpath connection by writing them to the controller.
14791 static __inline void
14792 bxe_update_rx_prod(struct bxe_softc *sc, struct bxe_fastpath *fp,
14793 uint16_t bd_prod, uint16_t cqe_prod, uint16_t sge_prod)
14795 volatile struct ustorm_eth_rx_producers rx_prods = {0};
14798 /* Update producers. */
14799 rx_prods.bd_prod = bd_prod;
14800 rx_prods.cqe_prod = cqe_prod;
14801 rx_prods.sge_prod = sge_prod;
14805 for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++){
14806 REG_WR(sc, BAR_USTORM_INTMEM +
14807 USTORM_RX_PRODS_OFFSET(BP_PORT(sc), fp->cl_id) + i * 4,
14808 ((volatile uint32_t *) &rx_prods)[i]);
14811 DBPRINT(sc, BXE_EXTREME_RECV, "%s(%d): Wrote fp[%02d] bd_prod = 0x%04X, "
14812 "cqe_prod = 0x%04X, sge_prod = 0x%04X\n", __FUNCTION__, curcpu,
14813 fp->index, bd_prod, cqe_prod, sge_prod);
14817 * Processes received frames.
14823 bxe_rxeof(struct bxe_fastpath *fp)
14825 struct bxe_softc *sc;
14827 uint16_t rx_bd_cons, rx_bd_cons_idx;
14828 uint16_t rx_bd_prod, rx_bd_prod_idx;
14829 uint16_t rx_cq_cons, rx_cq_cons_idx;
14830 uint16_t rx_cq_prod, rx_cq_cons_sb;
14831 unsigned long rx_pkts = 0;
14837 DBENTER(BXE_EXTREME_RECV);
14839 /* Get the status block's view of the RX completion consumer index. */
14840 rx_cq_cons_sb = bxe_rx_cq_cons(fp);
14843 * Get working copies of the driver's view of the
14844 * RX indices. These are 16 bit values that are
14845 * expected to increment from 0 to 65535 and then
14846 * wrap-around to 0 again.
14848 rx_bd_cons = fp->rx_bd_cons;
14849 rx_bd_prod = fp->rx_bd_prod;
14850 rx_cq_cons = fp->rx_cq_cons;
14851 rx_cq_prod = fp->rx_cq_prod;
14853 DBPRINT(sc, (BXE_EXTREME_RECV),
14854 "%s(%d): BEFORE: fp[%02d], rx_bd_cons = 0x%04X, rx_bd_prod = 0x%04X, "
14855 "rx_cq_cons_sw = 0x%04X, rx_cq_prod_sw = 0x%04X\n", __FUNCTION__,
14856 curcpu, fp->index, rx_bd_cons, rx_bd_prod, rx_cq_cons, rx_cq_prod);
14859 * Memory barrier to prevent speculative reads of the RX buffer
14860 * from getting ahead of the index in the status block.
14865 * Scan through the receive chain as long
14866 * as there is work to do.
14868 while (rx_cq_cons != rx_cq_cons_sb) {
14870 union eth_rx_cqe *cqe;
14871 uint8_t cqe_fp_flags;
14875 * Convert the 16 bit indices used by hardware
14876 * into array indices used by the driver.
14878 rx_cq_cons_idx = RCQ_ENTRY(rx_cq_cons);
14879 rx_bd_prod_idx = RX_BD(rx_bd_prod);
14880 rx_bd_cons_idx = RX_BD(rx_bd_cons);
14883 /* Fetch the completion queue entry (i.e. cookie). */
14884 cqe = (union eth_rx_cqe *)
14885 &fp->rcq_chain[rx_cq_cons_idx];
14886 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
14888 /* Sanity check the cookie flags. */
14889 if (__predict_false(cqe_fp_flags == 0)) {
14890 fp->rx_null_cqe_flags++;
14891 DBRUN(bxe_dump_cqe(fp, rx_cq_cons_idx, cqe));
14892 /* ToDo: What error handling can be done here? */
14895 /* Check the CQE type for slowpath or fastpath completion. */
14896 if (__predict_false(CQE_TYPE(cqe_fp_flags) ==
14897 RX_ETH_CQE_TYPE_ETH_RAMROD)) {
14898 /* This is a slowpath completion. */
14899 bxe_sp_event(fp, cqe);
14900 goto bxe_rxeof_next_cqe;
14903 /* This is a fastpath completion. */
14905 /* Get the length and pad information from the CQE. */
14906 len = le16toh(cqe->fast_path_cqe.pkt_len);
14907 pad = cqe->fast_path_cqe.placement_offset;
14909 /* Check if the completion is for TPA. */
14910 if ((fp->disable_tpa == FALSE) &&
14911 (TPA_TYPE(cqe_fp_flags) !=
14912 (TPA_TYPE_START | TPA_TYPE_END))) {
14913 uint16_t queue = cqe->fast_path_cqe.queue_index;
14916 * No need to worry about error flags in
14917 * the frame as the firmware has already
14918 * managed that for us when aggregating
14922 /* Check if TPA aggregation has started. */
14923 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_START) {
14924 bxe_tpa_start(fp, queue, rx_bd_cons_idx,
14926 goto bxe_rxeof_next_rx;
14929 /* Check if TPA aggregation has completed. */
14930 if (TPA_TYPE(cqe_fp_flags) == TPA_TYPE_END) {
14931 DBRUNIF(!BXE_RX_SUM_FIX(cqe),
14932 DBPRINT(sc, BXE_FATAL,
14933 "%s(): STOP on non-TCP data.\n",
14937 * This is the size of the linear
14938 * data on this mbuf.
14940 len = le16toh(cqe->fast_path_cqe.len_on_bd);
14943 * Stop the aggregation and pass
14946 bxe_tpa_stop(sc, fp, queue, pad, len,
14947 cqe, rx_cq_cons_idx);
14948 bxe_update_sge_prod(fp,
14949 &cqe->fast_path_cqe);
14950 goto bxe_rxeof_next_cqe;
14954 m = fp->rx_mbuf_ptr[rx_bd_cons_idx];
14956 /* Allocate a replacement before modifying existing mbuf. */
14957 rc = bxe_alloc_rx_bd_mbuf(fp, rx_bd_prod_idx);
14959 /* Drop the frame and log a soft error. */
14960 fp->rx_soft_errors++;
14961 goto bxe_rxeof_next_rx;
14964 /* Check if the received frame has any errors. */
14965 if (__predict_false(cqe_fp_flags &
14966 ETH_RX_ERROR_FLAGS)) {
14967 DBPRINT(sc, BXE_WARN ,
14968 "%s(): fp[%02d].cqe[0x%04X] has errors "
14969 "(0x%08X)!\n", __FUNCTION__, fp->index,
14970 rx_cq_cons, cqe_fp_flags);
14972 fp->rx_soft_errors++;
14973 goto bxe_rxeof_next_rx;
14976 /* We have a replacement, fixup the current mbuf. */
14978 m->m_pkthdr.len = m->m_len = len;
14980 /* Assign packet to the appropriate interface. */
14981 m->m_pkthdr.rcvif = ifp;
14983 /* Assume no hardware checksum complated. */
14984 m->m_pkthdr.csum_flags = 0;
14986 /* Validate checksum if offload enabled. */
14987 if (ifp->if_capenable & IFCAP_RXCSUM) {
14988 /* Check whether IP checksummed or not. */
14990 !(cqe->fast_path_cqe.status_flags &
14991 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) {
14992 m->m_pkthdr.csum_flags |=
14994 if (__predict_false(cqe_fp_flags &
14995 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) {
14996 DBPRINT(sc, BXE_WARN_SEND,
14997 "%s(): Invalid IP checksum!\n",
15000 m->m_pkthdr.csum_flags |=
15004 /* Check for a valid TCP/UDP frame. */
15006 !(cqe->fast_path_cqe.status_flags &
15007 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) {
15008 /* Check for a good TCP/UDP checksum. */
15009 if (__predict_false(cqe_fp_flags &
15010 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) {
15011 DBPRINT(sc, BXE_VERBOSE_RECV,
15012 "%s(): Invalid TCP/UDP checksum!\n",
15015 m->m_pkthdr.csum_data = 0xFFFF;
15016 m->m_pkthdr.csum_flags |=
15024 * If we received a packet with a vlan tag,
15025 * attach that information to the packet.
15027 if (cqe->fast_path_cqe.pars_flags.flags &
15028 PARSING_FLAGS_VLAN) {
15029 m->m_pkthdr.ether_vtag =
15030 cqe->fast_path_cqe.vlan_tag;
15031 m->m_flags |= M_VLANTAG;
15034 #if __FreeBSD_version >= 800000
15035 /* Tell OS what RSS queue was used for this flow. */
15036 m->m_pkthdr.flowid = fp->index;
15037 m->m_flags |= M_FLOWID;
15040 /* Last chance to check for problems. */
15041 DBRUN(bxe_validate_rx_packet(fp, rx_cq_cons, cqe, m));
15043 /* Update packet statistics. */
15044 ifp->if_ipackets++;
15047 /* ToDo: Any potential locking issues here? */
15048 /* Pass the frame to the stack. */
15049 (*ifp->if_input)(ifp, m);
15051 DBRUN(fp->rx_mbuf_alloc--);
15055 rx_bd_prod = NEXT_RX_BD(rx_bd_prod);
15056 rx_bd_cons = NEXT_RX_BD(rx_bd_cons);
15058 bxe_rxeof_next_cqe:
15059 rx_cq_prod = NEXT_RCQ_IDX(rx_cq_prod);
15060 rx_cq_cons = NEXT_RCQ_IDX(rx_cq_cons);
15063 * Memory barrier to prevent speculative reads of the RX buffer
15064 * from getting ahead of the index in the status block.
15069 /* Update driver copy of the fastpath indices. */
15070 fp->rx_bd_cons = rx_bd_cons;
15071 fp->rx_bd_prod = rx_bd_prod;
15072 fp->rx_cq_cons = rx_cq_cons;
15073 fp->rx_cq_prod = rx_cq_prod;
15075 DBPRINT(sc, (BXE_EXTREME_RECV),
15076 "%s(%d): AFTER: fp[%02d], rx_bd_cons = 0x%04X, rx_bd_prod = 0x%04X, "
15077 "rx_cq_cons_sw = 0x%04X, rx_cq_prod_sw = 0x%04X\n", __FUNCTION__,
15078 curcpu, fp->index, rx_bd_cons, rx_bd_prod, rx_cq_cons, rx_cq_prod);
15080 /* Update producers */
15081 bxe_update_rx_prod(sc, fp, fp->rx_bd_prod,
15082 fp->rx_cq_prod, fp->rx_sge_prod);
15083 bus_space_barrier(sc->bxe_btag, sc->bxe_bhandle, 0, 0,
15084 BUS_SPACE_BARRIER_READ);
15086 fp->rx_pkts += rx_pkts;
15087 DBEXIT(BXE_EXTREME_RECV);
15091 * Processes transmit completions.
15097 bxe_txeof(struct bxe_fastpath *fp)
15099 struct bxe_softc *sc;
15101 struct eth_tx_start_bd *txbd;
15102 uint16_t hw_pkt_cons, sw_pkt_cons, sw_tx_bd_cons;
15103 uint16_t bd_index, pkt_index, nbds;
15109 DBENTER(BXE_EXTREME_SEND);
15111 /* Get the hardware's view of the TX packet consumer index. */
15112 hw_pkt_cons = le16toh(*fp->tx_pkt_cons_sb);
15113 sw_pkt_cons = fp->tx_pkt_cons;
15114 sw_tx_bd_cons = fp->tx_bd_cons;
15116 /* Cycle through any completed TX chain page entries. */
15117 while (sw_pkt_cons != hw_pkt_cons) {
15118 bd_index = TX_BD(sw_tx_bd_cons);
15119 pkt_index = TX_BD(sw_pkt_cons);
15121 txbd = &fp->tx_chain[bd_index].start_bd;
15124 /* Free the completed frame's mbuf. */
15125 if (__predict_true(fp->tx_mbuf_ptr[pkt_index] != NULL)) {
15126 /* Unmap the mbuf from non-paged memory. */
15127 bus_dmamap_unload(fp->tx_mbuf_tag,
15128 fp->tx_mbuf_map[pkt_index]);
15130 /* Return the mbuf to the system. */
15131 m_freem(fp->tx_mbuf_ptr[pkt_index]);
15132 fp->tx_mbuf_alloc--;
15133 fp->tx_mbuf_ptr[pkt_index] = NULL;
15136 fp->tx_chain_lost_mbuf++;
15139 /* Updated packet consumer value. */
15142 /* Skip over the remaining used buffer descriptors. */
15143 fp->tx_bd_used -= nbds;
15144 for (i = 0; i < nbds; i++)
15145 sw_tx_bd_cons = NEXT_TX_BD(sw_tx_bd_cons);
15147 /* Check for new work since we started. */
15148 hw_pkt_cons = le16toh(*fp->tx_pkt_cons_sb);
15152 /* Enable new transmits if we've made enough room. */
15153 if (fp->tx_bd_used < BXE_TX_CLEANUP_THRESHOLD) {
15154 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
15155 if (fp->tx_bd_used == 0) {
15157 * Clear the watchdog timer if we've emptied
15160 fp->watchdog_timer = 0;
15163 * Reset the watchdog timer if we still have
15164 * transmits pending.
15166 fp->watchdog_timer = BXE_TX_TIMEOUT;
15170 /* Save our indices. */
15171 fp->tx_pkt_cons = sw_pkt_cons;
15172 fp->tx_bd_cons = sw_tx_bd_cons;
15173 DBEXIT(BXE_EXTREME_SEND);
15177 * Transmit timeout handler.
15180 * 0 = No timeout, !0 = timeout occurred.
15183 bxe_watchdog(struct bxe_fastpath *fp)
15185 struct bxe_softc *sc;
15189 DBENTER(BXE_INSANE_SEND);
15192 if (fp->watchdog_timer == 0 || --fp->watchdog_timer) {
15195 goto bxe_watchdog_exit;
15199 BXE_PRINTF("TX watchdog timeout occurred on fp[%02d], "
15200 "resetting!\n", fp->index);
15202 /* DBRUNLV(BXE_FATAL, bxe_breakpoint(sc)); */
15206 /* Mark the interface as down. */
15207 sc->bxe_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
15209 bxe_stop_locked(sc, UNLOAD_NORMAL);
15211 bxe_init_locked(sc, LOAD_OPEN);
15213 BXE_CORE_UNLOCK(sc);
15216 DBEXIT(BXE_INSANE_SEND);
15222 * The periodic timer tick routine.
15224 * This code only runs when the interface is up.
15230 bxe_tick(void *xsc)
15232 struct bxe_softc *sc;
15233 struct bxe_fastpath *fp;
15235 /* Re-enable at a later time. */
15236 uint32_t drv_pulse, mcp_pulse;
15241 DBENTER(BXE_INSANE_MISC);
15244 /* Check for TX timeouts on any fastpath. */
15245 for (i = 0; i < sc->num_queues; i++) {
15248 if (bxe_watchdog(fp) != 0)
15252 func = BP_FUNC(sc);
15254 /* Schedule the next tick. */
15255 callout_reset(&sc->bxe_tick_callout, hz, bxe_tick, sc);
15259 func = BP_FUNC(sc);
15261 ++sc->fw_drv_pulse_wr_seq;
15262 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
15264 /* Let the MCP know we're alive. */
15265 drv_pulse = sc->fw_drv_pulse_wr_seq;
15266 SHMEM_WR(sc, func_mb[func].drv_pulse_mb, drv_pulse);
15268 /* Check if the MCP is still alive. */
15269 mcp_pulse = (SHMEM_RD(sc, func_mb[func].mcp_pulse_mb) &
15270 MCP_PULSE_SEQ_MASK);
15273 * The delta between driver pulse and MCP response should be 1
15274 * (before MCP response) or 0 (after MCP response).
15276 if ((drv_pulse != mcp_pulse) && (drv_pulse != ((mcp_pulse + 1) &
15277 MCP_PULSE_SEQ_MASK))) {
15278 /* Someone's in cardiac arrest. */
15279 DBPRINT(sc, BXE_WARN,
15280 "%s(): drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
15281 __FUNCTION__, drv_pulse, mcp_pulse);
15286 if ((sc->state == BXE_STATE_OPEN) || (sc->state == BXE_STATE_DISABLED))
15287 bxe_stats_handle(sc, STATS_EVENT_UPDATE);
15292 * Allows the driver state to be dumped through the sysctl interface.
15295 * 0 for success, positive value for failure.
15298 bxe_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
15300 struct bxe_softc *sc;
15301 struct bxe_fastpath *fp;
15302 int error, i, result;
15304 sc = (struct bxe_softc *)arg1;
15306 error = sysctl_handle_int(oidp, &result, 0, req);
15307 if (error || !req->newptr)
15311 bxe_dump_driver_state(sc);
15312 for (i = 0; i < sc->num_queues; i++) {
15314 bxe_dump_fp_state(fp);
15316 bxe_dump_status_block(sc);
15323 * Allows the hardware state to be dumped through the sysctl interface.
15326 * 0 for success, positive value for failure.
15329 bxe_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
15331 struct bxe_softc *sc;
15334 sc = (struct bxe_softc *)arg1;
15336 error = sysctl_handle_int(oidp, &result, 0, req);
15337 if (error || !req->newptr)
15341 bxe_dump_hw_state(sc);
15347 * Allows the MCP firmware to be dumped through the sysctl interface.
15350 * 0 for success, positive value for failure.
15353 bxe_sysctl_dump_fw(SYSCTL_HANDLER_ARGS)
15355 struct bxe_softc *sc;
15358 sc = (struct bxe_softc *)arg1;
15360 error = sysctl_handle_int(oidp, &result, 0, req);
15361 if (error || !req->newptr)
15371 * Provides a sysctl interface to allow dumping the RX completion chain.
15374 * 0 for success, positive value for failure.
15377 bxe_sysctl_dump_rx_cq_chain(SYSCTL_HANDLER_ARGS)
15379 struct bxe_softc *sc;
15380 struct bxe_fastpath *fp;
15383 sc = (struct bxe_softc *)arg1;
15385 error = sysctl_handle_int(oidp, &result, 0, req);
15386 if (error || !req->newptr)
15389 if ((result >= 0) && (result < sc->num_queues)) {
15390 fp = &sc->fp[result];
15391 bxe_dump_rx_cq_chain(fp, 0, TOTAL_RCQ_ENTRIES);
15399 * Provides a sysctl interface to allow dumping the RX chain.
15402 * 0 for success, positive value for failure.
15405 bxe_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
15407 struct bxe_softc *sc;
15408 struct bxe_fastpath *fp;
15411 sc = (struct bxe_softc *)arg1;
15413 error = sysctl_handle_int(oidp, &result, 0, req);
15414 if (error || !req->newptr)
15417 if ((result >= 0) && (result < sc->num_queues)) {
15418 fp = &sc->fp[result];
15419 bxe_dump_rx_bd_chain(fp, 0, TOTAL_RX_BD);
15426 * Provides a sysctl interface to allow dumping the TX chain.
15429 * 0 for success, positive value for failure.
15432 bxe_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
15434 struct bxe_softc *sc;
15435 struct bxe_fastpath *fp;
15438 sc = (struct bxe_softc *)arg1;
15440 error = sysctl_handle_int(oidp, &result, 0, req);
15441 if (error || !req->newptr)
15444 if ((result >= 0) && (result < sc->num_queues)) {
15445 fp = &sc->fp[result];
15446 bxe_dump_tx_chain(fp, 0, TOTAL_TX_BD);
15453 * Provides a sysctl interface to allow reading arbitrary registers in the
15454 * device. DO NOT ENABLE ON PRODUCTION SYSTEMS!
15457 * 0 for success, positive value for failure.
15460 bxe_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
15462 struct bxe_softc *sc;
15463 uint32_t result, val;
15466 sc = (struct bxe_softc *)arg1;
15468 error = sysctl_handle_int(oidp, &result, 0, req);
15469 if (error || (req->newptr == NULL))
15472 val = REG_RD(sc, result);
15473 BXE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
15479 * Provides a sysctl interface to allow generating a grcdump.
15482 * 0 for success, positive value for failure.
15485 bxe_sysctl_grcdump(SYSCTL_HANDLER_ARGS)
15487 struct bxe_softc *sc;
15490 sc = (struct bxe_softc *)arg1;
15492 error = sysctl_handle_int(oidp, &result, 0, req);
15493 if (error || !req->newptr)
15497 /* Generate a grcdump and log the contents.*/
15498 bxe_grcdump(sc, 1);
15500 /* Generate a grcdump and don't log the contents. */
15501 bxe_grcdump(sc, 0);
15508 * Provides a sysctl interface to forcing the driver to dump state and
15509 * enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS!
15512 * 0 for success, positive value for failure.
15515 bxe_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
15517 struct bxe_softc *sc;
15521 error = sysctl_handle_int(oidp, &result, 0, req);
15522 if (error || !req->newptr)
15526 sc = (struct bxe_softc *)arg1;
15527 bxe_breakpoint(sc);
15535 * Adds any sysctl parameters for tuning or debugging purposes.
15541 bxe_add_sysctls(struct bxe_softc *sc)
15543 struct sysctl_ctx_list *ctx =
15544 device_get_sysctl_ctx(sc->dev);
15545 struct sysctl_oid_list *children =
15546 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev));
15547 struct bxe_port_stats *estats = &sc->eth_stats;
15549 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15550 "estats_total_bytes_received_hi",
15551 CTLFLAG_RD, &estats->total_bytes_received_hi,
15552 0, "Total bytes received (hi)");
15554 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15555 "estats_total_bytes_received_lo",
15556 CTLFLAG_RD, &estats->total_bytes_received_lo,
15557 0, "Total bytes received (lo)");
15559 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15560 "estats_valid_bytes_received_hi",
15561 CTLFLAG_RD, &estats->valid_bytes_received_hi,
15562 0, "Valid bytes received (hi)");
15564 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15565 "estats_valid_bytes_received_lo",
15566 CTLFLAG_RD, &estats->valid_bytes_received_lo,
15567 0, "Valid bytes received (lo)");
15569 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15570 "estats_total_unicast_packets_received_hi",
15571 CTLFLAG_RD, &estats->total_unicast_packets_received_hi,
15572 0, "Total unicast packets received (hi)");
15574 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15575 "estats_total_unicast_packets_received_lo",
15576 CTLFLAG_RD, &estats->total_unicast_packets_received_lo,
15577 0, "Total unicast packets received (lo)");
15579 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15580 "estats_total_bytes_transmitted_hi",
15581 CTLFLAG_RD, &estats->total_bytes_transmitted_hi,
15582 0, "Total bytes transmitted (hi)");
15584 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15585 "estats_total_bytes_transmitted_lo",
15586 CTLFLAG_RD, &estats->total_bytes_transmitted_lo,
15587 0, "Total bytes transmitted (lo)");
15589 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15590 "estats_total_unicast_packets_transmitted_hi",
15591 CTLFLAG_RD, &estats->total_unicast_packets_transmitted_hi,
15592 0, "Total unicast packets transmitted (hi)");
15594 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15595 "estats_total_unicast_packets_transmitted_lo",
15596 CTLFLAG_RD, &estats->total_unicast_packets_transmitted_lo,
15597 0, "Total unicast packets transmitted (lo)");
15599 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15600 "estats_total_broadcast_packets_received_lo",
15601 CTLFLAG_RD, &estats->total_broadcast_packets_received_lo,
15602 0, "Total broadcast packets received (lo)");
15604 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15605 "estats_total_broadcast_packets_transmitted_lo",
15606 CTLFLAG_RD, &estats->total_broadcast_packets_transmitted_lo,
15607 0, "Total broadcast packets transmitted (lo)");
15609 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15610 "estats_total_multicast_packets_received_lo",
15611 CTLFLAG_RD, &estats->total_multicast_packets_received_lo,
15612 0, "Total multicast packets received (lo)");
15614 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15615 "estats_total_multicast_packets_transmitted_lo",
15616 CTLFLAG_RD, &estats->total_multicast_packets_transmitted_lo,
15617 0, "Total multicast packets transmitted (lo)");
15619 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15620 "tx_stat_etherstatspkts64octets_hi",
15621 CTLFLAG_RD, &estats->tx_stat_etherstatspkts64octets_hi,
15622 0, "Total 64 byte packets transmitted (hi)");
15624 /* ToDo: Fix for 64 bit access. */
15625 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15626 "tx_stat_etherstatspkts64octets_lo",
15627 CTLFLAG_RD, &estats->tx_stat_etherstatspkts64octets_lo,
15628 0, "Total 64 byte packets transmitted (lo)");
15630 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
15632 CTLFLAG_RD, &estats->driver_xoff,
15633 0, "Driver transmit queue full count");
15635 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
15636 "tx_start_called_with_link_down",
15637 CTLFLAG_RD, &sc->tx_start_called_with_link_down,
15638 "TX start routine called while link down count");
15640 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
15641 "tx_start_called_with_queue_full",
15642 CTLFLAG_RD, &sc->tx_start_called_with_queue_full,
15643 "TX start routine called with queue full count");
15645 /* ToDo: Add more statistics here. */
15648 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "bxe_debug",
15649 CTLFLAG_RW, &bxe_debug, 0,
15650 "Debug message level flag");
15654 #define QUEUE_NAME_LEN 32
15655 char namebuf[QUEUE_NAME_LEN];
15656 struct sysctl_oid *queue_node;
15657 struct sysctl_oid_list *queue_list;
15659 for (int i = 0; i < sc->num_queues; i++) {
15660 struct bxe_fastpath *fp = &sc->fp[i];
15661 snprintf(namebuf, QUEUE_NAME_LEN, "fp[%02d]", i);
15663 queue_node = SYSCTL_ADD_NODE(ctx, children, OID_AUTO,
15664 namebuf, CTLFLAG_RD, NULL, "Queue Name");
15665 queue_list = SYSCTL_CHILDREN(queue_node);
15668 * Receive related fastpath statistics.*
15670 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15672 CTLFLAG_RD, &fp->rx_pkts,
15673 "Received packets");
15675 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15677 CTLFLAG_RD, &fp->rx_tpa_pkts,
15678 "Received TPA packets");
15680 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15681 "rx_null_cqe_flags",
15682 CTLFLAG_RD, &fp->rx_null_cqe_flags,
15683 "CQEs with NULL flags count");
15685 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15687 CTLFLAG_RD, &fp->rx_soft_errors,
15688 "Received frames dropped by driver count");
15691 * Transmit related fastpath statistics.*
15693 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15695 CTLFLAG_RD, &fp->tx_pkts,
15696 "Transmitted packets");
15698 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15700 CTLFLAG_RD, &fp->tx_soft_errors,
15701 "Transmit frames dropped by driver count");
15703 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15704 "tx_offload_frames_csum_ip",
15705 CTLFLAG_RD, &fp->tx_offload_frames_csum_ip,
15706 "IP checksum offload frame count");
15708 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15709 "tx_offload_frames_csum_tcp",
15710 CTLFLAG_RD, &fp->tx_offload_frames_csum_tcp,
15711 "TCP checksum offload frame count");
15713 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15714 "tx_offload_frames_csum_udp",
15715 CTLFLAG_RD, &fp->tx_offload_frames_csum_udp,
15716 "UDP checksum offload frame count");
15718 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15719 "tx_offload_frames_tso",
15720 CTLFLAG_RD, &fp->tx_offload_frames_tso,
15721 "TSO offload frame count");
15723 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15724 "tx_header_splits",
15725 CTLFLAG_RD, &fp->tx_header_splits,
15726 "TSO frame header/data split count");
15728 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15729 "tx_encap_failures",
15730 CTLFLAG_RD, &fp->tx_encap_failures,
15731 "TX encapsulation failure count");
15733 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15734 "tx_hw_queue_full",
15735 CTLFLAG_RD, &fp->tx_hw_queue_full,
15736 "TX H/W queue too full to add a frame count");
15738 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15739 "tx_hw_max_queue_depth",
15740 CTLFLAG_RD, &fp->tx_hw_max_queue_depth,
15741 "TX H/W maximum queue depth count");
15743 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15744 "tx_dma_mapping_failure",
15745 CTLFLAG_RD, &fp->tx_dma_mapping_failure,
15746 "TX DMA mapping failure");
15748 SYSCTL_ADD_INT(ctx, queue_list, OID_AUTO,
15749 "tx_max_drbr_queue_depth",
15750 CTLFLAG_RD, &fp->tx_max_drbr_queue_depth,
15751 0, "TX S/W queue maximum depth");
15753 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15754 "tx_window_violation_std",
15755 CTLFLAG_RD, &fp->tx_window_violation_std,
15756 "Standard frame TX BD window violation count");
15758 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15759 "tx_window_violation_tso",
15760 CTLFLAG_RD, &fp->tx_window_violation_tso,
15761 "TSO frame TX BD window violation count");
15763 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15764 "tx_unsupported_tso_request_ipv6",
15765 CTLFLAG_RD, &fp->tx_unsupported_tso_request_ipv6,
15766 "TSO frames with unsupported IPv6 protocol count");
15768 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15769 "tx_unsupported_tso_request_not_tcp",
15770 CTLFLAG_RD, &fp->tx_unsupported_tso_request_not_tcp,
15771 "TSO frames with unsupported protocol count");
15773 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15774 "tx_chain_lost_mbuf",
15775 CTLFLAG_RD, &fp->tx_chain_lost_mbuf,
15776 "Mbufs lost on TX chain count");
15778 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15779 "tx_frame_deferred",
15780 CTLFLAG_RD, &fp->tx_frame_deferred,
15781 "TX frame deferred from H/W queue to S/W queue count");
15783 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15785 CTLFLAG_RD, &fp->tx_queue_xoff,
15786 "TX queue full count");
15789 * Memory related fastpath statistics.*
15791 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15792 "mbuf_rx_bd_alloc_failed",
15793 CTLFLAG_RD, &fp->mbuf_rx_bd_alloc_failed,
15794 "RX BD mbuf allocation failure count");
15796 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15797 "mbuf_rx_bd_mapping_failed",
15798 CTLFLAG_RD, &fp->mbuf_rx_bd_mapping_failed,
15799 "RX BD mbuf mapping failure count");
15801 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15802 "mbuf_tpa_alloc_failed",
15803 CTLFLAG_RD, &fp->mbuf_tpa_alloc_failed,
15804 "TPA mbuf allocation failure count");
15806 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15807 "mbuf_tpa_mapping_failed",
15808 CTLFLAG_RD, &fp->mbuf_tpa_mapping_failed,
15809 "TPA mbuf mapping failure count");
15811 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15812 "mbuf_sge_alloc_failed",
15813 CTLFLAG_RD, &fp->mbuf_sge_alloc_failed,
15814 "SGE mbuf allocation failure count");
15816 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15817 "mbuf_sge_mapping_failed",
15818 CTLFLAG_RD, &fp->mbuf_sge_mapping_failed,
15819 "SGE mbuf mapping failure count");
15821 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15822 "mbuf_defrag_attempts",
15823 CTLFLAG_RD, &fp->mbuf_defrag_attempts,
15824 "Mbuf defrag attempt count");
15826 SYSCTL_ADD_ULONG(ctx, queue_list, OID_AUTO,
15827 "mbuf_defrag_failures",
15828 CTLFLAG_RD, &fp->mbuf_defrag_failures,
15829 "Mbuf defrag failure count");
15835 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "driver_state",
15836 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15837 bxe_sysctl_driver_state, "I", "Drive state information");
15839 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_state",
15840 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15841 bxe_sysctl_hw_state, "I", "Hardware state information");
15843 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_fw",
15844 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15845 bxe_sysctl_dump_fw, "I", "Dump MCP firmware");
15847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_rx_bd_chain",
15848 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15849 bxe_sysctl_dump_rx_bd_chain, "I", "Dump rx_bd chain");
15851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_rx_cq_chain",
15852 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15853 bxe_sysctl_dump_rx_cq_chain, "I", "Dump cqe chain");
15855 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dump_tx_chain",
15856 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15857 bxe_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
15860 * Generates a GRCdump (run sysctl dev.bxe.0.grcdump=0
15861 * before accessing buffer below).
15863 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "grcdump",
15864 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0, bxe_sysctl_grcdump,
15865 "I", "Initiate a grcdump operation");
15869 * Use "sysctl -b dev.bxe.0.grcdump_buffer > buf.bin".
15871 SYSCTL_ADD_OPAQUE(ctx, children, OID_AUTO, "grcdump_buffer",
15872 CTLFLAG_RD | CTLFLAG_SKIP, sc->grcdump_buffer,
15873 BXE_GRCDUMP_BUF_SIZE, "IU", "Access grcdump buffer");
15875 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "breakpoint",
15876 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15877 bxe_sysctl_breakpoint, "I", "Driver breakpoint");
15879 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
15880 CTLTYPE_INT | CTLFLAG_RW, (void *)sc, 0,
15881 bxe_sysctl_reg_read, "I", "Register read");
15883 #endif /* BXE_DEBUG */
15887 * BXE Debug Routines
15891 * Writes out the header for the debug dump buffer.
15900 bxe_dump_debug_header(struct bxe_softc *sc, uint32_t *index)
15902 struct hd_param hd_param_cu = {0};
15905 buf = sc->grcdump_buffer;
15906 if (CHIP_IS_E1H(sc))
15907 hd_param_cu = hd_param_e1h;
15909 hd_param_cu = hd_param_e1;
15911 buf[(*index)++] = hd_param_cu.time_stamp;
15912 buf[(*index)++] = hd_param_cu.diag_ver;
15913 buf[(*index)++] = hd_param_cu.grc_dump_ver;
15915 buf[(*index)++] = REG_RD_IND(sc, XSTORM_WAITP_ADDRESS);
15916 buf[(*index)++] = REG_RD_IND(sc, TSTORM_WAITP_ADDRESS);
15917 buf[(*index)++] = REG_RD_IND(sc, USTORM_WAITP_ADDRESS);
15918 buf[(*index)++] = REG_RD_IND(sc, CSTORM_WAITP_ADDRESS);
15920 /* The size of the header is stored at the first DWORD. */
15921 buf[0] = (*index) - 1;
15926 * Writes to the controller to prepare it for a dump.
15935 bxe_dump_debug_writes(struct bxe_softc *sc)
15937 uint32_t write_val;
15940 /* Halt the STORMs to get a consistent device state. */
15941 REG_WR_IND(sc, XSTORM_WAITP_ADDRESS, write_val);
15942 REG_WR_IND(sc, TSTORM_WAITP_ADDRESS, write_val);
15943 REG_WR_IND(sc, USTORM_WAITP_ADDRESS, write_val);
15944 REG_WR_IND(sc, CSTORM_WAITP_ADDRESS, write_val);
15946 if (CHIP_IS_E1H(sc))
15947 REG_WR_IND(sc, TSTORM_CAM_MODE, write_val);
15952 * Cycles through the required register reads and dumps them
15953 * to the debug buffer.
15962 bxe_dump_debug_reg_read(struct bxe_softc *sc, uint32_t *index)
15964 preg_addr preg_addrs;
15965 uint32_t regs_count, *buf;
15966 uint32_t i, reg_addrs_index;
15968 buf = sc->grcdump_buffer;
15971 /* Read different registers for different controllers. */
15972 if (CHIP_IS_E1H(sc)) {
15973 regs_count = regs_count_e1h;
15974 preg_addrs = ®_addrs_e1h[0];
15976 regs_count = regs_count_e1;
15977 preg_addrs = ®_addrs_e1[0];
15980 /* ToDo: Add a buffer size check. */
15981 for (reg_addrs_index = 0; reg_addrs_index < regs_count;
15982 reg_addrs_index++) {
15983 for (i = 0; i < preg_addrs[reg_addrs_index].size; i++) {
15984 buf[(*index)++] = REG_RD_IND(sc,
15985 preg_addrs[reg_addrs_index].addr + (i * 4));
15991 * Cycles through the required wide register reads and dumps them
15992 * to the debug buffer.
15998 bxe_dump_debug_reg_wread(struct bxe_softc *sc, uint32_t *index)
16000 pwreg_addr pwreg_addrs;
16001 uint32_t reg_addrs_index, reg_add_read, reg_add_count;
16002 uint32_t *buf, cam_index, wregs_count;
16004 buf = sc->grcdump_buffer;
16005 pwreg_addrs = NULL;
16007 /* Read different registers for different controllers. */
16008 if (CHIP_IS_E1H(sc)) {
16009 wregs_count = wregs_count_e1h;
16010 pwreg_addrs = &wreg_addrs_e1h[0];
16012 wregs_count = wregs_count_e1;
16013 pwreg_addrs = &wreg_addrs_e1[0];
16016 for (reg_addrs_index = 0; reg_addrs_index < wregs_count;
16017 reg_addrs_index++) {
16018 reg_add_read = pwreg_addrs[reg_addrs_index].addr;
16019 for (reg_add_count = 0; reg_add_count <
16020 pwreg_addrs[reg_addrs_index].size; reg_add_count++) {
16021 buf[(*index)++] = REG_RD_IND(sc, reg_add_read);
16022 reg_add_read += sizeof(uint32_t);
16024 for (cam_index = 0; cam_index <
16025 pwreg_addrs[reg_addrs_index].const_regs_count;
16027 buf[(*index)++] = REG_RD_IND(sc,
16028 pwreg_addrs[reg_addrs_index].const_regs[cam_index]);
16034 * Performs a debug dump for offline diagnostics.
16036 * Note that when this routine is called the STORM
16037 * processors will be stopped in order to create a
16038 * cohesive dump. The controller will need to be
16039 * reset before the device can begin passing traffic
16046 bxe_grcdump(struct bxe_softc *sc, int log)
16048 uint32_t *buf, i, index;
16051 buf = sc->grcdump_buffer;
16054 /* Write the header and regsiters contents to the dump buffer. */
16055 bxe_dump_debug_header(sc, &index);
16056 bxe_dump_debug_writes(sc);
16057 bxe_dump_debug_reg_read(sc,&index);
16058 bxe_dump_debug_reg_wread(sc, &index);
16060 /* Print the results to the system log is necessary. */
16063 "-----------------------------"
16065 "-----------------------------\n");
16066 BXE_PRINTF("Buffer length = 0x%08X bytes\n", index * 4);
16068 for (i = 0; i < index; i += 8) {
16070 "0x%08X - 0x%08X 0x%08X 0x%08X 0x%08X "
16071 "0x%08X 0x%08X 0x%08X 0x%08X\n", i * 4,
16072 buf[i + 0], buf[i + 1], buf[i + 2],
16073 buf[i + 3], buf[i + 4], buf[i + 5],
16074 buf[i + 6], buf[i + 7]);
16078 "-----------------------------"
16080 "-----------------------------\n");
16083 BXE_PRINTF("No grcdump buffer allocated!\n");
16088 * Check that an Etherent frame is valid and prints out debug info if it's
16095 void bxe_validate_rx_packet(struct bxe_fastpath *fp, uint16_t comp_cons,
16096 union eth_rx_cqe *cqe, struct mbuf *m)
16098 struct bxe_softc *sc;
16103 /* Check that the mbuf is sane. */
16104 error = m_sanity(m, FALSE);
16105 if (error != 1 || ((m->m_len < ETHER_HDR_LEN) |
16106 (m->m_len > ETH_MAX_JUMBO_PACKET_SIZE + ETH_OVREHEAD))) {
16108 bxe_dump_enet(sc, m);
16109 bxe_dump_cqe(fp, comp_cons, cqe);
16110 /* Make sure the packet has a valid length. */
16115 * Prints out Ethernet frame information from an mbuf.
16117 * Partially decode an Ethernet frame to look at some important headers.
16123 void bxe_dump_enet(struct bxe_softc *sc, struct mbuf *m)
16125 struct ether_vlan_header *eh;
16134 "-----------------------------"
16136 "-----------------------------\n");
16138 eh = mtod(m, struct ether_vlan_header *);
16140 /* Handle VLAN encapsulation if present. */
16141 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
16142 etype = ntohs(eh->evl_proto);
16143 e_hlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
16145 etype = ntohs(eh->evl_encap_proto);
16146 e_hlen = ETHER_HDR_LEN;
16149 BXE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, e_hlen = %d\n",
16150 eh->evl_dhost, ":", eh->evl_shost, ":", etype, e_hlen);
16154 ip = (struct ip *)(m->m_data + e_hlen);
16156 "--ip: dest = 0x%08X , src = 0x%08X, "
16157 "ip_hlen = %d bytes, len = %d bytes, protocol = 0x%02X, "
16158 "ip_id = 0x%04X, csum = 0x%04X\n",
16159 ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
16160 (ip->ip_hl << 2), ntohs(ip->ip_len), ip->ip_p,
16161 ntohs(ip->ip_id), ntohs(ip->ip_sum));
16163 switch (ip->ip_p) {
16165 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
16167 "-tcp: dest = %d, src = %d, tcp_hlen = %d "
16168 "bytes, flags = 0x%b, csum = 0x%04X\n",
16169 ntohs(th->th_dport), ntohs(th->th_sport),
16170 (th->th_off << 2), th->th_flags,
16171 "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST\02SYN\01FIN",
16172 ntohs(th->th_sum));
16175 uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
16177 "-udp: dest = %d, src = %d, udp_hlen = %d "
16178 "bytes, len = %d bytes, csum = 0x%04X\n",
16179 ntohs(uh->uh_dport), ntohs(uh->uh_sport),
16180 (int)sizeof(struct udphdr), ntohs(uh->uh_ulen),
16181 ntohs(uh->uh_sum));
16184 BXE_PRINTF("icmp:\n");
16187 BXE_PRINTF("----: Other IP protocol.\n");
16190 case ETHERTYPE_IPV6:
16191 /* ToDo: Add IPv6 support. */
16192 BXE_PRINTF("IPv6 not supported!.\n");
16194 case ETHERTYPE_ARP:
16195 BXE_PRINTF("-arp: ");
16196 ah = (struct arphdr *) (m->m_data + e_hlen);
16197 switch (ntohs(ah->ar_op)) {
16198 case ARPOP_REVREQUEST:
16199 printf("reverse ARP request\n");
16201 case ARPOP_REVREPLY:
16202 printf("reverse ARP reply\n");
16204 case ARPOP_REQUEST:
16205 printf("ARP request\n");
16208 printf("ARP reply\n");
16211 printf("other ARP operation\n");
16215 BXE_PRINTF("----: Other protocol.\n");
16219 "-----------------------------"
16221 "-----------------------------\n");
16226 bxe_dump_mbuf_data(struct mbuf *m, int len)
16231 ptr = mtod(m, uint8_t *);
16232 printf("\nmbuf->m_data:");
16234 for (i = 0; i < len; i++){
16235 if (i != 0 && i % 40 == 0)
16237 else if (i != 0 && i % 6 == 0)
16239 printf("%02x", *ptr++);
16247 * Prints out information about an mbuf.
16253 void bxe_dump_mbuf(struct bxe_softc *sc, struct mbuf *m)
16256 BXE_PRINTF("mbuf: null pointer\n");
16261 BXE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
16262 "m_data = %p\n", m, m->m_len, m->m_flags,
16263 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data);
16265 if (m->m_flags & M_PKTHDR) {
16266 BXE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
16267 "csum_flags = %b\n", m->m_pkthdr.len,
16268 m->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
16269 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
16270 "\22M_PROMISC\23M_NOFREE",
16271 m->m_pkthdr.csum_flags,
16272 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP"
16273 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
16274 "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
16275 "\14CSUM_PSEUDO_HDR");
16278 if (m->m_flags & M_EXT) {
16279 BXE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
16280 m->m_ext.ext_buf, m->m_ext.ext_size);
16281 switch (m->m_ext.ext_type) {
16283 printf("EXT_CLUSTER\n"); break;
16285 printf("EXT_SFBUF\n"); break;
16287 printf("EXT_JUMBO9\n"); break;
16289 printf("EXT_JUMBO16\n"); break;
16291 printf("EXT_PACKET\n"); break;
16293 printf("EXT_MBUF\n"); break;
16295 printf("EXT_NET_DRV\n"); break;
16297 printf("EXT_MOD_TYPE\n"); break;
16298 case EXT_DISPOSABLE:
16299 printf("EXT_DISPOSABLE\n"); break;
16301 printf("EXT_EXTREF\n"); break;
16303 printf("UNKNOWN\n");
16312 * Prints out information about an rx_bd.
16318 void bxe_dump_rxbd(struct bxe_fastpath *fp, int idx,
16319 struct eth_rx_bd *rx_bd)
16321 struct bxe_softc *sc;
16325 /* Check if index out of range. */
16326 if (idx > MAX_RX_BD) {
16327 BXE_PRINTF("fp[%02d].rx_bd[0x%04X] XX: Invalid rx_bd index!\n",
16329 } else if ((idx & RX_BD_PER_PAGE_MASK) >= USABLE_RX_BD_PER_PAGE) {
16330 /* RX Chain page pointer. */
16331 BXE_PRINTF("fp[%02d].rx_bd[0x%04X] NP: haddr=0x%08X:%08X\n",
16332 fp->index, idx, rx_bd->addr_hi, rx_bd->addr_lo);
16334 BXE_PRINTF("fp[%02d].rx_bd[0x%04X] RX: haddr=0x%08X:%08X\n",
16335 fp->index, idx, rx_bd->addr_hi, rx_bd->addr_lo);
16340 * Prints out a completion queue entry.
16346 void bxe_dump_cqe(struct bxe_fastpath *fp, int idx,
16347 union eth_rx_cqe *cqe)
16349 struct bxe_softc *sc;
16353 if (idx > MAX_RCQ_ENTRIES) {
16354 /* Index out of range. */
16355 BXE_PRINTF("fp[%02d].rx_cqe[0x%04X]: Invalid rx_cqe index!\n",
16357 } else if ((idx & USABLE_RCQ_ENTRIES_PER_PAGE) ==
16358 USABLE_RCQ_ENTRIES_PER_PAGE) {
16359 /* CQE next page pointer. */
16360 BXE_PRINTF("fp[%02d].rx_cqe[0x%04X] NP: haddr=0x%08X:%08X\n",
16362 le32toh(cqe->next_page_cqe.addr_hi),
16363 le32toh(cqe->next_page_cqe.addr_lo));
16366 BXE_PRINTF("fp[%02d].rx_cqe[0x%04X] CQ: error_flags=0x%b, "
16367 "pkt_len=0x%04X, status_flags=0x%02X, vlan=0x%04X "
16368 "rss_hash=0x%08X\n", fp->index, idx,
16369 cqe->fast_path_cqe.type_error_flags,
16370 BXE_ETH_FAST_PATH_RX_CQE_ERROR_FLAGS_PRINTFB,
16371 le16toh(cqe->fast_path_cqe.pkt_len),
16372 cqe->fast_path_cqe.status_flags,
16373 le16toh(cqe->fast_path_cqe.vlan_tag),
16374 le32toh(cqe->fast_path_cqe.rss_hash_result));
16379 * Prints out information about a TX parsing BD.
16385 void bxe_dump_tx_parsing_bd(struct bxe_fastpath *fp, int idx,
16386 struct eth_tx_parse_bd *p_bd)
16388 struct bxe_softc *sc;
16392 if (idx > MAX_TX_BD){
16393 /* Index out of range. */
16394 BXE_PRINTF("fp[%02d].tx_bd[0x%04X] XX: Invalid tx_bd index!\n",
16397 BXE_PRINTF("fp[%02d]:tx_bd[0x%04X] PB: global_data=0x%b, "
16398 "tcp_flags=0x%b, ip_hlen=%04d, total_hlen=%04d, "
16399 "tcp_pseudo_csum=0x%04X, lso_mss=0x%04X, ip_id=0x%04X, "
16400 "tcp_send_seq=0x%08X\n", fp->index, idx,
16401 p_bd->global_data, BXE_ETH_TX_PARSE_BD_GLOBAL_DATA_PRINTFB,
16402 p_bd->tcp_flags, BXE_ETH_TX_PARSE_BD_TCP_FLAGS_PRINTFB,
16403 p_bd->ip_hlen, p_bd->total_hlen, p_bd->tcp_pseudo_csum,
16404 p_bd->lso_mss, p_bd->ip_id, p_bd->tcp_send_seq);
16409 * Prints out information about a tx_bd.
16415 void bxe_dump_txbd(struct bxe_fastpath *fp, int idx,
16416 union eth_tx_bd_types *tx_bd)
16418 struct bxe_softc *sc;
16422 if (idx > MAX_TX_BD){
16423 /* Index out of range. */
16424 BXE_PRINTF("fp[%02d]:tx_bd[0x%04X] XX: Invalid tx_bd index!\n",
16426 } else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE) {
16427 /* TX next page BD. */
16428 BXE_PRINTF("fp[%02d]:tx_bd[0x%04X] NP: haddr=0x%08X:%08X\n",
16429 fp->index, idx, tx_bd->next_bd.addr_hi,
16430 tx_bd->next_bd.addr_lo);
16431 } else if ((tx_bd->start_bd.bd_flags.as_bitfield &
16432 ETH_TX_BD_FLAGS_START_BD) != 0) {
16434 BXE_PRINTF("fp[%02d]:tx_bd[0x%04X] ST: haddr=0x%08X:%08X, "
16435 "nbd=%02d, nbytes=%05d, vlan/idx=0x%04X, flags=0x%b, "
16436 "gendata=0x%02X\n",
16437 fp->index, idx, tx_bd->start_bd.addr_hi,
16438 tx_bd->start_bd.addr_lo, tx_bd->start_bd.nbd,
16439 tx_bd->start_bd.nbytes, tx_bd->start_bd.vlan,
16440 tx_bd->start_bd.bd_flags.as_bitfield,
16441 BXE_ETH_TX_BD_FLAGS_PRINTFB,
16442 tx_bd->start_bd.general_data);
16444 /* Regular TX BD. */
16445 BXE_PRINTF("fp[%02d]:tx_bd[0x%04X] TX: haddr=0x%08X:%08X, "
16446 "total_pkt_bytes=%05d, nbytes=%05d\n", fp->index, idx,
16447 tx_bd->reg_bd.addr_hi, tx_bd->reg_bd.addr_lo,
16448 tx_bd->reg_bd.total_pkt_bytes, tx_bd->reg_bd.nbytes);
16454 * Prints out the transmit chain.
16460 void bxe_dump_tx_chain(struct bxe_fastpath * fp, int tx_bd_prod, int count)
16462 struct bxe_softc *sc;
16463 union eth_tx_bd_types *tx_bd;
16464 uint32_t val_hi, val_lo;
16465 int i, parsing_bd = 0;
16469 /* First some info about the tx_bd chain structure. */
16471 "----------------------------"
16473 "----------------------------\n");
16475 val_hi = U64_HI(fp->tx_dma.paddr);
16476 val_lo = U64_LO(fp->tx_dma.paddr);
16478 "0x%08X:%08X - (fp[%02d]->tx_dma.paddr) TX Chain physical address\n",
16479 val_hi, val_lo, fp->index);
16481 "page size = 0x%08X, tx chain pages = 0x%08X\n",
16482 (uint32_t)BCM_PAGE_SIZE, (uint32_t)NUM_TX_PAGES);
16484 "tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
16485 (uint32_t)TOTAL_TX_BD_PER_PAGE, (uint32_t)USABLE_TX_BD_PER_PAGE);
16487 "total tx_bd = 0x%08X\n", (uint32_t)TOTAL_TX_BD);
16490 "-----------------------------"
16492 "-----------------------------\n");
16494 /* Now print out the tx_bd's themselves. */
16495 for (i = 0; i < count; i++) {
16496 tx_bd = &fp->tx_chain[tx_bd_prod];
16498 struct eth_tx_parse_bd *p_bd;
16499 p_bd = (struct eth_tx_parse_bd *)
16500 &fp->tx_chain[tx_bd_prod].parse_bd;
16501 bxe_dump_tx_parsing_bd(fp, tx_bd_prod, p_bd);
16504 bxe_dump_txbd(fp, tx_bd_prod, tx_bd);
16505 if ((tx_bd->start_bd.bd_flags.as_bitfield &
16506 ETH_TX_BD_FLAGS_START_BD) != 0)
16508 * There is always a parsing BD following the
16509 * tx_bd with the start bit set.
16513 /* Don't skip next page pointers. */
16514 tx_bd_prod = ((tx_bd_prod + 1) & MAX_TX_BD);
16518 "-----------------------------"
16520 "-----------------------------\n");
16524 * Prints out the receive completion queue chain.
16530 void bxe_dump_rx_cq_chain(struct bxe_fastpath *fp, int rx_cq_prod, int count)
16532 struct bxe_softc *sc;
16533 union eth_rx_cqe *cqe;
16538 /* First some info about the tx_bd chain structure. */
16540 "----------------------------"
16542 "----------------------------\n");
16544 BXE_PRINTF("fp[%02d]->rcq_dma.paddr = 0x%jX\n",
16545 fp->index, (uintmax_t) fp->rcq_dma.paddr);
16547 BXE_PRINTF("page size = 0x%08X, cq chain pages "
16549 (uint32_t)BCM_PAGE_SIZE, (uint32_t) NUM_RCQ_PAGES);
16551 BXE_PRINTF("cqe_bd per page = 0x%08X, usable cqe_bd per "
16553 (uint32_t) TOTAL_RCQ_ENTRIES_PER_PAGE,
16554 (uint32_t) USABLE_RCQ_ENTRIES_PER_PAGE);
16556 BXE_PRINTF("total cqe_bd = 0x%08X\n",(uint32_t) TOTAL_RCQ_ENTRIES);
16558 /* Now the CQE entries themselves. */
16560 "----------------------------"
16562 "----------------------------\n");
16564 for (i = 0; i < count; i++) {
16565 cqe = (union eth_rx_cqe *)&fp->rcq_chain[rx_cq_prod];
16567 bxe_dump_cqe(fp, rx_cq_prod, cqe);
16569 /* Don't skip next page pointers. */
16570 rx_cq_prod = ((rx_cq_prod + 1) & MAX_RCQ_ENTRIES);
16574 "----------------------------"
16576 "----------------------------\n");
16580 * Prints out the receive chain.
16586 void bxe_dump_rx_bd_chain(struct bxe_fastpath *fp, int prod, int count)
16588 struct bxe_softc *sc;
16589 struct eth_rx_bd *rx_bd;
16595 /* First some info about the tx_bd chain structure. */
16597 "----------------------------"
16599 "----------------------------\n");
16602 "----- RX_BD Chain -----\n");
16604 BXE_PRINTF("fp[%02d]->rx_dma.paddr = 0x%jX\n",
16605 fp->index, (uintmax_t) fp->rx_dma.paddr);
16608 "page size = 0x%08X, rx chain pages = 0x%08X\n",
16609 (uint32_t)BCM_PAGE_SIZE, (uint32_t)NUM_RX_PAGES);
16612 "rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
16613 (uint32_t)TOTAL_RX_BD_PER_PAGE, (uint32_t)USABLE_RX_BD_PER_PAGE);
16616 "total rx_bd = 0x%08X\n", (uint32_t)TOTAL_RX_BD);
16618 /* Now the rx_bd entries themselves. */
16620 "----------------------------"
16622 "----------------------------\n");
16624 /* Now print out the rx_bd's themselves. */
16625 for (i = 0; i < count; i++) {
16626 rx_bd = (struct eth_rx_bd *) (&fp->rx_chain[prod]);
16627 m = sc->fp->rx_mbuf_ptr[prod];
16629 bxe_dump_rxbd(fp, prod, rx_bd);
16630 bxe_dump_mbuf(sc, m);
16632 /* Don't skip next page pointers. */
16633 prod = ((prod + 1) & MAX_RX_BD);
16637 "----------------------------"
16639 "----------------------------\n");
16643 * Prints out a register dump.
16649 void bxe_dump_hw_state(struct bxe_softc *sc)
16654 "----------------------------"
16656 "----------------------------\n");
16658 for (i = 0x2000; i < 0x10000; i += 0x10)
16659 BXE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
16660 REG_RD(sc, 0 + i), REG_RD(sc, 0 + i + 0x4),
16661 REG_RD(sc, 0 + i + 0x8), REG_RD(sc, 0 + i + 0xC));
16664 "----------------------------"
16666 "----------------------------\n");
16670 * Prints out the RX mbuf chain.
16676 void bxe_dump_rx_mbuf_chain(struct bxe_softc *sc, int chain_prod, int count)
16682 "----------------------------"
16684 "----------------------------\n");
16686 for (i = 0; i < count; i++) {
16687 m = sc->fp->rx_mbuf_ptr[chain_prod];
16688 BXE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
16689 bxe_dump_mbuf(sc, m);
16690 chain_prod = RX_BD(NEXT_RX_BD(chain_prod));
16694 "----------------------------"
16696 "----------------------------\n");
16700 * Prints out the mbufs in the TX mbuf chain.
16706 void bxe_dump_tx_mbuf_chain(struct bxe_softc *sc, int chain_prod, int count)
16712 "----------------------------"
16714 "----------------------------\n");
16716 for (i = 0; i < count; i++) {
16717 m = sc->fp->tx_mbuf_ptr[chain_prod];
16718 BXE_PRINTF("txmbuf[%d]\n", chain_prod);
16719 bxe_dump_mbuf(sc, m);
16720 chain_prod = TX_BD(NEXT_TX_BD(chain_prod));
16724 "----------------------------"
16726 "----------------------------\n");
16730 * Prints out the status block from host memory.
16736 void bxe_dump_status_block(struct bxe_softc *sc)
16738 struct bxe_fastpath *fp;
16739 struct host_def_status_block *def_sb;
16740 struct host_status_block *fpsb;
16743 def_sb = sc->def_sb;
16745 "----------------------------"
16747 "----------------------------\n");
16749 for (i = 0; i < sc->num_queues; i++) {
16751 fpsb = fp->status_block;
16753 "----------------------------"
16755 "----------------------------\n", fp->index);
16757 /* Print the USTORM fields (HC_USTORM_SB_NUM_INDICES). */
16759 "0x%08X - USTORM Flags (F/W RESERVED)\n",
16760 fpsb->u_status_block.__flags);
16762 " 0x%02X - USTORM PCIe Function\n",
16763 fpsb->u_status_block.func);
16765 " 0x%02X - USTORM Status Block ID\n",
16766 fpsb->u_status_block.status_block_id);
16768 " 0x%04X - USTORM Status Block Index (Tag)\n",
16769 fpsb->u_status_block.status_block_index);
16771 " 0x%04X - USTORM [TOE_RX_CQ_CONS]\n",
16772 fpsb->u_status_block.index_values[HC_INDEX_U_TOE_RX_CQ_CONS]);
16774 " 0x%04X - USTORM [ETH_RX_CQ_CONS]\n",
16775 fpsb->u_status_block.index_values[HC_INDEX_U_ETH_RX_CQ_CONS]);
16777 " 0x%04X - USTORM [ETH_RX_BD_CONS]\n",
16778 fpsb->u_status_block.index_values[HC_INDEX_U_ETH_RX_BD_CONS]);
16780 " 0x%04X - USTORM [RESERVED]\n",
16781 fpsb->u_status_block.index_values[3]);
16783 /* Print the CSTORM fields (HC_CSTORM_SB_NUM_INDICES). */
16785 "0x%08X - CSTORM Flags (F/W RESERVED)\n",
16786 fpsb->c_status_block.__flags);
16788 " 0x%02X - CSTORM PCIe Function\n",
16789 fpsb->c_status_block.func);
16791 " 0x%02X - CSTORM Status Block ID\n",
16792 fpsb->c_status_block.status_block_id);
16794 " 0x%04X - CSTORM Status Block Index (Tag)\n",
16795 fpsb->c_status_block.status_block_index);
16797 " 0x%04X - CSTORM [TOE_TX_CQ_CONS]\n",
16798 fpsb->c_status_block.index_values[HC_INDEX_C_TOE_TX_CQ_CONS]);
16800 " 0x%04X - CSTORM [ETH_TX_CQ_CONS]\n",
16801 fpsb->c_status_block.index_values[HC_INDEX_C_ETH_TX_CQ_CONS]);
16803 " 0x%04X - CSTORM [ISCSI_EQ_CONS]\n",
16804 fpsb->c_status_block.index_values[HC_INDEX_C_ISCSI_EQ_CONS]);
16806 " 0x%04X - CSTORM [RESERVED]\n",
16807 fpsb->c_status_block.index_values[3]);
16811 "--------------------------"
16812 " Def Status Block "
16813 "--------------------------\n");
16815 /* Print attention information. */
16817 " 0x%02X - Status Block ID\n",
16818 def_sb->atten_status_block.status_block_id);
16820 "0x%08X - Attn Bits\n",
16821 def_sb->atten_status_block.attn_bits);
16823 "0x%08X - Attn Bits Ack\n",
16824 def_sb->atten_status_block.attn_bits_ack);
16826 " 0x%04X - Attn Block Index\n",
16827 le16toh(def_sb->atten_status_block.attn_bits_index));
16829 /* Print the USTORM fields (HC_USTORM_DEF_SB_NUM_INDICES). */
16831 " 0x%02X - USTORM Status Block ID\n",
16832 def_sb->u_def_status_block.status_block_id);
16834 " 0x%04X - USTORM Status Block Index\n",
16835 le16toh(def_sb->u_def_status_block.status_block_index));
16837 " 0x%04X - USTORM [ETH_RDMA_RX_CQ_CONS]\n",
16838 le16toh(def_sb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_RDMA_RX_CQ_CONS]));
16840 " 0x%04X - USTORM [ETH_ISCSI_RX_CQ_CONS]\n",
16841 le16toh(def_sb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_ISCSI_RX_CQ_CONS]));
16843 " 0x%04X - USTORM [ETH_RDMA_RX_BD_CONS]\n",
16844 le16toh(def_sb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_RDMA_RX_BD_CONS]));
16846 " 0x%04X - USTORM [ETH_ISCSI_RX_BD_CONS]\n",
16847 le16toh(def_sb->u_def_status_block.index_values[HC_INDEX_DEF_U_ETH_ISCSI_RX_BD_CONS]));
16849 /* Print the CSTORM fields (HC_CSTORM_DEF_SB_NUM_INDICES). */
16851 " 0x%02X - CSTORM Status Block ID\n",
16852 def_sb->c_def_status_block.status_block_id);
16854 " 0x%04X - CSTORM Status Block Index\n",
16855 le16toh(def_sb->c_def_status_block.status_block_index));
16857 " 0x%04X - CSTORM [RDMA_EQ_CONS]\n",
16858 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_RDMA_EQ_CONS]));
16860 " 0x%04X - CSTORM [RDMA_NAL_PROD]\n",
16861 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_RDMA_NAL_PROD]));
16863 " 0x%04X - CSTORM [ETH_FW_TX_CQ_CONS]\n",
16864 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_FW_TX_CQ_CONS]));
16866 " 0x%04X - CSTORM [ETH_SLOW_PATH]\n",
16867 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_SLOW_PATH]));
16869 " 0x%04X - CSTORM [ETH_RDMA_CQ_CONS]\n",
16870 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_RDMA_CQ_CONS]));
16872 " 0x%04X - CSTORM [ETH_ISCSI_CQ_CONS]\n",
16873 le16toh(def_sb->c_def_status_block.index_values[HC_INDEX_DEF_C_ETH_ISCSI_CQ_CONS]));
16875 " 0x%04X - CSTORM [UNUSED]\n",
16876 le16toh(def_sb->c_def_status_block.index_values[6]));
16878 " 0x%04X - CSTORM [UNUSED]\n",
16879 le16toh(def_sb->c_def_status_block.index_values[7]));
16881 /* Print the TSTORM fields (HC_TSTORM_DEF_SB_NUM_INDICES). */
16883 " 0x%02X - TSTORM Status Block ID\n",
16884 def_sb->t_def_status_block.status_block_id);
16886 " 0x%04X - TSTORM Status Block Index\n",
16887 le16toh(def_sb->t_def_status_block.status_block_index));
16888 for (i = 0; i < HC_TSTORM_DEF_SB_NUM_INDICES; i++)
16890 " 0x%04X - TSTORM [UNUSED]\n",
16891 le16toh(def_sb->t_def_status_block.index_values[i]));
16893 /* Print the XSTORM fields (HC_XSTORM_DEF_SB_NUM_INDICES). */
16895 " 0x%02X - XSTORM Status Block ID\n",
16896 def_sb->x_def_status_block.status_block_id);
16898 " 0x%04X - XSTORM Status Block Index\n",
16899 le16toh(def_sb->x_def_status_block.status_block_index));
16900 for (i = 0; i < HC_XSTORM_DEF_SB_NUM_INDICES; i++)
16902 " 0x%04X - XSTORM [UNUSED]\n",
16903 le16toh(def_sb->x_def_status_block.index_values[i]));
16906 "----------------------------"
16908 "----------------------------\n");
16913 * Prints out the statistics block from host memory.
16919 void bxe_dump_stats_block(struct bxe_softc *sc)
16925 * Prints out a summary of the fastpath state.
16931 void bxe_dump_fp_state(struct bxe_fastpath *fp)
16933 struct bxe_softc *sc;
16934 uint32_t val_hi, val_lo;
16939 "----------------------------"
16941 "----------------------------\n");
16943 val_hi = U64_HI(fp);
16944 val_lo = U64_LO(fp);
16946 "0x%08X:%08X - (fp[%02d]) fastpath virtual address\n",
16947 val_hi, val_lo, fp->index);
16949 " %3d - (fp[%02d]->sb_id)\n",
16950 fp->sb_id, fp->index);
16952 " %3d - (fp[%02d]->cl_id)\n",
16953 fp->cl_id, fp->index);
16955 " 0x%08X - (fp[%02d]->state)\n",
16956 (uint32_t)fp->state, fp->index);
16958 /* Receive state. */
16960 " 0x%04X - (fp[%02d]->rx_bd_prod)\n",
16961 fp->rx_bd_prod, fp->index);
16963 " 0x%04X - (fp[%02d]->rx_bd_cons)\n",
16964 fp->rx_bd_cons, fp->index);
16966 " 0x%04X - (fp[%02d]->rx_cq_prod)\n",
16967 fp->rx_cq_prod, fp->index);
16969 " 0x%04X - (fp[%02d]->rx_cq_cons)\n",
16970 fp->rx_cq_cons, fp->index);
16972 " %16lu - (fp[%02d]->rx_pkts)\n",
16973 fp->rx_pkts, fp->index);
16975 " 0x%08X - (fp[%02d]->rx_mbuf_alloc)\n",
16976 fp->rx_mbuf_alloc, fp->index);
16978 " %16lu - (fp[%02d]->ipackets)\n",
16979 fp->ipackets, fp->index);
16981 " %16lu - (fp[%02d]->rx_soft_errors)\n",
16982 fp->rx_soft_errors, fp->index);
16984 /* Transmit state. */
16986 " 0x%04X - (fp[%02d]->tx_bd_used)\n",
16987 fp->tx_bd_used, fp->index);
16989 " 0x%04X - (fp[%02d]->tx_bd_prod)\n",
16990 fp->tx_bd_prod, fp->index);
16992 " 0x%04X - (fp[%02d]->tx_bd_cons)\n",
16993 fp->tx_bd_cons, fp->index);
16995 " 0x%04X - (fp[%02d]->tx_pkt_prod)\n",
16996 fp->tx_pkt_prod, fp->index);
16998 " 0x%04X - (fp[%02d]->tx_pkt_cons)\n",
16999 fp->tx_pkt_cons, fp->index);
17001 " %16lu - (fp[%02d]->tx_pkts)\n",
17002 fp->tx_pkts, fp->index);
17004 " 0x%08X - (fp[%02d]->tx_mbuf_alloc)\n",
17005 fp->tx_mbuf_alloc, fp->index);
17007 " %16lu - (fp[%02d]->opackets)\n",
17008 fp->opackets, fp->index);
17010 " %16lu - (fp[%02d]->tx_soft_errors)\n",
17011 fp->tx_soft_errors, fp->index);
17014 if (TPA_ENABLED(sc)) {
17016 " %16lu - (fp[%02d]->rx_tpa_pkts)\n",
17017 fp->rx_tpa_pkts, fp->index);
17019 " 0x%08X - (fp[%02d]->tpa_mbuf_alloc)\n",
17020 fp->tpa_mbuf_alloc, fp->index);
17022 " 0x%08X - (fp[%02d]->sge_mbuf_alloc)\n",
17023 fp->sge_mbuf_alloc, fp->index);
17025 if (CHIP_IS_E1(sc)) {
17026 for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1; i++)
17028 " 0x%08X - (fp[%02d]->tpa_state[%02d])\n",
17029 (uint32_t)fp->tpa_state[i], fp->index, i);
17031 for (i = 0; i < ETH_MAX_AGGREGATION_QUEUES_E1; i++)
17033 " 0x%08X - (fp[%02d]->tpa_state[%02d])\n",
17034 (uint32_t)fp->tpa_state[i], fp->index, i);
17039 "----------------------------"
17041 "----------------------------\n");
17049 void bxe_dump_port_state_locked(struct bxe_softc *sc)
17053 "------------------------------"
17055 "------------------------------\n");
17058 " %2d - (port) pmf\n", sc->port.pmf);
17060 "0x%08X - (port) link_config\n", sc->port.link_config);
17062 "0x%08X - (port) supported\n", sc->port.supported);
17064 "0x%08X - (port) advertising\n", sc->port.advertising);
17066 "0x%08X - (port) port_stx\n", sc->port.port_stx);
17069 "----------------------------"
17071 "----------------------------\n");
17079 void bxe_dump_link_vars_state_locked(struct bxe_softc *sc)
17082 "---------------------------"
17083 " Link Vars State "
17084 "----------------------------\n");
17086 switch (sc->link_vars.mac_type) {
17087 case MAC_TYPE_NONE:
17088 BXE_PRINTF(" NONE");
17090 case MAC_TYPE_EMAC:
17091 BXE_PRINTF(" EMAC");
17093 case MAC_TYPE_BMAC:
17094 BXE_PRINTF(" BMAC");
17097 BXE_PRINTF(" UNKN");
17099 printf(" - (link_vars->mac_type)\n");
17102 " %2d - (link_vars->phy_link_up)\n",
17103 sc->link_vars.phy_link_up);
17105 " %2d - (link_vars->link_up)\n",
17106 sc->link_vars.link_up);
17108 " %2d - (link_vars->duplex)\n",
17109 sc->link_vars.duplex);
17111 " 0x%04X - (link_vars->flow_ctrl)\n",
17112 sc->link_vars.flow_ctrl);
17114 " 0x%04X - (link_vars->line_speed)\n",
17115 sc->link_vars.line_speed);
17117 "0x%08X - (link_vars->ieee_fc)\n",
17118 sc->link_vars.ieee_fc);
17120 "0x%08X - (link_vars->autoneg)\n",
17121 sc->link_vars.autoneg);
17123 "0x%08X - (link_vars->phy_flags)\n",
17124 sc->link_vars.phy_flags);
17126 "0x%08X - (link_vars->link_status)\n",
17127 sc->link_vars.link_status);
17130 "----------------------------"
17132 "----------------------------\n");
17142 void bxe_dump_link_params_state_locked(struct bxe_softc *sc)
17145 "--------------------------"
17146 " Link Params State "
17147 "---------------------------\n");
17150 " %2d - (link_params->port)\n",
17151 sc->link_params.port);
17153 " %2d - (link_params->loopback_mode)\n",
17154 sc->link_params.loopback_mode);
17156 " %3d - (link_params->phy_addr)\n",
17157 sc->link_params.phy_addr);
17159 " 0x%04X - (link_params->req_duplex)\n",
17160 sc->link_params.req_duplex);
17162 " 0x%04X - (link_params->req_flow_ctrl)\n",
17163 sc->link_params.req_flow_ctrl);
17165 " 0x%04X - (link_params->req_line_speed)\n",
17166 sc->link_params.req_line_speed);
17168 " %5d - (link_params->ether_mtu)\n",
17169 sc->port.ether_mtu);
17171 "0x%08X - (link_params->shmem_base) shared memory base address\n",
17172 sc->link_params.shmem_base);
17174 "0x%08X - (link_params->speed_cap_mask)\n",
17175 sc->link_params.speed_cap_mask);
17177 "0x%08X - (link_params->ext_phy_config)\n",
17178 sc->link_params.ext_phy_config);
17180 "0x%08X - (link_params->switch_cfg)\n",
17181 sc->link_params.switch_cfg);
17184 "----------------------------"
17186 "----------------------------\n");
17190 * Prints out a summary of the driver state.
17196 void bxe_dump_driver_state(struct bxe_softc *sc)
17198 uint32_t val_hi, val_lo;
17201 "-----------------------------"
17203 "-----------------------------\n");
17205 val_hi = U64_HI(sc);
17206 val_lo = U64_LO(sc);
17208 "0x%08X:%08X - (sc) driver softc structure virtual address\n",
17211 val_hi = U64_HI(sc->bxe_vhandle);
17212 val_lo = U64_LO(sc->bxe_vhandle);
17214 "0x%08X:%08X - (sc->bxe_vhandle) PCI BAR0 virtual address\n",
17217 val_hi = U64_HI(sc->bxe_db_vhandle);
17218 val_lo = U64_LO(sc->bxe_db_vhandle);
17220 "0x%08X:%08X - (sc->bxe_db_vhandle) PCI BAR2 virtual address\n",
17223 BXE_PRINTF(" 0x%08X - (sc->num_queues) Fastpath queues\n",
17225 BXE_PRINTF(" 0x%08X - (sc->rx_lane_swap) RX XAUI lane swap\n",
17227 BXE_PRINTF(" 0x%08X - (sc->tx_lane_swap) TX XAUI lane swap\n",
17229 BXE_PRINTF(" %16lu - (sc->debug_sim_mbuf_alloc_failed)\n",
17230 sc->debug_sim_mbuf_alloc_failed);
17231 BXE_PRINTF(" %16lu - (sc->debug_sim_mbuf_map_failed)\n",
17232 sc->debug_sim_mbuf_map_failed);
17235 "----------------------------"
17237 "----------------------------\n");
17239 bxe_dump_port_state_locked(sc);
17240 bxe_dump_link_params_state_locked(sc);
17241 bxe_dump_link_vars_state_locked(sc);
17245 * Dump bootcode (MCP) debug buffer to the console.
17251 void bxe_dump_fw(struct bxe_softc *sc)
17253 uint32_t addr, mark, data[9], offset;
17256 addr = sc->common.shmem_base - 0x0800 + 4;
17257 mark = REG_RD(sc, addr);
17258 mark = MCP_REG_MCPR_SCRATCH + ((mark + 0x3) & ~0x3) - 0x08000000;
17261 "---------------------------"
17262 " MCP Debug Buffer "
17263 "---------------------------\n");
17265 /* Read from "mark" to the end of the buffer. */
17266 for (offset = mark; offset <= sc->common.shmem_base;
17267 offset += (0x8 * 4)) {
17268 for (word = 0; word < 8; word++)
17269 data[word] = htonl(REG_RD(sc, offset + 4 * word));
17271 printf("%s", (char *) data);
17274 /* Read from the start of the buffer to "mark". */
17275 for (offset = addr + 4; offset <= mark; offset += (0x8 * 4)) {
17276 for (word = 0; word < 8; word++)
17277 data[word] = htonl(REG_RD(sc, offset + 4 * word));
17279 printf("%s", (char *) data);
17283 "----------------------------"
17285 "----------------------------\n");
17289 * Decode firmware messages.
17295 bxe_decode_mb_msgs(struct bxe_softc *sc, uint32_t drv_mb_header,
17296 uint32_t fw_mb_header)
17299 if (drv_mb_header) {
17300 BXE_PRINTF("Driver message is ");
17301 switch (drv_mb_header & DRV_MSG_CODE_MASK) {
17302 case DRV_MSG_CODE_LOAD_REQ:
17304 "LOAD_REQ (0x%08X)",
17305 (uint32_t)DRV_MSG_CODE_LOAD_REQ);
17307 case DRV_MSG_CODE_LOAD_DONE:
17309 "LOAD_DONE (0x%08X)",
17310 (uint32_t)DRV_MSG_CODE_LOAD_DONE);
17312 case DRV_MSG_CODE_UNLOAD_REQ_WOL_EN:
17314 "UNLOAD_REQ_WOL_EN (0x%08X)",
17315 (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_EN);
17317 case DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS:
17319 "UNLOAD_REQ_WOL_DIS (0x%08X)",
17320 (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS);
17322 case DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP:
17324 "UNLOADREQ_WOL_MCP (0x%08X)",
17325 (uint32_t)DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP);
17327 case DRV_MSG_CODE_UNLOAD_DONE:
17329 "UNLOAD_DONE (0x%08X)",
17330 (uint32_t)DRV_MSG_CODE_UNLOAD_DONE);
17332 case DRV_MSG_CODE_DIAG_ENTER_REQ:
17334 "DIAG_ENTER_REQ (0x%08X)",
17335 (uint32_t)DRV_MSG_CODE_DIAG_ENTER_REQ);
17337 case DRV_MSG_CODE_DIAG_EXIT_REQ:
17339 "DIAG_EXIT_REQ (0x%08X)",
17340 (uint32_t)DRV_MSG_CODE_DIAG_EXIT_REQ);
17342 case DRV_MSG_CODE_VALIDATE_KEY:
17344 "CODE_VALIDITY_KEY (0x%08X)",
17345 (uint32_t)DRV_MSG_CODE_VALIDATE_KEY);
17347 case DRV_MSG_CODE_GET_CURR_KEY:
17349 "GET_CURR_KEY (0x%08X)",
17350 (uint32_t) DRV_MSG_CODE_GET_CURR_KEY);
17352 case DRV_MSG_CODE_GET_UPGRADE_KEY:
17354 "GET_UPGRADE_KEY (0x%08X)",
17355 (uint32_t)DRV_MSG_CODE_GET_UPGRADE_KEY);
17357 case DRV_MSG_CODE_GET_MANUF_KEY:
17359 "GET_MANUF_KEY (0x%08X)",
17360 (uint32_t)DRV_MSG_CODE_GET_MANUF_KEY);
17362 case DRV_MSG_CODE_LOAD_L2B_PRAM:
17364 "LOAD_L2B_PRAM (0x%08X)",
17365 (uint32_t)DRV_MSG_CODE_LOAD_L2B_PRAM);
17367 case BIOS_MSG_CODE_LIC_CHALLENGE:
17369 "LIC_CHALLENGE (0x%08X)",
17370 (uint32_t)BIOS_MSG_CODE_LIC_CHALLENGE);
17372 case BIOS_MSG_CODE_LIC_RESPONSE:
17374 "LIC_RESPONSE (0x%08X)",
17375 (uint32_t)BIOS_MSG_CODE_LIC_RESPONSE);
17377 case BIOS_MSG_CODE_VIRT_MAC_PRIM:
17379 "VIRT_MAC_PRIM (0x%08X)",
17380 (uint32_t)BIOS_MSG_CODE_VIRT_MAC_PRIM);
17382 case BIOS_MSG_CODE_VIRT_MAC_ISCSI:
17384 "VIRT_MAC_ISCSI (0x%08X)",
17385 (uint32_t)BIOS_MSG_CODE_VIRT_MAC_ISCSI);
17389 "Unknown command (0x%08X)!",
17390 (drv_mb_header & DRV_MSG_CODE_MASK));
17393 printf(" (seq = 0x%04X)\n", (drv_mb_header &
17394 DRV_MSG_SEQ_NUMBER_MASK));
17397 if (fw_mb_header) {
17398 BXE_PRINTF("Firmware response is ");
17399 switch (fw_mb_header & FW_MSG_CODE_MASK) {
17400 case FW_MSG_CODE_DRV_LOAD_COMMON:
17402 "DRV_LOAD_COMMON (0x%08X)",
17403 (uint32_t)FW_MSG_CODE_DRV_LOAD_COMMON);
17405 case FW_MSG_CODE_DRV_LOAD_PORT:
17407 "DRV_LOAD_PORT (0x%08X)",
17408 (uint32_t)FW_MSG_CODE_DRV_LOAD_PORT);
17410 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
17412 "DRV_LOAD_FUNCTION (0x%08X)",
17413 (uint32_t)FW_MSG_CODE_DRV_LOAD_FUNCTION);
17415 case FW_MSG_CODE_DRV_LOAD_REFUSED:
17417 "DRV_LOAD_REFUSED (0x%08X)",
17418 (uint32_t)FW_MSG_CODE_DRV_LOAD_REFUSED);
17420 case FW_MSG_CODE_DRV_LOAD_DONE:
17422 "DRV_LOAD_DONE (0x%08X)",
17423 (uint32_t)FW_MSG_CODE_DRV_LOAD_DONE);
17425 case FW_MSG_CODE_DRV_UNLOAD_COMMON:
17427 "DRV_UNLOAD_COMMON (0x%08X)",
17428 (uint32_t)FW_MSG_CODE_DRV_UNLOAD_COMMON);
17430 case FW_MSG_CODE_DRV_UNLOAD_PORT:
17432 "DRV_UNLOAD_PORT (0x%08X)",
17433 (uint32_t)FW_MSG_CODE_DRV_UNLOAD_PORT);
17435 case FW_MSG_CODE_DRV_UNLOAD_FUNCTION:
17437 "DRV_UNLOAD_FUNCTION (0x%08X)",
17438 (uint32_t)FW_MSG_CODE_DRV_UNLOAD_FUNCTION);
17440 case FW_MSG_CODE_DRV_UNLOAD_DONE:
17442 "DRV_UNLOAD_DONE (0x%08X)",
17443 (uint32_t)FW_MSG_CODE_DRV_UNLOAD_DONE);
17445 case FW_MSG_CODE_DIAG_ENTER_DONE:
17447 "DIAG_ENTER_DONE (0x%08X)",
17448 (uint32_t)FW_MSG_CODE_DIAG_ENTER_DONE);
17450 case FW_MSG_CODE_DIAG_REFUSE:
17452 "DIAG_REFUSE (0x%08X)",
17453 (uint32_t)FW_MSG_CODE_DIAG_REFUSE);
17455 case FW_MSG_CODE_DIAG_EXIT_DONE:
17457 "DIAG_EXIT_DONE (0x%08X)",
17458 (uint32_t)FW_MSG_CODE_DIAG_EXIT_DONE);
17460 case FW_MSG_CODE_VALIDATE_KEY_SUCCESS:
17462 "VALIDATE_KEY_SUCCESS (0x%08X)",
17463 (uint32_t)FW_MSG_CODE_VALIDATE_KEY_SUCCESS);
17465 case FW_MSG_CODE_VALIDATE_KEY_FAILURE:
17467 "VALIDATE_KEY_FAILURE (0x%08X)",
17468 (uint32_t)FW_MSG_CODE_VALIDATE_KEY_FAILURE);
17470 case FW_MSG_CODE_GET_KEY_DONE:
17472 "GET_KEY_DONE (0x%08X)",
17473 (uint32_t)FW_MSG_CODE_GET_KEY_DONE);
17475 case FW_MSG_CODE_NO_KEY:
17478 (uint32_t)FW_MSG_CODE_NO_KEY);
17482 "unknown value (0x%08X)!",
17483 (fw_mb_header & FW_MSG_CODE_MASK));
17486 printf(" (seq = 0x%04X)\n", (fw_mb_header &
17487 FW_MSG_SEQ_NUMBER_MASK));
17492 * Prints a text string for the ramrod command.
17498 bxe_decode_ramrod_cmd(struct bxe_softc *sc, int command)
17500 BXE_PRINTF("Ramrod command = ");
17503 case RAMROD_CMD_ID_ETH_PORT_SETUP:
17504 printf("ETH_PORT_SETUP\n");
17506 case RAMROD_CMD_ID_ETH_CLIENT_SETUP:
17507 printf("ETH_CLIENT_SETUP\n");
17509 case RAMROD_CMD_ID_ETH_STAT_QUERY:
17510 printf("ETH_STAT_QUERY\n");
17512 case RAMROD_CMD_ID_ETH_UPDATE:
17513 printf("ETH_UPDATE\n");
17515 case RAMROD_CMD_ID_ETH_HALT:
17516 printf("ETH_HALT\n");
17518 case RAMROD_CMD_ID_ETH_SET_MAC:
17519 printf("ETH_SET_MAC\n");
17521 case RAMROD_CMD_ID_ETH_CFC_DEL:
17522 printf("ETH_CFC_DEL\n");
17524 case RAMROD_CMD_ID_ETH_PORT_DEL:
17525 printf("ETH_PORT_DEL\n");
17527 case RAMROD_CMD_ID_ETH_FORWARD_SETUP:
17528 printf("ETH_FORWARD_SETUP\n");
17531 printf("Unknown ramrod command!\n");
17537 * Prints out driver information and forces a kernel breakpoint.
17543 bxe_breakpoint(struct bxe_softc *sc)
17545 struct bxe_fastpath *fp;
17549 /* Unreachable code to silence the compiler about unused functions. */
17551 bxe_reg_read16(sc, PCICFG_OFFSET);
17552 bxe_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
17553 bxe_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
17554 bxe_dump_tx_chain(fp, 0, USABLE_TX_BD);
17555 bxe_dump_rx_cq_chain(fp, 0, USABLE_RCQ_ENTRIES);
17556 bxe_dump_rx_bd_chain(fp, 0, USABLE_RX_BD);
17557 bxe_dump_status_block(sc);
17558 bxe_dump_stats_block(sc);
17559 bxe_dump_fp_state(fp);
17560 bxe_dump_driver_state(sc);
17561 bxe_dump_hw_state(sc);
17566 * Do some device sanity checking. Run it twice in case
17567 * the hardware is still running so we can identify any
17568 * transient conditions.
17570 bxe_idle_chk(sc); bxe_idle_chk(sc);
17572 bxe_dump_driver_state(sc);
17574 for (i = 0; i < sc->num_queues; i++)
17575 bxe_dump_fp_state(&sc->fp[i]);
17577 bxe_dump_status_block(sc);
17580 /* Call the OS debugger. */