2 * Copyright (c) 2007-2011 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
38 #include <sys/systm.h>
39 #include <sys/sockio.h>
41 #include <sys/malloc.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/socket.h>
45 #include <sys/sysctl.h>
46 #include <sys/queue.h>
47 #include <sys/taskqueue.h>
51 #include <net/if_arp.h>
52 #include <net/ethernet.h>
53 #include <net/if_dl.h>
54 #include <net/if_media.h>
56 #include <net/if_types.h>
57 #include <net/if_vlan_var.h>
61 #include <netinet/in_systm.h>
62 #include <netinet/in.h>
63 #include <netinet/ip.h>
64 #include <netinet/ip6.h>
65 #include <netinet/tcp.h>
66 #include <netinet/udp.h>
68 #include <machine/resource.h>
69 #include <machine/in_cksum.h>
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
77 * Device identification definitions.
79 #define BRCM_VENDORID 0x14E4
80 #define BRCM_DEVICEID_BCM57710 0x164E
81 #define BRCM_DEVICEID_BCM57711 0x164F
82 #define BRCM_DEVICEID_BCM57711E 0x1650
84 #define PCI_ANY_ID (u_int16_t) (~0U)
95 #define STORM_ASSERT_ARRAY_SIZE 50
97 #define ATTN_NIG_FOR_FUNC (1L << 8)
98 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
99 #define GPIO_2_FUNC (1L << 10)
100 #define GPIO_3_FUNC (1L << 11)
101 #define GPIO_4_FUNC (1L << 12)
103 #define ATTN_GENERAL_ATTN_1 (1L << 13)
104 #define ATTN_GENERAL_ATTN_2 (1L << 14)
105 #define ATTN_GENERAL_ATTN_3 (1L << 15)
106 #define ATTN_GENERAL_ATTN_4 (1L << 13)
107 #define ATTN_GENERAL_ATTN_5 (1L << 14)
108 #define ATTN_GENERAL_ATTN_6 (1L << 15)
110 #define ATTN_HARD_WIRED_MASK 0xff00
114 * Convenience definitions.
116 #define BXE_CORE_LOCK_INIT(sc, name) \
117 mtx_init(&(sc->bxe_core_mtx), name, \
118 "BXE Core Lock", MTX_DEF)
119 #define BXE_SP_LOCK_INIT(sc, name) \
120 mtx_init(&(sc->bxe_sp_mtx), name, \
121 "BXE Slowpath Lock", MTX_DEF)
122 #define BXE_DMAE_LOCK_INIT(sc, name) \
123 mtx_init(&(sc->bxe_dmae_mtx), name, \
124 "BXE DMAE Lock", MTX_DEF)
125 #define BXE_PHY_LOCK_INIT(sc, name) \
126 mtx_init(&(sc->port.bxe_phy_mtx), name, \
127 "BXE PHY Lock", MTX_DEF)
128 #define BXE_FWMB_LOCK_INIT(sc, name) \
129 mtx_init(&(sc->bxe_fwmb_mtx), name, \
130 "BXE FWMB Lock", MTX_DEF)
132 #define BXE_PRINT_LOCK_INIT(sc, name) \
133 mtx_init(&(sc->bxe_print_mtx), name, \
134 "BXE PRINT Lock", MTX_DEF)
136 #define BXE_CORE_LOCK(sc) \
137 mtx_lock(&(sc->bxe_core_mtx))
138 #define BXE_SP_LOCK(sc) \
139 mtx_lock(&(sc->bxe_sp_mtx))
140 #define BXE_FP_LOCK(fp) \
142 #define BXE_DMAE_LOCK(sc) \
143 mtx_lock(&(sc->bxe_dmae_mtx))
144 #define BXE_PHY_LOCK(sc) \
145 mtx_lock(&(sc->port.bxe_phy_mtx))
146 #define BXE_FWMB_LOCK(sc) \
147 mtx_lock(&(sc->bxe_fwmb_mtx))
149 #define BXE_PRINT_LOCK(sc) \
150 mtx_lock(&(sc->bxe_print_mtx))
152 #define BXE_CORE_LOCK_ASSERT(sc) \
153 mtx_assert(&(sc->bxe_core_mtx), MA_OWNED)
154 #define BXE_SP_LOCK_ASSERT(sc) \
155 mtx_assert(&(sc->bxe_sp_mtx), MA_OWNED)
156 #define BXE_FP_LOCK_ASSERT(fp) \
157 mtx_assert(&(fp->mtx), MA_OWNED)
158 #define BXE_DMAE_LOCK_ASSERT(sc) \
159 mtx_assert(&(sc->bxe_dmae_mtx), MA_OWNED)
160 #define BXE_PHY_LOCK_ASSERT(sc) \
161 mtx_assert(&(sc->port.bxe_phy_mtx), MA_OWNED)
163 #define BXE_CORE_UNLOCK(sc) \
164 mtx_unlock(&(sc->bxe_core_mtx))
165 #define BXE_SP_UNLOCK(sc) \
166 mtx_unlock(&(sc->bxe_sp_mtx))
167 #define BXE_FP_UNLOCK(fp) \
168 mtx_unlock(&(fp->mtx))
169 #define BXE_DMAE_UNLOCK(sc) \
170 mtx_unlock(&(sc->bxe_dmae_mtx))
171 #define BXE_PHY_UNLOCK(sc) \
172 mtx_unlock(&(sc->port.bxe_phy_mtx))
173 #define BXE_FWMB_UNLOCK(sc) \
174 mtx_unlock(&(sc->bxe_fwmb_mtx))
176 #define BXE_PRINT_UNLOCK(sc) \
177 mtx_unlock(&(sc->bxe_print_mtx))
179 #define BXE_CORE_LOCK_DESTROY(sc) \
180 if (mtx_initialized(&(sc->bxe_core_mtx))) { \
181 mtx_destroy(&(sc->bxe_core_mtx)); \
183 #define BXE_SP_LOCK_DESTROY(sc) \
184 if (mtx_initialized(&(sc->bxe_sp_mtx))) { \
185 mtx_destroy(&(sc->bxe_sp_mtx)); \
187 #define BXE_DMAE_LOCK_DESTROY(sc) \
188 if (mtx_initialized(&(sc->bxe_dmae_mtx))) { \
189 mtx_destroy(&(sc->bxe_dmae_mtx)); \
191 #define BXE_PHY_LOCK_DESTROY(sc) \
192 if (mtx_initialized(&(sc->port.bxe_phy_mtx))) { \
193 mtx_destroy(&(sc->port.bxe_phy_mtx)); \
196 #define BXE_FWMB_LOCK_DESTROY(sc) \
197 if (mtx_initialized(&(sc->bxe_fwmb_mtx))) { \
198 mtx_destroy(&(sc->bxe_fwmb_mtx)); \
201 #define BXE_PRINT_LOCK_DESTROY(sc) \
202 if (mtx_initialized(&(sc->bxe_print_mtx))) { \
203 mtx_destroy(&(sc->bxe_print_mtx)); \
206 /* Must be used on a CID before placing it on a HW chain. */
207 #define HW_CID(sc, x) \
208 ((BP_PORT(sc) << 23) | (BP_E1HVN(sc) << 17) | x)
210 /* Used on a CID received from the HW. */
212 (le32toh(x) & (COMMON_RAMROD_ETH_RX_CQE_CID >> 7))
215 (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
217 #define DPM_TRIGGER_TYPE 0x40
218 #define DOORBELL(sc, cid, val) do{ \
219 bus_space_write_4(sc->bxe_db_btag, sc->bxe_db_bhandle, \
220 ((BCM_PAGE_SIZE * (cid)) + DPM_TRIGGER_TYPE), (uint32_t)val); \
223 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
224 /* Define the macro based on whether CPU is 32 or 64 bit. */
225 #define U64_LO(y) ((uint64_t) (y) & 0xFFFFFFFF)
226 #define U64_HI(y) ((uint64_t) (y) >> 32)
228 #define U64_LO(y) ((uint32_t)y)
229 #define U64_HI(y) (0)
232 #define HILO_U64(hi, lo) (((uint64_t)hi << 32) + lo)
234 #define BXE_HAS_WORK(fp) \
235 (bxe_has_rx_work(fp) || bxe_has_tx_work(fp))
237 /* Define the page size of the host CPU. */
238 #define BCM_PAGE_SHIFT 12
239 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
240 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
241 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
243 #if BCM_PAGE_SIZE != 4096
244 #error Page sizes other than 4KB not currently supported!
248 #define PAGES_PER_SGE_SHIFT 0
249 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
250 #define SGE_PAGE_SIZE PAGE_SIZE
251 #define SGE_PAGE_SHIFT PAGE_SHIFT
252 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN(addr)
254 /* NUM_RX_SGE_PAGES must be a power of 2. */
255 #define NUM_RX_SGE_PAGES 2
256 #define TOTAL_RX_SGE_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) /* 512 */
257 #define USABLE_RX_SGE_PER_PAGE (TOTAL_RX_SGE_PER_PAGE - 2) /* 510 */
258 #define RX_SGE_PER_PAGE_MASK (TOTAL_RX_SGE_PER_PAGE - 1) /* 511 */
259 #define TOTAL_RX_SGE (TOTAL_RX_SGE_PER_PAGE * NUM_RX_SGE_PAGES) /* 1024 */
260 #define USABLE_RX_SGE (USABLE_RX_SGE_PER_PAGE * NUM_RX_SGE_PAGES) /* 1020 */
261 #define MAX_RX_SGE (TOTAL_RX_SGE - 1) /* 1023 */
264 #define NEXT_SGE_IDX(x) \
265 ((((x) & RX_SGE_PER_PAGE_MASK) == (USABLE_RX_SGE_PER_PAGE - 1)) \
267 #define RX_SGE(x) ((x) & MAX_RX_SGE)
268 #define RX_SGE_PAGE(x) (((x) & ~RX_SGE_PER_PAGE_MASK) >> 9)
269 #define RX_SGE_IDX(x) ((x) & RX_SGE_PER_PAGE_MASK)
271 /* SGE producer mask related macros. */
272 /* Number of bits in one sge_mask array element. */
273 #define RX_SGE_MASK_ELEM_SZ 64
274 #define RX_SGE_MASK_ELEM_SHIFT 6
275 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
278 * Creates a bitmask of all ones in less significant bits.
279 * idx - index of the most significant bit in the created mask.
281 #define RX_SGE_ONES_MASK(idx) \
282 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
283 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
285 /* Number of uint64_t elements in SGE mask array. */
286 #define RX_SGE_MASK_LEN \
287 ((NUM_RX_SGE_PAGES * TOTAL_RX_SGE_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
288 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
289 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
293 * Transmit Buffer Descriptor (tx_bd) definitions*
296 /* NUM_TX_PAGES must be a power of 2. */
297 #define NUM_TX_PAGES 1
298 #define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) /* 256 */
299 #define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1) /* 255 */
300 #define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * NUM_TX_PAGES) /* 512 */
301 #define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * NUM_TX_PAGES) /* 510 */
302 #define MAX_TX_BD (TOTAL_TX_BD - 1) /* 511 */
304 #define NEXT_TX_BD(x) \
305 ((((x) & USABLE_TX_BD_PER_PAGE) == \
306 (USABLE_TX_BD_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
307 #define TX_BD(x) ((x) & MAX_TX_BD)
308 #define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
309 #define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
312 * Receive Buffer Descriptor (rx_bd) definitions*
315 /* NUM_RX_PAGES must be a power of 2. */
316 #define NUM_RX_PAGES 1
317 #define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) /* 512 */
318 #define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 2) /* 510 */
319 #define RX_BD_PER_PAGE_MASK (TOTAL_RX_BD_PER_PAGE - 1) /* 511 */
320 #define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * NUM_RX_PAGES) /* 1024 */
321 #define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * NUM_RX_PAGES) /* 1020 */
322 #define MAX_RX_BD (TOTAL_RX_BD - 1) /* 1023 */
324 #define NEXT_RX_BD(x) \
325 ((((x) & RX_BD_PER_PAGE_MASK) == \
326 (USABLE_RX_BD_PER_PAGE - 1)) ? (x) + 3 : (x) + 1)
328 #define RX_BD(x) ((x) & MAX_RX_BD)
329 #define RX_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
330 #define RX_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
333 * Receive Completion Queue definitions*
335 #define NUM_RCQ_PAGES (NUM_RX_PAGES * 4)
336 #define TOTAL_RCQ_ENTRIES_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) /* 128 */
337 #define USABLE_RCQ_ENTRIES_PER_PAGE (TOTAL_RCQ_ENTRIES_PER_PAGE - 1) /* 127 */
338 #define TOTAL_RCQ_ENTRIES (TOTAL_RCQ_ENTRIES_PER_PAGE * NUM_RCQ_PAGES) /* 1024 */
339 #define USABLE_RCQ_ENTRIES (USABLE_RCQ_ENTRIES_PER_PAGE * NUM_RCQ_PAGES) /* 1016 */
340 #define MAX_RCQ_ENTRIES (TOTAL_RCQ_ENTRIES - 1) /* 1023 */
342 #define NEXT_RCQ_IDX(x) \
343 ((((x) & USABLE_RCQ_ENTRIES_PER_PAGE) == \
344 (USABLE_RCQ_ENTRIES_PER_PAGE - 1)) ? (x) + 2 : (x) + 1)
345 #define RCQ_ENTRY(x) ((x) & MAX_RCQ_ENTRIES)
346 #define RCQ_PAGE(x) (((x) & ~USABLE_RCQ_ENTRIES_PER_PAGE) >> 7)
347 #define RCQ_IDX(x) ((x) & USABLE_RCQ_ENTRIES_PER_PAGE)
349 /* Slowpath Queue definitions. */
350 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
351 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
352 #define NEXT_SPE(x) (((x) + 1 == (MAX_SP_DESC_CNT)) ? 0 : (x) + 1)
354 /* This is needed for determening of last_max */
355 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
357 #define __SGE_MASK_SET_BIT(el, bit) do { \
358 el = ((el) | ((uint64_t)0x1 << (bit))); \
361 #define __SGE_MASK_CLEAR_BIT(el, bit) do { \
362 el = ((el) & (~((uint64_t)0x1 << (bit)))); \
365 #define SGE_MASK_SET_BIT(fp, idx) \
366 __SGE_MASK_SET_BIT(fp->rx_sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
367 ((idx) & RX_SGE_MASK_ELEM_MASK))
369 #define SGE_MASK_CLEAR_BIT(fp, idx) \
370 __SGE_MASK_CLEAR_BIT(fp->rx_sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
371 ((idx) & RX_SGE_MASK_ELEM_MASK))
373 #define BXE_TX_TIMEOUT 5
374 #define BXE_TX_CLEANUP_THRESHOLD ((USABLE_TX_BD * 7 ) / 8)
376 #define BXE_DMA_ALIGN 8
377 #define BXE_DMA_BOUNDARY 0
379 /* ToDo: Need to verify the following 3 values. */
381 /* Reduce from 13 to leave room for the parsing buffer. */
382 #define BXE_MAX_SEGMENTS 12
383 #define BXE_TSO_MAX_SEGMENTS 32
384 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
385 #define BXE_TSO_MAX_SEG_SIZE 4096
388 * Hardware Support For IP and TCP checksum.
389 * (Per packet hardware assist capabilites, derived.
390 * from CSUM_* in sys/mbuf.h).
392 #define BXE_IF_HWASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_TSO)
395 * Per interface capabilities.
397 * ToDo: Consider adding IFCAP_WOL_MAGIC, IFCAP_TOE4,
398 * IFCAP_TSO6, IFCAP_WOL_UCAST.
400 #if __FreeBSD_version < 700000
401 #define BXE_IF_CAPABILITIES \
402 (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | \
405 /* TSO/LRO was introduced in FreeBSD 7 */
406 #define BXE_IF_CAPABILITIES \
407 (IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | IFCAP_HWCSUM | \
408 IFCAP_JUMBO_MTU | IFCAP_TSO4 | IFCAP_VLAN_HWCSUM | IFCAP_LRO)
411 /* Some typical Ethernet frame sizes */
412 #define BXE_MIN_MTU 60
413 #define BXE_MIN_ETHER_MTU 64
415 #define BXE_STD_MTU 1500
416 #define BXE_STD_ETHER_MTU 1518
417 #define BXE_STD_ETHER_MTU_VLAN 1522
419 #define BXE_JUMBO_MTU 9000
420 #define BXE_JUMBO_ETHER_MTU 9018
421 #define BXE_JUMBO_ETHER_MTU_VLAN 9022
424 #define MAX_SPQ_PENDING 8
426 /* Derived E1HVN constants for rate shaping. */
427 #define DEF_MIN_RATE 100
429 /* Resolution of the rate shaping timer - 100 usec */
430 #define RS_PERIODIC_TIMEOUT_USEC 100
432 #define BXE_MBUF_ALLOC_RETRY_COUNT 10
433 #define BXE_MBUF_MAPPING_RETRY_COUNT 10
434 #define BXE_MBUF_RETRY_DELAY 100
437 * Resolution of fairness algorithm, in usecs.
438 * Coefficient for calculating the actual t_fair.
440 #define T_FAIR_COEF 10000000
443 * Number of bytes in single QM arbitration cycle.
444 * Coefficient for calculating the fairness timer.
446 #define QM_ARB_BYTES 40000
449 #define MIN_BXE_BC_VER 0x00040200
451 #define BXE_BR_SIZE 4096
453 #define BXE_NO_RX_FLAGS \
454 (TSTORM_ETH_DROP_FLAGS_DROP_ALL_PACKETS)
456 #define BXE_NORMAL_RX_FLAGS \
457 (TSTORM_ETH_DROP_FLAGS_DROP_TCP_CS_ERROR_FLG | \
458 TSTORM_ETH_DROP_FLAGS_DROP_IP_CS_ERROR_FLG | \
459 TSTORM_ETH_DROP_FLAGS_DONT_DROP_MAC_ERR_FLG | \
460 TSTORM_ETH_DROP_FLAGS_DROP_TOO_BIG_PACKETS | \
461 TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_UNICAST | \
462 TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_MULTICAST | \
463 TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
465 #define BXE_ALLMULTI_RX_FLAGS \
466 (TSTORM_ETH_DROP_FLAGS_DROP_TCP_CS_ERROR_FLG | \
467 TSTORM_ETH_DROP_FLAGS_DROP_IP_CS_ERROR_FLG | \
468 TSTORM_ETH_DROP_FLAGS_DONT_DROP_MAC_ERR_FLG | \
469 TSTORM_ETH_DROP_FLAGS_DROP_TOO_BIG_PACKETS | \
470 TSTORM_ETH_DROP_FLAGS_DROP_UNMATCH_UNICAST | \
471 TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
473 #define BXE_PROMISC_RX_FLAGS \
474 (TSTORM_ETH_DROP_FLAGS_DONT_DROP_TTL0_FLG)
479 * External definitions.
481 /* FreeBSD multip proc number of active cpus on the system. */
484 #define MAX_DYNAMIC_ATTN_GRPS 8
486 #define MAC_STX_NA 0xffffffff
488 /* Attention group wiring. */
499 uint32_t brb_discard;
501 uint32_t brb_truncate;
502 uint32_t flow_ctrl_discard;
503 uint32_t flow_ctrl_octets;
504 uint32_t flow_ctrl_packet;
505 uint32_t mng_discard;
506 uint32_t mng_octet_inp;
507 uint32_t mng_octet_out;
508 uint32_t mng_packet_inp;
509 uint32_t mng_packet_out;
513 uint32_t egress_mac_pkt0_lo;
514 uint32_t egress_mac_pkt0_hi;
515 uint32_t egress_mac_pkt1_lo;
516 uint32_t egress_mac_pkt1_hi;
519 enum bxe_stats_event {
527 enum bxe_stats_state {
528 STATS_STATE_DISABLED = 0,
533 /* Statistics for an Ethernet port. */
534 struct bxe_port_stats {
535 uint32_t total_bytes_received_hi;
536 uint32_t total_bytes_received_lo;
537 uint32_t total_bytes_transmitted_hi;
538 uint32_t total_bytes_transmitted_lo;
539 uint32_t total_unicast_packets_received_hi;
540 uint32_t total_unicast_packets_received_lo;
541 uint32_t total_multicast_packets_received_hi;
542 uint32_t total_multicast_packets_received_lo;
543 uint32_t total_broadcast_packets_received_hi;
544 uint32_t total_broadcast_packets_received_lo;
545 uint32_t total_unicast_packets_transmitted_hi;
546 uint32_t total_unicast_packets_transmitted_lo;
547 uint32_t total_multicast_packets_transmitted_hi;
548 uint32_t total_multicast_packets_transmitted_lo;
549 uint32_t total_broadcast_packets_transmitted_hi;
550 uint32_t total_broadcast_packets_transmitted_lo;
551 uint32_t valid_bytes_received_hi;
552 uint32_t valid_bytes_received_lo;
553 uint32_t error_bytes_received_hi;
554 uint32_t error_bytes_received_lo;
555 uint32_t etherstatsoverrsizepkts_hi;
556 uint32_t etherstatsoverrsizepkts_lo;
557 uint32_t no_buff_discard_hi;
558 uint32_t no_buff_discard_lo;
560 /* Layout must match struct mac_stx. */
561 uint32_t rx_stat_ifhcinbadoctets_hi;
562 uint32_t rx_stat_ifhcinbadoctets_lo;
563 uint32_t tx_stat_ifhcoutbadoctets_hi;
564 uint32_t tx_stat_ifhcoutbadoctets_lo;
565 uint32_t rx_stat_dot3statsfcserrors_hi;
566 uint32_t rx_stat_dot3statsfcserrors_lo;
567 uint32_t rx_stat_dot3statsalignmenterrors_hi;
568 uint32_t rx_stat_dot3statsalignmenterrors_lo;
569 uint32_t rx_stat_dot3statscarriersenseerrors_hi;
570 uint32_t rx_stat_dot3statscarriersenseerrors_lo;
571 uint32_t rx_stat_falsecarriererrors_hi;
572 uint32_t rx_stat_falsecarriererrors_lo;
573 uint32_t rx_stat_etherstatsundersizepkts_hi;
574 uint32_t rx_stat_etherstatsundersizepkts_lo;
575 uint32_t rx_stat_dot3statsframestoolong_hi;
576 uint32_t rx_stat_dot3statsframestoolong_lo;
577 uint32_t rx_stat_etherstatsfragments_hi;
578 uint32_t rx_stat_etherstatsfragments_lo;
579 uint32_t rx_stat_etherstatsjabbers_hi;
580 uint32_t rx_stat_etherstatsjabbers_lo;
581 uint32_t rx_stat_maccontrolframesreceived_hi;
582 uint32_t rx_stat_maccontrolframesreceived_lo;
583 uint32_t rx_stat_bmac_xpf_hi;
584 uint32_t rx_stat_bmac_xpf_lo;
585 uint32_t rx_stat_bmac_xcf_hi;
586 uint32_t rx_stat_bmac_xcf_lo;
587 uint32_t rx_stat_xoffstateentered_hi;
588 uint32_t rx_stat_xoffstateentered_lo;
589 uint32_t rx_stat_xonpauseframesreceived_hi;
590 uint32_t rx_stat_xonpauseframesreceived_lo;
591 uint32_t rx_stat_xoffpauseframesreceived_hi;
592 uint32_t rx_stat_xoffpauseframesreceived_lo;
593 uint32_t tx_stat_outxonsent_hi;
594 uint32_t tx_stat_outxonsent_lo;
595 uint32_t tx_stat_outxoffsent_hi;
596 uint32_t tx_stat_outxoffsent_lo;
597 uint32_t tx_stat_flowcontroldone_hi;
598 uint32_t tx_stat_flowcontroldone_lo;
599 uint32_t tx_stat_etherstatscollisions_hi;
600 uint32_t tx_stat_etherstatscollisions_lo;
601 uint32_t tx_stat_dot3statssinglecollisionframes_hi;
602 uint32_t tx_stat_dot3statssinglecollisionframes_lo;
603 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
604 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
605 uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
606 uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
607 uint32_t tx_stat_dot3statsexcessivecollisions_hi;
608 uint32_t tx_stat_dot3statsexcessivecollisions_lo;
609 uint32_t tx_stat_dot3statslatecollisions_hi;
610 uint32_t tx_stat_dot3statslatecollisions_lo;
611 uint32_t tx_stat_etherstatspkts64octets_hi;
612 uint32_t tx_stat_etherstatspkts64octets_lo;
613 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
614 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
615 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
616 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
617 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
618 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
619 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
620 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
621 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
622 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
623 uint32_t tx_stat_etherstatspktsover1522octets_hi;
624 uint32_t tx_stat_etherstatspktsover1522octets_lo;
625 uint32_t tx_stat_bmac_2047_hi;
626 uint32_t tx_stat_bmac_2047_lo;
627 uint32_t tx_stat_bmac_4095_hi;
628 uint32_t tx_stat_bmac_4095_lo;
629 uint32_t tx_stat_bmac_9216_hi;
630 uint32_t tx_stat_bmac_9216_lo;
631 uint32_t tx_stat_bmac_16383_hi;
632 uint32_t tx_stat_bmac_16383_lo;
633 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
634 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
635 uint32_t tx_stat_bmac_ufl_hi;
636 uint32_t tx_stat_bmac_ufl_lo;
637 /* End of mac_stx. */
639 uint32_t pause_frames_received_hi;
640 uint32_t pause_frames_received_lo;
641 uint32_t pause_frames_sent_hi;
642 uint32_t pause_frames_sent_lo;
643 uint32_t etherstatspkts1024octetsto1522octets_hi;
644 uint32_t etherstatspkts1024octetsto1522octets_lo;
645 uint32_t etherstatspktsover1522octets_hi;
646 uint32_t etherstatspktsover1522octets_lo;
647 uint32_t brb_drop_hi;
648 uint32_t brb_drop_lo;
649 uint32_t brb_truncate_hi;
650 uint32_t brb_truncate_lo;
651 uint32_t mac_filter_discard;
652 uint32_t xxoverflow_discard;
653 uint32_t brb_truncate_discard;
654 uint32_t mac_discard;
655 uint32_t driver_xoff;
656 uint32_t rx_err_discard_pkt;
657 uint32_t rx_skb_alloc_failed;
658 uint32_t hw_csum_err;
659 uint32_t nig_timer_max;
662 #define STATS_OFFSET32(stat_name) \
663 (offsetof(struct bxe_port_stats, stat_name) / 4)
665 #define MAX_CONTEXT 16
668 struct eth_context eth;
672 /* Load/unload mode. */
673 #define LOAD_NORMAL 0
676 #define UNLOAD_NORMAL 0
677 #define UNLOAD_CLOSE 1
679 #define BXE_MAX_POLL_COUNT 1024
686 * Common data structure.
687 * This information is shared across all ports and functions.
691 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
692 #define CHIP_ID(sc) (sc->common.chip_id & 0xfffffff0)
693 #define CHIP_NUM(sc) (sc->common.chip_id >> 16)
694 #define CHIP_NUM_57710 0x164e
695 #define CHIP_NUM_57711 0x164f
696 #define CHIP_NUM_57711E 0x1650
697 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
698 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
699 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
700 #define CHIP_IS_E1H(sc) (CHIP_IS_57711(sc) || CHIP_IS_57711E(sc))
701 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc))
702 #define IS_E1H_OFFSET CHIP_IS_E1H(sc)
704 #define CHIP_REV(sc) ((sc->common.chip_id) & 0x0000f000)
705 #define CHIP_REV_Ax 0x00000000
706 #define CHIP_REV_Bx 0x00001000
707 #define CHIP_REV_Cx 0x00002000
709 #define CHIP_METAL(sc) ((sc->common.chip_id) & 0x00000ff0)
710 #define CHIP_BOND_ID(sc) ((sc->common.chip_id) & 0x0000000f)
713 #define NVRAM_1MB_SIZE 0x20000
714 #define NVRAM_TIMEOUT_COUNT 30000
715 #define NVRAM_PAGE_SIZE 256
717 /* Bootcode shared memory address in BAR memory. */
719 uint32_t shmem2_base;
721 /* Device configuration read from bootcode shared memory. */
725 }; /* End struct bxe_common */
728 * Port specifc data structure.
732 * Port Management Function (for 57711E only).
733 * When this field is set the driver instance is
734 * responsible for managing port specifc
735 * configurations such as handling link attentions.
739 /* Ethernet maximum transmission unit. */
742 uint32_t link_config;
744 /* Defines the features supported by the PHY. */
746 #define SUPPORTED_10baseT_Half (1 << 1)
747 #define SUPPORTED_10baseT_Full (1 << 2)
748 #define SUPPORTED_100baseT_Half (1 << 3)
749 #define SUPPORTED_100baseT_Full (1 << 4)
750 #define SUPPORTED_1000baseT_Half (1 << 5)
751 #define SUPPORTED_1000baseT_Full (1 << 6)
752 #define SUPPORTED_TP (1 << 7)
753 #define SUPPORTED_FIBRE (1 << 8)
754 #define SUPPORTED_Autoneg (1 << 9)
755 #define SUPPORTED_Asym_Pause (1 << 10)
756 #define SUPPORTED_Pause (1 << 11)
757 #define SUPPORTED_2500baseX_Full (1 << 15)
758 #define SUPPORTED_10000baseT_Full (1 << 16)
760 /* Defines the features advertised by the PHY. */
761 uint32_t advertising;
762 #define ADVERTISED_10baseT_Half (1 << 1)
763 #define ADVERTISED_10baseT_Full (1 << 2)
764 #define ADVERTISED_100baseT_Half (1 << 3)
765 #define ADVERTISED_100baseT_Full (1 << 4)
766 #define ADVERTISED_1000baseT_Half (1 << 5)
767 #define ADVERTISED_1000baseT_Full (1 << 6)
768 #define ADVERTISED_TP (1 << 7)
769 #define ADVERTISED_FIBRE (1 << 8)
770 #define ADVERTISED_Autoneg (1 << 9)
771 #define ADVERTISED_Asym_Pause (1 << 10)
772 #define ADVERTISED_Pause (1 << 11)
773 #define ADVERTISED_2500baseX_Full (1 << 15)
774 #define ADVERTISED_10000baseT_Full (1 << 16)
778 /* Used to synchronize phy accesses. */
779 struct mtx bxe_phy_mtx;
782 * MCP scratchpad address for port specific statistics.
783 * The device is responsible for writing statistcss
784 * back to the MCP for use with management firmware such
789 struct nig_stats old_nig_stats;
790 }; /* End struct bxe_port */
792 /* DMAE command defines */
793 #define DMAE_CMD_SRC_PCI 0
794 #define DMAE_CMD_SRC_GRC DMAE_COMMAND_SRC
796 #define DMAE_CMD_DST_PCI (1 << DMAE_COMMAND_DST_SHIFT)
797 #define DMAE_CMD_DST_GRC (2 << DMAE_COMMAND_DST_SHIFT)
799 #define DMAE_CMD_C_DST_PCI 0
800 #define DMAE_CMD_C_DST_GRC (1 << DMAE_COMMAND_C_DST_SHIFT)
802 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
804 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
805 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
806 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
807 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
809 #define DMAE_CMD_PORT_0 0
810 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
812 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
813 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
814 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
816 #define DMAE_LEN32_RD_MAX 0x80
817 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
819 #define DMAE_COMP_VAL 0xe0d0d0ae
822 #define MAX_DMAE_C_PER_PORT 8
824 #define INIT_DMAE_C(sc) \
825 (BP_PORT(sc) * MAX_DMAE_C_PER_PORT + BP_E1HVN(sc))
826 #define PMF_DMAE_C(sc) \
827 (BP_PORT(sc) * MAX_DMAE_C_PER_PORT + E1HVN_MAX)
830 /* Used to manage DMA allocations. */
836 bus_dma_segment_t seg;
842 * This is the slowpath data structure. It is mapped into non-paged memory
843 * so that the hardware can access it's contents directly and must be page
846 struct bxe_slowpath {
848 * The cdu_context array MUST be the first element in this
849 * structure. It is used during the leading edge ramrod
852 union cdu_context context[MAX_CONTEXT];
854 struct eth_stats_query fw_stats;
856 /* Used as a DMA source for MAC configuration. */
857 struct mac_configuration_cmd mac_config;
858 struct mac_configuration_cmd mcast_config;
860 /* Used by the DMAE command executer. */
861 struct dmae_command dmae[MAX_DMAE_C];
863 /* Statistics completion. */
866 /* Firmware defined statistics blocks. */
867 union mac_stats mac_stats;
868 struct nig_stats nig_stats;
869 struct host_port_stats port_stats;
870 struct host_func_stats func_stats;
871 struct host_func_stats func_stats_base;
873 /* DMAE completion value. */
875 #define BXE_WB_COMP_VAL 0xe0d0d0ae
877 /* DMAE data source/sink. */
879 }; /* End struct bxe_slowpath */
881 #define BXE_SP(sc, var) (&sc->slowpath->var)
882 #define BXE_SP_CHECK(sc, var) ((sc->slowpath) ? (&sc->slowpath->var) : NULL)
883 #define BXE_SP_MAPPING(sc, var) \
884 (sc->slowpath_dma.paddr + offsetof(struct bxe_slowpath, var))
887 struct doorbell_set_prod data;
892 uint32_t total_bytes_received_hi;
893 uint32_t total_bytes_received_lo;
894 uint32_t total_bytes_transmitted_hi;
895 uint32_t total_bytes_transmitted_lo;
896 uint32_t total_unicast_packets_received_hi;
897 uint32_t total_unicast_packets_received_lo;
898 uint32_t total_multicast_packets_received_hi;
899 uint32_t total_multicast_packets_received_lo;
900 uint32_t total_broadcast_packets_received_hi;
901 uint32_t total_broadcast_packets_received_lo;
902 uint32_t total_unicast_packets_transmitted_hi;
903 uint32_t total_unicast_packets_transmitted_lo;
904 uint32_t total_multicast_packets_transmitted_hi;
905 uint32_t total_multicast_packets_transmitted_lo;
906 uint32_t total_broadcast_packets_transmitted_hi;
907 uint32_t total_broadcast_packets_transmitted_lo;
908 uint32_t valid_bytes_received_hi;
909 uint32_t valid_bytes_received_lo;
910 uint32_t error_bytes_received_hi;
911 uint32_t error_bytes_received_lo;
912 uint32_t etherstatsoverrsizepkts_hi;
913 uint32_t etherstatsoverrsizepkts_lo;
914 uint32_t no_buff_discard_hi;
915 uint32_t no_buff_discard_lo;
916 uint32_t driver_xoff;
917 uint32_t rx_err_discard_pkt;
918 uint32_t rx_skb_alloc_failed;
919 uint32_t hw_csum_err;
923 * This is the fastpath data structure. There can be up to MAX_CONTEXT
924 * instances of the fastpath structure when using RSS/multi-queue.
926 struct bxe_fastpath {
927 /* Pointer back to parent structure. */
928 struct bxe_softc *sc;
934 struct bxe_dma sb_dma;
935 struct host_status_block *status_block;
937 /* Transmit chain. */
938 struct bxe_dma tx_dma;
939 union eth_tx_bd_types *tx_chain;
942 struct bxe_dma rx_dma;
943 struct eth_rx_bd *rx_chain;
945 /* Receive completion queue chain. */
946 struct bxe_dma rcq_dma;
947 union eth_rx_cqe *rcq_chain;
949 /* Bus resource tag, map, and mbufs for TX chain. */
950 bus_dma_tag_t tx_mbuf_tag;
951 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
952 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];
954 /* Bus resource tag, map, and mbufs for RX chain. */
955 bus_dma_tag_t rx_mbuf_tag;
956 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
957 bus_dmamap_t rx_mbuf_spare_map;
958 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
960 /* Ticks until chip reset. */
963 /* Taskqueue reqources. */
965 struct taskqueue *tq;
967 /* Fastpath state. */
968 /* ToDo: Why use 'int' here, why not 'uint32_t'? */
970 #define BXE_FP_STATE_CLOSED 0x00000
971 #define BXE_FP_STATE_IRQ 0x80000
972 #define BXE_FP_STATE_OPENING 0x90000
973 #define BXE_FP_STATE_OPEN 0xa0000
974 #define BXE_FP_STATE_HALTING 0xb0000
975 #define BXE_FP_STATE_HALTED 0xc0000
977 /* Self-reference back to this fastpath's queue number. */
979 #define FP_IDX(fp) (fp->index)
981 /* Ethernet client ID (each fastpath set of RX/TX/CQE is a client). */
983 #define BP_CL_ID(sc) (sc->fp[0].cl_id)
985 /* Status block number in hardware. */
987 #define FP_SB_ID(fp) (fp->sb_id)
989 /* Class of service. */
994 /* Transmit packet producer index (used in eth_tx_bd). */
995 uint16_t tx_pkt_prod;
996 uint16_t tx_pkt_cons;
998 /* Transmit buffer descriptor prod/cons indices. */
1000 uint16_t tx_bd_cons;
1002 /* Driver's copy of the fastpath CSTORM/USTORM indices. */
1006 /* Driver's copy of the receive buffer descriptor prod/cons indices. */
1007 uint16_t rx_bd_prod;
1008 uint16_t rx_bd_cons;
1010 /* Driver's copy of the receive completion queue prod/cons indices. */
1011 uint16_t rx_cq_prod;
1012 uint16_t rx_cq_cons;
1014 /* Pointer to the receive consumer index in the status block. */
1015 uint16_t *rx_cq_cons_sb;
1018 * Pointer to the receive buffer descriptor consumer in the
1021 uint16_t *rx_bd_cons_sb;
1023 /* Pointer to the transmit consumer in the status block. */
1024 uint16_t *tx_pkt_cons_sb;
1026 /* Used TX buffer descriptor counters. */
1027 uint16_t tx_bd_used;
1029 /* Begin: TPA Related data structure. */
1031 struct bxe_dma sg_dma;
1032 struct eth_rx_sge *sg_chain;
1034 /* Bus tag for RX SGE bufs. */
1035 bus_dma_tag_t rx_sge_buf_tag;
1036 bus_dmamap_t rx_sge_buf_map[TOTAL_RX_SGE];
1037 bus_dmamap_t rx_sge_spare_map;
1038 struct mbuf *rx_sge_buf_ptr[TOTAL_RX_SGE];
1041 * Bitmask for each SGE element indicating which
1042 * aggregation that element is a part of.
1044 uint64_t rx_sge_mask[RX_SGE_MASK_LEN];
1045 uint16_t rx_sge_prod;
1047 /* The last maximal completed SGE. */
1048 uint16_t last_max_sge;
1050 uint16_t rx_sge_free_idx;
1052 /* Use the larger supported size for TPA queue length. */
1053 bus_dmamap_t tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H];
1054 bus_dmamap_t tpa_mbuf_spare_map;
1055 struct mbuf *tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H];
1056 bus_dma_segment_t tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H];
1058 uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H];
1059 #define BXE_TPA_STATE_START 1
1060 #define BXE_TPA_STATE_STOP 2
1063 uint8_t disable_tpa;
1064 /* End: TPA related data structure. */
1066 struct tstorm_per_client_stats old_tclient;
1067 struct ustorm_per_client_stats old_uclient;
1068 struct xstorm_per_client_stats old_xclient;
1069 struct bxe_q_stats eth_q_stats;
1071 #if __FreeBSD_version >= 800000
1072 struct buf_ring *br;
1075 /* Receive path driver statistics. */
1076 unsigned long rx_pkts;
1077 unsigned long rx_tpa_pkts;
1078 unsigned long rx_null_cqe_flags;
1079 unsigned long rx_soft_errors;
1081 /* Transmit path driver statistics. */
1082 unsigned long tx_pkts;
1083 unsigned long tx_soft_errors;
1084 unsigned long tx_offload_frames_csum_ip;
1085 unsigned long tx_offload_frames_csum_tcp;
1086 unsigned long tx_offload_frames_csum_udp;
1087 unsigned long tx_offload_frames_tso;
1088 unsigned long tx_header_splits;
1089 unsigned long tx_encap_failures;
1090 unsigned long tx_hw_queue_full;
1091 unsigned long tx_hw_max_queue_depth;
1092 unsigned long tx_dma_mapping_failure;
1093 int tx_max_drbr_queue_depth;
1094 unsigned long tx_window_violation_std;
1095 unsigned long tx_window_violation_tso;
1096 unsigned long tx_unsupported_tso_request_ipv6;
1097 unsigned long tx_unsupported_tso_request_not_tcp;
1098 unsigned long tx_chain_lost_mbuf;
1099 unsigned long tx_frame_deferred;
1100 unsigned long tx_queue_xoff;
1102 /* Memory path driver statistics. */
1103 unsigned long mbuf_defrag_attempts;
1104 unsigned long mbuf_defrag_failures;
1105 unsigned long mbuf_rx_bd_alloc_failed;
1106 unsigned long mbuf_rx_bd_mapping_failed;
1107 unsigned long mbuf_tpa_alloc_failed;
1108 unsigned long mbuf_tpa_mapping_failed;
1109 unsigned long mbuf_sge_alloc_failed;
1110 unsigned long mbuf_sge_mapping_failed;
1112 /* Track the number of enqueued mbufs. */
1118 uint64_t tpa_queue_used;
1120 /* FreeBSD interface statistics. */
1121 unsigned long ipackets;
1122 unsigned long opackets;
1124 }; /* bxe_fastpath */
1127 * BXE Device State Data Structure
1129 #define BXE_STATUS_BLK_SZ \
1130 sizeof(struct host_status_block) /* +sizeof(struct eth_tx_db_data) */
1131 #define BXE_DEF_STATUS_BLK_SZ sizeof(struct host_def_status_block)
1132 #define BXE_STATS_BLK_SZ sizeof(struct bxe_port_stats)
1133 #define BXE_SLOWPATH_SZ sizeof(struct bxe_slowpath)
1134 #define BXE_SPQ_SZ BCM_PAGE_SIZE
1135 #define BXE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
1136 #define BXE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
1139 struct ifnet *bxe_ifp;
1142 /* Parent device handle. */
1145 /* Driver instance number. */
1148 /* FreeBSD network interface media structure. */
1149 struct ifmedia bxe_ifmedia;
1151 /* Bus tag for the bxe controller. */
1152 bus_dma_tag_t parent_tag;
1154 /* OS resources for BAR0 memory. */
1155 struct resource *bxe_res;
1156 bus_space_tag_t bxe_btag;
1157 bus_space_handle_t bxe_bhandle;
1158 vm_offset_t bxe_vhandle;
1160 /* OS resources for BAR1 doorbell memory. */
1161 #define BXE_DB_SIZE (16 * 2048)
1162 struct resource *bxe_db_res;
1163 bus_space_tag_t bxe_db_btag;
1164 bus_space_handle_t bxe_db_bhandle;
1165 vm_offset_t bxe_db_vhandle;
1168 struct mtx bxe_core_mtx;
1169 struct mtx bxe_sp_mtx;
1170 struct mtx bxe_dmae_mtx;
1171 struct mtx bxe_fwmb_mtx;
1172 struct mtx bxe_print_mtx;
1174 /* Per-queue state. */
1175 /* ToDo: Convert to an array of pointers to conserve memory. */
1176 struct bxe_fastpath fp[MAX_CONTEXT];
1180 /* Legacy interrupt handler resources. */
1181 struct resource *bxe_irq_res;
1185 /* MSI-X interrupt handler resources (up to 17 vectors). */
1186 struct resource *bxe_msix_res[MAX_CONTEXT + 1];
1187 int bxe_msix_rid[MAX_CONTEXT + 1];
1188 void *bxe_msix_tag[MAX_CONTEXT + 1];
1191 /* MSI interrupt handler resources (up to XX vectors). */
1192 #define BXE_MSI_VECTOR_COUNT 8
1193 struct resource *bxe_msi_res[BXE_MSI_VECTOR_COUNT];
1194 int bxe_msi_rid[BXE_MSI_VECTOR_COUNT];
1195 void *bxe_msi_tag[BXE_MSI_VECTOR_COUNT];
1198 /* Taskqueue resources. */
1200 struct taskqueue *tq;
1201 /* RX Driver parameters*/
1204 /* ToDo: Replace with OS specific defintions. */
1206 #define ETH_OVREHEAD (ETH_HLEN + 8) /* 8 for CRC + VLAN */
1207 #define ETH_MIN_PACKET_SIZE 60
1208 #define ETH_MAX_PACKET_SIZE 1500
1209 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1211 struct bxe_dma def_sb_dma;
1212 struct host_def_status_block *def_sb;
1214 #define DEF_SB_ID 16
1219 uint16_t def_att_idx;
1221 uint32_t attn_state;
1222 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1224 struct bxe_dma stats_dma;
1225 struct statistics_block *stats;
1227 struct bxe_dma slowpath_dma;
1228 struct bxe_slowpath *slowpath;
1230 struct bxe_dma spq_dma;
1231 struct eth_spe *spq;
1233 uint16_t spq_prod_idx;
1234 struct eth_spe *spq_prod_bd;
1235 struct eth_spe *spq_last_bd;
1236 uint16_t *dsb_sp_prod;
1237 uint16_t *spq_hw_con;
1240 /* State information for pending ramrod commands. */
1241 uint8_t stats_pending;
1242 uint8_t set_mac_pending;
1248 #define BXE_ONE_PORT_FLAG 0x00000001
1249 #define BXE_NO_WOL_FLAG 0x00000002
1250 #define BXE_USING_DAC_FLAG 0x00000004
1251 #define BXE_TPA_ENABLE_FLAG 0x00000008
1252 #define BXE_NO_MCP_FLAG 0x00000010
1254 #define TPA_ENABLED(sc) (sc->bxe_flags & BXE_TPA_ENABLE_FLAG)
1255 #define NOMCP(sc) (sc->bxe_flags & BXE_NO_MCP_FLAG)
1258 /* PCI Express function number for the device. */
1262 * Ethernet port to PCIe function mapping for
1264 * +---------------+---------------+-------------+
1265 * | Ethernet Port | PCIe Function | Virtual NIC |
1268 * +---------------+---------------+-------------+
1270 * Ethernet port to PCIe function mapping for
1272 * +---------------+---------------+-------------+
1273 * | Ethernet Port | PCIe Function | Virtual NIC |
1282 * +---------------+---------------+-------------+
1285 #define BP_PORT(sc) (sc->bxe_func % PORT_MAX)
1286 #define BP_FUNC(sc) (sc->bxe_func)
1287 #define BP_E1HVN(sc) (sc->bxe_func >> 1)
1288 #define BP_L_ID(sc) (BP_E1HVN(sc) << 2)
1290 /* PCI Express link information. */
1291 uint16_t pcie_link_width;
1292 uint16_t pcie_link_speed;
1293 uint32_t bxe_cap_flags;
1294 #define BXE_MSI_CAPABLE_FLAG 0x00000001
1295 #define BXE_MSIX_CAPABLE_FLAG 0x00000002
1296 #define BXE_PCIE_CAPABLE_FLAG 0x00000004
1300 /* ToDo: Is this really needed? */
1301 uint16_t sp_running;
1303 /* Driver/firmware synchronization. */
1305 uint16_t fw_drv_pulse_wr_seq;
1309 * MCP scratchpad address for function specific statistics.
1310 * The device is responsible for writing statistics back to
1311 * the MCP for use with management firmware such as UMP/NC-SI.
1315 struct link_params link_params;
1316 struct link_vars link_vars;
1318 struct bxe_common common;
1319 struct bxe_port port;
1321 struct cmng_struct_per_port cmng;
1326 uint8_t rx_lane_swap;
1327 uint8_t tx_lane_swap;
1333 /* RX/TX Interrupt Coalescing Parameters */
1337 /* Device State: Used for Driver-FW communication. */
1339 #define BXE_STATE_CLOSED 0x0
1340 #define BXE_STATE_OPENING_WAIT4_LOAD 0x1000
1341 #define BXE_STATE_OPENING_WAIT4_PORT 0x2000
1342 #define BXE_STATE_OPEN 0x3000
1343 #define BXE_STATE_CLOSING_WAIT4_HALT 0x4000
1344 #define BXE_STATE_CLOSING_WAIT4_DELETE 0x5000
1345 #define BXE_STATE_CLOSING_WAIT4_UNLOAD 0x6000
1346 #define BXE_STATE_DISABLED 0xD000
1347 #define BXE_STATE_DIAG 0xE000
1348 #define BXE_STATE_ERROR 0xF000
1350 /* Driver tunable options. */
1359 #define BXE_MAX_QUEUES(sc) \
1360 (IS_E1HMF(sc) ? (MAX_CONTEXT / E1HVN_MAX) : MAX_CONTEXT)
1363 #define BXE_MAX_COS 3
1364 #define BXE_MAX_PRIORITY 8
1365 #define BXE_MAX_ENTRIES_PER_PRI 16
1367 /* Used for multiple function devices. */
1368 uint32_t mf_config[E1HVN_MAX];
1370 /* Outer VLAN tag. */
1372 #define IS_E1HOV(sc) (sc->e1hov != 0)
1375 #define IS_E1HMF(sc) (sc->e1hmf != 0)
1377 /* Receive mode settings (i.e promiscuous, multicast, etc.). */
1380 #define BXE_RX_MODE_NONE 0
1381 #define BXE_RX_MODE_NORMAL 1
1382 #define BXE_RX_MODE_ALLMULTI 2
1383 #define BXE_RX_MODE_PROMISC 3
1384 #define BXE_MAX_MULTICAST 64
1385 #define BXE_MAX_EMUL_MULTI 16
1387 uint32_t rx_mode_cl_mask;
1392 /* Used to synchronize statistics collection. */
1394 #define STATS_STATE_DISABLE 0
1395 #define STATS_STATE_ENABLE 1
1396 #define STATS_STATE_STOP 2
1400 /* Used by the DMAE command loader. */
1401 struct dmae_command stats_dmae;
1402 struct dmae_command init_dmae;
1406 uint16_t stats_counter;
1408 struct bxe_port_stats eth_stats;
1410 /* Support for DMAE and compressed firmware. */
1412 struct bxe_dma gz_dma;
1414 #define BXE_FW_BUF_SIZE 0x40000
1416 struct raw_op *init_ops;
1417 /* Init blocks offsets inside init_ops */
1418 const uint16_t *init_ops_offsets;
1419 /* Data blob - has 32 bit granularity */
1420 const uint32_t *init_data;
1421 /* PRAM blobs - raw data */
1422 const uint8_t *tsem_int_table_data;
1423 const uint8_t *tsem_pram_data;
1424 const uint8_t *usem_int_table_data;
1425 const uint8_t *usem_pram_data;
1426 const uint8_t *xsem_int_table_data;
1427 const uint8_t *xsem_pram_data;
1428 const uint8_t *csem_int_table_data;
1429 const uint8_t *csem_pram_data;
1430 #define INIT_OPS(sc) (sc->init_ops)
1431 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1432 #define INIT_DATA(sc) (sc->init_data)
1433 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1434 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1435 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1436 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1437 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1438 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1439 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1440 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1442 /* OS handle for periodic tick routine. */
1443 struct callout bxe_tick_callout;
1447 /* Frame size and mbuf allocation size for RX frames. */
1448 uint32_t max_frame_size;
1449 int mbuf_alloc_size;
1453 /* Verify bxe_function_init is run before handling interrupts. */
1457 unsigned long debug_sim_mbuf_alloc_failed;
1458 unsigned long debug_sim_mbuf_map_failed;
1459 unsigned long debug_received_frame_error;
1461 /* A buffer for hardware/firmware state information (grcdump). */
1462 uint32_t *grcdump_buffer;
1465 unsigned long tx_start_called_with_link_down;
1466 unsigned long tx_start_called_with_queue_full;
1467 }; /* end of struct bxe_softc */
1469 #define MDIO_AN_CL73_OR_37_COMPLETE \
1470 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
1471 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
1473 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
1474 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
1475 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
1476 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
1477 #define GP_STATUS_SPEED_MASK \
1478 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
1479 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
1480 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
1481 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
1482 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
1483 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
1484 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
1485 #define GP_STATUS_10G_HIG \
1486 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
1487 #define GP_STATUS_10G_CX4 \
1488 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
1489 #define GP_STATUS_12G_HIG \
1490 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG
1491 #define GP_STATUS_12_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G
1492 #define GP_STATUS_13G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G
1493 #define GP_STATUS_15G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G
1494 #define GP_STATUS_16G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G
1495 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
1496 #define GP_STATUS_10G_KX4 \
1497 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
1499 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
1500 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
1501 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
1502 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
1503 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
1504 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
1505 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
1506 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
1507 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
1508 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
1509 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
1510 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
1511 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
1512 #define LINK_12GTFD LINK_STATUS_SPEED_AND_DUPLEX_12GTFD
1513 #define LINK_12GXFD LINK_STATUS_SPEED_AND_DUPLEX_12GXFD
1514 #define LINK_12_5GTFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GTFD
1515 #define LINK_12_5GXFD LINK_STATUS_SPEED_AND_DUPLEX_12_5GXFD
1516 #define LINK_13GTFD LINK_STATUS_SPEED_AND_DUPLEX_13GTFD
1517 #define LINK_13GXFD LINK_STATUS_SPEED_AND_DUPLEX_13GXFD
1518 #define LINK_15GTFD LINK_STATUS_SPEED_AND_DUPLEX_15GTFD
1519 #define LINK_15GXFD LINK_STATUS_SPEED_AND_DUPLEX_15GXFD
1520 #define LINK_16GTFD LINK_STATUS_SPEED_AND_DUPLEX_16GTFD
1521 #define LINK_16GXFD LINK_STATUS_SPEED_AND_DUPLEX_16GXFD
1523 #define MEDIUM_FULL_DUPLEX 0
1524 #define MEDIUM_HALF_DUPLEX 1
1526 #define DUPLEX_FULL 0
1527 #define DUPLEX_HALF 1
1530 #define SPEED_100 100
1531 #define SPEED_1000 1000
1532 #define SPEED_2500 2500
1533 #define SPEED_10000 10000
1536 #define NIG_STATUS_XGXS0_LINK10G \
1537 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
1538 #define NIG_STATUS_XGXS0_LINK_STATUS \
1539 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
1540 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
1541 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
1542 #define NIG_STATUS_SERDES0_LINK_STATUS \
1543 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
1544 #define NIG_MASK_MI_INT \
1545 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
1546 #define NIG_MASK_XGXS0_LINK10G \
1547 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
1548 #define NIG_MASK_XGXS0_LINK_STATUS \
1549 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
1550 #define NIG_MASK_SERDES0_LINK_STATUS \
1551 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
1553 #define XGXS_RESET_BITS \
1554 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
1555 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
1556 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
1557 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
1558 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
1560 #define SERDES_RESET_BITS \
1561 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
1562 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
1563 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
1564 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
1566 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
1567 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
1568 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
1570 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
1571 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
1572 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
1573 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
1574 #define SFP_EEPROM_OPTIONS_SIZE 2
1577 #define BXE_PMF_LINK_ASSERT \
1578 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(sc))
1580 #define BXE_MC_ASSERT_BITS \
1581 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1582 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1583 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1584 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1586 #define BXE_MCP_ASSERT \
1587 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1589 #define BXE_GRC_TIMEOUT \
1590 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1592 #define BXE_GRC_RSV \
1593 (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1594 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1595 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1596 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1597 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1598 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1600 #define HW_INTERRUT_ASSERT_SET_0 \
1601 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1602 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1603 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1604 AEU_INPUTS_ATTN_BITS_PBF_HW_INTERRUPT)
1606 #define HW_PRTY_ASSERT_SET_0 \
1607 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1608 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1609 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1610 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR | \
1611 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR)
1613 #define HW_INTERRUT_ASSERT_SET_1 \
1614 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1615 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1616 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1617 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1618 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
1619 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
1620 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
1621 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
1622 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
1623 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
1624 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
1626 #define HW_PRTY_ASSERT_SET_1 \
1627 (AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR | \
1628 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
1629 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
1630 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
1631 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR | \
1632 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR | \
1633 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
1634 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
1635 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
1636 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
1637 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR)
1639 #define HW_INTERRUT_ASSERT_SET_2 \
1640 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
1641 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
1642 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
1643 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT | \
1644 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
1646 #define HW_PRTY_ASSERT_SET_2 \
1647 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
1648 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
1649 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR | \
1650 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
1651 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
1652 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
1653 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
1655 /* Stuff added to make the code fit 80Col. */
1656 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
1658 #define TPA_TYPE_START ETH_FAST_PATH_RX_CQE_START_FLG
1659 #define TPA_TYPE_END ETH_FAST_PATH_RX_CQE_END_FLG
1660 #define TPA_TYPE(cqe_fp_flags) \
1661 ((cqe_fp_flags) & (TPA_TYPE_START | TPA_TYPE_END))
1663 #define ETH_RX_ERROR_FLAGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
1665 #define BXE_IP_CSUM_ERR(cqe) \
1666 (!((cqe)->fast_path_cqe.status_flags & \
1667 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
1668 ((cqe)->fast_path_cqe.type_error_flags & \
1669 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
1671 #define BXE_L4_CSUM_ERR(cqe) \
1672 (!((cqe)->fast_path_cqe.status_flags & \
1673 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
1674 ((cqe)->fast_path_cqe.type_error_flags & \
1675 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
1677 #define BXE_RX_CSUM_OK(cqe) \
1678 (!(BXE_L4_CSUM_ERR(cqe) || BXE_IP_CSUM_ERR(cqe)))
1680 #define BXE_RX_SUM_FIX(cqe) \
1681 ((le16toh(cqe->fast_path_cqe.pars_flags.flags) & \
1682 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) == \
1683 (1 << PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT))
1685 #define MULTI_FLAGS(sc) \
1686 (TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY | \
1687 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY | \
1688 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY | \
1689 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY | \
1690 (sc->multi_mode << \
1691 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT))
1693 #define MULTI_MASK 0x7f
1695 #define FP_USB_FUNC_OFF (2 + 2 * HC_USTORM_SB_NUM_INDICES)
1696 #define FP_CSB_FUNC_OFF (2 + 2 * HC_CSTORM_SB_NUM_INDICES)
1698 #define U_SB_ETH_RX_CQ_INDEX HC_INDEX_U_ETH_RX_CQ_CONS
1699 #define U_SB_ETH_RX_BD_INDEX HC_INDEX_U_ETH_RX_BD_CONS
1700 #define C_SB_ETH_TX_CQ_INDEX HC_INDEX_C_ETH_TX_CQ_CONS
1702 #define DEF_USB_FUNC_OFF (2 + 2 * HC_USTORM_DEF_SB_NUM_INDICES)
1703 #define DEF_CSB_FUNC_OFF (2 + 2 * HC_CSTORM_DEF_SB_NUM_INDICES)
1704 #define DEF_XSB_FUNC_OFF (2 + 2 * HC_XSTORM_DEF_SB_NUM_INDICES)
1705 #define DEF_TSB_FUNC_OFF (2 + 2 * HC_TSTORM_DEF_SB_NUM_INDICES)
1707 #define C_DEF_SB_SP_INDEX HC_INDEX_DEF_C_ETH_SLOW_PATH
1709 #define BXE_RX_SB_INDEX \
1710 &fp->status_block->u_status_block.index_values[U_SB_ETH_RX_CQ_INDEX]
1712 #define BXE_RX_SB_BD_INDEX \
1713 (&fp->status_block->u_status_block.index_values[U_SB_ETH_RX_BD_INDEX])
1715 #define BXE_TX_SB_INDEX \
1716 (&fp->status_block->c_status_block.index_values[C_SB_ETH_TX_CQ_INDEX])
1718 #define BXE_SP_DSB_INDEX \
1719 &sc->def_sb->c_def_status_block.index_values[C_DEF_SB_SP_INDEX]
1721 #define BXE_RX_SB_INDEX_NUM \
1722 (((U_SB_ETH_RX_CQ_INDEX << \
1723 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER_SHIFT) & \
1724 USTORM_ETH_ST_CONTEXT_CONFIG_CQE_SB_INDEX_NUMBER) | \
1725 ((U_SB_ETH_RX_BD_INDEX << \
1726 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER_SHIFT) & \
1727 USTORM_ETH_ST_CONTEXT_CONFIG_BD_SB_INDEX_NUMBER))
1729 #define CAM_IS_INVALID(x) \
1730 ((x)->target_table_entry.flags == \
1731 TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1733 #define CAM_INVALIDATE(x) \
1734 ((x)->target_table_entry.flags = TSTORM_CAM_TARGET_TABLE_ENTRY_ACTION_TYPE)
1736 /* Number of uint32_t elements in multicast hash array. */
1737 #define MC_HASH_SIZE 8
1738 #define MC_HASH_OFFSET(sc, i) \
1739 (BAR_TSTORM_INTMEM + \
1740 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(sc)) + \
1743 #define UINT_MAX (~0U)
1746 * PCIE Capability Register Definitions. Need to replace with the system
1747 * header file later.
1749 #define PCI_EXP_DEVCTL 8
1750 #define PCI_EXP_DEVCTL_CERE 0x0001
1751 #define PCI_EXP_DEVCTL_NFERE 0x0002
1752 #define PCI_EXP_DEVCTL_FERE 0x0004
1753 #define PCI_EXP_DEVCTL_URRE 0x0008
1754 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010
1755 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0
1756 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100
1757 #define PCI_EXP_DEVCTL_PHANTOM 0x0200
1758 #define PCI_EXP_DEVCTL_AUX_PME 0x0400
1759 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800
1760 #define PCI_EXP_DEVCTL_READRQ 0x7000
1763 * Return Value for bxe_attach/bxe_detach when device is not found.
1765 /* ToDo: Are these necessary? */
1770 /* Return Vlaue for sp_post */
1771 #ifndef ESPQOVERFLOW
1772 #define ESPQOVERFLOW 4
1775 /* Return Value for bxe_write_phy, bxe_read_phy. */
1780 #ifndef PCI_EXP_DEVCTL
1781 #define PCI_EXP_DEVCTL 8 /* Device Control */
1784 #ifndef PCI_EXP_DEVCTL_PAYLOAD
1785 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
1788 #ifndef PCI_EXP_DEVCTL_READRQ
1789 #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
1792 #if defined(__i386__) || defined(__amd64__)
1793 /* ToDo: Validate this! */
1794 /* 128 byte L1 cache size. */
1795 #define BXE_RX_ALIGN_SHIFT 7
1797 /* ToDo: Validate this! */
1798 /* 256 byte L1 cache size. */
1799 #define BXE_RX_ALIGN_SHIFT 8
1802 #define BXE_RX_ALIGN (1 << BXE_RX_ALIGN_SHIFT)
1804 #if __FreeBSD_version < 800054
1805 #if defined(__i386__) || defined(__amd64__)
1806 #define mb() __asm volatile("mfence" ::: "memory")
1807 #define wmb() __asm volatile("sfence" ::: "memory")
1808 #define rmb() __asm volatile("lfence" ::: "memory")
1809 static __inline void
1812 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
1822 #define BXE_RX_ALIGN (1 << BXE_RX_ALIGN_SHIFT)
1824 #define PAGE_ALIGN(addr) (((addr) + PAGE_SIZE - 1) & (~PAGE_MASK))
1826 /* External PHY definitions. */
1827 #define LED_MODE_OFF 0
1828 #define LED_MODE_OPER 2
1830 #endif /*_IF_BXE_H */