sys/dev/cadence/if_cgem.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * A network interface driver for Cadence GEM Gigabit Ethernet
  31  * interface such as the one used in Xilinx Zynq-7000 SoC.
  32  *
  33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
  34  * (v1.4) November 16, 2012.  Xilinx doc UG585.  GEM is covered in Ch. 16
  35  * and register definitions are in appendix B.18.
  36  */
  37
  38 #include <sys/cdefs.h>
  39 __FBSDID("$FreeBSD$");
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/bus.h>
  44 #include <sys/kernel.h>
  45 #include <sys/malloc.h>
  46 #include <sys/mbuf.h>
  47 #include <sys/module.h>
  48 #include <sys/rman.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <machine/bus.h>
  54
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_arp.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_media.h>
  60 #include <net/if_mib.h>
  61 #include <net/if_types.h>
  62
  63 #ifdef INET
  64 #include <netinet/in.h>
  65 #include <netinet/in_systm.h>
  66 #include <netinet/in_var.h>
  67 #include <netinet/ip.h>
  68 #endif
  69
  70 #include <net/bpf.h>
  71 #include <net/bpfdesc.h>
  72
  73 #include <dev/fdt/fdt_common.h>
  74 #include <dev/ofw/ofw_bus.h>
  75 #include <dev/ofw/ofw_bus_subr.h>
  76
  77 #include <dev/mii/mii.h>
  78 #include <dev/mii/miivar.h>
  79
  80 #include <dev/cadence/if_cgem_hw.h>
  81
  82 #include "miibus_if.h"
  83
  84 #define IF_CGEM_NAME "cgem"
  85
  86 #define CGEM_NUM_RX_DESCS       512     /* size of receive descriptor ring */
  87 #define CGEM_NUM_TX_DESCS       512     /* size of transmit descriptor ring */
  88
  89 #define MAX_DESC_RING_SIZE (MAX(CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),\
  90                                 CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc)))
  91
  92
  93 /* Default for sysctl rxbufs.  Must be < CGEM_NUM_RX_DESCS of course. */
  94 #define DEFAULT_NUM_RX_BUFS     256     /* number of receive bufs to queue. */
  95
  96 #define TX_MAX_DMA_SEGS         8       /* maximum segs in a tx mbuf dma */
  97
  98 #define CGEM_CKSUM_ASSIST       (CSUM_IP | CSUM_TCP | CSUM_UDP | \
  99                                  CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
 100
 101 static struct ofw_compat_data compat_data[] = {
 102         { "cadence,gem",        1 },
 103         { "cdns,macb",          1 },
 104         { NULL,                 0 },
 105 };
 106
 107 struct cgem_softc {
 108         if_t                    ifp;
 109         struct mtx              sc_mtx;
 110         device_t                dev;
 111         device_t                miibus;
 112         u_int                   mii_media_active;       /* last active media */
 113         int                     if_old_flags;
 114         struct resource         *mem_res;
 115         struct resource         *irq_res;
 116         void                    *intrhand;
 117         struct callout          tick_ch;
 118         uint32_t                net_ctl_shadow;
 119         int                     ref_clk_num;
 120         u_char                  eaddr[6];
 121
 122         bus_dma_tag_t           desc_dma_tag;
 123         bus_dma_tag_t           mbuf_dma_tag;
 124
 125         /* receive descriptor ring */
 126         struct cgem_rx_desc     *rxring;
 127         bus_addr_t              rxring_physaddr;
 128         struct mbuf             *rxring_m[CGEM_NUM_RX_DESCS];
 129         bus_dmamap_t            rxring_m_dmamap[CGEM_NUM_RX_DESCS];
 130         int                     rxring_hd_ptr;  /* where to put rcv bufs */
 131         int                     rxring_tl_ptr;  /* where to get receives */
 132         int                     rxring_queued;  /* how many rcv bufs queued */
 133         bus_dmamap_t            rxring_dma_map;
 134         int                     rxbufs;         /* tunable number rcv bufs */
 135         int                     rxhangwar;      /* rx hang work-around */
 136         u_int                   rxoverruns;     /* rx overruns */
 137         u_int                   rxnobufs;       /* rx buf ring empty events */
 138         u_int                   rxdmamapfails;  /* rx dmamap failures */
 139         uint32_t                rx_frames_prev;
 140
 141         /* transmit descriptor ring */
 142         struct cgem_tx_desc     *txring;
 143         bus_addr_t              txring_physaddr;
 144         struct mbuf             *txring_m[CGEM_NUM_TX_DESCS];
 145         bus_dmamap_t            txring_m_dmamap[CGEM_NUM_TX_DESCS];
 146         int                     txring_hd_ptr;  /* where to put next xmits */
 147         int                     txring_tl_ptr;  /* next xmit mbuf to free */
 148         int                     txring_queued;  /* num xmits segs queued */
 149         bus_dmamap_t            txring_dma_map;
 150         u_int                   txfull;         /* tx ring full events */
 151         u_int                   txdefrags;      /* tx calls to m_defrag() */
 152         u_int                   txdefragfails;  /* tx m_defrag() failures */
 153         u_int                   txdmamapfails;  /* tx dmamap failures */
 154
 155         /* hardware provided statistics */
 156         struct cgem_hw_stats {
 157                 uint64_t                tx_bytes;
 158                 uint32_t                tx_frames;
 159                 uint32_t                tx_frames_bcast;
 160                 uint32_t                tx_frames_multi;
 161                 uint32_t                tx_frames_pause;
 162                 uint32_t                tx_frames_64b;
 163                 uint32_t                tx_frames_65to127b;
 164                 uint32_t                tx_frames_128to255b;
 165                 uint32_t                tx_frames_256to511b;
 166                 uint32_t                tx_frames_512to1023b;
 167                 uint32_t                tx_frames_1024to1536b;
 168                 uint32_t                tx_under_runs;
 169                 uint32_t                tx_single_collisn;
 170                 uint32_t                tx_multi_collisn;
 171                 uint32_t                tx_excsv_collisn;
 172                 uint32_t                tx_late_collisn;
 173                 uint32_t                tx_deferred_frames;
 174                 uint32_t                tx_carrier_sense_errs;
 175
 176                 uint64_t                rx_bytes;
 177                 uint32_t                rx_frames;
 178                 uint32_t                rx_frames_bcast;
 179                 uint32_t                rx_frames_multi;
 180                 uint32_t                rx_frames_pause;
 181                 uint32_t                rx_frames_64b;
 182                 uint32_t                rx_frames_65to127b;
 183                 uint32_t                rx_frames_128to255b;
 184                 uint32_t                rx_frames_256to511b;
 185                 uint32_t                rx_frames_512to1023b;
 186                 uint32_t                rx_frames_1024to1536b;
 187                 uint32_t                rx_frames_undersize;
 188                 uint32_t                rx_frames_oversize;
 189                 uint32_t                rx_frames_jabber;
 190                 uint32_t                rx_frames_fcs_errs;
 191                 uint32_t                rx_frames_length_errs;
 192                 uint32_t                rx_symbol_errs;
 193                 uint32_t                rx_align_errs;
 194                 uint32_t                rx_resource_errs;
 195                 uint32_t                rx_overrun_errs;
 196                 uint32_t                rx_ip_hdr_csum_errs;
 197                 uint32_t                rx_tcp_csum_errs;
 198                 uint32_t                rx_udp_csum_errs;
 199         } stats;
 200 };
 201
 202 #define RD4(sc, off)            (bus_read_4((sc)->mem_res, (off)))
 203 #define WR4(sc, off, val)       (bus_write_4((sc)->mem_res, (off), (val)))
 204 #define BARRIER(sc, off, len, flags) \
 205         (bus_barrier((sc)->mem_res, (off), (len), (flags))
 206
 207 #define CGEM_LOCK(sc)           mtx_lock(&(sc)->sc_mtx)
 208 #define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
 209 #define CGEM_LOCK_INIT(sc)      \
 210         mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
 211                  MTX_NETWORK_LOCK, MTX_DEF)
 212 #define CGEM_LOCK_DESTROY(sc)   mtx_destroy(&(sc)->sc_mtx)
 213 #define CGEM_ASSERT_LOCKED(sc)  mtx_assert(&(sc)->sc_mtx, MA_OWNED)
 214
 215 /* Allow platforms to optionally provide a way to set the reference clock. */
 216 int cgem_set_ref_clk(int unit, int frequency);
 217
 218 static devclass_t cgem_devclass;
 219
 220 static int cgem_probe(device_t dev);
 221 static int cgem_attach(device_t dev);
 222 static int cgem_detach(device_t dev);
 223 static void cgem_tick(void *);
 224 static void cgem_intr(void *);
 225
 226 static void cgem_mediachange(struct cgem_softc *, struct mii_data *);
 227
 228 static void
 229 cgem_get_mac(struct cgem_softc *sc, u_char eaddr[])
 230 {
 231         int i;
 232         uint32_t rnd;
 233
 234         /* See if boot loader gave us a MAC address already. */
 235         for (i = 0; i < 4; i++) {
 236                 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
 237                 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
 238                 if (low != 0 || high != 0) {
 239                         eaddr[0] = low & 0xff;
 240                         eaddr[1] = (low >> 8) & 0xff;
 241                         eaddr[2] = (low >> 16) & 0xff;
 242                         eaddr[3] = (low >> 24) & 0xff;
 243                         eaddr[4] = high & 0xff;
 244                         eaddr[5] = (high >> 8) & 0xff;
 245                         break;
 246                 }
 247         }
 248
 249         /* No MAC from boot loader?  Assign a random one. */
 250         if (i == 4) {
 251                 rnd = arc4random();
 252
 253                 eaddr[0] = 'b';
 254                 eaddr[1] = 's';
 255                 eaddr[2] = 'd';
 256                 eaddr[3] = (rnd >> 16) & 0xff;
 257                 eaddr[4] = (rnd >> 8) & 0xff;
 258                 eaddr[5] = rnd & 0xff;
 259
 260                 device_printf(sc->dev, "no mac address found, assigning "
 261                               "random: %02x:%02x:%02x:%02x:%02x:%02x\n",
 262                               eaddr[0], eaddr[1], eaddr[2],
 263                               eaddr[3], eaddr[4], eaddr[5]);
 264         }
 265
 266         /* Move address to first slot and zero out the rest. */
 267         WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
 268             (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]);
 269         WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
 270
 271         for (i = 1; i < 4; i++) {
 272                 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
 273                 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
 274         }
 275 }
 276
 277 /* cgem_mac_hash():  map 48-bit address to a 6-bit hash.
 278  * The 6-bit hash corresponds to a bit in a 64-bit hash
 279  * register.  Setting that bit in the hash register enables
 280  * reception of all frames with a destination address that hashes
 281  * to that 6-bit value.
 282  *
 283  * The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech
 284  * Reference Manual.  Bits 0-5 in the hash are the exclusive-or of
 285  * every sixth bit in the destination address.
 286  */
 287 static int
 288 cgem_mac_hash(u_char eaddr[])
 289 {
 290         int hash;
 291         int i, j;
 292
 293         hash = 0;
 294         for (i = 0; i < 6; i++)
 295                 for (j = i; j < 48; j += 6)
 296                         if ((eaddr[j >> 3] & (1 << (j & 7))) != 0)
 297                                 hash ^= (1 << i);
 298
 299         return hash;
 300 }
 301
 302 /* After any change in rx flags or multi-cast addresses, set up
 303  * hash registers and net config register bits.
 304  */
 305 static void
 306 cgem_rx_filter(struct cgem_softc *sc)
 307 {
 308         if_t ifp = sc->ifp;
 309         u_char *mta;
 310
 311         int index, i, mcnt;
 312         uint32_t hash_hi, hash_lo;
 313         uint32_t net_cfg;
 314
 315         hash_hi = 0;
 316         hash_lo = 0;
 317
 318         net_cfg = RD4(sc, CGEM_NET_CFG);
 319
 320         net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN |
 321                      CGEM_NET_CFG_NO_BCAST |
 322                      CGEM_NET_CFG_COPY_ALL);
 323
 324         if ((if_getflags(ifp) & IFF_PROMISC) != 0)
 325                 net_cfg |= CGEM_NET_CFG_COPY_ALL;
 326         else {
 327                 if ((if_getflags(ifp) & IFF_BROADCAST) == 0)
 328                         net_cfg |= CGEM_NET_CFG_NO_BCAST;
 329                 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
 330                         hash_hi = 0xffffffff;
 331                         hash_lo = 0xffffffff;
 332                 } else {
 333                         mcnt = if_multiaddr_count(ifp, -1);
 334                         mta = malloc(ETHER_ADDR_LEN * mcnt, M_DEVBUF,
 335                                      M_NOWAIT);
 336                         if (mta == NULL) {
 337                                 device_printf(sc->dev,
 338                                       "failed to allocate temp mcast list\n");
 339                                 return;
 340                         }
 341                         if_multiaddr_array(ifp, mta, &mcnt, mcnt);
 342                         for (i = 0; i < mcnt; i++) {
 343                                 index = cgem_mac_hash(
 344                                         LLADDR((struct sockaddr_dl *)
 345                                                (mta + (i * ETHER_ADDR_LEN))));
 346                                 if (index > 31)
 347                                         hash_hi |= (1 << (index - 32));
 348                                 else
 349                                         hash_lo |= (1 << index);
 350                         }
 351                         free(mta, M_DEVBUF);
 352                 }
 353
 354                 if (hash_hi != 0 || hash_lo != 0)
 355                         net_cfg |= CGEM_NET_CFG_MULTI_HASH_EN;
 356         }
 357
 358         WR4(sc, CGEM_HASH_TOP, hash_hi);
 359         WR4(sc, CGEM_HASH_BOT, hash_lo);
 360         WR4(sc, CGEM_NET_CFG, net_cfg);
 361 }
 362
 363 /* For bus_dmamap_load() callback. */
 364 static void
 365 cgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 366 {
 367
 368         if (nsegs != 1 || error != 0)
 369                 return;
 370         *(bus_addr_t *)arg = segs[0].ds_addr;
 371 }
 372
 373 /* Create DMA'able descriptor rings. */
 374 static int
 375 cgem_setup_descs(struct cgem_softc *sc)
 376 {
 377         int i, err;
 378
 379         sc->txring = NULL;
 380         sc->rxring = NULL;
 381
 382         /* Allocate non-cached DMA space for RX and TX descriptors.
 383          */
 384         err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
 385                                  BUS_SPACE_MAXADDR_32BIT,
 386                                  BUS_SPACE_MAXADDR,
 387                                  NULL, NULL,
 388                                  MAX_DESC_RING_SIZE,
 389                                  1,
 390                                  MAX_DESC_RING_SIZE,
 391                                  0,
 392                                  busdma_lock_mutex,
 393                                  &sc->sc_mtx,
 394                                  &sc->desc_dma_tag);
 395         if (err)
 396                 return (err);
 397
 398         /* Set up a bus_dma_tag for mbufs. */
 399         err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
 400                                  BUS_SPACE_MAXADDR_32BIT,
 401                                  BUS_SPACE_MAXADDR,
 402                                  NULL, NULL,
 403                                  MCLBYTES,
 404                                  TX_MAX_DMA_SEGS,
 405                                  MCLBYTES,
 406                                  0,
 407                                  busdma_lock_mutex,
 408                                  &sc->sc_mtx,
 409                                  &sc->mbuf_dma_tag);
 410         if (err)
 411                 return (err);
 412
 413         /* Allocate DMA memory in non-cacheable space. */
 414         err = bus_dmamem_alloc(sc->desc_dma_tag,
 415                                (void **)&sc->rxring,
 416                                BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
 417                                &sc->rxring_dma_map);
 418         if (err)
 419                 return (err);
 420
 421         /* Load descriptor DMA memory. */
 422         err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map,
 423                               (void *)sc->rxring,
 424                               CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),
 425                               cgem_getaddr, &sc->rxring_physaddr,
 426                               BUS_DMA_NOWAIT);
 427         if (err)
 428                 return (err);
 429
 430         /* Initialize RX descriptors. */
 431         for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
 432                 sc->rxring[i].addr = CGEM_RXDESC_OWN;
 433                 sc->rxring[i].ctl = 0;
 434                 sc->rxring_m[i] = NULL;
 435                 sc->rxring_m_dmamap[i] = NULL;
 436         }
 437         sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP;
 438
 439         sc->rxring_hd_ptr = 0;
 440         sc->rxring_tl_ptr = 0;
 441         sc->rxring_queued = 0;
 442
 443         /* Allocate DMA memory for TX descriptors in non-cacheable space. */
 444         err = bus_dmamem_alloc(sc->desc_dma_tag,
 445                                (void **)&sc->txring,
 446                                BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
 447                                &sc->txring_dma_map);
 448         if (err)
 449                 return (err);
 450
 451         /* Load TX descriptor DMA memory. */
 452         err = bus_dmamap_load(sc->desc_dma_tag, sc->txring_dma_map,
 453                               (void *)sc->txring,
 454                               CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc),
 455                               cgem_getaddr, &sc->txring_physaddr,
 456                               BUS_DMA_NOWAIT);
 457         if (err)
 458                 return (err);
 459
 460         /* Initialize TX descriptor ring. */
 461         for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
 462                 sc->txring[i].addr = 0;
 463                 sc->txring[i].ctl = CGEM_TXDESC_USED;
 464                 sc->txring_m[i] = NULL;
 465                 sc->txring_m_dmamap[i] = NULL;
 466         }
 467         sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP;
 468
 469         sc->txring_hd_ptr = 0;
 470         sc->txring_tl_ptr = 0;
 471         sc->txring_queued = 0;
 472
 473         return (0);
 474 }
 475
 476 /* Fill receive descriptor ring with mbufs. */
 477 static void
 478 cgem_fill_rqueue(struct cgem_softc *sc)
 479 {
 480         struct mbuf *m = NULL;
 481         bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
 482         int nsegs;
 483
 484         CGEM_ASSERT_LOCKED(sc);
 485
 486         while (sc->rxring_queued < sc->rxbufs) {
 487                 /* Get a cluster mbuf. */
 488                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 489                 if (m == NULL)
 490                         break;
 491
 492                 m->m_len = MCLBYTES;
 493                 m->m_pkthdr.len = MCLBYTES;
 494                 m->m_pkthdr.rcvif = sc->ifp;
 495
 496                 /* Load map and plug in physical address. */
 497                 if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
 498                               &sc->rxring_m_dmamap[sc->rxring_hd_ptr])) {
 499                         sc->rxdmamapfails++;
 500                         m_free(m);
 501                         break;
 502                 }
 503                 if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 504                               sc->rxring_m_dmamap[sc->rxring_hd_ptr], m,
 505                               segs, &nsegs, BUS_DMA_NOWAIT)) {
 506                         sc->rxdmamapfails++;
 507                         bus_dmamap_destroy(sc->mbuf_dma_tag,
 508                                    sc->rxring_m_dmamap[sc->rxring_hd_ptr]);
 509                         sc->rxring_m_dmamap[sc->rxring_hd_ptr] = NULL;
 510                         m_free(m);
 511                         break;
 512                 }
 513                 sc->rxring_m[sc->rxring_hd_ptr] = m;
 514
 515                 /* Sync cache with receive buffer. */
 516                 bus_dmamap_sync(sc->mbuf_dma_tag,
 517                                 sc->rxring_m_dmamap[sc->rxring_hd_ptr],
 518                                 BUS_DMASYNC_PREREAD);
 519
 520                 /* Write rx descriptor and increment head pointer. */
 521                 sc->rxring[sc->rxring_hd_ptr].ctl = 0;
 522                 if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) {
 523                         sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr |
 524                                 CGEM_RXDESC_WRAP;
 525                         sc->rxring_hd_ptr = 0;
 526                 } else
 527                         sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr;
 528
 529                 sc->rxring_queued++;
 530         }
 531 }
 532
 533 /* Pull received packets off of receive descriptor ring. */
 534 static void
 535 cgem_recv(struct cgem_softc *sc)
 536 {
 537         if_t ifp = sc->ifp;
 538         struct mbuf *m, *m_hd, **m_tl;
 539         uint32_t ctl;
 540
 541         CGEM_ASSERT_LOCKED(sc);
 542
 543         /* Pick up all packets in which the OWN bit is set. */
 544         m_hd = NULL;
 545         m_tl = &m_hd;
 546         while (sc->rxring_queued > 0 &&
 547                (sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) {
 548
 549                 ctl = sc->rxring[sc->rxring_tl_ptr].ctl;
 550
 551                 /* Grab filled mbuf. */
 552                 m = sc->rxring_m[sc->rxring_tl_ptr];
 553                 sc->rxring_m[sc->rxring_tl_ptr] = NULL;
 554
 555                 /* Sync cache with receive buffer. */
 556                 bus_dmamap_sync(sc->mbuf_dma_tag,
 557                                 sc->rxring_m_dmamap[sc->rxring_tl_ptr],
 558                                 BUS_DMASYNC_POSTREAD);
 559
 560                 /* Unload and destroy dmamap. */
 561                 bus_dmamap_unload(sc->mbuf_dma_tag,
 562                         sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
 563                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 564                                    sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
 565                 sc->rxring_m_dmamap[sc->rxring_tl_ptr] = NULL;
 566
 567                 /* Increment tail pointer. */
 568                 if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS)
 569                         sc->rxring_tl_ptr = 0;
 570                 sc->rxring_queued--;
 571
 572                 /* Check FCS and make sure entire packet landed in one mbuf
 573                  * cluster (which is much bigger than the largest ethernet
 574                  * packet).
 575                  */
 576                 if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 ||
 577                     (ctl & (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) !=
 578                            (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) {
 579                         /* discard. */
 580                         m_free(m);
 581                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 582                         continue;
 583                 }
 584
 585                 /* Ready it to hand off to upper layers. */
 586                 m->m_data += ETHER_ALIGN;
 587                 m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK);
 588                 m->m_pkthdr.rcvif = ifp;
 589                 m->m_pkthdr.len = m->m_len;
 590
 591                 /* Are we using hardware checksumming?  Check the
 592                  * status in the receive descriptor.
 593                  */
 594                 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
 595                         /* TCP or UDP checks out, IP checks out too. */
 596                         if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 597                             CGEM_RXDESC_CKSUM_STAT_TCP_GOOD ||
 598                             (ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 599                             CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) {
 600                                 m->m_pkthdr.csum_flags |=
 601                                         CSUM_IP_CHECKED | CSUM_IP_VALID |
 602                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 603                                 m->m_pkthdr.csum_data = 0xffff;
 604                         } else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 605                                    CGEM_RXDESC_CKSUM_STAT_IP_GOOD) {
 606                                 /* Only IP checks out. */
 607                                 m->m_pkthdr.csum_flags |=
 608                                         CSUM_IP_CHECKED | CSUM_IP_VALID;
 609                                 m->m_pkthdr.csum_data = 0xffff;
 610                         }
 611                 }
 612
 613                 /* Queue it up for delivery below. */
 614                 *m_tl = m;
 615                 m_tl = &m->m_next;
 616         }
 617
 618         /* Replenish receive buffers. */
 619         cgem_fill_rqueue(sc);
 620
 621         /* Unlock and send up packets. */
 622         CGEM_UNLOCK(sc);
 623         while (m_hd != NULL) {
 624                 m = m_hd;
 625                 m_hd = m_hd->m_next;
 626                 m->m_next = NULL;
 627                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 628                 if_input(ifp, m);
 629         }
 630         CGEM_LOCK(sc);
 631 }
 632
 633 /* Find completed transmits and free their mbufs. */
 634 static void
 635 cgem_clean_tx(struct cgem_softc *sc)
 636 {
 637         struct mbuf *m;
 638         uint32_t ctl;
 639
 640         CGEM_ASSERT_LOCKED(sc);
 641
 642         /* free up finished transmits. */
 643         while (sc->txring_queued > 0 &&
 644                ((ctl = sc->txring[sc->txring_tl_ptr].ctl) &
 645                 CGEM_TXDESC_USED) != 0) {
 646
 647                 /* Sync cache. */
 648                 bus_dmamap_sync(sc->mbuf_dma_tag,
 649                                 sc->txring_m_dmamap[sc->txring_tl_ptr],
 650                                 BUS_DMASYNC_POSTWRITE);
 651
 652                 /* Unload and destroy DMA map. */
 653                 bus_dmamap_unload(sc->mbuf_dma_tag,
 654                                   sc->txring_m_dmamap[sc->txring_tl_ptr]);
 655                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 656                                    sc->txring_m_dmamap[sc->txring_tl_ptr]);
 657                 sc->txring_m_dmamap[sc->txring_tl_ptr] = NULL;
 658
 659                 /* Free up the mbuf. */
 660                 m = sc->txring_m[sc->txring_tl_ptr];
 661                 sc->txring_m[sc->txring_tl_ptr] = NULL;
 662                 m_freem(m);
 663
 664                 /* Check the status. */
 665                 if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) {
 666                         /* Serious bus error. log to console. */
 667                         device_printf(sc->dev, "cgem_clean_tx: Whoa! "
 668                                    "AHB error, addr=0x%x\n",
 669                                    sc->txring[sc->txring_tl_ptr].addr);
 670                 } else if ((ctl & (CGEM_TXDESC_RETRY_ERR |
 671                                    CGEM_TXDESC_LATE_COLL)) != 0) {
 672                         if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
 673                 } else
 674                         if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
 675
 676                 /* If the packet spanned more than one tx descriptor,
 677                  * skip descriptors until we find the end so that only
 678                  * start-of-frame descriptors are processed.
 679                  */
 680                 while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) {
 681                         if ((ctl & CGEM_TXDESC_WRAP) != 0)
 682                                 sc->txring_tl_ptr = 0;
 683                         else
 684                                 sc->txring_tl_ptr++;
 685                         sc->txring_queued--;
 686
 687                         ctl = sc->txring[sc->txring_tl_ptr].ctl;
 688
 689                         sc->txring[sc->txring_tl_ptr].ctl =
 690                                 ctl | CGEM_TXDESC_USED;
 691                 }
 692
 693                 /* Next descriptor. */
 694                 if ((ctl & CGEM_TXDESC_WRAP) != 0)
 695                         sc->txring_tl_ptr = 0;
 696                 else
 697                         sc->txring_tl_ptr++;
 698                 sc->txring_queued--;
 699
 700                 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
 701         }
 702 }
 703
 704 /* Start transmits. */
 705 static void
 706 cgem_start_locked(if_t ifp)
 707 {
 708         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
 709         struct mbuf *m;
 710         bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
 711         uint32_t ctl;
 712         int i, nsegs, wrap, err;
 713
 714         CGEM_ASSERT_LOCKED(sc);
 715
 716         if ((if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0)
 717                 return;
 718
 719         for (;;) {
 720                 /* Check that there is room in the descriptor ring. */
 721                 if (sc->txring_queued >=
 722                     CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
 723
 724                         /* Try to make room. */
 725                         cgem_clean_tx(sc);
 726
 727                         /* Still no room? */
 728                         if (sc->txring_queued >=
 729                             CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
 730                                 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
 731                                 sc->txfull++;
 732                                 break;
 733                         }
 734                 }
 735
 736                 /* Grab next transmit packet. */
 737                 m = if_dequeue(ifp);
 738                 if (m == NULL)
 739                         break;
 740
 741                 /* Create and load DMA map. */
 742                 if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
 743                               &sc->txring_m_dmamap[sc->txring_hd_ptr])) {
 744                         m_freem(m);
 745                         sc->txdmamapfails++;
 746                         continue;
 747                 }
 748                 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 749                                       sc->txring_m_dmamap[sc->txring_hd_ptr],
 750                                       m, segs, &nsegs, BUS_DMA_NOWAIT);
 751                 if (err == EFBIG) {
 752                         /* Too many segments!  defrag and try again. */
 753                         struct mbuf *m2 = m_defrag(m, M_NOWAIT);
 754
 755                         if (m2 == NULL) {
 756                                 sc->txdefragfails++;
 757                                 m_freem(m);
 758                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 759                                    sc->txring_m_dmamap[sc->txring_hd_ptr]);
 760                                 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
 761                                 continue;
 762                         }
 763                         m = m2;
 764                         err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 765                                       sc->txring_m_dmamap[sc->txring_hd_ptr],
 766                                       m, segs, &nsegs, BUS_DMA_NOWAIT);
 767                         sc->txdefrags++;
 768                 }
 769                 if (err) {
 770                         /* Give up. */
 771                         m_freem(m);
 772                         bus_dmamap_destroy(sc->mbuf_dma_tag,
 773                                    sc->txring_m_dmamap[sc->txring_hd_ptr]);
 774                         sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
 775                         sc->txdmamapfails++;
 776                         continue;
 777                 }
 778                 sc->txring_m[sc->txring_hd_ptr] = m;
 779
 780                 /* Sync tx buffer with cache. */
 781                 bus_dmamap_sync(sc->mbuf_dma_tag,
 782                                 sc->txring_m_dmamap[sc->txring_hd_ptr],
 783                                 BUS_DMASYNC_PREWRITE);
 784
 785                 /* Set wrap flag if next packet might run off end of ring. */
 786                 wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >=
 787                         CGEM_NUM_TX_DESCS;
 788
 789                 /* Fill in the TX descriptors back to front so that USED
 790                  * bit in first descriptor is cleared last.
 791                  */
 792                 for (i = nsegs - 1; i >= 0; i--) {
 793                         /* Descriptor address. */
 794                         sc->txring[sc->txring_hd_ptr + i].addr =
 795                                 segs[i].ds_addr;
 796
 797                         /* Descriptor control word. */
 798                         ctl = segs[i].ds_len;
 799                         if (i == nsegs - 1) {
 800                                 ctl |= CGEM_TXDESC_LAST_BUF;
 801                                 if (wrap)
 802                                         ctl |= CGEM_TXDESC_WRAP;
 803                         }
 804                         sc->txring[sc->txring_hd_ptr + i].ctl = ctl;
 805
 806                         if (i != 0)
 807                                 sc->txring_m[sc->txring_hd_ptr + i] = NULL;
 808                 }
 809
 810                 if (wrap)
 811                         sc->txring_hd_ptr = 0;
 812                 else
 813                         sc->txring_hd_ptr += nsegs;
 814                 sc->txring_queued += nsegs;
 815
 816                 /* Kick the transmitter. */
 817                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
 818                     CGEM_NET_CTRL_START_TX);
 819
 820                 /* If there is a BPF listener, bounce a copy to him. */
 821                 ETHER_BPF_MTAP(ifp, m);
 822         }
 823 }
 824
 825 static void
 826 cgem_start(if_t ifp)
 827 {
 828         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
 829
 830         CGEM_LOCK(sc);
 831         cgem_start_locked(ifp);
 832         CGEM_UNLOCK(sc);
 833 }
 834
 835 static void
 836 cgem_poll_hw_stats(struct cgem_softc *sc)
 837 {
 838         uint32_t n;
 839
 840         CGEM_ASSERT_LOCKED(sc);
 841
 842         sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
 843         sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
 844
 845         sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
 846         sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
 847         sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
 848         sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX);
 849         sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX);
 850         sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX);
 851         sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX);
 852         sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX);
 853         sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX);
 854         sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX);
 855         sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS);
 856
 857         n = RD4(sc, CGEM_SINGLE_COLL_FRAMES);
 858         sc->stats.tx_single_collisn += n;
 859         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 860         n = RD4(sc, CGEM_MULTI_COLL_FRAMES);
 861         sc->stats.tx_multi_collisn += n;
 862         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 863         n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES);
 864         sc->stats.tx_excsv_collisn += n;
 865         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 866         n = RD4(sc, CGEM_LATE_COLL);
 867         sc->stats.tx_late_collisn += n;
 868         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 869
 870         sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES);
 871         sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS);
 872
 873         sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT);
 874         sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32;
 875
 876         sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX);
 877         sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX);
 878         sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX);
 879         sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX);
 880         sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX);
 881         sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX);
 882         sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX);
 883         sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX);
 884         sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX);
 885         sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX);
 886         sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX);
 887         sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX);
 888         sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX);
 889         sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS);
 890         sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS);
 891         sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS);
 892         sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS);
 893         sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS);
 894         sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS);
 895         sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS);
 896         sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS);
 897         sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS);
 898 }
 899
 900 static void
 901 cgem_tick(void *arg)
 902 {
 903         struct cgem_softc *sc = (struct cgem_softc *)arg;
 904         struct mii_data *mii;
 905
 906         CGEM_ASSERT_LOCKED(sc);
 907
 908         /* Poll the phy. */
 909         if (sc->miibus != NULL) {
 910                 mii = device_get_softc(sc->miibus);
 911                 mii_tick(mii);
 912         }
 913
 914         /* Poll statistics registers. */
 915         cgem_poll_hw_stats(sc);
 916
 917         /* Check for receiver hang. */
 918         if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) {
 919                 /*
 920                  * Reset receiver logic by toggling RX_EN bit.  1usec
 921                  * delay is necessary especially when operating at 100mbps
 922                  * and 10mbps speeds.
 923                  */
 924                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &
 925                     ~CGEM_NET_CTRL_RX_EN);
 926                 DELAY(1);
 927                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
 928         }
 929         sc->rx_frames_prev = sc->stats.rx_frames;
 930
 931         /* Next callout in one second. */
 932         callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
 933 }
 934
 935 /* Interrupt handler. */
 936 static void
 937 cgem_intr(void *arg)
 938 {
 939         struct cgem_softc *sc = (struct cgem_softc *)arg;
 940         if_t ifp = sc->ifp;
 941         uint32_t istatus;
 942
 943         CGEM_LOCK(sc);
 944
 945         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
 946                 CGEM_UNLOCK(sc);
 947                 return;
 948         }
 949
 950         /* Read interrupt status and immediately clear the bits. */
 951         istatus = RD4(sc, CGEM_INTR_STAT);
 952         WR4(sc, CGEM_INTR_STAT, istatus);
 953
 954         /* Packets received. */
 955         if ((istatus & CGEM_INTR_RX_COMPLETE) != 0)
 956                 cgem_recv(sc);
 957
 958         /* Free up any completed transmit buffers. */
 959         cgem_clean_tx(sc);
 960
 961         /* Hresp not ok.  Something is very bad with DMA.  Try to clear. */
 962         if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) {
 963                 device_printf(sc->dev, "cgem_intr: hresp not okay! "
 964                               "rx_status=0x%x\n", RD4(sc, CGEM_RX_STAT));
 965                 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);
 966         }
 967
 968         /* Receiver overrun. */
 969         if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) {
 970                 /* Clear status bit. */
 971                 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);
 972                 sc->rxoverruns++;
 973         }
 974
 975         /* Receiver ran out of bufs. */
 976         if ((istatus & CGEM_INTR_RX_USED_READ) != 0) {
 977                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
 978                     CGEM_NET_CTRL_FLUSH_DPRAM_PKT);
 979                 cgem_fill_rqueue(sc);
 980                 sc->rxnobufs++;
 981         }
 982
 983         /* Restart transmitter if needed. */
 984         if (!if_sendq_empty(ifp))
 985                 cgem_start_locked(ifp);
 986
 987         CGEM_UNLOCK(sc);
 988 }
 989
 990 /* Reset hardware. */
 991 static void
 992 cgem_reset(struct cgem_softc *sc)
 993 {
 994
 995         CGEM_ASSERT_LOCKED(sc);
 996
 997         WR4(sc, CGEM_NET_CTRL, 0);
 998         WR4(sc, CGEM_NET_CFG, 0);
 999         WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
1000         WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
1001         WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
1002         WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);
1003         WR4(sc, CGEM_HASH_BOT, 0);
1004         WR4(sc, CGEM_HASH_TOP, 0);
1005         WR4(sc, CGEM_TX_QBAR, 0);       /* manual says do this. */
1006         WR4(sc, CGEM_RX_QBAR, 0);
1007
1008         /* Get management port running even if interface is down. */
1009         WR4(sc, CGEM_NET_CFG,
1010             CGEM_NET_CFG_DBUS_WIDTH_32 |
1011             CGEM_NET_CFG_MDC_CLK_DIV_64);
1012
1013         sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN;
1014         WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1015 }
1016
1017 /* Bring up the hardware. */
1018 static void
1019 cgem_config(struct cgem_softc *sc)
1020 {
1021         if_t ifp = sc->ifp;
1022         uint32_t net_cfg;
1023         uint32_t dma_cfg;
1024         u_char *eaddr = if_getlladdr(ifp);
1025
1026         CGEM_ASSERT_LOCKED(sc);
1027
1028         /* Program Net Config Register. */
1029         net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 |
1030                 CGEM_NET_CFG_MDC_CLK_DIV_64 |
1031                 CGEM_NET_CFG_FCS_REMOVE |
1032                 CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) |
1033                 CGEM_NET_CFG_GIGE_EN |
1034                 CGEM_NET_CFG_1536RXEN |
1035                 CGEM_NET_CFG_FULL_DUPLEX |
1036                 CGEM_NET_CFG_SPEED100;
1037
1038         /* Enable receive checksum offloading? */
1039         if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1040                 net_cfg |=  CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
1041
1042         WR4(sc, CGEM_NET_CFG, net_cfg);
1043
1044         /* Program DMA Config Register. */
1045         dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) |
1046                 CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K |
1047                 CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL |
1048                 CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 |
1049                 CGEM_DMA_CFG_DISC_WHEN_NO_AHB;
1050
1051         /* Enable transmit checksum offloading? */
1052         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1053                 dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN;
1054
1055         WR4(sc, CGEM_DMA_CFG, dma_cfg);
1056
1057         /* Write the rx and tx descriptor ring addresses to the QBAR regs. */
1058         WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr);
1059         WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr);
1060
1061         /* Enable rx and tx. */
1062         sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN);
1063         WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1064
1065         /* Set receive address in case it changed. */
1066         WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
1067             (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]);
1068         WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
1069
1070         /* Set up interrupts. */
1071         WR4(sc, CGEM_INTR_EN,
1072             CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN |
1073             CGEM_INTR_TX_USED_READ | CGEM_INTR_RX_USED_READ |
1074             CGEM_INTR_HRESP_NOT_OK);
1075 }
1076
1077 /* Turn on interface and load up receive ring with buffers. */
1078 static void
1079 cgem_init_locked(struct cgem_softc *sc)
1080 {
1081         struct mii_data *mii;
1082
1083         CGEM_ASSERT_LOCKED(sc);
1084
1085         if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0)
1086                 return;
1087
1088         cgem_config(sc);
1089         cgem_fill_rqueue(sc);
1090
1091         if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1092
1093         mii = device_get_softc(sc->miibus);
1094         mii_mediachg(mii);
1095
1096         callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
1097 }
1098
1099 static void
1100 cgem_init(void *arg)
1101 {
1102         struct cgem_softc *sc = (struct cgem_softc *)arg;
1103
1104         CGEM_LOCK(sc);
1105         cgem_init_locked(sc);
1106         CGEM_UNLOCK(sc);
1107 }
1108
1109 /* Turn off interface.  Free up any buffers in transmit or receive queues. */
1110 static void
1111 cgem_stop(struct cgem_softc *sc)
1112 {
1113         int i;
1114
1115         CGEM_ASSERT_LOCKED(sc);
1116
1117         callout_stop(&sc->tick_ch);
1118
1119         /* Shut down hardware. */
1120         cgem_reset(sc);
1121
1122         /* Clear out transmit queue. */
1123         for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
1124                 sc->txring[i].ctl = CGEM_TXDESC_USED;
1125                 sc->txring[i].addr = 0;
1126                 if (sc->txring_m[i]) {
1127                         /* Unload and destroy dmamap. */
1128                         bus_dmamap_unload(sc->mbuf_dma_tag,
1129                                           sc->txring_m_dmamap[i]);
1130                         bus_dmamap_destroy(sc->mbuf_dma_tag,
1131                                            sc->txring_m_dmamap[i]);
1132                         sc->txring_m_dmamap[i] = NULL;
1133                         m_freem(sc->txring_m[i]);
1134                         sc->txring_m[i] = NULL;
1135                 }
1136         }
1137         sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP;
1138
1139         sc->txring_hd_ptr = 0;
1140         sc->txring_tl_ptr = 0;
1141         sc->txring_queued = 0;
1142
1143         /* Clear out receive queue. */
1144         for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
1145                 sc->rxring[i].addr = CGEM_RXDESC_OWN;
1146                 sc->rxring[i].ctl = 0;
1147                 if (sc->rxring_m[i]) {
1148                         /* Unload and destroy dmamap. */
1149                         bus_dmamap_unload(sc->mbuf_dma_tag,
1150                                   sc->rxring_m_dmamap[i]);
1151                         bus_dmamap_destroy(sc->mbuf_dma_tag,
1152                                    sc->rxring_m_dmamap[i]);
1153                         sc->rxring_m_dmamap[i] = NULL;
1154
1155                         m_freem(sc->rxring_m[i]);
1156                         sc->rxring_m[i] = NULL;
1157                 }
1158         }
1159         sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP;
1160
1161         sc->rxring_hd_ptr = 0;
1162         sc->rxring_tl_ptr = 0;
1163         sc->rxring_queued = 0;
1164
1165         /* Force next statchg or linkchg to program net config register. */
1166         sc->mii_media_active = 0;
1167 }
1168
1169
1170 static int
1171 cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
1172 {
1173         struct cgem_softc *sc = if_getsoftc(ifp);
1174         struct ifreq *ifr = (struct ifreq *)data;
1175         struct mii_data *mii;
1176         int error = 0, mask;
1177
1178         switch (cmd) {
1179         case SIOCSIFFLAGS:
1180                 CGEM_LOCK(sc);
1181                 if ((if_getflags(ifp) & IFF_UP) != 0) {
1182                         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1183                                 if (((if_getflags(ifp) ^ sc->if_old_flags) &
1184                                      (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1185                                         cgem_rx_filter(sc);
1186                                 }
1187                         } else {
1188                                 cgem_init_locked(sc);
1189                         }
1190                 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1191                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1192                         cgem_stop(sc);
1193                 }
1194                 sc->if_old_flags = if_getflags(ifp);
1195                 CGEM_UNLOCK(sc);
1196                 break;
1197
1198         case SIOCADDMULTI:
1199         case SIOCDELMULTI:
1200                 /* Set up multi-cast filters. */
1201                 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1202                         CGEM_LOCK(sc);
1203                         cgem_rx_filter(sc);
1204                         CGEM_UNLOCK(sc);
1205                 }
1206                 break;
1207
1208         case SIOCSIFMEDIA:
1209         case SIOCGIFMEDIA:
1210                 mii = device_get_softc(sc->miibus);
1211                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1212                 break;
1213
1214         case SIOCSIFCAP:
1215                 CGEM_LOCK(sc);
1216                 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
1217
1218                 if ((mask & IFCAP_TXCSUM) != 0) {
1219                         if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) {
1220                                 /* Turn on TX checksumming. */
1221                                 if_setcapenablebit(ifp, IFCAP_TXCSUM |
1222                                                    IFCAP_TXCSUM_IPV6, 0);
1223                                 if_sethwassistbits(ifp, CGEM_CKSUM_ASSIST, 0);
1224
1225                                 WR4(sc, CGEM_DMA_CFG,
1226                                     RD4(sc, CGEM_DMA_CFG) |
1227                                      CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1228                         } else {
1229                                 /* Turn off TX checksumming. */
1230                                 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM |
1231                                                    IFCAP_TXCSUM_IPV6);
1232                                 if_sethwassistbits(ifp, 0, CGEM_CKSUM_ASSIST);
1233
1234                                 WR4(sc, CGEM_DMA_CFG,
1235                                     RD4(sc, CGEM_DMA_CFG) &
1236                                      ~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1237                         }
1238                 }
1239                 if ((mask & IFCAP_RXCSUM) != 0) {
1240                         if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) {
1241                                 /* Turn on RX checksumming. */
1242                                 if_setcapenablebit(ifp, IFCAP_RXCSUM |
1243                                                    IFCAP_RXCSUM_IPV6, 0);
1244                                 WR4(sc, CGEM_NET_CFG,
1245                                     RD4(sc, CGEM_NET_CFG) |
1246                                      CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1247                         } else {
1248                                 /* Turn off RX checksumming. */
1249                                 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM |
1250                                                    IFCAP_RXCSUM_IPV6);
1251                                 WR4(sc, CGEM_NET_CFG,
1252                                     RD4(sc, CGEM_NET_CFG) &
1253                                      ~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1254                         }
1255                 }
1256                 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) ==
1257                     (IFCAP_RXCSUM | IFCAP_TXCSUM))
1258                         if_setcapenablebit(ifp, IFCAP_VLAN_HWCSUM, 0);
1259                 else
1260                         if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM);
1261
1262                 CGEM_UNLOCK(sc);
1263                 break;
1264         default:
1265                 error = ether_ioctl(ifp, cmd, data);
1266                 break;
1267         }
1268
1269         return (error);
1270 }
1271
1272 /* MII bus support routines.
1273  */
1274 static void
1275 cgem_child_detached(device_t dev, device_t child)
1276 {
1277         struct cgem_softc *sc = device_get_softc(dev);
1278
1279         if (child == sc->miibus)
1280                 sc->miibus = NULL;
1281 }
1282
1283 static int
1284 cgem_ifmedia_upd(if_t ifp)
1285 {
1286         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
1287         struct mii_data *mii;
1288         struct mii_softc *miisc;
1289         int error = 0;
1290
1291         mii = device_get_softc(sc->miibus);
1292         CGEM_LOCK(sc);
1293         if ((if_getflags(ifp) & IFF_UP) != 0) {
1294                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1295                         PHY_RESET(miisc);
1296                 error = mii_mediachg(mii);
1297         }
1298         CGEM_UNLOCK(sc);
1299
1300         return (error);
1301 }
1302
1303 static void
1304 cgem_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1305 {
1306         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
1307         struct mii_data *mii;
1308
1309         mii = device_get_softc(sc->miibus);
1310         CGEM_LOCK(sc);
1311         mii_pollstat(mii);
1312         ifmr->ifm_active = mii->mii_media_active;
1313         ifmr->ifm_status = mii->mii_media_status;
1314         CGEM_UNLOCK(sc);
1315 }
1316
1317 static int
1318 cgem_miibus_readreg(device_t dev, int phy, int reg)
1319 {
1320         struct cgem_softc *sc = device_get_softc(dev);
1321         int tries, val;
1322
1323         WR4(sc, CGEM_PHY_MAINT,
1324             CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 |
1325             CGEM_PHY_MAINT_OP_READ |
1326             (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1327             (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT));
1328
1329         /* Wait for completion. */
1330         tries=0;
1331         while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1332                 DELAY(5);
1333                 if (++tries > 200) {
1334                         device_printf(dev, "phy read timeout: %d\n", reg);
1335                         return (-1);
1336                 }
1337         }
1338
1339         val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK;
1340
1341         if (reg == MII_EXTSR)
1342                 /*
1343                  * MAC does not support half-duplex at gig speeds.
1344                  * Let mii(4) exclude the capability.
1345                  */
1346                 val &= ~(EXTSR_1000XHDX | EXTSR_1000THDX);
1347
1348         return (val);
1349 }
1350
1351 static int
1352 cgem_miibus_writereg(device_t dev, int phy, int reg, int data)
1353 {
1354         struct cgem_softc *sc = device_get_softc(dev);
1355         int tries;
1356
1357         WR4(sc, CGEM_PHY_MAINT,
1358             CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 |
1359             CGEM_PHY_MAINT_OP_WRITE |
1360             (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1361             (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) |
1362             (data & CGEM_PHY_MAINT_DATA_MASK));
1363
1364         /* Wait for completion. */
1365         tries = 0;
1366         while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1367                 DELAY(5);
1368                 if (++tries > 200) {
1369                         device_printf(dev, "phy write timeout: %d\n", reg);
1370                         return (-1);
1371                 }
1372         }
1373
1374         return (0);
1375 }
1376
1377 static void
1378 cgem_miibus_statchg(device_t dev)
1379 {
1380         struct cgem_softc *sc  = device_get_softc(dev);
1381         struct mii_data *mii = device_get_softc(sc->miibus);
1382
1383         CGEM_ASSERT_LOCKED(sc);
1384
1385         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1386             (IFM_ACTIVE | IFM_AVALID) &&
1387             sc->mii_media_active != mii->mii_media_active)
1388                 cgem_mediachange(sc, mii);
1389 }
1390
1391 static void
1392 cgem_miibus_linkchg(device_t dev)
1393 {
1394         struct cgem_softc *sc  = device_get_softc(dev);
1395         struct mii_data *mii = device_get_softc(sc->miibus);
1396
1397         CGEM_ASSERT_LOCKED(sc);
1398
1399         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1400             (IFM_ACTIVE | IFM_AVALID) &&
1401             sc->mii_media_active != mii->mii_media_active)
1402                 cgem_mediachange(sc, mii);
1403 }
1404
1405 /*
1406  * Overridable weak symbol cgem_set_ref_clk().  This allows platforms to
1407  * provide a function to set the cgem's reference clock.
1408  */
1409 static int __used
1410 cgem_default_set_ref_clk(int unit, int frequency)
1411 {
1412
1413         return 0;
1414 }
1415 __weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk);
1416
1417 /* Call to set reference clock and network config bits according to media. */
1418 static void
1419 cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii)
1420 {
1421         uint32_t net_cfg;
1422         int ref_clk_freq;
1423
1424         CGEM_ASSERT_LOCKED(sc);
1425
1426         /* Update hardware to reflect media. */
1427         net_cfg = RD4(sc, CGEM_NET_CFG);
1428         net_cfg &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN |
1429                      CGEM_NET_CFG_FULL_DUPLEX);
1430
1431         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1432         case IFM_1000_T:
1433                 net_cfg |= (CGEM_NET_CFG_SPEED100 |
1434                             CGEM_NET_CFG_GIGE_EN);
1435                 ref_clk_freq = 125000000;
1436                 break;
1437         case IFM_100_TX:
1438                 net_cfg |= CGEM_NET_CFG_SPEED100;
1439                 ref_clk_freq = 25000000;
1440                 break;
1441         default:
1442                 ref_clk_freq = 2500000;
1443         }
1444
1445         if ((mii->mii_media_active & IFM_FDX) != 0)
1446                 net_cfg |= CGEM_NET_CFG_FULL_DUPLEX;
1447
1448         WR4(sc, CGEM_NET_CFG, net_cfg);
1449
1450         /* Set the reference clock if necessary. */
1451         if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq))
1452                 device_printf(sc->dev, "cgem_mediachange: "
1453                               "could not set ref clk%d to %d.\n",
1454                               sc->ref_clk_num, ref_clk_freq);
1455
1456         sc->mii_media_active = mii->mii_media_active;
1457 }
1458
1459 static void
1460 cgem_add_sysctls(device_t dev)
1461 {
1462         struct cgem_softc *sc = device_get_softc(dev);
1463         struct sysctl_ctx_list *ctx;
1464         struct sysctl_oid_list *child;
1465         struct sysctl_oid *tree;
1466
1467         ctx = device_get_sysctl_ctx(dev);
1468         child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
1469
1470         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW,
1471                        &sc->rxbufs, 0,
1472                        "Number receive buffers to provide");
1473
1474         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW,
1475                        &sc->rxhangwar, 0,
1476                        "Enable receive hang work-around");
1477
1478         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD,
1479                         &sc->rxoverruns, 0,
1480                         "Receive overrun events");
1481
1482         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD,
1483                         &sc->rxnobufs, 0,
1484                         "Receive buf queue empty events");
1485
1486         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD,
1487                         &sc->rxdmamapfails, 0,
1488                         "Receive DMA map failures");
1489
1490         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD,
1491                         &sc->txfull, 0,
1492                         "Transmit ring full events");
1493
1494         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD,
1495                         &sc->txdmamapfails, 0,
1496                         "Transmit DMA map failures");
1497
1498         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD,
1499                         &sc->txdefrags, 0,
1500                         "Transmit m_defrag() calls");
1501
1502         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD,
1503                         &sc->txdefragfails, 0,
1504                         "Transmit m_defrag() failures");
1505
1506         tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
1507                                NULL, "GEM statistics");
1508         child = SYSCTL_CHILDREN(tree);
1509
1510         SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD,
1511                          &sc->stats.tx_bytes, "Total bytes transmitted");
1512
1513         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD,
1514                         &sc->stats.tx_frames, 0, "Total frames transmitted");
1515         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD,
1516                         &sc->stats.tx_frames_bcast, 0,
1517                         "Number broadcast frames transmitted");
1518         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD,
1519                         &sc->stats.tx_frames_multi, 0,
1520                         "Number multicast frames transmitted");
1521         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause",
1522                         CTLFLAG_RD, &sc->stats.tx_frames_pause, 0,
1523                         "Number pause frames transmitted");
1524         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD,
1525                         &sc->stats.tx_frames_64b, 0,
1526                         "Number frames transmitted of size 64 bytes or less");
1527         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD,
1528                         &sc->stats.tx_frames_65to127b, 0,
1529                         "Number frames transmitted of size 65-127 bytes");
1530         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b",
1531                         CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0,
1532                         "Number frames transmitted of size 128-255 bytes");
1533         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b",
1534                         CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0,
1535                         "Number frames transmitted of size 256-511 bytes");
1536         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b",
1537                         CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0,
1538                         "Number frames transmitted of size 512-1023 bytes");
1539         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b",
1540                         CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0,
1541                         "Number frames transmitted of size 1024-1536 bytes");
1542         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs",
1543                         CTLFLAG_RD, &sc->stats.tx_under_runs, 0,
1544                         "Number transmit under-run events");
1545         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn",
1546                         CTLFLAG_RD, &sc->stats.tx_single_collisn, 0,
1547                         "Number single-collision transmit frames");
1548         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn",
1549                         CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0,
1550                         "Number multi-collision transmit frames");
1551         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn",
1552                         CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0,
1553                         "Number excessive collision transmit frames");
1554         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn",
1555                         CTLFLAG_RD, &sc->stats.tx_late_collisn, 0,
1556                         "Number late-collision transmit frames");
1557         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames",
1558                         CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0,
1559                         "Number deferred transmit frames");
1560         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs",
1561                         CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0,
1562                         "Number carrier sense errors on transmit");
1563
1564         SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD,
1565                          &sc->stats.rx_bytes, "Total bytes received");
1566
1567         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD,
1568                         &sc->stats.rx_frames, 0, "Total frames received");
1569         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast",
1570                         CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0,
1571                         "Number broadcast frames received");
1572         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi",
1573                         CTLFLAG_RD, &sc->stats.rx_frames_multi, 0,
1574                         "Number multicast frames received");
1575         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause",
1576                         CTLFLAG_RD, &sc->stats.rx_frames_pause, 0,
1577                         "Number pause frames received");
1578         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b",
1579                         CTLFLAG_RD, &sc->stats.rx_frames_64b, 0,
1580                         "Number frames received of size 64 bytes or less");
1581         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b",
1582                         CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0,
1583                         "Number frames received of size 65-127 bytes");
1584         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b",
1585                         CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0,
1586                         "Number frames received of size 128-255 bytes");
1587         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b",
1588                         CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0,
1589                         "Number frames received of size 256-511 bytes");
1590         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b",
1591                         CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0,
1592                         "Number frames received of size 512-1023 bytes");
1593         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b",
1594                         CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0,
1595                         "Number frames received of size 1024-1536 bytes");
1596         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize",
1597                         CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0,
1598                         "Number undersize frames received");
1599         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize",
1600                         CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0,
1601                         "Number oversize frames received");
1602         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber",
1603                         CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0,
1604                         "Number jabber frames received");
1605         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs",
1606                         CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0,
1607                         "Number frames received with FCS errors");
1608         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs",
1609                         CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0,
1610                         "Number frames received with length errors");
1611         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs",
1612                         CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0,
1613                         "Number receive symbol errors");
1614         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs",
1615                         CTLFLAG_RD, &sc->stats.rx_align_errs, 0,
1616                         "Number receive alignment errors");
1617         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs",
1618                         CTLFLAG_RD, &sc->stats.rx_resource_errs, 0,
1619                         "Number frames received when no rx buffer available");
1620         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs",
1621                         CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0,
1622                         "Number frames received but not copied due to "
1623                         "receive overrun");
1624         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs",
1625                         CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0,
1626                         "Number frames received with IP header checksum "
1627                         "errors");
1628         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs",
1629                         CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0,
1630                         "Number frames received with TCP checksum errors");
1631         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs",
1632                         CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0,
1633                         "Number frames received with UDP checksum errors");
1634 }
1635
1636
1637 static int
1638 cgem_probe(device_t dev)
1639 {
1640
1641         if (!ofw_bus_status_okay(dev))
1642                 return (ENXIO);
1643
1644         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1645                 return (ENXIO);
1646
1647         device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface");
1648         return (0);
1649 }
1650
1651 static int
1652 cgem_attach(device_t dev)
1653 {
1654         struct cgem_softc *sc = device_get_softc(dev);
1655         if_t ifp = NULL;
1656         phandle_t node;
1657         pcell_t cell;
1658         int rid, err;
1659         u_char eaddr[ETHER_ADDR_LEN];
1660
1661         sc->dev = dev;
1662         CGEM_LOCK_INIT(sc);
1663
1664         /* Get reference clock number and base divider from fdt. */
1665         node = ofw_bus_get_node(dev);
1666         sc->ref_clk_num = 0;
1667         if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0)
1668                 sc->ref_clk_num = fdt32_to_cpu(cell);
1669
1670         /* Get memory resource. */
1671         rid = 0;
1672         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1673                                              RF_ACTIVE);
1674         if (sc->mem_res == NULL) {
1675                 device_printf(dev, "could not allocate memory resources.\n");
1676                 return (ENOMEM);
1677         }
1678
1679         /* Get IRQ resource. */
1680         rid = 0;
1681         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1682                                              RF_ACTIVE);
1683         if (sc->irq_res == NULL) {
1684                 device_printf(dev, "could not allocate interrupt resource.\n");
1685                 cgem_detach(dev);
1686                 return (ENOMEM);
1687         }
1688
1689         /* Set up ifnet structure. */
1690         ifp = sc->ifp = if_alloc(IFT_ETHER);
1691         if (ifp == NULL) {
1692                 device_printf(dev, "could not allocate ifnet structure\n");
1693                 cgem_detach(dev);
1694                 return (ENOMEM);
1695         }
1696         if_setsoftc(ifp, sc);
1697         if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev));
1698         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1699         if_setinitfn(ifp, cgem_init);
1700         if_setioctlfn(ifp, cgem_ioctl);
1701         if_setstartfn(ifp, cgem_start);
1702         if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
1703                               IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM, 0);
1704         if_setsendqlen(ifp, CGEM_NUM_TX_DESCS);
1705         if_setsendqready(ifp);
1706
1707         /* Disable hardware checksumming by default. */
1708         if_sethwassist(ifp, 0);
1709         if_setcapenable(ifp, if_getcapabilities(ifp) &
1710                 ~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM));
1711
1712         sc->if_old_flags = if_getflags(ifp);
1713         sc->rxbufs = DEFAULT_NUM_RX_BUFS;
1714         sc->rxhangwar = 1;
1715
1716         /* Reset hardware. */
1717         CGEM_LOCK(sc);
1718         cgem_reset(sc);
1719         CGEM_UNLOCK(sc);
1720
1721         /* Attach phy to mii bus. */
1722         err = mii_attach(dev, &sc->miibus, ifp,
1723                          cgem_ifmedia_upd, cgem_ifmedia_sts,
1724                          BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1725         if (err) {
1726                 device_printf(dev, "attaching PHYs failed\n");
1727                 cgem_detach(dev);
1728                 return (err);
1729         }
1730
1731         /* Set up TX and RX descriptor area. */
1732         err = cgem_setup_descs(sc);
1733         if (err) {
1734                 device_printf(dev, "could not set up dma mem for descs.\n");
1735                 cgem_detach(dev);
1736                 return (ENOMEM);
1737         }
1738
1739         /* Get a MAC address. */
1740         cgem_get_mac(sc, eaddr);
1741
1742         /* Start ticks. */
1743         callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
1744
1745         ether_ifattach(ifp, eaddr);
1746
1747         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE |
1748                              INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand);
1749         if (err) {
1750                 device_printf(dev, "could not set interrupt handler.\n");
1751                 ether_ifdetach(ifp);
1752                 cgem_detach(dev);
1753                 return (err);
1754         }
1755
1756         cgem_add_sysctls(dev);
1757
1758         return (0);
1759 }
1760
1761 static int
1762 cgem_detach(device_t dev)
1763 {
1764         struct cgem_softc *sc = device_get_softc(dev);
1765         int i;
1766
1767         if (sc == NULL)
1768                 return (ENODEV);
1769
1770         if (device_is_attached(dev)) {
1771                 CGEM_LOCK(sc);
1772                 cgem_stop(sc);
1773                 CGEM_UNLOCK(sc);
1774                 callout_drain(&sc->tick_ch);
1775                 if_setflagbits(sc->ifp, 0, IFF_UP);
1776                 ether_ifdetach(sc->ifp);
1777         }
1778
1779         if (sc->miibus != NULL) {
1780                 device_delete_child(dev, sc->miibus);
1781                 sc->miibus = NULL;
1782         }
1783
1784         /* Release resources. */
1785         if (sc->mem_res != NULL) {
1786                 bus_release_resource(dev, SYS_RES_MEMORY,
1787                                      rman_get_rid(sc->mem_res), sc->mem_res);
1788                 sc->mem_res = NULL;
1789         }
1790         if (sc->irq_res != NULL) {
1791                 if (sc->intrhand)
1792                         bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1793                 bus_release_resource(dev, SYS_RES_IRQ,
1794                                      rman_get_rid(sc->irq_res), sc->irq_res);
1795                 sc->irq_res = NULL;
1796         }
1797
1798         /* Release DMA resources. */
1799         if (sc->rxring != NULL) {
1800                 if (sc->rxring_physaddr != 0) {
1801                         bus_dmamap_unload(sc->desc_dma_tag,
1802                                           sc->rxring_dma_map);
1803                         sc->rxring_physaddr = 0;
1804                 }
1805                 bus_dmamem_free(sc->desc_dma_tag, sc->rxring,
1806                                 sc->rxring_dma_map);
1807                 sc->rxring = NULL;
1808                 for (i = 0; i < CGEM_NUM_RX_DESCS; i++)
1809                         if (sc->rxring_m_dmamap[i] != NULL) {
1810                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
1811                                                    sc->rxring_m_dmamap[i]);
1812                                 sc->rxring_m_dmamap[i] = NULL;
1813                         }
1814         }
1815         if (sc->txring != NULL) {
1816                 if (sc->txring_physaddr != 0) {
1817                         bus_dmamap_unload(sc->desc_dma_tag,
1818                                           sc->txring_dma_map);
1819                         sc->txring_physaddr = 0;
1820                 }
1821                 bus_dmamem_free(sc->desc_dma_tag, sc->txring,
1822                                 sc->txring_dma_map);
1823                 sc->txring = NULL;
1824                 for (i = 0; i < CGEM_NUM_TX_DESCS; i++)
1825                         if (sc->txring_m_dmamap[i] != NULL) {
1826                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
1827                                                    sc->txring_m_dmamap[i]);
1828                                 sc->txring_m_dmamap[i] = NULL;
1829                         }
1830         }
1831         if (sc->desc_dma_tag != NULL) {
1832                 bus_dma_tag_destroy(sc->desc_dma_tag);
1833                 sc->desc_dma_tag = NULL;
1834         }
1835         if (sc->mbuf_dma_tag != NULL) {
1836                 bus_dma_tag_destroy(sc->mbuf_dma_tag);
1837                 sc->mbuf_dma_tag = NULL;
1838         }
1839
1840         bus_generic_detach(dev);
1841
1842         CGEM_LOCK_DESTROY(sc);
1843
1844         return (0);
1845 }
1846
1847 static device_method_t cgem_methods[] = {
1848         /* Device interface */
1849         DEVMETHOD(device_probe,         cgem_probe),
1850         DEVMETHOD(device_attach,        cgem_attach),
1851         DEVMETHOD(device_detach,        cgem_detach),
1852
1853         /* Bus interface */
1854         DEVMETHOD(bus_child_detached,   cgem_child_detached),
1855
1856         /* MII interface */
1857         DEVMETHOD(miibus_readreg,       cgem_miibus_readreg),
1858         DEVMETHOD(miibus_writereg,      cgem_miibus_writereg),
1859         DEVMETHOD(miibus_statchg,       cgem_miibus_statchg),
1860         DEVMETHOD(miibus_linkchg,       cgem_miibus_linkchg),
1861
1862         DEVMETHOD_END
1863 };
1864
1865 static driver_t cgem_driver = {
1866         "cgem",
1867         cgem_methods,
1868         sizeof(struct cgem_softc),
1869 };
1870
1871 DRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL);
1872 DRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL);
1873 MODULE_DEPEND(cgem, miibus, 1, 1, 1);
1874 MODULE_DEPEND(cgem, ether, 1, 1, 1);