sys/dev/cadence/if_cgem.c

   1 /*-
   2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
   3  *
   4  * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * A network interface driver for Cadence GEM Gigabit Ethernet
  31  * interface such as the one used in Xilinx Zynq-7000 SoC.
  32  *
  33  * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
  34  * (v1.4) November 16, 2012.  Xilinx doc UG585.  GEM is covered in Ch. 16
  35  * and register definitions are in appendix B.18.
  36  */
  37
  38 #include <sys/cdefs.h>
  39 __FBSDID("$FreeBSD$");
  40
  41 #include <sys/param.h>
  42 #include <sys/systm.h>
  43 #include <sys/bus.h>
  44 #include <sys/kernel.h>
  45 #include <sys/malloc.h>
  46 #include <sys/mbuf.h>
  47 #include <sys/module.h>
  48 #include <sys/rman.h>
  49 #include <sys/socket.h>
  50 #include <sys/sockio.h>
  51 #include <sys/sysctl.h>
  52
  53 #include <machine/bus.h>
  54
  55 #include <net/ethernet.h>
  56 #include <net/if.h>
  57 #include <net/if_arp.h>
  58 #include <net/if_dl.h>
  59 #include <net/if_media.h>
  60 #include <net/if_mib.h>
  61 #include <net/if_types.h>
  62
  63 #ifdef INET
  64 #include <netinet/in.h>
  65 #include <netinet/in_systm.h>
  66 #include <netinet/in_var.h>
  67 #include <netinet/ip.h>
  68 #endif
  69
  70 #include <net/bpf.h>
  71 #include <net/bpfdesc.h>
  72
  73 #include <dev/fdt/fdt_common.h>
  74 #include <dev/ofw/ofw_bus.h>
  75 #include <dev/ofw/ofw_bus_subr.h>
  76
  77 #include <dev/mii/mii.h>
  78 #include <dev/mii/miivar.h>
  79
  80 #include <dev/cadence/if_cgem_hw.h>
  81
  82 #include "miibus_if.h"
  83
  84 #define IF_CGEM_NAME "cgem"
  85
  86 #define CGEM_NUM_RX_DESCS       512     /* size of receive descriptor ring */
  87 #define CGEM_NUM_TX_DESCS       512     /* size of transmit descriptor ring */
  88
  89 #define MAX_DESC_RING_SIZE (MAX(CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),\
  90                                 CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc)))
  91
  92
  93 /* Default for sysctl rxbufs.  Must be < CGEM_NUM_RX_DESCS of course. */
  94 #define DEFAULT_NUM_RX_BUFS     256     /* number of receive bufs to queue. */
  95
  96 #define TX_MAX_DMA_SEGS         8       /* maximum segs in a tx mbuf dma */
  97
  98 #define CGEM_CKSUM_ASSIST       (CSUM_IP | CSUM_TCP | CSUM_UDP | \
  99                                  CSUM_TCP_IPV6 | CSUM_UDP_IPV6)
 100
 101 static struct ofw_compat_data compat_data[] = {
 102         { "cadence,gem",                1 },
 103         { "cdns,macb",                  1 },
 104         { "sifive,fu540-c000-gem",      1 },
 105         { NULL,                         0 },
 106 };
 107
 108 struct cgem_softc {
 109         if_t                    ifp;
 110         struct mtx              sc_mtx;
 111         device_t                dev;
 112         device_t                miibus;
 113         u_int                   mii_media_active;       /* last active media */
 114         int                     if_old_flags;
 115         struct resource         *mem_res;
 116         struct resource         *irq_res;
 117         void                    *intrhand;
 118         struct callout          tick_ch;
 119         uint32_t                net_ctl_shadow;
 120         int                     ref_clk_num;
 121         u_char                  eaddr[6];
 122
 123         bus_dma_tag_t           desc_dma_tag;
 124         bus_dma_tag_t           mbuf_dma_tag;
 125
 126         /* receive descriptor ring */
 127         struct cgem_rx_desc     *rxring;
 128         bus_addr_t              rxring_physaddr;
 129         struct mbuf             *rxring_m[CGEM_NUM_RX_DESCS];
 130         bus_dmamap_t            rxring_m_dmamap[CGEM_NUM_RX_DESCS];
 131         int                     rxring_hd_ptr;  /* where to put rcv bufs */
 132         int                     rxring_tl_ptr;  /* where to get receives */
 133         int                     rxring_queued;  /* how many rcv bufs queued */
 134         bus_dmamap_t            rxring_dma_map;
 135         int                     rxbufs;         /* tunable number rcv bufs */
 136         int                     rxhangwar;      /* rx hang work-around */
 137         u_int                   rxoverruns;     /* rx overruns */
 138         u_int                   rxnobufs;       /* rx buf ring empty events */
 139         u_int                   rxdmamapfails;  /* rx dmamap failures */
 140         uint32_t                rx_frames_prev;
 141
 142         /* transmit descriptor ring */
 143         struct cgem_tx_desc     *txring;
 144         bus_addr_t              txring_physaddr;
 145         struct mbuf             *txring_m[CGEM_NUM_TX_DESCS];
 146         bus_dmamap_t            txring_m_dmamap[CGEM_NUM_TX_DESCS];
 147         int                     txring_hd_ptr;  /* where to put next xmits */
 148         int                     txring_tl_ptr;  /* next xmit mbuf to free */
 149         int                     txring_queued;  /* num xmits segs queued */
 150         bus_dmamap_t            txring_dma_map;
 151         u_int                   txfull;         /* tx ring full events */
 152         u_int                   txdefrags;      /* tx calls to m_defrag() */
 153         u_int                   txdefragfails;  /* tx m_defrag() failures */
 154         u_int                   txdmamapfails;  /* tx dmamap failures */
 155
 156         /* hardware provided statistics */
 157         struct cgem_hw_stats {
 158                 uint64_t                tx_bytes;
 159                 uint32_t                tx_frames;
 160                 uint32_t                tx_frames_bcast;
 161                 uint32_t                tx_frames_multi;
 162                 uint32_t                tx_frames_pause;
 163                 uint32_t                tx_frames_64b;
 164                 uint32_t                tx_frames_65to127b;
 165                 uint32_t                tx_frames_128to255b;
 166                 uint32_t                tx_frames_256to511b;
 167                 uint32_t                tx_frames_512to1023b;
 168                 uint32_t                tx_frames_1024to1536b;
 169                 uint32_t                tx_under_runs;
 170                 uint32_t                tx_single_collisn;
 171                 uint32_t                tx_multi_collisn;
 172                 uint32_t                tx_excsv_collisn;
 173                 uint32_t                tx_late_collisn;
 174                 uint32_t                tx_deferred_frames;
 175                 uint32_t                tx_carrier_sense_errs;
 176
 177                 uint64_t                rx_bytes;
 178                 uint32_t                rx_frames;
 179                 uint32_t                rx_frames_bcast;
 180                 uint32_t                rx_frames_multi;
 181                 uint32_t                rx_frames_pause;
 182                 uint32_t                rx_frames_64b;
 183                 uint32_t                rx_frames_65to127b;
 184                 uint32_t                rx_frames_128to255b;
 185                 uint32_t                rx_frames_256to511b;
 186                 uint32_t                rx_frames_512to1023b;
 187                 uint32_t                rx_frames_1024to1536b;
 188                 uint32_t                rx_frames_undersize;
 189                 uint32_t                rx_frames_oversize;
 190                 uint32_t                rx_frames_jabber;
 191                 uint32_t                rx_frames_fcs_errs;
 192                 uint32_t                rx_frames_length_errs;
 193                 uint32_t                rx_symbol_errs;
 194                 uint32_t                rx_align_errs;
 195                 uint32_t                rx_resource_errs;
 196                 uint32_t                rx_overrun_errs;
 197                 uint32_t                rx_ip_hdr_csum_errs;
 198                 uint32_t                rx_tcp_csum_errs;
 199                 uint32_t                rx_udp_csum_errs;
 200         } stats;
 201 };
 202
 203 #define RD4(sc, off)            (bus_read_4((sc)->mem_res, (off)))
 204 #define WR4(sc, off, val)       (bus_write_4((sc)->mem_res, (off), (val)))
 205 #define BARRIER(sc, off, len, flags) \
 206         (bus_barrier((sc)->mem_res, (off), (len), (flags))
 207
 208 #define CGEM_LOCK(sc)           mtx_lock(&(sc)->sc_mtx)
 209 #define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
 210 #define CGEM_LOCK_INIT(sc)      \
 211         mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
 212                  MTX_NETWORK_LOCK, MTX_DEF)
 213 #define CGEM_LOCK_DESTROY(sc)   mtx_destroy(&(sc)->sc_mtx)
 214 #define CGEM_ASSERT_LOCKED(sc)  mtx_assert(&(sc)->sc_mtx, MA_OWNED)
 215
 216 /* Allow platforms to optionally provide a way to set the reference clock. */
 217 int cgem_set_ref_clk(int unit, int frequency);
 218
 219 static devclass_t cgem_devclass;
 220
 221 static int cgem_probe(device_t dev);
 222 static int cgem_attach(device_t dev);
 223 static int cgem_detach(device_t dev);
 224 static void cgem_tick(void *);
 225 static void cgem_intr(void *);
 226
 227 static void cgem_mediachange(struct cgem_softc *, struct mii_data *);
 228
 229 static void
 230 cgem_get_mac(struct cgem_softc *sc, u_char eaddr[])
 231 {
 232         int i;
 233         uint32_t rnd;
 234
 235         /* See if boot loader gave us a MAC address already. */
 236         for (i = 0; i < 4; i++) {
 237                 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i));
 238                 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff;
 239                 if (low != 0 || high != 0) {
 240                         eaddr[0] = low & 0xff;
 241                         eaddr[1] = (low >> 8) & 0xff;
 242                         eaddr[2] = (low >> 16) & 0xff;
 243                         eaddr[3] = (low >> 24) & 0xff;
 244                         eaddr[4] = high & 0xff;
 245                         eaddr[5] = (high >> 8) & 0xff;
 246                         break;
 247                 }
 248         }
 249
 250         /* No MAC from boot loader?  Assign a random one. */
 251         if (i == 4) {
 252                 rnd = arc4random();
 253
 254                 eaddr[0] = 'b';
 255                 eaddr[1] = 's';
 256                 eaddr[2] = 'd';
 257                 eaddr[3] = (rnd >> 16) & 0xff;
 258                 eaddr[4] = (rnd >> 8) & 0xff;
 259                 eaddr[5] = rnd & 0xff;
 260
 261                 device_printf(sc->dev, "no mac address found, assigning "
 262                               "random: %02x:%02x:%02x:%02x:%02x:%02x\n",
 263                               eaddr[0], eaddr[1], eaddr[2],
 264                               eaddr[3], eaddr[4], eaddr[5]);
 265         }
 266
 267         /* Move address to first slot and zero out the rest. */
 268         WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
 269             (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]);
 270         WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
 271
 272         for (i = 1; i < 4; i++) {
 273                 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0);
 274                 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0);
 275         }
 276 }
 277
 278 /* cgem_mac_hash():  map 48-bit address to a 6-bit hash.
 279  * The 6-bit hash corresponds to a bit in a 64-bit hash
 280  * register.  Setting that bit in the hash register enables
 281  * reception of all frames with a destination address that hashes
 282  * to that 6-bit value.
 283  *
 284  * The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech
 285  * Reference Manual.  Bits 0-5 in the hash are the exclusive-or of
 286  * every sixth bit in the destination address.
 287  */
 288 static int
 289 cgem_mac_hash(u_char eaddr[])
 290 {
 291         int hash;
 292         int i, j;
 293
 294         hash = 0;
 295         for (i = 0; i < 6; i++)
 296                 for (j = i; j < 48; j += 6)
 297                         if ((eaddr[j >> 3] & (1 << (j & 7))) != 0)
 298                                 hash ^= (1 << i);
 299
 300         return hash;
 301 }
 302
 303 static u_int
 304 cgem_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
 305 {
 306         uint32_t *hashes = arg;
 307         int index;
 308
 309         index = cgem_mac_hash(LLADDR(sdl));
 310         if (index > 31)
 311                 hashes[0] |= (1 << (index - 32));
 312         else
 313                 hashes[1] |= (1 << index);
 314
 315         return (1);
 316 }
 317
 318 /* After any change in rx flags or multi-cast addresses, set up
 319  * hash registers and net config register bits.
 320  */
 321 static void
 322 cgem_rx_filter(struct cgem_softc *sc)
 323 {
 324         if_t ifp = sc->ifp;
 325         uint32_t hashes[2] = { 0, 0 };
 326         uint32_t net_cfg;
 327
 328         net_cfg = RD4(sc, CGEM_NET_CFG);
 329
 330         net_cfg &= ~(CGEM_NET_CFG_MULTI_HASH_EN |
 331                      CGEM_NET_CFG_NO_BCAST |
 332                      CGEM_NET_CFG_COPY_ALL);
 333
 334         if ((if_getflags(ifp) & IFF_PROMISC) != 0)
 335                 net_cfg |= CGEM_NET_CFG_COPY_ALL;
 336         else {
 337                 if ((if_getflags(ifp) & IFF_BROADCAST) == 0)
 338                         net_cfg |= CGEM_NET_CFG_NO_BCAST;
 339                 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) {
 340                         hashes[0] = 0xffffffff;
 341                         hashes[1] = 0xffffffff;
 342                 } else
 343                         if_foreach_llmaddr(ifp, cgem_hash_maddr, hashes);
 344
 345                 if (hashes[0] != 0 || hashes[1] != 0)
 346                         net_cfg |= CGEM_NET_CFG_MULTI_HASH_EN;
 347         }
 348
 349         WR4(sc, CGEM_HASH_TOP, hashes[0]);
 350         WR4(sc, CGEM_HASH_BOT, hashes[1]);
 351         WR4(sc, CGEM_NET_CFG, net_cfg);
 352 }
 353
 354 /* For bus_dmamap_load() callback. */
 355 static void
 356 cgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 357 {
 358
 359         if (nsegs != 1 || error != 0)
 360                 return;
 361         *(bus_addr_t *)arg = segs[0].ds_addr;
 362 }
 363
 364 /* Create DMA'able descriptor rings. */
 365 static int
 366 cgem_setup_descs(struct cgem_softc *sc)
 367 {
 368         int i, err;
 369
 370         sc->txring = NULL;
 371         sc->rxring = NULL;
 372
 373         /* Allocate non-cached DMA space for RX and TX descriptors.
 374          */
 375         err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
 376                                  BUS_SPACE_MAXADDR_32BIT,
 377                                  BUS_SPACE_MAXADDR,
 378                                  NULL, NULL,
 379                                  MAX_DESC_RING_SIZE,
 380                                  1,
 381                                  MAX_DESC_RING_SIZE,
 382                                  0,
 383                                  busdma_lock_mutex,
 384                                  &sc->sc_mtx,
 385                                  &sc->desc_dma_tag);
 386         if (err)
 387                 return (err);
 388
 389         /* Set up a bus_dma_tag for mbufs. */
 390         err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
 391                                  BUS_SPACE_MAXADDR_32BIT,
 392                                  BUS_SPACE_MAXADDR,
 393                                  NULL, NULL,
 394                                  MCLBYTES,
 395                                  TX_MAX_DMA_SEGS,
 396                                  MCLBYTES,
 397                                  0,
 398                                  busdma_lock_mutex,
 399                                  &sc->sc_mtx,
 400                                  &sc->mbuf_dma_tag);
 401         if (err)
 402                 return (err);
 403
 404         /* Allocate DMA memory in non-cacheable space. */
 405         err = bus_dmamem_alloc(sc->desc_dma_tag,
 406                                (void **)&sc->rxring,
 407                                BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
 408                                &sc->rxring_dma_map);
 409         if (err)
 410                 return (err);
 411
 412         /* Load descriptor DMA memory. */
 413         err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map,
 414                               (void *)sc->rxring,
 415                               CGEM_NUM_RX_DESCS*sizeof(struct cgem_rx_desc),
 416                               cgem_getaddr, &sc->rxring_physaddr,
 417                               BUS_DMA_NOWAIT);
 418         if (err)
 419                 return (err);
 420
 421         /* Initialize RX descriptors. */
 422         for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
 423                 sc->rxring[i].addr = CGEM_RXDESC_OWN;
 424                 sc->rxring[i].ctl = 0;
 425                 sc->rxring_m[i] = NULL;
 426                 sc->rxring_m_dmamap[i] = NULL;
 427         }
 428         sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP;
 429
 430         sc->rxring_hd_ptr = 0;
 431         sc->rxring_tl_ptr = 0;
 432         sc->rxring_queued = 0;
 433
 434         /* Allocate DMA memory for TX descriptors in non-cacheable space. */
 435         err = bus_dmamem_alloc(sc->desc_dma_tag,
 436                                (void **)&sc->txring,
 437                                BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
 438                                &sc->txring_dma_map);
 439         if (err)
 440                 return (err);
 441
 442         /* Load TX descriptor DMA memory. */
 443         err = bus_dmamap_load(sc->desc_dma_tag, sc->txring_dma_map,
 444                               (void *)sc->txring,
 445                               CGEM_NUM_TX_DESCS*sizeof(struct cgem_tx_desc),
 446                               cgem_getaddr, &sc->txring_physaddr,
 447                               BUS_DMA_NOWAIT);
 448         if (err)
 449                 return (err);
 450
 451         /* Initialize TX descriptor ring. */
 452         for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
 453                 sc->txring[i].addr = 0;
 454                 sc->txring[i].ctl = CGEM_TXDESC_USED;
 455                 sc->txring_m[i] = NULL;
 456                 sc->txring_m_dmamap[i] = NULL;
 457         }
 458         sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP;
 459
 460         sc->txring_hd_ptr = 0;
 461         sc->txring_tl_ptr = 0;
 462         sc->txring_queued = 0;
 463
 464         return (0);
 465 }
 466
 467 /* Fill receive descriptor ring with mbufs. */
 468 static void
 469 cgem_fill_rqueue(struct cgem_softc *sc)
 470 {
 471         struct mbuf *m = NULL;
 472         bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
 473         int nsegs;
 474
 475         CGEM_ASSERT_LOCKED(sc);
 476
 477         while (sc->rxring_queued < sc->rxbufs) {
 478                 /* Get a cluster mbuf. */
 479                 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
 480                 if (m == NULL)
 481                         break;
 482
 483                 m->m_len = MCLBYTES;
 484                 m->m_pkthdr.len = MCLBYTES;
 485                 m->m_pkthdr.rcvif = sc->ifp;
 486
 487                 /* Load map and plug in physical address. */
 488                 if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
 489                               &sc->rxring_m_dmamap[sc->rxring_hd_ptr])) {
 490                         sc->rxdmamapfails++;
 491                         m_free(m);
 492                         break;
 493                 }
 494                 if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 495                               sc->rxring_m_dmamap[sc->rxring_hd_ptr], m,
 496                               segs, &nsegs, BUS_DMA_NOWAIT)) {
 497                         sc->rxdmamapfails++;
 498                         bus_dmamap_destroy(sc->mbuf_dma_tag,
 499                                    sc->rxring_m_dmamap[sc->rxring_hd_ptr]);
 500                         sc->rxring_m_dmamap[sc->rxring_hd_ptr] = NULL;
 501                         m_free(m);
 502                         break;
 503                 }
 504                 sc->rxring_m[sc->rxring_hd_ptr] = m;
 505
 506                 /* Sync cache with receive buffer. */
 507                 bus_dmamap_sync(sc->mbuf_dma_tag,
 508                                 sc->rxring_m_dmamap[sc->rxring_hd_ptr],
 509                                 BUS_DMASYNC_PREREAD);
 510
 511                 /* Write rx descriptor and increment head pointer. */
 512                 sc->rxring[sc->rxring_hd_ptr].ctl = 0;
 513                 if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) {
 514                         sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr |
 515                                 CGEM_RXDESC_WRAP;
 516                         sc->rxring_hd_ptr = 0;
 517                 } else
 518                         sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr;
 519
 520                 sc->rxring_queued++;
 521         }
 522 }
 523
 524 /* Pull received packets off of receive descriptor ring. */
 525 static void
 526 cgem_recv(struct cgem_softc *sc)
 527 {
 528         if_t ifp = sc->ifp;
 529         struct mbuf *m, *m_hd, **m_tl;
 530         uint32_t ctl;
 531
 532         CGEM_ASSERT_LOCKED(sc);
 533
 534         /* Pick up all packets in which the OWN bit is set. */
 535         m_hd = NULL;
 536         m_tl = &m_hd;
 537         while (sc->rxring_queued > 0 &&
 538                (sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) {
 539
 540                 ctl = sc->rxring[sc->rxring_tl_ptr].ctl;
 541
 542                 /* Grab filled mbuf. */
 543                 m = sc->rxring_m[sc->rxring_tl_ptr];
 544                 sc->rxring_m[sc->rxring_tl_ptr] = NULL;
 545
 546                 /* Sync cache with receive buffer. */
 547                 bus_dmamap_sync(sc->mbuf_dma_tag,
 548                                 sc->rxring_m_dmamap[sc->rxring_tl_ptr],
 549                                 BUS_DMASYNC_POSTREAD);
 550
 551                 /* Unload and destroy dmamap. */
 552                 bus_dmamap_unload(sc->mbuf_dma_tag,
 553                         sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
 554                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 555                                    sc->rxring_m_dmamap[sc->rxring_tl_ptr]);
 556                 sc->rxring_m_dmamap[sc->rxring_tl_ptr] = NULL;
 557
 558                 /* Increment tail pointer. */
 559                 if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS)
 560                         sc->rxring_tl_ptr = 0;
 561                 sc->rxring_queued--;
 562
 563                 /* Check FCS and make sure entire packet landed in one mbuf
 564                  * cluster (which is much bigger than the largest ethernet
 565                  * packet).
 566                  */
 567                 if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 ||
 568                     (ctl & (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) !=
 569                            (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) {
 570                         /* discard. */
 571                         m_free(m);
 572                         if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
 573                         continue;
 574                 }
 575
 576                 /* Ready it to hand off to upper layers. */
 577                 m->m_data += ETHER_ALIGN;
 578                 m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK);
 579                 m->m_pkthdr.rcvif = ifp;
 580                 m->m_pkthdr.len = m->m_len;
 581
 582                 /* Are we using hardware checksumming?  Check the
 583                  * status in the receive descriptor.
 584                  */
 585                 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) {
 586                         /* TCP or UDP checks out, IP checks out too. */
 587                         if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 588                             CGEM_RXDESC_CKSUM_STAT_TCP_GOOD ||
 589                             (ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 590                             CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) {
 591                                 m->m_pkthdr.csum_flags |=
 592                                         CSUM_IP_CHECKED | CSUM_IP_VALID |
 593                                         CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
 594                                 m->m_pkthdr.csum_data = 0xffff;
 595                         } else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) ==
 596                                    CGEM_RXDESC_CKSUM_STAT_IP_GOOD) {
 597                                 /* Only IP checks out. */
 598                                 m->m_pkthdr.csum_flags |=
 599                                         CSUM_IP_CHECKED | CSUM_IP_VALID;
 600                                 m->m_pkthdr.csum_data = 0xffff;
 601                         }
 602                 }
 603
 604                 /* Queue it up for delivery below. */
 605                 *m_tl = m;
 606                 m_tl = &m->m_next;
 607         }
 608
 609         /* Replenish receive buffers. */
 610         cgem_fill_rqueue(sc);
 611
 612         /* Unlock and send up packets. */
 613         CGEM_UNLOCK(sc);
 614         while (m_hd != NULL) {
 615                 m = m_hd;
 616                 m_hd = m_hd->m_next;
 617                 m->m_next = NULL;
 618                 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
 619                 if_input(ifp, m);
 620         }
 621         CGEM_LOCK(sc);
 622 }
 623
 624 /* Find completed transmits and free their mbufs. */
 625 static void
 626 cgem_clean_tx(struct cgem_softc *sc)
 627 {
 628         struct mbuf *m;
 629         uint32_t ctl;
 630
 631         CGEM_ASSERT_LOCKED(sc);
 632
 633         /* free up finished transmits. */
 634         while (sc->txring_queued > 0 &&
 635                ((ctl = sc->txring[sc->txring_tl_ptr].ctl) &
 636                 CGEM_TXDESC_USED) != 0) {
 637
 638                 /* Sync cache. */
 639                 bus_dmamap_sync(sc->mbuf_dma_tag,
 640                                 sc->txring_m_dmamap[sc->txring_tl_ptr],
 641                                 BUS_DMASYNC_POSTWRITE);
 642
 643                 /* Unload and destroy DMA map. */
 644                 bus_dmamap_unload(sc->mbuf_dma_tag,
 645                                   sc->txring_m_dmamap[sc->txring_tl_ptr]);
 646                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 647                                    sc->txring_m_dmamap[sc->txring_tl_ptr]);
 648                 sc->txring_m_dmamap[sc->txring_tl_ptr] = NULL;
 649
 650                 /* Free up the mbuf. */
 651                 m = sc->txring_m[sc->txring_tl_ptr];
 652                 sc->txring_m[sc->txring_tl_ptr] = NULL;
 653                 m_freem(m);
 654
 655                 /* Check the status. */
 656                 if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) {
 657                         /* Serious bus error. log to console. */
 658                         device_printf(sc->dev, "cgem_clean_tx: Whoa! "
 659                                    "AHB error, addr=0x%x\n",
 660                                    sc->txring[sc->txring_tl_ptr].addr);
 661                 } else if ((ctl & (CGEM_TXDESC_RETRY_ERR |
 662                                    CGEM_TXDESC_LATE_COLL)) != 0) {
 663                         if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1);
 664                 } else
 665                         if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1);
 666
 667                 /* If the packet spanned more than one tx descriptor,
 668                  * skip descriptors until we find the end so that only
 669                  * start-of-frame descriptors are processed.
 670                  */
 671                 while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) {
 672                         if ((ctl & CGEM_TXDESC_WRAP) != 0)
 673                                 sc->txring_tl_ptr = 0;
 674                         else
 675                                 sc->txring_tl_ptr++;
 676                         sc->txring_queued--;
 677
 678                         ctl = sc->txring[sc->txring_tl_ptr].ctl;
 679
 680                         sc->txring[sc->txring_tl_ptr].ctl =
 681                                 ctl | CGEM_TXDESC_USED;
 682                 }
 683
 684                 /* Next descriptor. */
 685                 if ((ctl & CGEM_TXDESC_WRAP) != 0)
 686                         sc->txring_tl_ptr = 0;
 687                 else
 688                         sc->txring_tl_ptr++;
 689                 sc->txring_queued--;
 690
 691                 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE);
 692         }
 693 }
 694
 695 /* Start transmits. */
 696 static void
 697 cgem_start_locked(if_t ifp)
 698 {
 699         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
 700         struct mbuf *m;
 701         bus_dma_segment_t segs[TX_MAX_DMA_SEGS];
 702         uint32_t ctl;
 703         int i, nsegs, wrap, err;
 704
 705         CGEM_ASSERT_LOCKED(sc);
 706
 707         if ((if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0)
 708                 return;
 709
 710         for (;;) {
 711                 /* Check that there is room in the descriptor ring. */
 712                 if (sc->txring_queued >=
 713                     CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
 714
 715                         /* Try to make room. */
 716                         cgem_clean_tx(sc);
 717
 718                         /* Still no room? */
 719                         if (sc->txring_queued >=
 720                             CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) {
 721                                 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
 722                                 sc->txfull++;
 723                                 break;
 724                         }
 725                 }
 726
 727                 /* Grab next transmit packet. */
 728                 m = if_dequeue(ifp);
 729                 if (m == NULL)
 730                         break;
 731
 732                 /* Create and load DMA map. */
 733                 if (bus_dmamap_create(sc->mbuf_dma_tag, 0,
 734                               &sc->txring_m_dmamap[sc->txring_hd_ptr])) {
 735                         m_freem(m);
 736                         sc->txdmamapfails++;
 737                         continue;
 738                 }
 739                 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 740                                       sc->txring_m_dmamap[sc->txring_hd_ptr],
 741                                       m, segs, &nsegs, BUS_DMA_NOWAIT);
 742                 if (err == EFBIG) {
 743                         /* Too many segments!  defrag and try again. */
 744                         struct mbuf *m2 = m_defrag(m, M_NOWAIT);
 745
 746                         if (m2 == NULL) {
 747                                 sc->txdefragfails++;
 748                                 m_freem(m);
 749                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
 750                                    sc->txring_m_dmamap[sc->txring_hd_ptr]);
 751                                 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
 752                                 continue;
 753                         }
 754                         m = m2;
 755                         err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag,
 756                                       sc->txring_m_dmamap[sc->txring_hd_ptr],
 757                                       m, segs, &nsegs, BUS_DMA_NOWAIT);
 758                         sc->txdefrags++;
 759                 }
 760                 if (err) {
 761                         /* Give up. */
 762                         m_freem(m);
 763                         bus_dmamap_destroy(sc->mbuf_dma_tag,
 764                                    sc->txring_m_dmamap[sc->txring_hd_ptr]);
 765                         sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL;
 766                         sc->txdmamapfails++;
 767                         continue;
 768                 }
 769                 sc->txring_m[sc->txring_hd_ptr] = m;
 770
 771                 /* Sync tx buffer with cache. */
 772                 bus_dmamap_sync(sc->mbuf_dma_tag,
 773                                 sc->txring_m_dmamap[sc->txring_hd_ptr],
 774                                 BUS_DMASYNC_PREWRITE);
 775
 776                 /* Set wrap flag if next packet might run off end of ring. */
 777                 wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >=
 778                         CGEM_NUM_TX_DESCS;
 779
 780                 /* Fill in the TX descriptors back to front so that USED
 781                  * bit in first descriptor is cleared last.
 782                  */
 783                 for (i = nsegs - 1; i >= 0; i--) {
 784                         /* Descriptor address. */
 785                         sc->txring[sc->txring_hd_ptr + i].addr =
 786                                 segs[i].ds_addr;
 787
 788                         /* Descriptor control word. */
 789                         ctl = segs[i].ds_len;
 790                         if (i == nsegs - 1) {
 791                                 ctl |= CGEM_TXDESC_LAST_BUF;
 792                                 if (wrap)
 793                                         ctl |= CGEM_TXDESC_WRAP;
 794                         }
 795                         sc->txring[sc->txring_hd_ptr + i].ctl = ctl;
 796
 797                         if (i != 0)
 798                                 sc->txring_m[sc->txring_hd_ptr + i] = NULL;
 799                 }
 800
 801                 if (wrap)
 802                         sc->txring_hd_ptr = 0;
 803                 else
 804                         sc->txring_hd_ptr += nsegs;
 805                 sc->txring_queued += nsegs;
 806
 807                 /* Kick the transmitter. */
 808                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
 809                     CGEM_NET_CTRL_START_TX);
 810
 811                 /* If there is a BPF listener, bounce a copy to him. */
 812                 ETHER_BPF_MTAP(ifp, m);
 813         }
 814 }
 815
 816 static void
 817 cgem_start(if_t ifp)
 818 {
 819         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
 820
 821         CGEM_LOCK(sc);
 822         cgem_start_locked(ifp);
 823         CGEM_UNLOCK(sc);
 824 }
 825
 826 static void
 827 cgem_poll_hw_stats(struct cgem_softc *sc)
 828 {
 829         uint32_t n;
 830
 831         CGEM_ASSERT_LOCKED(sc);
 832
 833         sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT);
 834         sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32;
 835
 836         sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX);
 837         sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX);
 838         sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX);
 839         sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX);
 840         sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX);
 841         sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX);
 842         sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX);
 843         sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX);
 844         sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX);
 845         sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX);
 846         sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS);
 847
 848         n = RD4(sc, CGEM_SINGLE_COLL_FRAMES);
 849         sc->stats.tx_single_collisn += n;
 850         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 851         n = RD4(sc, CGEM_MULTI_COLL_FRAMES);
 852         sc->stats.tx_multi_collisn += n;
 853         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 854         n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES);
 855         sc->stats.tx_excsv_collisn += n;
 856         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 857         n = RD4(sc, CGEM_LATE_COLL);
 858         sc->stats.tx_late_collisn += n;
 859         if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n);
 860
 861         sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES);
 862         sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS);
 863
 864         sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT);
 865         sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32;
 866
 867         sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX);
 868         sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX);
 869         sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX);
 870         sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX);
 871         sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX);
 872         sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX);
 873         sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX);
 874         sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX);
 875         sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX);
 876         sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX);
 877         sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX);
 878         sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX);
 879         sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX);
 880         sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS);
 881         sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS);
 882         sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS);
 883         sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS);
 884         sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS);
 885         sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS);
 886         sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS);
 887         sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS);
 888         sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS);
 889 }
 890
 891 static void
 892 cgem_tick(void *arg)
 893 {
 894         struct cgem_softc *sc = (struct cgem_softc *)arg;
 895         struct mii_data *mii;
 896
 897         CGEM_ASSERT_LOCKED(sc);
 898
 899         /* Poll the phy. */
 900         if (sc->miibus != NULL) {
 901                 mii = device_get_softc(sc->miibus);
 902                 mii_tick(mii);
 903         }
 904
 905         /* Poll statistics registers. */
 906         cgem_poll_hw_stats(sc);
 907
 908         /* Check for receiver hang. */
 909         if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) {
 910                 /*
 911                  * Reset receiver logic by toggling RX_EN bit.  1usec
 912                  * delay is necessary especially when operating at 100mbps
 913                  * and 10mbps speeds.
 914                  */
 915                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow &
 916                     ~CGEM_NET_CTRL_RX_EN);
 917                 DELAY(1);
 918                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
 919         }
 920         sc->rx_frames_prev = sc->stats.rx_frames;
 921
 922         /* Next callout in one second. */
 923         callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
 924 }
 925
 926 /* Interrupt handler. */
 927 static void
 928 cgem_intr(void *arg)
 929 {
 930         struct cgem_softc *sc = (struct cgem_softc *)arg;
 931         if_t ifp = sc->ifp;
 932         uint32_t istatus;
 933
 934         CGEM_LOCK(sc);
 935
 936         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
 937                 CGEM_UNLOCK(sc);
 938                 return;
 939         }
 940
 941         /* Read interrupt status and immediately clear the bits. */
 942         istatus = RD4(sc, CGEM_INTR_STAT);
 943         WR4(sc, CGEM_INTR_STAT, istatus);
 944
 945         /* Packets received. */
 946         if ((istatus & CGEM_INTR_RX_COMPLETE) != 0)
 947                 cgem_recv(sc);
 948
 949         /* Free up any completed transmit buffers. */
 950         cgem_clean_tx(sc);
 951
 952         /* Hresp not ok.  Something is very bad with DMA.  Try to clear. */
 953         if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) {
 954                 device_printf(sc->dev, "cgem_intr: hresp not okay! "
 955                               "rx_status=0x%x\n", RD4(sc, CGEM_RX_STAT));
 956                 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK);
 957         }
 958
 959         /* Receiver overrun. */
 960         if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) {
 961                 /* Clear status bit. */
 962                 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN);
 963                 sc->rxoverruns++;
 964         }
 965
 966         /* Receiver ran out of bufs. */
 967         if ((istatus & CGEM_INTR_RX_USED_READ) != 0) {
 968                 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow |
 969                     CGEM_NET_CTRL_FLUSH_DPRAM_PKT);
 970                 cgem_fill_rqueue(sc);
 971                 sc->rxnobufs++;
 972         }
 973
 974         /* Restart transmitter if needed. */
 975         if (!if_sendq_empty(ifp))
 976                 cgem_start_locked(ifp);
 977
 978         CGEM_UNLOCK(sc);
 979 }
 980
 981 /* Reset hardware. */
 982 static void
 983 cgem_reset(struct cgem_softc *sc)
 984 {
 985
 986         CGEM_ASSERT_LOCKED(sc);
 987
 988         WR4(sc, CGEM_NET_CTRL, 0);
 989         WR4(sc, CGEM_NET_CFG, 0);
 990         WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS);
 991         WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL);
 992         WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL);
 993         WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL);
 994         WR4(sc, CGEM_HASH_BOT, 0);
 995         WR4(sc, CGEM_HASH_TOP, 0);
 996         WR4(sc, CGEM_TX_QBAR, 0);       /* manual says do this. */
 997         WR4(sc, CGEM_RX_QBAR, 0);
 998
 999         /* Get management port running even if interface is down. */
1000         WR4(sc, CGEM_NET_CFG,
1001             CGEM_NET_CFG_DBUS_WIDTH_32 |
1002             CGEM_NET_CFG_MDC_CLK_DIV_64);
1003
1004         sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN;
1005         WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1006 }
1007
1008 /* Bring up the hardware. */
1009 static void
1010 cgem_config(struct cgem_softc *sc)
1011 {
1012         if_t ifp = sc->ifp;
1013         uint32_t net_cfg;
1014         uint32_t dma_cfg;
1015         u_char *eaddr = if_getlladdr(ifp);
1016
1017         CGEM_ASSERT_LOCKED(sc);
1018
1019         /* Program Net Config Register. */
1020         net_cfg = CGEM_NET_CFG_DBUS_WIDTH_32 |
1021                 CGEM_NET_CFG_MDC_CLK_DIV_64 |
1022                 CGEM_NET_CFG_FCS_REMOVE |
1023                 CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) |
1024                 CGEM_NET_CFG_GIGE_EN |
1025                 CGEM_NET_CFG_1536RXEN |
1026                 CGEM_NET_CFG_FULL_DUPLEX |
1027                 CGEM_NET_CFG_SPEED100;
1028
1029         /* Enable receive checksum offloading? */
1030         if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0)
1031                 net_cfg |=  CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN;
1032
1033         WR4(sc, CGEM_NET_CFG, net_cfg);
1034
1035         /* Program DMA Config Register. */
1036         dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) |
1037                 CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K |
1038                 CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL |
1039                 CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 |
1040                 CGEM_DMA_CFG_DISC_WHEN_NO_AHB;
1041
1042         /* Enable transmit checksum offloading? */
1043         if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
1044                 dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN;
1045
1046         WR4(sc, CGEM_DMA_CFG, dma_cfg);
1047
1048         /* Write the rx and tx descriptor ring addresses to the QBAR regs. */
1049         WR4(sc, CGEM_RX_QBAR, (uint32_t) sc->rxring_physaddr);
1050         WR4(sc, CGEM_TX_QBAR, (uint32_t) sc->txring_physaddr);
1051
1052         /* Enable rx and tx. */
1053         sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN);
1054         WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow);
1055
1056         /* Set receive address in case it changed. */
1057         WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) |
1058             (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]);
1059         WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]);
1060
1061         /* Set up interrupts. */
1062         WR4(sc, CGEM_INTR_EN,
1063             CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN |
1064             CGEM_INTR_TX_USED_READ | CGEM_INTR_RX_USED_READ |
1065             CGEM_INTR_HRESP_NOT_OK);
1066 }
1067
1068 /* Turn on interface and load up receive ring with buffers. */
1069 static void
1070 cgem_init_locked(struct cgem_softc *sc)
1071 {
1072         struct mii_data *mii;
1073
1074         CGEM_ASSERT_LOCKED(sc);
1075
1076         if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0)
1077                 return;
1078
1079         cgem_config(sc);
1080         cgem_fill_rqueue(sc);
1081
1082         if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE);
1083
1084         mii = device_get_softc(sc->miibus);
1085         mii_mediachg(mii);
1086
1087         callout_reset(&sc->tick_ch, hz, cgem_tick, sc);
1088 }
1089
1090 static void
1091 cgem_init(void *arg)
1092 {
1093         struct cgem_softc *sc = (struct cgem_softc *)arg;
1094
1095         CGEM_LOCK(sc);
1096         cgem_init_locked(sc);
1097         CGEM_UNLOCK(sc);
1098 }
1099
1100 /* Turn off interface.  Free up any buffers in transmit or receive queues. */
1101 static void
1102 cgem_stop(struct cgem_softc *sc)
1103 {
1104         int i;
1105
1106         CGEM_ASSERT_LOCKED(sc);
1107
1108         callout_stop(&sc->tick_ch);
1109
1110         /* Shut down hardware. */
1111         cgem_reset(sc);
1112
1113         /* Clear out transmit queue. */
1114         for (i = 0; i < CGEM_NUM_TX_DESCS; i++) {
1115                 sc->txring[i].ctl = CGEM_TXDESC_USED;
1116                 sc->txring[i].addr = 0;
1117                 if (sc->txring_m[i]) {
1118                         /* Unload and destroy dmamap. */
1119                         bus_dmamap_unload(sc->mbuf_dma_tag,
1120                                           sc->txring_m_dmamap[i]);
1121                         bus_dmamap_destroy(sc->mbuf_dma_tag,
1122                                            sc->txring_m_dmamap[i]);
1123                         sc->txring_m_dmamap[i] = NULL;
1124                         m_freem(sc->txring_m[i]);
1125                         sc->txring_m[i] = NULL;
1126                 }
1127         }
1128         sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP;
1129
1130         sc->txring_hd_ptr = 0;
1131         sc->txring_tl_ptr = 0;
1132         sc->txring_queued = 0;
1133
1134         /* Clear out receive queue. */
1135         for (i = 0; i < CGEM_NUM_RX_DESCS; i++) {
1136                 sc->rxring[i].addr = CGEM_RXDESC_OWN;
1137                 sc->rxring[i].ctl = 0;
1138                 if (sc->rxring_m[i]) {
1139                         /* Unload and destroy dmamap. */
1140                         bus_dmamap_unload(sc->mbuf_dma_tag,
1141                                   sc->rxring_m_dmamap[i]);
1142                         bus_dmamap_destroy(sc->mbuf_dma_tag,
1143                                    sc->rxring_m_dmamap[i]);
1144                         sc->rxring_m_dmamap[i] = NULL;
1145
1146                         m_freem(sc->rxring_m[i]);
1147                         sc->rxring_m[i] = NULL;
1148                 }
1149         }
1150         sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP;
1151
1152         sc->rxring_hd_ptr = 0;
1153         sc->rxring_tl_ptr = 0;
1154         sc->rxring_queued = 0;
1155
1156         /* Force next statchg or linkchg to program net config register. */
1157         sc->mii_media_active = 0;
1158 }
1159
1160
1161 static int
1162 cgem_ioctl(if_t ifp, u_long cmd, caddr_t data)
1163 {
1164         struct cgem_softc *sc = if_getsoftc(ifp);
1165         struct ifreq *ifr = (struct ifreq *)data;
1166         struct mii_data *mii;
1167         int error = 0, mask;
1168
1169         switch (cmd) {
1170         case SIOCSIFFLAGS:
1171                 CGEM_LOCK(sc);
1172                 if ((if_getflags(ifp) & IFF_UP) != 0) {
1173                         if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1174                                 if (((if_getflags(ifp) ^ sc->if_old_flags) &
1175                                      (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
1176                                         cgem_rx_filter(sc);
1177                                 }
1178                         } else {
1179                                 cgem_init_locked(sc);
1180                         }
1181                 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1182                         if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
1183                         cgem_stop(sc);
1184                 }
1185                 sc->if_old_flags = if_getflags(ifp);
1186                 CGEM_UNLOCK(sc);
1187                 break;
1188
1189         case SIOCADDMULTI:
1190         case SIOCDELMULTI:
1191                 /* Set up multi-cast filters. */
1192                 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) {
1193                         CGEM_LOCK(sc);
1194                         cgem_rx_filter(sc);
1195                         CGEM_UNLOCK(sc);
1196                 }
1197                 break;
1198
1199         case SIOCSIFMEDIA:
1200         case SIOCGIFMEDIA:
1201                 mii = device_get_softc(sc->miibus);
1202                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1203                 break;
1204
1205         case SIOCSIFCAP:
1206                 CGEM_LOCK(sc);
1207                 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap;
1208
1209                 if ((mask & IFCAP_TXCSUM) != 0) {
1210                         if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) {
1211                                 /* Turn on TX checksumming. */
1212                                 if_setcapenablebit(ifp, IFCAP_TXCSUM |
1213                                                    IFCAP_TXCSUM_IPV6, 0);
1214                                 if_sethwassistbits(ifp, CGEM_CKSUM_ASSIST, 0);
1215
1216                                 WR4(sc, CGEM_DMA_CFG,
1217                                     RD4(sc, CGEM_DMA_CFG) |
1218                                      CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1219                         } else {
1220                                 /* Turn off TX checksumming. */
1221                                 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM |
1222                                                    IFCAP_TXCSUM_IPV6);
1223                                 if_sethwassistbits(ifp, 0, CGEM_CKSUM_ASSIST);
1224
1225                                 WR4(sc, CGEM_DMA_CFG,
1226                                     RD4(sc, CGEM_DMA_CFG) &
1227                                      ~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN);
1228                         }
1229                 }
1230                 if ((mask & IFCAP_RXCSUM) != 0) {
1231                         if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) {
1232                                 /* Turn on RX checksumming. */
1233                                 if_setcapenablebit(ifp, IFCAP_RXCSUM |
1234                                                    IFCAP_RXCSUM_IPV6, 0);
1235                                 WR4(sc, CGEM_NET_CFG,
1236                                     RD4(sc, CGEM_NET_CFG) |
1237                                      CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1238                         } else {
1239                                 /* Turn off RX checksumming. */
1240                                 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM |
1241                                                    IFCAP_RXCSUM_IPV6);
1242                                 WR4(sc, CGEM_NET_CFG,
1243                                     RD4(sc, CGEM_NET_CFG) &
1244                                      ~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN);
1245                         }
1246                 }
1247                 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) ==
1248                     (IFCAP_RXCSUM | IFCAP_TXCSUM))
1249                         if_setcapenablebit(ifp, IFCAP_VLAN_HWCSUM, 0);
1250                 else
1251                         if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM);
1252
1253                 CGEM_UNLOCK(sc);
1254                 break;
1255         default:
1256                 error = ether_ioctl(ifp, cmd, data);
1257                 break;
1258         }
1259
1260         return (error);
1261 }
1262
1263 /* MII bus support routines.
1264  */
1265 static void
1266 cgem_child_detached(device_t dev, device_t child)
1267 {
1268         struct cgem_softc *sc = device_get_softc(dev);
1269
1270         if (child == sc->miibus)
1271                 sc->miibus = NULL;
1272 }
1273
1274 static int
1275 cgem_ifmedia_upd(if_t ifp)
1276 {
1277         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
1278         struct mii_data *mii;
1279         struct mii_softc *miisc;
1280         int error = 0;
1281
1282         mii = device_get_softc(sc->miibus);
1283         CGEM_LOCK(sc);
1284         if ((if_getflags(ifp) & IFF_UP) != 0) {
1285                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
1286                         PHY_RESET(miisc);
1287                 error = mii_mediachg(mii);
1288         }
1289         CGEM_UNLOCK(sc);
1290
1291         return (error);
1292 }
1293
1294 static void
1295 cgem_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
1296 {
1297         struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp);
1298         struct mii_data *mii;
1299
1300         mii = device_get_softc(sc->miibus);
1301         CGEM_LOCK(sc);
1302         mii_pollstat(mii);
1303         ifmr->ifm_active = mii->mii_media_active;
1304         ifmr->ifm_status = mii->mii_media_status;
1305         CGEM_UNLOCK(sc);
1306 }
1307
1308 static int
1309 cgem_miibus_readreg(device_t dev, int phy, int reg)
1310 {
1311         struct cgem_softc *sc = device_get_softc(dev);
1312         int tries, val;
1313
1314         WR4(sc, CGEM_PHY_MAINT,
1315             CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 |
1316             CGEM_PHY_MAINT_OP_READ |
1317             (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1318             (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT));
1319
1320         /* Wait for completion. */
1321         tries=0;
1322         while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1323                 DELAY(5);
1324                 if (++tries > 200) {
1325                         device_printf(dev, "phy read timeout: %d\n", reg);
1326                         return (-1);
1327                 }
1328         }
1329
1330         val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK;
1331
1332         if (reg == MII_EXTSR)
1333                 /*
1334                  * MAC does not support half-duplex at gig speeds.
1335                  * Let mii(4) exclude the capability.
1336                  */
1337                 val &= ~(EXTSR_1000XHDX | EXTSR_1000THDX);
1338
1339         return (val);
1340 }
1341
1342 static int
1343 cgem_miibus_writereg(device_t dev, int phy, int reg, int data)
1344 {
1345         struct cgem_softc *sc = device_get_softc(dev);
1346         int tries;
1347
1348         WR4(sc, CGEM_PHY_MAINT,
1349             CGEM_PHY_MAINT_CLAUSE_22 | CGEM_PHY_MAINT_MUST_10 |
1350             CGEM_PHY_MAINT_OP_WRITE |
1351             (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) |
1352             (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) |
1353             (data & CGEM_PHY_MAINT_DATA_MASK));
1354
1355         /* Wait for completion. */
1356         tries = 0;
1357         while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) {
1358                 DELAY(5);
1359                 if (++tries > 200) {
1360                         device_printf(dev, "phy write timeout: %d\n", reg);
1361                         return (-1);
1362                 }
1363         }
1364
1365         return (0);
1366 }
1367
1368 static void
1369 cgem_miibus_statchg(device_t dev)
1370 {
1371         struct cgem_softc *sc  = device_get_softc(dev);
1372         struct mii_data *mii = device_get_softc(sc->miibus);
1373
1374         CGEM_ASSERT_LOCKED(sc);
1375
1376         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1377             (IFM_ACTIVE | IFM_AVALID) &&
1378             sc->mii_media_active != mii->mii_media_active)
1379                 cgem_mediachange(sc, mii);
1380 }
1381
1382 static void
1383 cgem_miibus_linkchg(device_t dev)
1384 {
1385         struct cgem_softc *sc  = device_get_softc(dev);
1386         struct mii_data *mii = device_get_softc(sc->miibus);
1387
1388         CGEM_ASSERT_LOCKED(sc);
1389
1390         if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1391             (IFM_ACTIVE | IFM_AVALID) &&
1392             sc->mii_media_active != mii->mii_media_active)
1393                 cgem_mediachange(sc, mii);
1394 }
1395
1396 /*
1397  * Overridable weak symbol cgem_set_ref_clk().  This allows platforms to
1398  * provide a function to set the cgem's reference clock.
1399  */
1400 static int __used
1401 cgem_default_set_ref_clk(int unit, int frequency)
1402 {
1403
1404         return 0;
1405 }
1406 __weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk);
1407
1408 /* Call to set reference clock and network config bits according to media. */
1409 static void
1410 cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii)
1411 {
1412         uint32_t net_cfg;
1413         int ref_clk_freq;
1414
1415         CGEM_ASSERT_LOCKED(sc);
1416
1417         /* Update hardware to reflect media. */
1418         net_cfg = RD4(sc, CGEM_NET_CFG);
1419         net_cfg &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN |
1420                      CGEM_NET_CFG_FULL_DUPLEX);
1421
1422         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1423         case IFM_1000_T:
1424                 net_cfg |= (CGEM_NET_CFG_SPEED100 |
1425                             CGEM_NET_CFG_GIGE_EN);
1426                 ref_clk_freq = 125000000;
1427                 break;
1428         case IFM_100_TX:
1429                 net_cfg |= CGEM_NET_CFG_SPEED100;
1430                 ref_clk_freq = 25000000;
1431                 break;
1432         default:
1433                 ref_clk_freq = 2500000;
1434         }
1435
1436         if ((mii->mii_media_active & IFM_FDX) != 0)
1437                 net_cfg |= CGEM_NET_CFG_FULL_DUPLEX;
1438
1439         WR4(sc, CGEM_NET_CFG, net_cfg);
1440
1441         /* Set the reference clock if necessary. */
1442         if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq))
1443                 device_printf(sc->dev, "cgem_mediachange: "
1444                               "could not set ref clk%d to %d.\n",
1445                               sc->ref_clk_num, ref_clk_freq);
1446
1447         sc->mii_media_active = mii->mii_media_active;
1448 }
1449
1450 static void
1451 cgem_add_sysctls(device_t dev)
1452 {
1453         struct cgem_softc *sc = device_get_softc(dev);
1454         struct sysctl_ctx_list *ctx;
1455         struct sysctl_oid_list *child;
1456         struct sysctl_oid *tree;
1457
1458         ctx = device_get_sysctl_ctx(dev);
1459         child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
1460
1461         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW,
1462                        &sc->rxbufs, 0,
1463                        "Number receive buffers to provide");
1464
1465         SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW,
1466                        &sc->rxhangwar, 0,
1467                        "Enable receive hang work-around");
1468
1469         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD,
1470                         &sc->rxoverruns, 0,
1471                         "Receive overrun events");
1472
1473         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD,
1474                         &sc->rxnobufs, 0,
1475                         "Receive buf queue empty events");
1476
1477         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD,
1478                         &sc->rxdmamapfails, 0,
1479                         "Receive DMA map failures");
1480
1481         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD,
1482                         &sc->txfull, 0,
1483                         "Transmit ring full events");
1484
1485         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD,
1486                         &sc->txdmamapfails, 0,
1487                         "Transmit DMA map failures");
1488
1489         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD,
1490                         &sc->txdefrags, 0,
1491                         "Transmit m_defrag() calls");
1492
1493         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD,
1494                         &sc->txdefragfails, 0,
1495                         "Transmit m_defrag() failures");
1496
1497         tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
1498             CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GEM statistics");
1499         child = SYSCTL_CHILDREN(tree);
1500
1501         SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD,
1502                          &sc->stats.tx_bytes, "Total bytes transmitted");
1503
1504         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD,
1505                         &sc->stats.tx_frames, 0, "Total frames transmitted");
1506         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD,
1507                         &sc->stats.tx_frames_bcast, 0,
1508                         "Number broadcast frames transmitted");
1509         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD,
1510                         &sc->stats.tx_frames_multi, 0,
1511                         "Number multicast frames transmitted");
1512         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause",
1513                         CTLFLAG_RD, &sc->stats.tx_frames_pause, 0,
1514                         "Number pause frames transmitted");
1515         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD,
1516                         &sc->stats.tx_frames_64b, 0,
1517                         "Number frames transmitted of size 64 bytes or less");
1518         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD,
1519                         &sc->stats.tx_frames_65to127b, 0,
1520                         "Number frames transmitted of size 65-127 bytes");
1521         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b",
1522                         CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0,
1523                         "Number frames transmitted of size 128-255 bytes");
1524         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b",
1525                         CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0,
1526                         "Number frames transmitted of size 256-511 bytes");
1527         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b",
1528                         CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0,
1529                         "Number frames transmitted of size 512-1023 bytes");
1530         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b",
1531                         CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0,
1532                         "Number frames transmitted of size 1024-1536 bytes");
1533         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs",
1534                         CTLFLAG_RD, &sc->stats.tx_under_runs, 0,
1535                         "Number transmit under-run events");
1536         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn",
1537                         CTLFLAG_RD, &sc->stats.tx_single_collisn, 0,
1538                         "Number single-collision transmit frames");
1539         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn",
1540                         CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0,
1541                         "Number multi-collision transmit frames");
1542         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn",
1543                         CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0,
1544                         "Number excessive collision transmit frames");
1545         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn",
1546                         CTLFLAG_RD, &sc->stats.tx_late_collisn, 0,
1547                         "Number late-collision transmit frames");
1548         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames",
1549                         CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0,
1550                         "Number deferred transmit frames");
1551         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs",
1552                         CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0,
1553                         "Number carrier sense errors on transmit");
1554
1555         SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD,
1556                          &sc->stats.rx_bytes, "Total bytes received");
1557
1558         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD,
1559                         &sc->stats.rx_frames, 0, "Total frames received");
1560         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast",
1561                         CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0,
1562                         "Number broadcast frames received");
1563         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi",
1564                         CTLFLAG_RD, &sc->stats.rx_frames_multi, 0,
1565                         "Number multicast frames received");
1566         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause",
1567                         CTLFLAG_RD, &sc->stats.rx_frames_pause, 0,
1568                         "Number pause frames received");
1569         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b",
1570                         CTLFLAG_RD, &sc->stats.rx_frames_64b, 0,
1571                         "Number frames received of size 64 bytes or less");
1572         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b",
1573                         CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0,
1574                         "Number frames received of size 65-127 bytes");
1575         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b",
1576                         CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0,
1577                         "Number frames received of size 128-255 bytes");
1578         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b",
1579                         CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0,
1580                         "Number frames received of size 256-511 bytes");
1581         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b",
1582                         CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0,
1583                         "Number frames received of size 512-1023 bytes");
1584         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b",
1585                         CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0,
1586                         "Number frames received of size 1024-1536 bytes");
1587         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize",
1588                         CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0,
1589                         "Number undersize frames received");
1590         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize",
1591                         CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0,
1592                         "Number oversize frames received");
1593         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber",
1594                         CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0,
1595                         "Number jabber frames received");
1596         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs",
1597                         CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0,
1598                         "Number frames received with FCS errors");
1599         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs",
1600                         CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0,
1601                         "Number frames received with length errors");
1602         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs",
1603                         CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0,
1604                         "Number receive symbol errors");
1605         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs",
1606                         CTLFLAG_RD, &sc->stats.rx_align_errs, 0,
1607                         "Number receive alignment errors");
1608         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs",
1609                         CTLFLAG_RD, &sc->stats.rx_resource_errs, 0,
1610                         "Number frames received when no rx buffer available");
1611         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs",
1612                         CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0,
1613                         "Number frames received but not copied due to "
1614                         "receive overrun");
1615         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs",
1616                         CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0,
1617                         "Number frames received with IP header checksum "
1618                         "errors");
1619         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs",
1620                         CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0,
1621                         "Number frames received with TCP checksum errors");
1622         SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs",
1623                         CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0,
1624                         "Number frames received with UDP checksum errors");
1625 }
1626
1627
1628 static int
1629 cgem_probe(device_t dev)
1630 {
1631
1632         if (!ofw_bus_status_okay(dev))
1633                 return (ENXIO);
1634
1635         if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
1636                 return (ENXIO);
1637
1638         device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface");
1639         return (0);
1640 }
1641
1642 static int
1643 cgem_attach(device_t dev)
1644 {
1645         struct cgem_softc *sc = device_get_softc(dev);
1646         if_t ifp = NULL;
1647         phandle_t node;
1648         pcell_t cell;
1649         int rid, err;
1650         u_char eaddr[ETHER_ADDR_LEN];
1651
1652         sc->dev = dev;
1653         CGEM_LOCK_INIT(sc);
1654
1655         /* Get reference clock number and base divider from fdt. */
1656         node = ofw_bus_get_node(dev);
1657         sc->ref_clk_num = 0;
1658         if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0)
1659                 sc->ref_clk_num = fdt32_to_cpu(cell);
1660
1661         /* Get memory resource. */
1662         rid = 0;
1663         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1664                                              RF_ACTIVE);
1665         if (sc->mem_res == NULL) {
1666                 device_printf(dev, "could not allocate memory resources.\n");
1667                 return (ENOMEM);
1668         }
1669
1670         /* Get IRQ resource. */
1671         rid = 0;
1672         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1673                                              RF_ACTIVE);
1674         if (sc->irq_res == NULL) {
1675                 device_printf(dev, "could not allocate interrupt resource.\n");
1676                 cgem_detach(dev);
1677                 return (ENOMEM);
1678         }
1679
1680         /* Set up ifnet structure. */
1681         ifp = sc->ifp = if_alloc(IFT_ETHER);
1682         if (ifp == NULL) {
1683                 device_printf(dev, "could not allocate ifnet structure\n");
1684                 cgem_detach(dev);
1685                 return (ENOMEM);
1686         }
1687         if_setsoftc(ifp, sc);
1688         if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev));
1689         if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
1690         if_setinitfn(ifp, cgem_init);
1691         if_setioctlfn(ifp, cgem_ioctl);
1692         if_setstartfn(ifp, cgem_start);
1693         if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 |
1694                               IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM, 0);
1695         if_setsendqlen(ifp, CGEM_NUM_TX_DESCS);
1696         if_setsendqready(ifp);
1697
1698         /* Disable hardware checksumming by default. */
1699         if_sethwassist(ifp, 0);
1700         if_setcapenable(ifp, if_getcapabilities(ifp) &
1701                 ~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM));
1702
1703         sc->if_old_flags = if_getflags(ifp);
1704         sc->rxbufs = DEFAULT_NUM_RX_BUFS;
1705         sc->rxhangwar = 1;
1706
1707         /* Reset hardware. */
1708         CGEM_LOCK(sc);
1709         cgem_reset(sc);
1710         CGEM_UNLOCK(sc);
1711
1712         /* Attach phy to mii bus. */
1713         err = mii_attach(dev, &sc->miibus, ifp,
1714                          cgem_ifmedia_upd, cgem_ifmedia_sts,
1715                          BMSR_DEFCAPMASK, MII_PHY_ANY, MII_OFFSET_ANY, 0);
1716         if (err) {
1717                 device_printf(dev, "attaching PHYs failed\n");
1718                 cgem_detach(dev);
1719                 return (err);
1720         }
1721
1722         /* Set up TX and RX descriptor area. */
1723         err = cgem_setup_descs(sc);
1724         if (err) {
1725                 device_printf(dev, "could not set up dma mem for descs.\n");
1726                 cgem_detach(dev);
1727                 return (ENOMEM);
1728         }
1729
1730         /* Get a MAC address. */
1731         cgem_get_mac(sc, eaddr);
1732
1733         /* Start ticks. */
1734         callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0);
1735
1736         ether_ifattach(ifp, eaddr);
1737
1738         err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE |
1739                              INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand);
1740         if (err) {
1741                 device_printf(dev, "could not set interrupt handler.\n");
1742                 ether_ifdetach(ifp);
1743                 cgem_detach(dev);
1744                 return (err);
1745         }
1746
1747         cgem_add_sysctls(dev);
1748
1749         return (0);
1750 }
1751
1752 static int
1753 cgem_detach(device_t dev)
1754 {
1755         struct cgem_softc *sc = device_get_softc(dev);
1756         int i;
1757
1758         if (sc == NULL)
1759                 return (ENODEV);
1760
1761         if (device_is_attached(dev)) {
1762                 CGEM_LOCK(sc);
1763                 cgem_stop(sc);
1764                 CGEM_UNLOCK(sc);
1765                 callout_drain(&sc->tick_ch);
1766                 if_setflagbits(sc->ifp, 0, IFF_UP);
1767                 ether_ifdetach(sc->ifp);
1768         }
1769
1770         if (sc->miibus != NULL) {
1771                 device_delete_child(dev, sc->miibus);
1772                 sc->miibus = NULL;
1773         }
1774
1775         /* Release resources. */
1776         if (sc->mem_res != NULL) {
1777                 bus_release_resource(dev, SYS_RES_MEMORY,
1778                                      rman_get_rid(sc->mem_res), sc->mem_res);
1779                 sc->mem_res = NULL;
1780         }
1781         if (sc->irq_res != NULL) {
1782                 if (sc->intrhand)
1783                         bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
1784                 bus_release_resource(dev, SYS_RES_IRQ,
1785                                      rman_get_rid(sc->irq_res), sc->irq_res);
1786                 sc->irq_res = NULL;
1787         }
1788
1789         /* Release DMA resources. */
1790         if (sc->rxring != NULL) {
1791                 if (sc->rxring_physaddr != 0) {
1792                         bus_dmamap_unload(sc->desc_dma_tag,
1793                                           sc->rxring_dma_map);
1794                         sc->rxring_physaddr = 0;
1795                 }
1796                 bus_dmamem_free(sc->desc_dma_tag, sc->rxring,
1797                                 sc->rxring_dma_map);
1798                 sc->rxring = NULL;
1799                 for (i = 0; i < CGEM_NUM_RX_DESCS; i++)
1800                         if (sc->rxring_m_dmamap[i] != NULL) {
1801                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
1802                                                    sc->rxring_m_dmamap[i]);
1803                                 sc->rxring_m_dmamap[i] = NULL;
1804                         }
1805         }
1806         if (sc->txring != NULL) {
1807                 if (sc->txring_physaddr != 0) {
1808                         bus_dmamap_unload(sc->desc_dma_tag,
1809                                           sc->txring_dma_map);
1810                         sc->txring_physaddr = 0;
1811                 }
1812                 bus_dmamem_free(sc->desc_dma_tag, sc->txring,
1813                                 sc->txring_dma_map);
1814                 sc->txring = NULL;
1815                 for (i = 0; i < CGEM_NUM_TX_DESCS; i++)
1816                         if (sc->txring_m_dmamap[i] != NULL) {
1817                                 bus_dmamap_destroy(sc->mbuf_dma_tag,
1818                                                    sc->txring_m_dmamap[i]);
1819                                 sc->txring_m_dmamap[i] = NULL;
1820                         }
1821         }
1822         if (sc->desc_dma_tag != NULL) {
1823                 bus_dma_tag_destroy(sc->desc_dma_tag);
1824                 sc->desc_dma_tag = NULL;
1825         }
1826         if (sc->mbuf_dma_tag != NULL) {
1827                 bus_dma_tag_destroy(sc->mbuf_dma_tag);
1828                 sc->mbuf_dma_tag = NULL;
1829         }
1830
1831         bus_generic_detach(dev);
1832
1833         CGEM_LOCK_DESTROY(sc);
1834
1835         return (0);
1836 }
1837
1838 static device_method_t cgem_methods[] = {
1839         /* Device interface */
1840         DEVMETHOD(device_probe,         cgem_probe),
1841         DEVMETHOD(device_attach,        cgem_attach),
1842         DEVMETHOD(device_detach,        cgem_detach),
1843
1844         /* Bus interface */
1845         DEVMETHOD(bus_child_detached,   cgem_child_detached),
1846
1847         /* MII interface */
1848         DEVMETHOD(miibus_readreg,       cgem_miibus_readreg),
1849         DEVMETHOD(miibus_writereg,      cgem_miibus_writereg),
1850         DEVMETHOD(miibus_statchg,       cgem_miibus_statchg),
1851         DEVMETHOD(miibus_linkchg,       cgem_miibus_linkchg),
1852
1853         DEVMETHOD_END
1854 };
1855
1856 static driver_t cgem_driver = {
1857         "cgem",
1858         cgem_methods,
1859         sizeof(struct cgem_softc),
1860 };
1861
1862 DRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL);
1863 DRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL);
1864 MODULE_DEPEND(cgem, miibus, 1, 1, 1);
1865 MODULE_DEPEND(cgem, ether, 1, 1, 1);