2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065
37 * Saturn Gigabit Ethernet controllers
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/callout.h>
48 #include <sys/endian.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/refcount.h>
56 #include <sys/resource.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/taskqueue.h>
63 #include <net/ethernet.h>
65 #include <net/if_arp.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <netinet/in.h>
72 #include <netinet/in_systm.h>
73 #include <netinet/ip.h>
74 #include <netinet/tcp.h>
75 #include <netinet/udp.h>
77 #include <machine/bus.h>
78 #if defined(__powerpc__) || defined(__sparc64__)
79 #include <dev/ofw/ofw_bus.h>
80 #include <dev/ofw/openfirm.h>
81 #include <machine/ofw_machdep.h>
83 #include <machine/resource.h>
85 #include <dev/mii/mii.h>
86 #include <dev/mii/miivar.h>
88 #include <dev/cas/if_casreg.h>
89 #include <dev/cas/if_casvar.h>
91 #include <dev/pci/pcireg.h>
92 #include <dev/pci/pcivar.h>
94 #include "miibus_if.h"
96 #define RINGASSERT(n , min, max) \
97 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max))
99 RINGASSERT(CAS_NRXCOMP, 128, 32768);
100 RINGASSERT(CAS_NRXDESC, 32, 8192);
101 RINGASSERT(CAS_NRXDESC2, 32, 8192);
102 RINGASSERT(CAS_NTXDESC, 32, 8192);
106 #define CCDASSERT(m, a) \
107 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0)
109 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN);
110 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN);
111 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN);
115 #define CAS_TRIES 10000
118 * According to documentation, the hardware has support for basic TCP
119 * checksum offloading only, in practice this can be also used for UDP
120 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0
121 * is not converted to 0xffff no longer exists).
123 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
125 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx);
126 static int cas_attach(struct cas_softc *sc);
127 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr,
129 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs,
130 int nsegs, int error);
131 static void cas_detach(struct cas_softc *sc);
132 static int cas_disable_rx(struct cas_softc *sc);
133 static int cas_disable_tx(struct cas_softc *sc);
134 static void cas_eint(struct cas_softc *sc, u_int status);
135 static void cas_free(void *arg1, void* arg2);
136 static void cas_init(void *xsc);
137 static void cas_init_locked(struct cas_softc *sc);
138 static void cas_init_regs(struct cas_softc *sc);
139 static int cas_intr(void *v);
140 static void cas_intr_task(void *arg, int pending __unused);
141 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
142 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head);
143 static int cas_mediachange(struct ifnet *ifp);
144 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
145 static void cas_meminit(struct cas_softc *sc);
146 static void cas_mifinit(struct cas_softc *sc);
147 static int cas_mii_readreg(device_t dev, int phy, int reg);
148 static void cas_mii_statchg(device_t dev);
149 static int cas_mii_writereg(device_t dev, int phy, int reg, int val);
150 static void cas_reset(struct cas_softc *sc);
151 static int cas_reset_rx(struct cas_softc *sc);
152 static int cas_reset_tx(struct cas_softc *sc);
153 static void cas_resume(struct cas_softc *sc);
154 static u_int cas_descsize(u_int sz);
155 static void cas_rint(struct cas_softc *sc);
156 static void cas_rint_timeout(void *arg);
157 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum);
158 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp);
159 static u_int cas_rxcompsize(u_int sz);
160 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs,
161 int nsegs, int error);
162 static void cas_setladrf(struct cas_softc *sc);
163 static void cas_start(struct ifnet *ifp);
164 static void cas_stop(struct ifnet *ifp);
165 static void cas_suspend(struct cas_softc *sc);
166 static void cas_tick(void *arg);
167 static void cas_tint(struct cas_softc *sc);
168 static void cas_tx_task(void *arg, int pending __unused);
169 static inline void cas_txkick(struct cas_softc *sc);
170 static void cas_watchdog(struct cas_softc *sc);
172 static devclass_t cas_devclass;
174 MODULE_DEPEND(cas, ether, 1, 1, 1);
175 MODULE_DEPEND(cas, miibus, 1, 1, 1);
179 #define KTR_CAS KTR_SPARE2
183 cas_attach(struct cas_softc *sc)
185 struct cas_txsoft *txs;
190 /* Set up ifnet structure. */
191 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
195 if_initname(ifp, device_get_name(sc->sc_dev),
196 device_get_unit(sc->sc_dev));
197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
198 ifp->if_start = cas_start;
199 ifp->if_ioctl = cas_ioctl;
200 ifp->if_init = cas_init;
201 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN);
202 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN;
203 IFQ_SET_READY(&ifp->if_snd);
205 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
206 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
207 /* Create local taskq. */
208 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc);
209 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp);
210 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK,
211 taskqueue_thread_enqueue, &sc->sc_tq);
212 if (sc->sc_tq == NULL) {
213 device_printf(sc->sc_dev, "could not create taskqueue\n");
217 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
218 device_get_nameunit(sc->sc_dev));
220 device_printf(sc->sc_dev, "could not start threads\n");
224 /* Make sure the chip is stopped. */
227 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
228 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
229 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL,
234 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
236 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag);
240 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
242 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES,
243 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
247 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0,
248 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
249 sizeof(struct cas_control_data), 1,
250 sizeof(struct cas_control_data), 0,
251 NULL, NULL, &sc->sc_cdmatag);
256 * Allocate the control data structures, create and load the
259 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
260 (void **)&sc->sc_control_data,
261 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
262 &sc->sc_cddmamap)) != 0) {
263 device_printf(sc->sc_dev,
264 "unable to allocate control data, error = %d\n", error);
269 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
270 sc->sc_control_data, sizeof(struct cas_control_data),
271 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
272 device_printf(sc->sc_dev,
273 "unable to load control data DMA map, error = %d\n",
279 * Initialize the transmit job descriptors.
281 STAILQ_INIT(&sc->sc_txfreeq);
282 STAILQ_INIT(&sc->sc_txdirtyq);
285 * Create the transmit buffer DMA maps.
288 for (i = 0; i < CAS_TXQUEUELEN; i++) {
289 txs = &sc->sc_txsoft[i];
290 txs->txs_mbuf = NULL;
292 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
293 &txs->txs_dmamap)) != 0) {
294 device_printf(sc->sc_dev,
295 "unable to create TX DMA map %d, error = %d\n",
299 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
303 * Allocate the receive buffers, create and load the DMA maps
306 for (i = 0; i < CAS_NRXDESC; i++) {
307 if ((error = bus_dmamem_alloc(sc->sc_rdmatag,
308 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK,
309 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) {
310 device_printf(sc->sc_dev,
311 "unable to allocate RX buffer %d, error = %d\n",
317 sc->sc_rxdsoft[i].rxds_paddr = 0;
318 if ((error = bus_dmamap_load(sc->sc_rdmatag,
319 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf,
320 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 ||
321 sc->sc_rxdsoft[i].rxds_paddr == 0) {
322 device_printf(sc->sc_dev,
323 "unable to load RX DMA map %d, error = %d\n",
329 if ((sc->sc_flags & CAS_SERDES) == 0) {
330 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
331 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4,
332 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
335 * Look for an external PHY.
338 v = CAS_READ_4(sc, CAS_MIF_CONF);
339 if ((v & CAS_MIF_CONF_MDI1) != 0) {
340 v |= CAS_MIF_CONF_PHY_SELECT;
341 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
342 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
343 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
344 /* Enable/unfreeze the GMII pins of Saturn. */
345 if (sc->sc_variant == CAS_SATURN) {
346 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
347 CAS_READ_4(sc, CAS_SATURN_PCFG) &
348 ~CAS_SATURN_PCFG_FSI);
349 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
350 BUS_SPACE_BARRIER_READ |
351 BUS_SPACE_BARRIER_WRITE);
354 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
355 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
356 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
359 * Fall back on an internal PHY if no external PHY was found.
361 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) {
362 v &= ~CAS_MIF_CONF_PHY_SELECT;
363 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
364 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
365 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
366 /* Freeze the GMII pins of Saturn for saving power. */
367 if (sc->sc_variant == CAS_SATURN) {
368 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
369 CAS_READ_4(sc, CAS_SATURN_PCFG) |
370 CAS_SATURN_PCFG_FSI);
371 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
372 BUS_SPACE_BARRIER_READ |
373 BUS_SPACE_BARRIER_WRITE);
376 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
377 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
378 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
382 * Use the external PCS SERDES.
384 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
385 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE);
386 /* Enable/unfreeze the SERDES pins of Saturn. */
387 if (sc->sc_variant == CAS_SATURN) {
388 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
389 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
390 BUS_SPACE_BARRIER_WRITE);
392 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
393 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4,
394 BUS_SPACE_BARRIER_WRITE);
395 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
396 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
397 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
398 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
399 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
400 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
403 device_printf(sc->sc_dev, "attaching PHYs failed\n");
406 sc->sc_mii = device_get_softc(sc->sc_miibus);
409 * From this point forward, the attachment cannot fail. A failure
410 * before this point releases all resources that may have been
414 /* Announce FIFO sizes. */
415 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE);
416 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
417 CAS_RX_FIFO_SIZE / 1024, v / 16);
419 /* Attach the interface. */
420 ether_ifattach(ifp, sc->sc_enaddr);
423 * Tell the upper layer(s) we support long frames/checksum offloads.
425 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
426 ifp->if_capabilities = IFCAP_VLAN_MTU;
427 if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
428 ifp->if_capabilities |= IFCAP_HWCSUM;
429 ifp->if_hwassist = CAS_CSUM_FEATURES;
431 ifp->if_capenable = ifp->if_capabilities;
436 * Free any resources we've allocated during the failed attach
437 * attempt. Do this in reverse order and fall through.
440 for (i = 0; i < CAS_NRXDESC; i++)
441 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
442 bus_dmamap_unload(sc->sc_rdmatag,
443 sc->sc_rxdsoft[i].rxds_dmamap);
445 for (i = 0; i < CAS_NRXDESC; i++)
446 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
447 bus_dmamem_free(sc->sc_rdmatag,
448 sc->sc_rxdsoft[i].rxds_buf,
449 sc->sc_rxdsoft[i].rxds_dmamap);
451 for (i = 0; i < CAS_TXQUEUELEN; i++)
452 if (sc->sc_txsoft[i].txs_dmamap != NULL)
453 bus_dmamap_destroy(sc->sc_tdmatag,
454 sc->sc_txsoft[i].txs_dmamap);
455 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
457 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
460 bus_dma_tag_destroy(sc->sc_cdmatag);
462 bus_dma_tag_destroy(sc->sc_tdmatag);
464 bus_dma_tag_destroy(sc->sc_rdmatag);
466 bus_dma_tag_destroy(sc->sc_pdmatag);
468 taskqueue_free(sc->sc_tq);
475 cas_detach(struct cas_softc *sc)
477 struct ifnet *ifp = sc->sc_ifp;
484 callout_drain(&sc->sc_tick_ch);
485 callout_drain(&sc->sc_rx_ch);
486 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task);
487 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task);
489 taskqueue_free(sc->sc_tq);
490 device_delete_child(sc->sc_dev, sc->sc_miibus);
492 for (i = 0; i < CAS_NRXDESC; i++)
493 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL)
494 bus_dmamap_sync(sc->sc_rdmatag,
495 sc->sc_rxdsoft[i].rxds_dmamap,
496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
497 for (i = 0; i < CAS_NRXDESC; i++)
498 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
499 bus_dmamap_unload(sc->sc_rdmatag,
500 sc->sc_rxdsoft[i].rxds_dmamap);
501 for (i = 0; i < CAS_NRXDESC; i++)
502 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
503 bus_dmamem_free(sc->sc_rdmatag,
504 sc->sc_rxdsoft[i].rxds_buf,
505 sc->sc_rxdsoft[i].rxds_dmamap);
506 for (i = 0; i < CAS_TXQUEUELEN; i++)
507 if (sc->sc_txsoft[i].txs_dmamap != NULL)
508 bus_dmamap_destroy(sc->sc_tdmatag,
509 sc->sc_txsoft[i].txs_dmamap);
510 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
511 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
512 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
514 bus_dma_tag_destroy(sc->sc_cdmatag);
515 bus_dma_tag_destroy(sc->sc_tdmatag);
516 bus_dma_tag_destroy(sc->sc_rdmatag);
517 bus_dma_tag_destroy(sc->sc_pdmatag);
521 cas_suspend(struct cas_softc *sc)
523 struct ifnet *ifp = sc->sc_ifp;
531 cas_resume(struct cas_softc *sc)
533 struct ifnet *ifp = sc->sc_ifp;
537 * On resume all registers have to be initialized again like
540 sc->sc_flags &= ~CAS_INITED;
541 if (ifp->if_flags & IFF_UP)
547 cas_rxcksum(struct mbuf *m, uint16_t cksum)
549 struct ether_header *eh;
553 int32_t hlen, len, pktlen;
556 pktlen = m->m_pkthdr.len;
557 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
559 eh = mtod(m, struct ether_header *);
560 if (eh->ether_type != htons(ETHERTYPE_IP))
562 ip = (struct ip *)(eh + 1);
563 if (ip->ip_v != IPVERSION)
566 hlen = ip->ip_hl << 2;
567 pktlen -= sizeof(struct ether_header);
568 if (hlen < sizeof(struct ip))
570 if (ntohs(ip->ip_len) < hlen)
572 if (ntohs(ip->ip_len) != pktlen)
574 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
575 return; /* Cannot handle fragmented packet. */
579 if (pktlen < (hlen + sizeof(struct tcphdr)))
583 if (pktlen < (hlen + sizeof(struct udphdr)))
585 uh = (struct udphdr *)((uint8_t *)ip + hlen);
587 return; /* no checksum */
594 /* checksum fixup for IP options */
595 len = hlen - sizeof(struct ip);
597 opts = (uint16_t *)(ip + 1);
598 for (; len > 0; len -= sizeof(uint16_t), opts++) {
599 temp32 = cksum - *opts;
600 temp32 = (temp32 >> 16) + (temp32 & 65535);
601 cksum = temp32 & 65535;
604 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
605 m->m_pkthdr.csum_data = cksum;
609 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
611 struct cas_softc *sc = xsc;
616 panic("%s: bad control buffer segment count", __func__);
617 sc->sc_cddma = segs[0].ds_addr;
621 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
623 struct cas_softc *sc = xsc;
628 panic("%s: bad RX buffer segment count", __func__);
629 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr;
635 struct cas_softc *sc = arg;
636 struct ifnet *ifp = sc->sc_ifp;
639 CAS_LOCK_ASSERT(sc, MA_OWNED);
642 * Unload collision and error counters.
644 ifp->if_collisions +=
645 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) +
646 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT);
647 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) +
648 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT);
649 ifp->if_collisions += v;
650 ifp->if_oerrors += v;
652 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) +
653 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) +
654 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) +
655 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL);
658 * Then clear the hardware counters.
660 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
661 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
662 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
663 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
664 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
665 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
666 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
667 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
669 mii_tick(sc->sc_mii);
671 if (sc->sc_txfree != CAS_MAXTXFREE)
676 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
680 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
685 for (i = CAS_TRIES; i--; DELAY(100)) {
686 reg = CAS_READ_4(sc, r);
687 if ((reg & clr) == 0 && (reg & set) == set)
694 cas_reset(struct cas_softc *sc)
698 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
700 /* Disable all interrupts in order to avoid spurious ones. */
701 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
707 * Do a full reset modulo the result of the last auto-negotiation
708 * when using the SERDES.
710 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
711 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
712 CAS_BARRIER(sc, CAS_RESET, 4,
713 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
715 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
716 device_printf(sc->sc_dev, "cannot reset device\n");
720 cas_stop(struct ifnet *ifp)
722 struct cas_softc *sc = ifp->if_softc;
723 struct cas_txsoft *txs;
726 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
729 callout_stop(&sc->sc_tick_ch);
730 callout_stop(&sc->sc_rx_ch);
732 /* Disable all interrupts in order to avoid spurious ones. */
733 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
739 * Release any queued transmit buffers.
741 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
742 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
743 if (txs->txs_ndescs != 0) {
744 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
745 BUS_DMASYNC_POSTWRITE);
746 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
747 if (txs->txs_mbuf != NULL) {
748 m_freem(txs->txs_mbuf);
749 txs->txs_mbuf = NULL;
752 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
756 * Mark the interface down and cancel the watchdog timer.
758 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
759 sc->sc_flags &= ~CAS_LINK;
760 sc->sc_wdog_timer = 0;
764 cas_reset_rx(struct cas_softc *sc)
768 * Resetting while DMA is in progress can cause a bus hang, so we
771 (void)cas_disable_rx(sc);
772 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
773 CAS_BARRIER(sc, CAS_RX_CONF, 4,
774 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
775 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0))
776 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
778 /* Finally, reset the ERX. */
779 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
780 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
781 CAS_BARRIER(sc, CAS_RESET, 4,
782 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
783 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) {
784 device_printf(sc->sc_dev, "cannot reset receiver\n");
791 cas_reset_tx(struct cas_softc *sc)
795 * Resetting while DMA is in progress can cause a bus hang, so we
798 (void)cas_disable_tx(sc);
799 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
800 CAS_BARRIER(sc, CAS_TX_CONF, 4,
801 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
802 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0))
803 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
805 /* Finally, reset the ETX. */
806 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
807 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
808 CAS_BARRIER(sc, CAS_RESET, 4,
809 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
810 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) {
811 device_printf(sc->sc_dev, "cannot reset transmitter\n");
818 cas_disable_rx(struct cas_softc *sc)
821 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
822 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN);
823 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
824 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
825 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
828 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
833 cas_disable_tx(struct cas_softc *sc)
836 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
837 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN);
838 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
839 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
840 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
843 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
848 cas_rxcompinit(struct cas_rx_comp *rxcomp)
851 rxcomp->crc_word1 = 0;
852 rxcomp->crc_word2 = 0;
854 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO));
855 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO);
859 cas_meminit(struct cas_softc *sc)
863 CAS_LOCK_ASSERT(sc, MA_OWNED);
866 * Initialize the transmit descriptor ring.
868 for (i = 0; i < CAS_NTXDESC; i++) {
869 sc->sc_txdescs[i].cd_flags = 0;
870 sc->sc_txdescs[i].cd_buf_ptr = 0;
872 sc->sc_txfree = CAS_MAXTXFREE;
877 * Initialize the receive completion ring.
879 for (i = 0; i < CAS_NRXCOMP; i++)
880 cas_rxcompinit(&sc->sc_rxcomps[i]);
884 * Initialize the first receive descriptor ring. We leave
885 * the second one zeroed as we don't actually use it.
887 for (i = 0; i < CAS_NRXDESC; i++)
888 CAS_INIT_RXDESC(sc, i, i);
891 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
895 cas_descsize(u_int sz)
900 return (CAS_DESC_32);
902 return (CAS_DESC_64);
904 return (CAS_DESC_128);
906 return (CAS_DESC_256);
908 return (CAS_DESC_512);
910 return (CAS_DESC_1K);
912 return (CAS_DESC_2K);
914 return (CAS_DESC_4K);
916 return (CAS_DESC_8K);
918 printf("%s: invalid descriptor ring size %d\n", __func__, sz);
919 return (CAS_DESC_32);
924 cas_rxcompsize(u_int sz)
929 return (CAS_RX_CONF_COMP_128);
931 return (CAS_RX_CONF_COMP_256);
933 return (CAS_RX_CONF_COMP_512);
935 return (CAS_RX_CONF_COMP_1K);
937 return (CAS_RX_CONF_COMP_2K);
939 return (CAS_RX_CONF_COMP_4K);
941 return (CAS_RX_CONF_COMP_8K);
943 return (CAS_RX_CONF_COMP_16K);
945 return (CAS_RX_CONF_COMP_32K);
947 printf("%s: invalid dcompletion ring size %d\n", __func__, sz);
948 return (CAS_RX_CONF_COMP_128);
955 struct cas_softc *sc = xsc;
963 * Initialization of interface; set up initialization block
964 * and transmit/receive descriptor rings.
967 cas_init_locked(struct cas_softc *sc)
969 struct ifnet *ifp = sc->sc_ifp;
972 CAS_LOCK_ASSERT(sc, MA_OWNED);
974 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
978 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev),
982 * Initialization sequence. The numbered steps below correspond
983 * to the sequence outlined in section 6.3.5.1 in the Ethernet
984 * Channel Engine manual (part of the PCIO manual).
985 * See also the STP2002-STQ document from Sun Microsystems.
988 /* step 1 & 2. Reset the Ethernet Channel. */
992 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev),
996 if ((sc->sc_flags & CAS_SERDES) == 0)
997 /* Re-initialize the MIF. */
1000 /* step 3. Setup data structures in host memory. */
1003 /* step 4. TX MAC registers & counters */
1006 /* step 5. RX MAC registers & counters */
1008 /* step 6 & 7. Program Ring Base Addresses. */
1009 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
1010 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32));
1011 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1012 CAS_CDTXDADDR(sc, 0) & 0xffffffff);
1014 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1015 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
1016 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1017 CAS_CDRXCADDR(sc, 0) & 0xffffffff);
1019 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1020 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32));
1021 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1022 CAS_CDRXDADDR(sc, 0) & 0xffffffff);
1024 if ((sc->sc_flags & CAS_REG_PLUS) != 0) {
1025 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1026 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32));
1027 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1028 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff);
1033 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx",
1034 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0),
1035 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma);
1038 /* step 8. Global Configuration & Interrupt Masks */
1040 /* Disable weighted round robin. */
1041 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1044 * Enable infinite bursts for revisions without PCI issues if
1045 * applicable. Doing so greatly improves the TX performance on
1046 * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX
1047 * performance only marginally but hurts RX throughput quite a bit).
1049 CAS_WRITE_4(sc, CAS_INF_BURST,
1050 #if !defined(__sparc64__)
1051 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN :
1055 /* Set up interrupts. */
1056 CAS_WRITE_4(sc, CAS_INTMASK,
1057 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
1058 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
1059 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
1060 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
1061 CAS_INTR_PCI_ERROR_INT
1063 | CAS_INTR_PCS_INT | CAS_INTR_MIF
1066 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */
1067 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1068 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1069 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1070 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR));
1072 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1073 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1074 CAS_MAC_CTRL_NON_PAUSE));
1076 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1077 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1078 CAS_MAC_CTRL_NON_PAUSE);
1081 /* Enable PCI error interrupts. */
1082 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1083 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO |
1084 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO));
1086 /* Enable PCI error interrupts in BIM configuration. */
1087 CAS_WRITE_4(sc, CAS_BIM_CONF,
1088 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN);
1091 * step 9. ETX Configuration: encode receive descriptor ring size,
1092 * enable DMA and disable pre-interrupt writeback completion.
1094 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT;
1095 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1096 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS);
1098 /* step 10. ERX Configuration */
1101 * Encode receive completion and descriptor ring sizes, set the
1104 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT;
1105 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT;
1106 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1107 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT;
1108 CAS_WRITE_4(sc, CAS_RX_CONF,
1109 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT));
1111 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */
1112 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1113 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT));
1116 CAS_WRITE_4(sc, CAS_RX_BLANK,
1117 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT));
1119 /* Set RX_COMP_AFULL threshold to half of the RX completions. */
1120 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1121 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT);
1123 /* Initialize the RX page size register as appropriate for 8k. */
1124 CAS_WRITE_4(sc, CAS_RX_PSZ,
1125 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) |
1126 (4 << CAS_RX_PSZ_MB_CNT_SHFT) |
1127 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) |
1128 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT));
1130 /* Disable RX random early detection. */
1131 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1133 /* Zero the RX reassembly DMA table. */
1134 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) {
1135 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1138 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1141 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */
1142 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1143 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1145 /* Finally, enable RX DMA. */
1146 CAS_WRITE_4(sc, CAS_RX_CONF,
1147 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN);
1149 /* step 11. Configure Media. */
1151 /* step 12. RX_MAC Configuration Register */
1152 v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
1153 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN);
1154 v |= CAS_MAC_RX_CONF_STRPFCS;
1155 sc->sc_mac_rxcfg = v;
1157 * Clear the RX filter and reprogram it. This will also set the
1158 * current RX MAC configuration and enable it.
1162 /* step 13. TX_MAC Configuration Register */
1163 v = CAS_READ_4(sc, CAS_MAC_TX_CONF);
1164 v |= CAS_MAC_TX_CONF_EN;
1165 (void)cas_disable_tx(sc);
1166 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1168 /* step 14. Issue Transmit Pending command. */
1170 /* step 15. Give the receiver a swift kick. */
1171 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1172 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1173 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1174 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1176 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1177 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1179 mii_mediachg(sc->sc_mii);
1181 /* Start the one second timer. */
1182 sc->sc_wdog_timer = 0;
1183 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
1187 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head)
1189 bus_dma_segment_t txsegs[CAS_NTXSEGS];
1190 struct cas_txsoft *txs;
1194 int error, nexttx, nsegs, offset, seg;
1196 CAS_LOCK_ASSERT(sc, MA_OWNED);
1198 /* Get a work queue entry. */
1199 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1200 /* Ran out of descriptors. */
1205 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) {
1206 if (M_WRITABLE(*m_head) == 0) {
1207 m = m_dup(*m_head, M_NOWAIT);
1213 offset = sizeof(struct ether_header);
1214 m = m_pullup(*m_head, offset + sizeof(struct ip));
1219 ip = (struct ip *)(mtod(m, caddr_t) + offset);
1220 offset += (ip->ip_hl << 2);
1221 cflags = (offset << CAS_TD_CKSUM_START_SHFT) |
1222 ((offset + m->m_pkthdr.csum_data) <<
1223 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN;
1227 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
1228 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1229 if (error == EFBIG) {
1230 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS);
1237 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag,
1238 txs->txs_dmamap, *m_head, txsegs, &nsegs,
1245 } else if (error != 0)
1247 /* If nsegs is wrong then the stack is corrupt. */
1248 KASSERT(nsegs <= CAS_NTXSEGS,
1249 ("%s: too many DMA segments (%d)", __func__, nsegs));
1257 * Ensure we have enough descriptors free to describe
1258 * the packet. Note, we always reserve one descriptor
1259 * at the end of the ring as a termination point, in
1260 * order to prevent wrap-around.
1262 if (nsegs > sc->sc_txfree - 1) {
1263 txs->txs_ndescs = 0;
1264 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1268 txs->txs_ndescs = nsegs;
1269 txs->txs_firstdesc = sc->sc_txnext;
1270 nexttx = txs->txs_firstdesc;
1271 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) {
1274 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1275 __func__, seg, nexttx, txsegs[seg].ds_len,
1276 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr));
1278 sc->sc_txdescs[nexttx].cd_buf_ptr =
1279 htole64(txsegs[seg].ds_addr);
1280 KASSERT(txsegs[seg].ds_len <
1281 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT,
1282 ("%s: segment size too large!", __func__));
1283 sc->sc_txdescs[nexttx].cd_flags =
1284 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT);
1285 txs->txs_lastdesc = nexttx;
1288 /* Set EOF on the last descriptor. */
1290 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d",
1291 __func__, seg, nexttx);
1293 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |=
1294 htole64(CAS_TD_END_OF_FRAME);
1296 /* Lastly set SOF on the first descriptor. */
1298 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d",
1299 __func__, seg, nexttx);
1301 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) {
1303 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1304 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME);
1306 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1307 htole64(cflags | CAS_TD_START_OF_FRAME);
1309 /* Sync the DMA map. */
1310 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1311 BUS_DMASYNC_PREWRITE);
1314 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1315 __func__, txs->txs_firstdesc, txs->txs_lastdesc,
1318 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1319 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1320 txs->txs_mbuf = *m_head;
1322 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc);
1323 sc->sc_txfree -= txs->txs_ndescs;
1329 cas_init_regs(struct cas_softc *sc)
1332 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1334 CAS_LOCK_ASSERT(sc, MA_OWNED);
1336 /* These registers are not cleared on reset. */
1337 if ((sc->sc_flags & CAS_INITED) == 0) {
1339 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1340 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1341 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1343 /* min frame length */
1344 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1345 /* max frame length and max burst size */
1346 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1347 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) <<
1348 CAS_MAC_MAX_BF_FRM_SHFT) |
1349 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT));
1351 /* more magic values */
1352 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1353 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1354 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1355 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1357 /* random number seed */
1358 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1359 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1361 /* secondary MAC addresses: 0:0:0:0:0:0 */
1362 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41;
1363 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3)
1364 CAS_WRITE_4(sc, i, 0);
1366 /* MAC control address: 01:80:c2:00:00:01 */
1367 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1368 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1369 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1371 /* MAC filter address: 0:0:0:0:0:0 */
1372 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1376 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1378 /* Zero the hash table. */
1379 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15;
1380 i += CAS_MAC_HASH1 - CAS_MAC_HASH0)
1381 CAS_WRITE_4(sc, i, 0);
1383 sc->sc_flags |= CAS_INITED;
1386 /* Counters need to be zeroed. */
1387 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1388 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1389 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1390 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1391 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1392 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1393 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1394 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1395 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1396 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1397 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1399 /* Set XOFF PAUSE time. */
1400 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1402 /* Set the station address. */
1403 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1404 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1405 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1407 /* Enable MII outputs. */
1408 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1412 cas_tx_task(void *arg, int pending __unused)
1416 ifp = (struct ifnet *)arg;
1421 cas_txkick(struct cas_softc *sc)
1425 * Update the TX kick register. This register has to point to the
1426 * descriptor after the last valid one and for optimum performance
1427 * should be incremented in multiples of 4 (the DMA engine fetches/
1428 * updates descriptors in batches of 4).
1431 CTR3(KTR_CAS, "%s: %s: kicking TX %d",
1432 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1434 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1435 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1439 cas_start(struct ifnet *ifp)
1441 struct cas_softc *sc = ifp->if_softc;
1447 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1448 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) {
1453 if (sc->sc_txfree < CAS_MAXTXFREE / 4)
1457 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d",
1458 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1463 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1464 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1467 if (cas_load_txmbuf(sc, &m) != 0) {
1470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1471 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1474 if ((sc->sc_txnext % 4) == 0) {
1487 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d",
1488 device_get_name(sc->sc_dev), sc->sc_txnext);
1491 /* Set a watchdog timer in case the chip flakes out. */
1492 sc->sc_wdog_timer = 5;
1494 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1495 device_get_name(sc->sc_dev), __func__,
1504 cas_tint(struct cas_softc *sc)
1506 struct ifnet *ifp = sc->sc_ifp;
1507 struct cas_txsoft *txs;
1513 CAS_LOCK_ASSERT(sc, MA_OWNED);
1515 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1519 * Go through our TX list and free mbufs for those
1520 * frames that have been transmitted.
1523 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1524 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1526 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1527 printf(" txsoft %p transmit chain:\n", txs);
1528 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) {
1529 printf("descriptor %d: ", i);
1530 printf("cd_flags: 0x%016llx\t",
1532 sc->sc_txdescs[i].cd_flags));
1533 printf("cd_buf_ptr: 0x%016llx\n",
1535 sc->sc_txdescs[i].cd_buf_ptr));
1536 if (i == txs->txs_lastdesc)
1543 * In theory, we could harvest some descriptors before
1544 * the ring is empty, but that's a bit complicated.
1546 * CAS_TX_COMPn points to the last descriptor
1549 txlast = CAS_READ_4(sc, CAS_TX_COMP3);
1551 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, "
1552 "txs->txs_lastdesc = %d, txlast = %d",
1553 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1555 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1556 if ((txlast >= txs->txs_firstdesc) &&
1557 (txlast <= txs->txs_lastdesc))
1560 /* Ick -- this command wraps. */
1561 if ((txlast >= txs->txs_firstdesc) ||
1562 (txlast <= txs->txs_lastdesc))
1567 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__);
1569 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1571 sc->sc_txfree += txs->txs_ndescs;
1573 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1574 BUS_DMASYNC_POSTWRITE);
1575 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1576 if (txs->txs_mbuf != NULL) {
1577 m_freem(txs->txs_mbuf);
1578 txs->txs_mbuf = NULL;
1581 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1588 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx "
1590 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2),
1591 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) |
1592 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO),
1593 CAS_READ_4(sc, CAS_TX_COMP3));
1597 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */
1598 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1599 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1600 sc->sc_wdog_timer = 0;
1604 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1605 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1610 cas_rint_timeout(void *arg)
1612 struct cas_softc *sc = arg;
1614 CAS_LOCK_ASSERT(sc, MA_OWNED);
1620 cas_rint(struct cas_softc *sc)
1622 struct cas_rxdsoft *rxds, *rxds2;
1623 struct ifnet *ifp = sc->sc_ifp;
1624 struct mbuf *m, *m2;
1625 uint64_t word1, word2, word3, word4;
1627 u_int idx, idx2, len, off, skip;
1629 CAS_LOCK_ASSERT(sc, MA_OWNED);
1631 callout_stop(&sc->sc_rx_ch);
1634 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1637 #define PRINTWORD(n, delimiter) \
1638 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter)
1640 #define SKIPASSERT(n) \
1641 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \
1642 ("%s: word ## n not 0", __func__))
1644 #define WORDTOH(n) \
1645 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n)
1648 * Read the completion head register once. This limits
1649 * how long the following loop can execute.
1651 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD);
1653 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1654 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead);
1657 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1658 for (; sc->sc_rxcptr != rxhead;
1659 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) {
1675 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1676 printf(" completion %d: ", sc->sc_rxcptr);
1684 if (__predict_false(
1685 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW ||
1686 (word4 & CAS_RC4_ZERO) != 0)) {
1688 * The descriptor is still marked as owned, although
1689 * it is supposed to have completed. This has been
1690 * observed on some machines. Just exiting here
1691 * might leave the packet sitting around until another
1692 * one arrives to trigger a new interrupt, which is
1693 * generally undesirable, so set up a timeout.
1695 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS,
1696 cas_rint_timeout, sc);
1700 if (__predict_false(
1701 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) {
1703 device_printf(sc->sc_dev,
1704 "receive error: CRC error\n");
1708 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1709 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1710 ("%s: data and header present", __func__));
1711 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 ||
1712 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1713 ("%s: split and header present", __func__));
1714 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1715 (word1 & CAS_RC1_RELEASE_HDR) == 0,
1716 ("%s: data present but header release", __func__));
1717 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 ||
1718 (word1 & CAS_RC1_RELEASE_DATA) == 0,
1719 ("%s: header present but data release", __func__));
1721 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) {
1722 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX);
1723 off = CAS_GET(word2, CAS_RC2_HDR_OFF);
1725 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d",
1726 __func__, idx, off, len);
1728 rxds = &sc->sc_rxdsoft[idx];
1729 MGETHDR(m, M_NOWAIT, MT_DATA);
1731 refcount_acquire(&rxds->rxds_refcount);
1732 bus_dmamap_sync(sc->sc_rdmatag,
1733 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1734 #if __FreeBSD_version < 800016
1735 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1736 off * 256 + ETHER_ALIGN, len, cas_free,
1737 rxds, M_RDONLY, EXT_NET_DRV);
1739 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1740 off * 256 + ETHER_ALIGN, len, cas_free,
1741 sc, (void *)(uintptr_t)idx,
1742 M_RDONLY, EXT_NET_DRV);
1744 if ((m->m_flags & M_EXT) == 0) {
1750 m->m_pkthdr.rcvif = ifp;
1751 m->m_pkthdr.len = m->m_len = len;
1753 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1754 cas_rxcksum(m, CAS_GET(word4,
1758 (*ifp->if_input)(ifp, m);
1763 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 &&
1764 refcount_release(&rxds->rxds_refcount) != 0)
1765 cas_add_rxdesc(sc, idx);
1766 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) {
1767 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX);
1768 off = CAS_GET(word1, CAS_RC1_DATA_OFF);
1770 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d",
1771 __func__, idx, off, len);
1773 rxds = &sc->sc_rxdsoft[idx];
1774 MGETHDR(m, M_NOWAIT, MT_DATA);
1776 refcount_acquire(&rxds->rxds_refcount);
1778 m->m_len = min(CAS_PAGE_SIZE - off, len);
1779 bus_dmamap_sync(sc->sc_rdmatag,
1780 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1781 #if __FreeBSD_version < 800016
1782 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1783 m->m_len, cas_free, rxds, M_RDONLY,
1786 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1787 m->m_len, cas_free, sc,
1788 (void *)(uintptr_t)idx, M_RDONLY,
1791 if ((m->m_flags & M_EXT) == 0) {
1799 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) {
1800 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0,
1801 ("%s: split but no release next",
1804 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX);
1806 CTR2(KTR_CAS, "%s: split at idx %d",
1809 rxds2 = &sc->sc_rxdsoft[idx2];
1811 MGET(m2, M_NOWAIT, MT_DATA);
1814 &rxds2->rxds_refcount);
1815 m2->m_len = len - m->m_len;
1819 BUS_DMASYNC_POSTREAD);
1820 #if __FreeBSD_version < 800016
1822 (caddr_t)rxds2->rxds_buf,
1823 m2->m_len, cas_free,
1828 (caddr_t)rxds2->rxds_buf,
1829 m2->m_len, cas_free, sc,
1830 (void *)(uintptr_t)idx2,
1831 M_RDONLY, EXT_NET_DRV);
1833 if ((m2->m_flags & M_EXT) ==
1842 else if (m != NULL) {
1848 m->m_pkthdr.rcvif = ifp;
1849 m->m_pkthdr.len = len;
1851 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1852 cas_rxcksum(m, CAS_GET(word4,
1856 (*ifp->if_input)(ifp, m);
1861 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 &&
1862 refcount_release(&rxds->rxds_refcount) != 0)
1863 cas_add_rxdesc(sc, idx);
1864 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 &&
1865 refcount_release(&rxds2->rxds_refcount) != 0)
1866 cas_add_rxdesc(sc, idx2);
1869 skip = CAS_GET(word1, CAS_RC1_SKIP);
1872 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]);
1873 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1876 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1877 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1884 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1885 __func__, sc->sc_rxcptr, sc->sc_rxdptr,
1886 CAS_READ_4(sc, CAS_RX_COMP_HEAD));
1891 cas_free(void *arg1, void *arg2)
1893 struct cas_rxdsoft *rxds;
1894 struct cas_softc *sc;
1897 #if __FreeBSD_version < 800016
1900 idx = rxds->rxds_idx;
1903 idx = (uintptr_t)arg2;
1904 rxds = &sc->sc_rxdsoft[idx];
1906 if (refcount_release(&rxds->rxds_refcount) == 0)
1910 * NB: this function can be called via m_freem(9) within
1913 if ((locked = CAS_LOCK_OWNED(sc)) == 0)
1915 cas_add_rxdesc(sc, idx);
1921 cas_add_rxdesc(struct cas_softc *sc, u_int idx)
1924 CAS_LOCK_ASSERT(sc, MA_OWNED);
1926 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap,
1927 BUS_DMASYNC_PREREAD);
1928 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx);
1929 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr);
1932 * Update the RX kick register. This register has to point to the
1933 * descriptor after the last valid one (before the current batch)
1934 * and for optimum performance should be incremented in multiples
1935 * of 4 (the DMA engine fetches/updates descriptors in batches of 4).
1937 if ((sc->sc_rxdptr % 4) == 0) {
1938 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1939 CAS_WRITE_4(sc, CAS_RX_KICK,
1940 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK);
1945 cas_eint(struct cas_softc *sc, u_int status)
1947 struct ifnet *ifp = sc->sc_ifp;
1949 CAS_LOCK_ASSERT(sc, MA_OWNED);
1953 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1954 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) {
1955 status = CAS_READ_4(sc, CAS_ERROR_STATUS);
1956 printf(", PCI bus error 0x%x", status);
1957 if ((status & CAS_ERROR_OTHER) != 0) {
1958 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
1959 printf(", PCI status 0x%x", status);
1960 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
1965 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1966 cas_init_locked(sc);
1967 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1968 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
1974 struct cas_softc *sc = v;
1976 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) &
1977 CAS_INTR_SUMMARY) == 0))
1978 return (FILTER_STRAY);
1980 /* Disable interrupts. */
1981 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
1982 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1984 return (FILTER_HANDLED);
1988 cas_intr_task(void *arg, int pending __unused)
1990 struct cas_softc *sc = arg;
1991 struct ifnet *ifp = sc->sc_ifp;
1992 uint32_t status, status2;
1994 CAS_LOCK_ASSERT(sc, MA_NOTOWNED);
1996 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1999 status = CAS_READ_4(sc, CAS_STATUS);
2000 if (__predict_false((status & CAS_INTR_SUMMARY) == 0))
2005 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x",
2006 device_get_name(sc->sc_dev), __func__,
2007 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status);
2010 * PCS interrupts must be cleared, otherwise no traffic is passed!
2012 if ((status & CAS_INTR_PCS_INT) != 0) {
2014 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) |
2015 CAS_READ_4(sc, CAS_PCS_INTR_STATUS);
2016 if ((status2 & CAS_PCS_INTR_LINK) != 0)
2017 device_printf(sc->sc_dev,
2018 "%s: PCS link status changed\n", __func__);
2020 if ((status & CAS_MAC_CTRL_STATUS) != 0) {
2021 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS);
2022 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2023 device_printf(sc->sc_dev,
2024 "%s: PAUSE received (PAUSE time %d slots)\n",
2026 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >>
2027 CAS_MAC_CTRL_STATUS_PT_SHFT);
2028 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2029 device_printf(sc->sc_dev,
2030 "%s: transited to PAUSE state\n", __func__);
2031 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0)
2032 device_printf(sc->sc_dev,
2033 "%s: transited to non-PAUSE state\n", __func__);
2035 if ((status & CAS_INTR_MIF) != 0)
2036 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
2039 if (__predict_false((status &
2040 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
2041 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) {
2042 cas_eint(sc, status);
2047 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) {
2048 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS);
2050 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0)
2052 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0)
2053 device_printf(sc->sc_dev,
2054 "MAC TX fault, status %x\n", status2);
2057 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) {
2058 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS);
2059 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0)
2061 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0)
2062 device_printf(sc->sc_dev,
2063 "MAC RX fault, status %x\n", status2);
2067 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2068 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) {
2071 if (__predict_false((status &
2072 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2073 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0))
2074 device_printf(sc->sc_dev,
2075 "RX fault, status %x\n", status);
2080 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0)
2083 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2086 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2087 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2090 status = CAS_READ_4(sc, CAS_STATUS_ALIAS);
2091 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) {
2092 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
2097 /* Re-enable interrupts. */
2098 CAS_WRITE_4(sc, CAS_INTMASK,
2099 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
2100 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
2101 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
2102 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
2103 CAS_INTR_PCI_ERROR_INT
2105 | CAS_INTR_PCS_INT | CAS_INTR_MIF
2111 cas_watchdog(struct cas_softc *sc)
2113 struct ifnet *ifp = sc->sc_ifp;
2115 CAS_LOCK_ASSERT(sc, MA_OWNED);
2119 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x",
2120 __func__, CAS_READ_4(sc, CAS_RX_CONF),
2121 CAS_READ_4(sc, CAS_MAC_RX_STATUS),
2122 CAS_READ_4(sc, CAS_MAC_RX_CONF));
2124 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x",
2125 __func__, CAS_READ_4(sc, CAS_TX_CONF),
2126 CAS_READ_4(sc, CAS_MAC_TX_STATUS),
2127 CAS_READ_4(sc, CAS_MAC_TX_CONF));
2130 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
2133 if ((sc->sc_flags & CAS_LINK) != 0)
2134 device_printf(sc->sc_dev, "device timeout\n");
2135 else if (bootverbose)
2136 device_printf(sc->sc_dev, "device timeout (no link)\n");
2139 /* Try to get more packets going. */
2140 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2141 cas_init_locked(sc);
2142 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2143 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2147 cas_mifinit(struct cas_softc *sc)
2150 /* Configure the MIF in frame mode. */
2151 CAS_WRITE_4(sc, CAS_MIF_CONF,
2152 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE);
2153 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
2154 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2160 * The MII interface supports at least three different operating modes:
2162 * Bitbang mode is implemented using data, clock and output enable registers.
2164 * Frame mode is implemented by loading a complete frame into the frame
2165 * register and polling the valid bit for completion.
2167 * Polling mode uses the frame register but completion is indicated by
2172 cas_mii_readreg(device_t dev, int phy, int reg)
2174 struct cas_softc *sc;
2178 #ifdef CAS_DEBUG_PHY
2179 printf("%s: phy %d reg %d\n", __func__, phy, reg);
2182 sc = device_get_softc(dev);
2183 if ((sc->sc_flags & CAS_SERDES) != 0) {
2189 reg = CAS_PCS_STATUS;
2198 reg = CAS_PCS_ANLPAR;
2201 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
2203 device_printf(sc->sc_dev,
2204 "%s: unhandled register %d\n", __func__, reg);
2207 return (CAS_READ_4(sc, reg));
2210 /* Construct the frame command. */
2211 v = CAS_MIF_FRAME_READ |
2212 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2213 (reg << CAS_MIF_FRAME_REG_SHFT);
2215 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2216 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2217 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2218 for (n = 0; n < 100; n++) {
2220 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2221 if (v & CAS_MIF_FRAME_TA_LSB)
2222 return (v & CAS_MIF_FRAME_DATA);
2225 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2230 cas_mii_writereg(device_t dev, int phy, int reg, int val)
2232 struct cas_softc *sc;
2236 #ifdef CAS_DEBUG_PHY
2237 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
2240 sc = device_get_softc(dev);
2241 if ((sc->sc_flags & CAS_SERDES) != 0) {
2244 reg = CAS_PCS_STATUS;
2248 if ((val & CAS_PCS_CTRL_RESET) == 0)
2250 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2251 CAS_BARRIER(sc, CAS_PCS_CTRL, 4,
2252 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2253 if (!cas_bitwait(sc, CAS_PCS_CTRL,
2254 CAS_PCS_CTRL_RESET, 0))
2255 device_printf(sc->sc_dev,
2256 "cannot reset PCS\n");
2259 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2260 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2261 BUS_SPACE_BARRIER_WRITE);
2262 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2263 CAS_BARRIER(sc, CAS_PCS_ANAR, 4,
2264 BUS_SPACE_BARRIER_WRITE);
2265 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2266 CAS_PCS_SERDES_CTRL_ESD);
2267 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2268 BUS_SPACE_BARRIER_WRITE);
2269 CAS_WRITE_4(sc, CAS_PCS_CONF,
2271 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2272 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2275 reg = CAS_PCS_ANLPAR;
2278 device_printf(sc->sc_dev,
2279 "%s: unhandled register %d\n", __func__, reg);
2282 CAS_WRITE_4(sc, reg, val);
2283 CAS_BARRIER(sc, reg, 4,
2284 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2288 /* Construct the frame command. */
2289 v = CAS_MIF_FRAME_WRITE |
2290 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2291 (reg << CAS_MIF_FRAME_REG_SHFT) |
2292 (val & CAS_MIF_FRAME_DATA);
2294 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2295 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2296 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2297 for (n = 0; n < 100; n++) {
2299 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2300 if (v & CAS_MIF_FRAME_TA_LSB)
2304 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2309 cas_mii_statchg(device_t dev)
2311 struct cas_softc *sc;
2314 uint32_t rxcfg, txcfg, v;
2316 sc = device_get_softc(dev);
2319 CAS_LOCK_ASSERT(sc, MA_OWNED);
2322 if ((ifp->if_flags & IFF_DEBUG) != 0)
2323 device_printf(sc->sc_dev, "%s: status changen", __func__);
2326 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2327 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2328 sc->sc_flags |= CAS_LINK;
2330 sc->sc_flags &= ~CAS_LINK;
2332 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2344 * The configuration done here corresponds to the steps F) and
2345 * G) and as far as enabling of RX and TX MAC goes also step H)
2346 * of the initialization sequence outlined in section 11.2.1 of
2347 * the Cassini+ ASIC Specification.
2350 rxcfg = sc->sc_mac_rxcfg;
2351 rxcfg &= ~CAS_MAC_RX_CONF_CARR;
2352 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU |
2353 CAS_MAC_TX_CONF_NGUL;
2354 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2355 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS;
2356 else if (gigabit != 0) {
2357 rxcfg |= CAS_MAC_RX_CONF_CARR;
2358 txcfg |= CAS_MAC_TX_CONF_CARR;
2360 (void)cas_disable_tx(sc);
2361 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2362 (void)cas_disable_rx(sc);
2363 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2365 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) &
2366 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP);
2367 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2368 IFM_ETH_RXPAUSE) != 0)
2369 v |= CAS_MAC_CTRL_CONF_RXP;
2370 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2371 IFM_ETH_TXPAUSE) != 0)
2372 v |= CAS_MAC_CTRL_CONF_TXP;
2373 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2376 * All supported chips have a bug causing incorrect checksum
2377 * to be calculated when letting them strip the FCS in half-
2378 * duplex mode. In theory we could disable FCS stripping and
2379 * manually adjust the checksum accordingly. It seems to make
2380 * more sense to optimze for the common case and just disable
2381 * hardware checksumming in half-duplex mode though.
2383 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) {
2384 ifp->if_capenable &= ~IFCAP_HWCSUM;
2385 ifp->if_hwassist = 0;
2386 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
2387 ifp->if_capenable = ifp->if_capabilities;
2388 ifp->if_hwassist = CAS_CSUM_FEATURES;
2391 if (sc->sc_variant == CAS_SATURN) {
2392 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2393 /* silicon bug workaround */
2394 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2396 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2399 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2401 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2402 CAS_MAC_SLOT_TIME_CARR);
2404 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2405 CAS_MAC_SLOT_TIME_NORM);
2407 /* XIF Configuration */
2408 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED;
2409 if ((sc->sc_flags & CAS_SERDES) == 0) {
2410 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2411 v |= CAS_MAC_XIF_CONF_NOECHO;
2412 v |= CAS_MAC_XIF_CONF_BUF_OE;
2415 v |= CAS_MAC_XIF_CONF_GMII;
2416 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2417 v |= CAS_MAC_XIF_CONF_FDXLED;
2418 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2420 sc->sc_mac_rxcfg = rxcfg;
2421 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2422 (sc->sc_flags & CAS_LINK) != 0) {
2423 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2424 txcfg | CAS_MAC_TX_CONF_EN);
2425 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2426 rxcfg | CAS_MAC_RX_CONF_EN);
2431 cas_mediachange(struct ifnet *ifp)
2433 struct cas_softc *sc = ifp->if_softc;
2436 /* XXX add support for serial media. */
2439 error = mii_mediachg(sc->sc_mii);
2445 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2447 struct cas_softc *sc = ifp->if_softc;
2450 if ((ifp->if_flags & IFF_UP) == 0) {
2455 mii_pollstat(sc->sc_mii);
2456 ifmr->ifm_active = sc->sc_mii->mii_media_active;
2457 ifmr->ifm_status = sc->sc_mii->mii_media_status;
2462 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2464 struct cas_softc *sc = ifp->if_softc;
2465 struct ifreq *ifr = (struct ifreq *)data;
2472 if ((ifp->if_flags & IFF_UP) != 0) {
2473 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2474 ((ifp->if_flags ^ sc->sc_ifflags) &
2475 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2478 cas_init_locked(sc);
2479 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2481 sc->sc_ifflags = ifp->if_flags;
2486 if ((sc->sc_flags & CAS_NO_CSUM) != 0) {
2491 ifp->if_capenable = ifr->ifr_reqcap;
2492 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2493 ifp->if_hwassist = CAS_CSUM_FEATURES;
2495 ifp->if_hwassist = 0;
2501 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2506 if ((ifr->ifr_mtu < ETHERMIN) ||
2507 (ifr->ifr_mtu > ETHERMTU_JUMBO))
2510 ifp->if_mtu = ifr->ifr_mtu;
2514 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
2517 error = ether_ioctl(ifp, cmd, data);
2525 cas_setladrf(struct cas_softc *sc)
2527 struct ifnet *ifp = sc->sc_ifp;
2528 struct ifmultiaddr *inm;
2533 CAS_LOCK_ASSERT(sc, MA_OWNED);
2536 * Turn off the RX MAC and the hash filter as required by the Sun
2537 * Cassini programming restrictions.
2539 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER |
2540 CAS_MAC_RX_CONF_EN);
2541 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2542 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
2543 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2544 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER |
2545 CAS_MAC_RX_CONF_EN, 0))
2546 device_printf(sc->sc_dev,
2547 "cannot disable RX MAC or hash filter\n");
2549 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP);
2550 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2551 v |= CAS_MAC_RX_CONF_PROMISC;
2554 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2555 v |= CAS_MAC_RX_CONF_PGRP;
2560 * Set up multicast address filter by passing all multicast
2561 * addresses through a crc generator, and then using the high
2562 * order 8 bits as an index into the 256 bit logical address
2563 * filter. The high order 4 bits selects the word, while the
2564 * other 4 bits select the bit within the word (where bit 0
2568 /* Clear the hash table. */
2569 memset(hash, 0, sizeof(hash));
2571 if_maddr_rlock(ifp);
2572 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
2573 if (inm->ifma_addr->sa_family != AF_LINK)
2575 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2576 inm->ifma_addr), ETHER_ADDR_LEN);
2578 /* We just want the 8 most significant bits. */
2581 /* Set the corresponding bit in the filter. */
2582 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2584 if_maddr_runlock(ifp);
2586 v |= CAS_MAC_RX_CONF_HFILTER;
2588 /* Now load the hash table into the chip (if we are using it). */
2589 for (i = 0; i < 16; i++)
2591 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
2595 sc->sc_mac_rxcfg = v;
2596 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2599 static int cas_pci_attach(device_t dev);
2600 static int cas_pci_detach(device_t dev);
2601 static int cas_pci_probe(device_t dev);
2602 static int cas_pci_resume(device_t dev);
2603 static int cas_pci_suspend(device_t dev);
2605 static device_method_t cas_pci_methods[] = {
2606 /* Device interface */
2607 DEVMETHOD(device_probe, cas_pci_probe),
2608 DEVMETHOD(device_attach, cas_pci_attach),
2609 DEVMETHOD(device_detach, cas_pci_detach),
2610 DEVMETHOD(device_suspend, cas_pci_suspend),
2611 DEVMETHOD(device_resume, cas_pci_resume),
2612 /* Use the suspend handler here, it is all that is required. */
2613 DEVMETHOD(device_shutdown, cas_pci_suspend),
2616 DEVMETHOD(miibus_readreg, cas_mii_readreg),
2617 DEVMETHOD(miibus_writereg, cas_mii_writereg),
2618 DEVMETHOD(miibus_statchg, cas_mii_statchg),
2623 static driver_t cas_pci_driver = {
2626 sizeof(struct cas_softc)
2629 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0);
2630 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0);
2631 MODULE_DEPEND(cas, pci, 1, 1, 1);
2633 static const struct cas_pci_dev {
2637 const char *cpd_desc;
2638 } cas_pci_devlist[] = {
2639 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" },
2640 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" },
2641 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" },
2646 cas_pci_probe(device_t dev)
2650 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2651 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2652 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2653 device_set_desc(dev, cas_pci_devlist[i].cpd_desc);
2654 return (BUS_PROBE_DEFAULT);
2661 static struct resource_spec cas_pci_res_spec[] = {
2662 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */
2663 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */
2667 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address"
2668 #define CAS_PHY_INTERFACE "phy-interface"
2669 #define CAS_PHY_TYPE "phy-type"
2670 #define CAS_PHY_TYPE_PCS "pcs"
2673 cas_pci_attach(device_t dev)
2675 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)];
2676 struct cas_softc *sc;
2678 #if !(defined(__powerpc__) || defined(__sparc64__))
2679 u_char enaddr[4][ETHER_ADDR_LEN];
2680 u_int j, k, lma, pcs[4], phy;
2683 sc = device_get_softc(dev);
2684 sc->sc_variant = CAS_UNKNOWN;
2685 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2686 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2687 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2688 sc->sc_variant = cas_pci_devlist[i].cpd_variant;
2692 if (sc->sc_variant == CAS_UNKNOWN) {
2693 device_printf(dev, "unknown adaptor\n");
2697 /* PCI configuration */
2698 pci_write_config(dev, PCIR_COMMAND,
2699 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN |
2700 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2);
2703 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02)
2704 /* Hardware checksumming may hang TX. */
2705 sc->sc_flags |= CAS_NO_CSUM;
2706 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN)
2707 sc->sc_flags |= CAS_REG_PLUS;
2708 if (sc->sc_variant == CAS_CAS ||
2709 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11))
2710 sc->sc_flags |= CAS_TABORT;
2712 device_printf(dev, "flags=0x%x\n", sc->sc_flags);
2714 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) {
2715 device_printf(dev, "failed to allocate resources\n");
2716 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2720 CAS_LOCK_INIT(sc, device_get_nameunit(dev));
2722 #if defined(__powerpc__) || defined(__sparc64__)
2723 OF_getetheraddr(dev, sc->sc_enaddr);
2724 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf,
2725 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev),
2726 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) {
2727 buf[sizeof(buf) - 1] = '\0';
2728 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2729 sc->sc_flags |= CAS_SERDES;
2733 * Dig out VPD (vital product data) and read the MAC address as well
2734 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI
2735 * FCode) and can't be accessed via the PCI capability pointer.
2736 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described
2737 * in the free US Patent 7149820.
2740 #define PCI_ROMHDR_SIZE 0x1c
2741 #define PCI_ROMHDR_SIG 0x00
2742 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
2743 #define PCI_ROMHDR_PTR_DATA 0x18
2744 #define PCI_ROM_SIZE 0x18
2745 #define PCI_ROM_SIG 0x00
2746 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
2748 #define PCI_ROM_VENDOR 0x04
2749 #define PCI_ROM_DEVICE 0x06
2750 #define PCI_ROM_PTR_VPD 0x08
2751 #define PCI_VPDRES_BYTE0 0x00
2752 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
2753 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
2754 #define PCI_VPDRES_LARGE_LEN_LSB 0x01
2755 #define PCI_VPDRES_LARGE_LEN_MSB 0x02
2756 #define PCI_VPDRES_LARGE_SIZE 0x03
2757 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */
2758 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
2759 #define PCI_VPD_KEY0 0x00
2760 #define PCI_VPD_KEY1 0x01
2761 #define PCI_VPD_LEN 0x02
2762 #define PCI_VPD_SIZE 0x03
2764 #define CAS_ROM_READ_1(sc, offs) \
2765 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs))
2766 #define CAS_ROM_READ_2(sc, offs) \
2767 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs))
2768 #define CAS_ROM_READ_4(sc, offs) \
2769 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs))
2772 memset(enaddr, 0, sizeof(enaddr));
2773 memset(pcs, 0, sizeof(pcs));
2775 /* Enable PCI Expansion ROM access. */
2776 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2777 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM);
2779 /* Read PCI Expansion ROM header. */
2780 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
2781 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
2783 device_printf(dev, "unexpected PCI Expansion ROM header\n");
2787 /* Read PCI Expansion ROM data. */
2788 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
2789 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
2790 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
2791 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
2793 device_printf(dev, "unexpected PCI Expansion ROM data\n");
2799 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc,
2800 j + PCI_VPDRES_BYTE0)) == 0) {
2801 device_printf(dev, "no large PCI VPD\n");
2805 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) |
2806 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB);
2807 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc,
2808 j + PCI_VPDRES_BYTE0))) {
2809 case PCI_VPDRES_TYPE_ID_STRING:
2810 /* Skip identifier string. */
2811 j += PCI_VPDRES_LARGE_SIZE + i;
2813 case PCI_VPDRES_TYPE_VPD:
2814 for (j += PCI_VPDRES_LARGE_SIZE; i > 0;
2815 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN),
2816 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) {
2817 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z')
2818 /* no Enhanced VPD */
2820 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I')
2821 /* no instance property */
2823 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') {
2825 if (CAS_ROM_READ_1(sc,
2826 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN)
2828 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2829 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2831 buf[sizeof(buf) - 1] = '\0';
2832 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0)
2834 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2835 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2836 5 + sizeof(CAS_LOCAL_MAC_ADDRESS),
2837 enaddr[lma], sizeof(enaddr[lma]));
2839 if (lma == 4 && phy == 4)
2841 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) ==
2844 if (CAS_ROM_READ_1(sc,
2845 j + PCI_VPD_SIZE + 4) !=
2846 sizeof(CAS_PHY_TYPE_PCS))
2848 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2849 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2851 buf[sizeof(buf) - 1] = '\0';
2852 if (strcmp(buf, CAS_PHY_INTERFACE) == 0)
2853 k = sizeof(CAS_PHY_INTERFACE);
2854 else if (strcmp(buf, CAS_PHY_TYPE) == 0)
2855 k = sizeof(CAS_PHY_TYPE);
2858 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2859 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2860 5 + k, buf, sizeof(buf));
2861 buf[sizeof(buf) - 1] = '\0';
2862 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2865 if (lma == 4 && phy == 4)
2871 device_printf(dev, "unexpected PCI VPD\n");
2876 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);
2879 device_printf(dev, "could not determine Ethernet address\n");
2883 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr))
2884 i = pci_get_slot(dev);
2885 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN);
2888 device_printf(dev, "could not determine PHY type\n");
2892 if (phy > 1 && pci_get_slot(dev) < nitems(pcs))
2893 i = pci_get_slot(dev);
2895 sc->sc_flags |= CAS_SERDES;
2898 if (cas_attach(sc) != 0) {
2899 device_printf(dev, "could not be attached\n");
2903 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET |
2904 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) {
2905 device_printf(dev, "failed to set up interrupt\n");
2912 CAS_LOCK_DESTROY(sc);
2913 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2918 cas_pci_detach(device_t dev)
2920 struct cas_softc *sc;
2922 sc = device_get_softc(dev);
2923 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih);
2925 CAS_LOCK_DESTROY(sc);
2926 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2931 cas_pci_suspend(device_t dev)
2934 cas_suspend(device_get_softc(dev));
2939 cas_pci_resume(device_t dev)
2942 cas_resume(device_get_softc(dev));