2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065
37 * Saturn Gigabit Ethernet controllers
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/callout.h>
48 #include <sys/endian.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/refcount.h>
56 #include <sys/resource.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/taskqueue.h>
63 #include <net/ethernet.h>
65 #include <net/if_var.h>
66 #include <net/if_arp.h>
67 #include <net/if_dl.h>
68 #include <net/if_media.h>
69 #include <net/if_types.h>
70 #include <net/if_vlan_var.h>
72 #include <netinet/in.h>
73 #include <netinet/in_systm.h>
74 #include <netinet/ip.h>
75 #include <netinet/tcp.h>
76 #include <netinet/udp.h>
78 #include <machine/bus.h>
79 #if defined(__powerpc__) || defined(__sparc64__)
80 #include <dev/ofw/ofw_bus.h>
81 #include <dev/ofw/openfirm.h>
82 #include <machine/ofw_machdep.h>
84 #include <machine/resource.h>
86 #include <dev/mii/mii.h>
87 #include <dev/mii/miivar.h>
89 #include <dev/cas/if_casreg.h>
90 #include <dev/cas/if_casvar.h>
92 #include <dev/pci/pcireg.h>
93 #include <dev/pci/pcivar.h>
95 #include "miibus_if.h"
97 #define RINGASSERT(n , min, max) \
98 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max))
100 RINGASSERT(CAS_NRXCOMP, 128, 32768);
101 RINGASSERT(CAS_NRXDESC, 32, 8192);
102 RINGASSERT(CAS_NRXDESC2, 32, 8192);
103 RINGASSERT(CAS_NTXDESC, 32, 8192);
107 #define CCDASSERT(m, a) \
108 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0)
110 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN);
111 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN);
112 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN);
116 #define CAS_TRIES 10000
119 * According to documentation, the hardware has support for basic TCP
120 * checksum offloading only, in practice this can be also used for UDP
121 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0
122 * is not converted to 0xffff no longer exists).
124 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
126 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx);
127 static int cas_attach(struct cas_softc *sc);
128 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr,
130 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs,
131 int nsegs, int error);
132 static void cas_detach(struct cas_softc *sc);
133 static int cas_disable_rx(struct cas_softc *sc);
134 static int cas_disable_tx(struct cas_softc *sc);
135 static void cas_eint(struct cas_softc *sc, u_int status);
136 static int cas_free(struct mbuf *m, void *arg1, void* arg2);
137 static void cas_init(void *xsc);
138 static void cas_init_locked(struct cas_softc *sc);
139 static void cas_init_regs(struct cas_softc *sc);
140 static int cas_intr(void *v);
141 static void cas_intr_task(void *arg, int pending __unused);
142 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
143 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head);
144 static int cas_mediachange(struct ifnet *ifp);
145 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
146 static void cas_meminit(struct cas_softc *sc);
147 static void cas_mifinit(struct cas_softc *sc);
148 static int cas_mii_readreg(device_t dev, int phy, int reg);
149 static void cas_mii_statchg(device_t dev);
150 static int cas_mii_writereg(device_t dev, int phy, int reg, int val);
151 static void cas_reset(struct cas_softc *sc);
152 static int cas_reset_rx(struct cas_softc *sc);
153 static int cas_reset_tx(struct cas_softc *sc);
154 static void cas_resume(struct cas_softc *sc);
155 static u_int cas_descsize(u_int sz);
156 static void cas_rint(struct cas_softc *sc);
157 static void cas_rint_timeout(void *arg);
158 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum);
159 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp);
160 static u_int cas_rxcompsize(u_int sz);
161 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs,
162 int nsegs, int error);
163 static void cas_setladrf(struct cas_softc *sc);
164 static void cas_start(struct ifnet *ifp);
165 static void cas_stop(struct ifnet *ifp);
166 static void cas_suspend(struct cas_softc *sc);
167 static void cas_tick(void *arg);
168 static void cas_tint(struct cas_softc *sc);
169 static void cas_tx_task(void *arg, int pending __unused);
170 static inline void cas_txkick(struct cas_softc *sc);
171 static void cas_watchdog(struct cas_softc *sc);
173 static devclass_t cas_devclass;
175 MODULE_DEPEND(cas, ether, 1, 1, 1);
176 MODULE_DEPEND(cas, miibus, 1, 1, 1);
180 #define KTR_CAS KTR_SPARE2
184 cas_attach(struct cas_softc *sc)
186 struct cas_txsoft *txs;
191 /* Set up ifnet structure. */
192 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
196 if_initname(ifp, device_get_name(sc->sc_dev),
197 device_get_unit(sc->sc_dev));
198 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
199 ifp->if_start = cas_start;
200 ifp->if_ioctl = cas_ioctl;
201 ifp->if_init = cas_init;
202 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN);
203 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN;
204 IFQ_SET_READY(&ifp->if_snd);
206 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
207 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
208 /* Create local taskq. */
209 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc);
210 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp);
211 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK,
212 taskqueue_thread_enqueue, &sc->sc_tq);
213 if (sc->sc_tq == NULL) {
214 device_printf(sc->sc_dev, "could not create taskqueue\n");
218 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
219 device_get_nameunit(sc->sc_dev));
221 device_printf(sc->sc_dev, "could not start threads\n");
225 /* Make sure the chip is stopped. */
228 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
229 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
230 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL,
235 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
236 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
237 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag);
241 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
242 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
243 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES,
244 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
248 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0,
249 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
250 sizeof(struct cas_control_data), 1,
251 sizeof(struct cas_control_data), 0,
252 NULL, NULL, &sc->sc_cdmatag);
257 * Allocate the control data structures, create and load the
260 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
261 (void **)&sc->sc_control_data,
262 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
263 &sc->sc_cddmamap)) != 0) {
264 device_printf(sc->sc_dev,
265 "unable to allocate control data, error = %d\n", error);
270 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
271 sc->sc_control_data, sizeof(struct cas_control_data),
272 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
273 device_printf(sc->sc_dev,
274 "unable to load control data DMA map, error = %d\n",
280 * Initialize the transmit job descriptors.
282 STAILQ_INIT(&sc->sc_txfreeq);
283 STAILQ_INIT(&sc->sc_txdirtyq);
286 * Create the transmit buffer DMA maps.
289 for (i = 0; i < CAS_TXQUEUELEN; i++) {
290 txs = &sc->sc_txsoft[i];
291 txs->txs_mbuf = NULL;
293 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
294 &txs->txs_dmamap)) != 0) {
295 device_printf(sc->sc_dev,
296 "unable to create TX DMA map %d, error = %d\n",
300 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
304 * Allocate the receive buffers, create and load the DMA maps
307 for (i = 0; i < CAS_NRXDESC; i++) {
308 if ((error = bus_dmamem_alloc(sc->sc_rdmatag,
309 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK,
310 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) {
311 device_printf(sc->sc_dev,
312 "unable to allocate RX buffer %d, error = %d\n",
318 sc->sc_rxdsoft[i].rxds_paddr = 0;
319 if ((error = bus_dmamap_load(sc->sc_rdmatag,
320 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf,
321 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 ||
322 sc->sc_rxdsoft[i].rxds_paddr == 0) {
323 device_printf(sc->sc_dev,
324 "unable to load RX DMA map %d, error = %d\n",
330 if ((sc->sc_flags & CAS_SERDES) == 0) {
331 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
332 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4,
333 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
336 * Look for an external PHY.
339 v = CAS_READ_4(sc, CAS_MIF_CONF);
340 if ((v & CAS_MIF_CONF_MDI1) != 0) {
341 v |= CAS_MIF_CONF_PHY_SELECT;
342 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
343 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
344 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
345 /* Enable/unfreeze the GMII pins of Saturn. */
346 if (sc->sc_variant == CAS_SATURN) {
347 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
348 CAS_READ_4(sc, CAS_SATURN_PCFG) &
349 ~CAS_SATURN_PCFG_FSI);
350 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
351 BUS_SPACE_BARRIER_READ |
352 BUS_SPACE_BARRIER_WRITE);
355 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
356 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
357 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
360 * Fall back on an internal PHY if no external PHY was found.
362 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) {
363 v &= ~CAS_MIF_CONF_PHY_SELECT;
364 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
365 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
366 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
367 /* Freeze the GMII pins of Saturn for saving power. */
368 if (sc->sc_variant == CAS_SATURN) {
369 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
370 CAS_READ_4(sc, CAS_SATURN_PCFG) |
371 CAS_SATURN_PCFG_FSI);
372 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
373 BUS_SPACE_BARRIER_READ |
374 BUS_SPACE_BARRIER_WRITE);
377 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
378 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
379 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
383 * Use the external PCS SERDES.
385 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
386 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE);
387 /* Enable/unfreeze the SERDES pins of Saturn. */
388 if (sc->sc_variant == CAS_SATURN) {
389 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
390 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
391 BUS_SPACE_BARRIER_WRITE);
393 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
394 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4,
395 BUS_SPACE_BARRIER_WRITE);
396 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
397 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
398 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
399 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
400 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
401 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
404 device_printf(sc->sc_dev, "attaching PHYs failed\n");
407 sc->sc_mii = device_get_softc(sc->sc_miibus);
410 * From this point forward, the attachment cannot fail. A failure
411 * before this point releases all resources that may have been
415 /* Announce FIFO sizes. */
416 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE);
417 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
418 CAS_RX_FIFO_SIZE / 1024, v / 16);
420 /* Attach the interface. */
421 ether_ifattach(ifp, sc->sc_enaddr);
424 * Tell the upper layer(s) we support long frames/checksum offloads.
426 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
427 ifp->if_capabilities = IFCAP_VLAN_MTU;
428 if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
429 ifp->if_capabilities |= IFCAP_HWCSUM;
430 ifp->if_hwassist = CAS_CSUM_FEATURES;
432 ifp->if_capenable = ifp->if_capabilities;
437 * Free any resources we've allocated during the failed attach
438 * attempt. Do this in reverse order and fall through.
441 for (i = 0; i < CAS_NRXDESC; i++)
442 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
443 bus_dmamap_unload(sc->sc_rdmatag,
444 sc->sc_rxdsoft[i].rxds_dmamap);
446 for (i = 0; i < CAS_NRXDESC; i++)
447 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
448 bus_dmamem_free(sc->sc_rdmatag,
449 sc->sc_rxdsoft[i].rxds_buf,
450 sc->sc_rxdsoft[i].rxds_dmamap);
452 for (i = 0; i < CAS_TXQUEUELEN; i++)
453 if (sc->sc_txsoft[i].txs_dmamap != NULL)
454 bus_dmamap_destroy(sc->sc_tdmatag,
455 sc->sc_txsoft[i].txs_dmamap);
456 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
458 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
461 bus_dma_tag_destroy(sc->sc_cdmatag);
463 bus_dma_tag_destroy(sc->sc_tdmatag);
465 bus_dma_tag_destroy(sc->sc_rdmatag);
467 bus_dma_tag_destroy(sc->sc_pdmatag);
469 taskqueue_free(sc->sc_tq);
476 cas_detach(struct cas_softc *sc)
478 struct ifnet *ifp = sc->sc_ifp;
485 callout_drain(&sc->sc_tick_ch);
486 callout_drain(&sc->sc_rx_ch);
487 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task);
488 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task);
490 taskqueue_free(sc->sc_tq);
491 device_delete_child(sc->sc_dev, sc->sc_miibus);
493 for (i = 0; i < CAS_NRXDESC; i++)
494 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL)
495 bus_dmamap_sync(sc->sc_rdmatag,
496 sc->sc_rxdsoft[i].rxds_dmamap,
497 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
498 for (i = 0; i < CAS_NRXDESC; i++)
499 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
500 bus_dmamap_unload(sc->sc_rdmatag,
501 sc->sc_rxdsoft[i].rxds_dmamap);
502 for (i = 0; i < CAS_NRXDESC; i++)
503 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
504 bus_dmamem_free(sc->sc_rdmatag,
505 sc->sc_rxdsoft[i].rxds_buf,
506 sc->sc_rxdsoft[i].rxds_dmamap);
507 for (i = 0; i < CAS_TXQUEUELEN; i++)
508 if (sc->sc_txsoft[i].txs_dmamap != NULL)
509 bus_dmamap_destroy(sc->sc_tdmatag,
510 sc->sc_txsoft[i].txs_dmamap);
511 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
512 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
513 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
515 bus_dma_tag_destroy(sc->sc_cdmatag);
516 bus_dma_tag_destroy(sc->sc_tdmatag);
517 bus_dma_tag_destroy(sc->sc_rdmatag);
518 bus_dma_tag_destroy(sc->sc_pdmatag);
522 cas_suspend(struct cas_softc *sc)
524 struct ifnet *ifp = sc->sc_ifp;
532 cas_resume(struct cas_softc *sc)
534 struct ifnet *ifp = sc->sc_ifp;
538 * On resume all registers have to be initialized again like
541 sc->sc_flags &= ~CAS_INITED;
542 if (ifp->if_flags & IFF_UP)
548 cas_rxcksum(struct mbuf *m, uint16_t cksum)
550 struct ether_header *eh;
554 int32_t hlen, len, pktlen;
557 pktlen = m->m_pkthdr.len;
558 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
560 eh = mtod(m, struct ether_header *);
561 if (eh->ether_type != htons(ETHERTYPE_IP))
563 ip = (struct ip *)(eh + 1);
564 if (ip->ip_v != IPVERSION)
567 hlen = ip->ip_hl << 2;
568 pktlen -= sizeof(struct ether_header);
569 if (hlen < sizeof(struct ip))
571 if (ntohs(ip->ip_len) < hlen)
573 if (ntohs(ip->ip_len) != pktlen)
575 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
576 return; /* Cannot handle fragmented packet. */
580 if (pktlen < (hlen + sizeof(struct tcphdr)))
584 if (pktlen < (hlen + sizeof(struct udphdr)))
586 uh = (struct udphdr *)((uint8_t *)ip + hlen);
588 return; /* no checksum */
595 /* checksum fixup for IP options */
596 len = hlen - sizeof(struct ip);
598 opts = (uint16_t *)(ip + 1);
599 for (; len > 0; len -= sizeof(uint16_t), opts++) {
600 temp32 = cksum - *opts;
601 temp32 = (temp32 >> 16) + (temp32 & 65535);
602 cksum = temp32 & 65535;
605 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
606 m->m_pkthdr.csum_data = cksum;
610 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
612 struct cas_softc *sc = xsc;
617 panic("%s: bad control buffer segment count", __func__);
618 sc->sc_cddma = segs[0].ds_addr;
622 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
624 struct cas_softc *sc = xsc;
629 panic("%s: bad RX buffer segment count", __func__);
630 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr;
636 struct cas_softc *sc = arg;
637 struct ifnet *ifp = sc->sc_ifp;
640 CAS_LOCK_ASSERT(sc, MA_OWNED);
643 * Unload collision and error counters.
645 ifp->if_collisions +=
646 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) +
647 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT);
648 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) +
649 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT);
650 ifp->if_collisions += v;
651 ifp->if_oerrors += v;
653 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) +
654 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) +
655 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) +
656 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL);
659 * Then clear the hardware counters.
661 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
662 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
663 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
664 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
665 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
666 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
667 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
668 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
670 mii_tick(sc->sc_mii);
672 if (sc->sc_txfree != CAS_MAXTXFREE)
677 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
681 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
686 for (i = CAS_TRIES; i--; DELAY(100)) {
687 reg = CAS_READ_4(sc, r);
688 if ((reg & clr) == 0 && (reg & set) == set)
695 cas_reset(struct cas_softc *sc)
699 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
701 /* Disable all interrupts in order to avoid spurious ones. */
702 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
708 * Do a full reset modulo the result of the last auto-negotiation
709 * when using the SERDES.
711 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
712 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
713 CAS_BARRIER(sc, CAS_RESET, 4,
714 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
716 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
717 device_printf(sc->sc_dev, "cannot reset device\n");
721 cas_stop(struct ifnet *ifp)
723 struct cas_softc *sc = ifp->if_softc;
724 struct cas_txsoft *txs;
727 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
730 callout_stop(&sc->sc_tick_ch);
731 callout_stop(&sc->sc_rx_ch);
733 /* Disable all interrupts in order to avoid spurious ones. */
734 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
740 * Release any queued transmit buffers.
742 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
743 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
744 if (txs->txs_ndescs != 0) {
745 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
746 BUS_DMASYNC_POSTWRITE);
747 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
748 if (txs->txs_mbuf != NULL) {
749 m_freem(txs->txs_mbuf);
750 txs->txs_mbuf = NULL;
753 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
757 * Mark the interface down and cancel the watchdog timer.
759 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
760 sc->sc_flags &= ~CAS_LINK;
761 sc->sc_wdog_timer = 0;
765 cas_reset_rx(struct cas_softc *sc)
769 * Resetting while DMA is in progress can cause a bus hang, so we
772 (void)cas_disable_rx(sc);
773 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
774 CAS_BARRIER(sc, CAS_RX_CONF, 4,
775 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
776 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0))
777 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
779 /* Finally, reset the ERX. */
780 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
781 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
782 CAS_BARRIER(sc, CAS_RESET, 4,
783 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
784 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) {
785 device_printf(sc->sc_dev, "cannot reset receiver\n");
792 cas_reset_tx(struct cas_softc *sc)
796 * Resetting while DMA is in progress can cause a bus hang, so we
799 (void)cas_disable_tx(sc);
800 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
801 CAS_BARRIER(sc, CAS_TX_CONF, 4,
802 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
803 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0))
804 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
806 /* Finally, reset the ETX. */
807 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
808 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
809 CAS_BARRIER(sc, CAS_RESET, 4,
810 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
811 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) {
812 device_printf(sc->sc_dev, "cannot reset transmitter\n");
819 cas_disable_rx(struct cas_softc *sc)
822 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
823 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN);
824 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
825 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
826 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
829 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
834 cas_disable_tx(struct cas_softc *sc)
837 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
838 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN);
839 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
840 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
841 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
844 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
849 cas_rxcompinit(struct cas_rx_comp *rxcomp)
852 rxcomp->crc_word1 = 0;
853 rxcomp->crc_word2 = 0;
855 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO));
856 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO);
860 cas_meminit(struct cas_softc *sc)
864 CAS_LOCK_ASSERT(sc, MA_OWNED);
867 * Initialize the transmit descriptor ring.
869 for (i = 0; i < CAS_NTXDESC; i++) {
870 sc->sc_txdescs[i].cd_flags = 0;
871 sc->sc_txdescs[i].cd_buf_ptr = 0;
873 sc->sc_txfree = CAS_MAXTXFREE;
878 * Initialize the receive completion ring.
880 for (i = 0; i < CAS_NRXCOMP; i++)
881 cas_rxcompinit(&sc->sc_rxcomps[i]);
885 * Initialize the first receive descriptor ring. We leave
886 * the second one zeroed as we don't actually use it.
888 for (i = 0; i < CAS_NRXDESC; i++)
889 CAS_INIT_RXDESC(sc, i, i);
892 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
896 cas_descsize(u_int sz)
901 return (CAS_DESC_32);
903 return (CAS_DESC_64);
905 return (CAS_DESC_128);
907 return (CAS_DESC_256);
909 return (CAS_DESC_512);
911 return (CAS_DESC_1K);
913 return (CAS_DESC_2K);
915 return (CAS_DESC_4K);
917 return (CAS_DESC_8K);
919 printf("%s: invalid descriptor ring size %d\n", __func__, sz);
920 return (CAS_DESC_32);
925 cas_rxcompsize(u_int sz)
930 return (CAS_RX_CONF_COMP_128);
932 return (CAS_RX_CONF_COMP_256);
934 return (CAS_RX_CONF_COMP_512);
936 return (CAS_RX_CONF_COMP_1K);
938 return (CAS_RX_CONF_COMP_2K);
940 return (CAS_RX_CONF_COMP_4K);
942 return (CAS_RX_CONF_COMP_8K);
944 return (CAS_RX_CONF_COMP_16K);
946 return (CAS_RX_CONF_COMP_32K);
948 printf("%s: invalid dcompletion ring size %d\n", __func__, sz);
949 return (CAS_RX_CONF_COMP_128);
956 struct cas_softc *sc = xsc;
964 * Initialization of interface; set up initialization block
965 * and transmit/receive descriptor rings.
968 cas_init_locked(struct cas_softc *sc)
970 struct ifnet *ifp = sc->sc_ifp;
973 CAS_LOCK_ASSERT(sc, MA_OWNED);
975 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
979 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev),
983 * Initialization sequence. The numbered steps below correspond
984 * to the sequence outlined in section 6.3.5.1 in the Ethernet
985 * Channel Engine manual (part of the PCIO manual).
986 * See also the STP2002-STQ document from Sun Microsystems.
989 /* step 1 & 2. Reset the Ethernet Channel. */
993 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev),
997 if ((sc->sc_flags & CAS_SERDES) == 0)
998 /* Re-initialize the MIF. */
1001 /* step 3. Setup data structures in host memory. */
1004 /* step 4. TX MAC registers & counters */
1007 /* step 5. RX MAC registers & counters */
1009 /* step 6 & 7. Program Ring Base Addresses. */
1010 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
1011 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32));
1012 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1013 CAS_CDTXDADDR(sc, 0) & 0xffffffff);
1015 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1016 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
1017 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1018 CAS_CDRXCADDR(sc, 0) & 0xffffffff);
1020 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1021 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32));
1022 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1023 CAS_CDRXDADDR(sc, 0) & 0xffffffff);
1025 if ((sc->sc_flags & CAS_REG_PLUS) != 0) {
1026 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1027 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32));
1028 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1029 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff);
1034 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx",
1035 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0),
1036 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma);
1039 /* step 8. Global Configuration & Interrupt Masks */
1041 /* Disable weighted round robin. */
1042 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1045 * Enable infinite bursts for revisions without PCI issues if
1046 * applicable. Doing so greatly improves the TX performance on
1047 * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX
1048 * performance only marginally but hurts RX throughput quite a bit).
1050 CAS_WRITE_4(sc, CAS_INF_BURST,
1051 #if !defined(__sparc64__)
1052 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN :
1056 /* Set up interrupts. */
1057 CAS_WRITE_4(sc, CAS_INTMASK,
1058 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
1059 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
1060 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
1061 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
1062 CAS_INTR_PCI_ERROR_INT
1064 | CAS_INTR_PCS_INT | CAS_INTR_MIF
1067 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */
1068 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1069 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1070 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1071 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR));
1073 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1074 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1075 CAS_MAC_CTRL_NON_PAUSE));
1077 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1078 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1079 CAS_MAC_CTRL_NON_PAUSE);
1082 /* Enable PCI error interrupts. */
1083 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1084 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO |
1085 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO));
1087 /* Enable PCI error interrupts in BIM configuration. */
1088 CAS_WRITE_4(sc, CAS_BIM_CONF,
1089 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN);
1092 * step 9. ETX Configuration: encode receive descriptor ring size,
1093 * enable DMA and disable pre-interrupt writeback completion.
1095 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT;
1096 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1097 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS);
1099 /* step 10. ERX Configuration */
1102 * Encode receive completion and descriptor ring sizes, set the
1105 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT;
1106 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT;
1107 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1108 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT;
1109 CAS_WRITE_4(sc, CAS_RX_CONF,
1110 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT));
1112 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */
1113 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1114 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT));
1117 CAS_WRITE_4(sc, CAS_RX_BLANK,
1118 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT));
1120 /* Set RX_COMP_AFULL threshold to half of the RX completions. */
1121 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1122 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT);
1124 /* Initialize the RX page size register as appropriate for 8k. */
1125 CAS_WRITE_4(sc, CAS_RX_PSZ,
1126 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) |
1127 (4 << CAS_RX_PSZ_MB_CNT_SHFT) |
1128 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) |
1129 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT));
1131 /* Disable RX random early detection. */
1132 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1134 /* Zero the RX reassembly DMA table. */
1135 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) {
1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1138 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1139 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1142 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */
1143 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1144 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1146 /* Finally, enable RX DMA. */
1147 CAS_WRITE_4(sc, CAS_RX_CONF,
1148 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN);
1150 /* step 11. Configure Media. */
1152 /* step 12. RX_MAC Configuration Register */
1153 v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
1154 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN);
1155 v |= CAS_MAC_RX_CONF_STRPFCS;
1156 sc->sc_mac_rxcfg = v;
1158 * Clear the RX filter and reprogram it. This will also set the
1159 * current RX MAC configuration and enable it.
1163 /* step 13. TX_MAC Configuration Register */
1164 v = CAS_READ_4(sc, CAS_MAC_TX_CONF);
1165 v |= CAS_MAC_TX_CONF_EN;
1166 (void)cas_disable_tx(sc);
1167 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1169 /* step 14. Issue Transmit Pending command. */
1171 /* step 15. Give the receiver a swift kick. */
1172 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1173 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1174 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1175 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1177 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1178 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1180 mii_mediachg(sc->sc_mii);
1182 /* Start the one second timer. */
1183 sc->sc_wdog_timer = 0;
1184 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
1188 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head)
1190 bus_dma_segment_t txsegs[CAS_NTXSEGS];
1191 struct cas_txsoft *txs;
1195 int error, nexttx, nsegs, offset, seg;
1197 CAS_LOCK_ASSERT(sc, MA_OWNED);
1199 /* Get a work queue entry. */
1200 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1201 /* Ran out of descriptors. */
1206 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) {
1207 if (M_WRITABLE(*m_head) == 0) {
1208 m = m_dup(*m_head, M_NOWAIT);
1214 offset = sizeof(struct ether_header);
1215 m = m_pullup(*m_head, offset + sizeof(struct ip));
1220 ip = (struct ip *)(mtod(m, caddr_t) + offset);
1221 offset += (ip->ip_hl << 2);
1222 cflags = (offset << CAS_TD_CKSUM_START_SHFT) |
1223 ((offset + m->m_pkthdr.csum_data) <<
1224 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN;
1228 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
1229 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1230 if (error == EFBIG) {
1231 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS);
1238 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag,
1239 txs->txs_dmamap, *m_head, txsegs, &nsegs,
1246 } else if (error != 0)
1248 /* If nsegs is wrong then the stack is corrupt. */
1249 KASSERT(nsegs <= CAS_NTXSEGS,
1250 ("%s: too many DMA segments (%d)", __func__, nsegs));
1258 * Ensure we have enough descriptors free to describe
1259 * the packet. Note, we always reserve one descriptor
1260 * at the end of the ring as a termination point, in
1261 * order to prevent wrap-around.
1263 if (nsegs > sc->sc_txfree - 1) {
1264 txs->txs_ndescs = 0;
1265 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1269 txs->txs_ndescs = nsegs;
1270 txs->txs_firstdesc = sc->sc_txnext;
1271 nexttx = txs->txs_firstdesc;
1272 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) {
1275 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1276 __func__, seg, nexttx, txsegs[seg].ds_len,
1277 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr));
1279 sc->sc_txdescs[nexttx].cd_buf_ptr =
1280 htole64(txsegs[seg].ds_addr);
1281 KASSERT(txsegs[seg].ds_len <
1282 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT,
1283 ("%s: segment size too large!", __func__));
1284 sc->sc_txdescs[nexttx].cd_flags =
1285 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT);
1286 txs->txs_lastdesc = nexttx;
1289 /* Set EOF on the last descriptor. */
1291 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d",
1292 __func__, seg, nexttx);
1294 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |=
1295 htole64(CAS_TD_END_OF_FRAME);
1297 /* Lastly set SOF on the first descriptor. */
1299 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d",
1300 __func__, seg, nexttx);
1302 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) {
1304 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1305 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME);
1307 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1308 htole64(cflags | CAS_TD_START_OF_FRAME);
1310 /* Sync the DMA map. */
1311 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1312 BUS_DMASYNC_PREWRITE);
1315 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1316 __func__, txs->txs_firstdesc, txs->txs_lastdesc,
1319 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1320 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1321 txs->txs_mbuf = *m_head;
1323 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc);
1324 sc->sc_txfree -= txs->txs_ndescs;
1330 cas_init_regs(struct cas_softc *sc)
1333 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1335 CAS_LOCK_ASSERT(sc, MA_OWNED);
1337 /* These registers are not cleared on reset. */
1338 if ((sc->sc_flags & CAS_INITED) == 0) {
1340 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1341 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1342 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1344 /* min frame length */
1345 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1346 /* max frame length and max burst size */
1347 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1348 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) <<
1349 CAS_MAC_MAX_BF_FRM_SHFT) |
1350 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT));
1352 /* more magic values */
1353 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1354 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1355 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1356 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1358 /* random number seed */
1359 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1360 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1362 /* secondary MAC addresses: 0:0:0:0:0:0 */
1363 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41;
1364 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3)
1365 CAS_WRITE_4(sc, i, 0);
1367 /* MAC control address: 01:80:c2:00:00:01 */
1368 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1369 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1370 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1372 /* MAC filter address: 0:0:0:0:0:0 */
1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1376 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1377 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1379 /* Zero the hash table. */
1380 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15;
1381 i += CAS_MAC_HASH1 - CAS_MAC_HASH0)
1382 CAS_WRITE_4(sc, i, 0);
1384 sc->sc_flags |= CAS_INITED;
1387 /* Counters need to be zeroed. */
1388 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1389 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1390 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1391 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1392 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1393 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1394 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1395 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1396 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1397 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1398 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1400 /* Set XOFF PAUSE time. */
1401 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1403 /* Set the station address. */
1404 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1405 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1406 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1408 /* Enable MII outputs. */
1409 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1413 cas_tx_task(void *arg, int pending __unused)
1417 ifp = (struct ifnet *)arg;
1422 cas_txkick(struct cas_softc *sc)
1426 * Update the TX kick register. This register has to point to the
1427 * descriptor after the last valid one and for optimum performance
1428 * should be incremented in multiples of 4 (the DMA engine fetches/
1429 * updates descriptors in batches of 4).
1432 CTR3(KTR_CAS, "%s: %s: kicking TX %d",
1433 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1435 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1436 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1440 cas_start(struct ifnet *ifp)
1442 struct cas_softc *sc = ifp->if_softc;
1448 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1449 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) {
1454 if (sc->sc_txfree < CAS_MAXTXFREE / 4)
1458 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d",
1459 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1464 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1465 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1468 if (cas_load_txmbuf(sc, &m) != 0) {
1471 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1472 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1475 if ((sc->sc_txnext % 4) == 0) {
1488 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d",
1489 device_get_name(sc->sc_dev), sc->sc_txnext);
1492 /* Set a watchdog timer in case the chip flakes out. */
1493 sc->sc_wdog_timer = 5;
1495 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1496 device_get_name(sc->sc_dev), __func__,
1505 cas_tint(struct cas_softc *sc)
1507 struct ifnet *ifp = sc->sc_ifp;
1508 struct cas_txsoft *txs;
1514 CAS_LOCK_ASSERT(sc, MA_OWNED);
1516 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1520 * Go through our TX list and free mbufs for those
1521 * frames that have been transmitted.
1524 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1525 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1527 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1528 printf(" txsoft %p transmit chain:\n", txs);
1529 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) {
1530 printf("descriptor %d: ", i);
1531 printf("cd_flags: 0x%016llx\t",
1533 sc->sc_txdescs[i].cd_flags));
1534 printf("cd_buf_ptr: 0x%016llx\n",
1536 sc->sc_txdescs[i].cd_buf_ptr));
1537 if (i == txs->txs_lastdesc)
1544 * In theory, we could harvest some descriptors before
1545 * the ring is empty, but that's a bit complicated.
1547 * CAS_TX_COMPn points to the last descriptor
1550 txlast = CAS_READ_4(sc, CAS_TX_COMP3);
1552 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, "
1553 "txs->txs_lastdesc = %d, txlast = %d",
1554 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1556 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1557 if ((txlast >= txs->txs_firstdesc) &&
1558 (txlast <= txs->txs_lastdesc))
1561 /* Ick -- this command wraps. */
1562 if ((txlast >= txs->txs_firstdesc) ||
1563 (txlast <= txs->txs_lastdesc))
1568 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__);
1570 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1572 sc->sc_txfree += txs->txs_ndescs;
1574 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1575 BUS_DMASYNC_POSTWRITE);
1576 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1577 if (txs->txs_mbuf != NULL) {
1578 m_freem(txs->txs_mbuf);
1579 txs->txs_mbuf = NULL;
1582 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1589 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx "
1591 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2),
1592 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) |
1593 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO),
1594 CAS_READ_4(sc, CAS_TX_COMP3));
1598 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */
1599 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1600 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1601 sc->sc_wdog_timer = 0;
1605 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1606 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1611 cas_rint_timeout(void *arg)
1613 struct cas_softc *sc = arg;
1615 CAS_LOCK_ASSERT(sc, MA_OWNED);
1621 cas_rint(struct cas_softc *sc)
1623 struct cas_rxdsoft *rxds, *rxds2;
1624 struct ifnet *ifp = sc->sc_ifp;
1625 struct mbuf *m, *m2;
1626 uint64_t word1, word2, word3, word4;
1628 u_int idx, idx2, len, off, skip;
1630 CAS_LOCK_ASSERT(sc, MA_OWNED);
1632 callout_stop(&sc->sc_rx_ch);
1635 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1638 #define PRINTWORD(n, delimiter) \
1639 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter)
1641 #define SKIPASSERT(n) \
1642 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \
1643 ("%s: word ## n not 0", __func__))
1645 #define WORDTOH(n) \
1646 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n)
1649 * Read the completion head register once. This limits
1650 * how long the following loop can execute.
1652 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD);
1654 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1655 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead);
1658 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1659 for (; sc->sc_rxcptr != rxhead;
1660 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) {
1676 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1677 printf(" completion %d: ", sc->sc_rxcptr);
1685 if (__predict_false(
1686 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW ||
1687 (word4 & CAS_RC4_ZERO) != 0)) {
1689 * The descriptor is still marked as owned, although
1690 * it is supposed to have completed. This has been
1691 * observed on some machines. Just exiting here
1692 * might leave the packet sitting around until another
1693 * one arrives to trigger a new interrupt, which is
1694 * generally undesirable, so set up a timeout.
1696 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS,
1697 cas_rint_timeout, sc);
1701 if (__predict_false(
1702 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) {
1704 device_printf(sc->sc_dev,
1705 "receive error: CRC error\n");
1709 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1710 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1711 ("%s: data and header present", __func__));
1712 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 ||
1713 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1714 ("%s: split and header present", __func__));
1715 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1716 (word1 & CAS_RC1_RELEASE_HDR) == 0,
1717 ("%s: data present but header release", __func__));
1718 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 ||
1719 (word1 & CAS_RC1_RELEASE_DATA) == 0,
1720 ("%s: header present but data release", __func__));
1722 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) {
1723 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX);
1724 off = CAS_GET(word2, CAS_RC2_HDR_OFF);
1726 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d",
1727 __func__, idx, off, len);
1729 rxds = &sc->sc_rxdsoft[idx];
1730 MGETHDR(m, M_NOWAIT, MT_DATA);
1732 refcount_acquire(&rxds->rxds_refcount);
1733 bus_dmamap_sync(sc->sc_rdmatag,
1734 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1735 #if __FreeBSD_version < 800016
1736 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1737 off * 256 + ETHER_ALIGN, len, cas_free,
1738 rxds, M_RDONLY, EXT_NET_DRV);
1740 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1741 off * 256 + ETHER_ALIGN, len, cas_free,
1742 sc, (void *)(uintptr_t)idx,
1743 M_RDONLY, EXT_NET_DRV);
1745 if ((m->m_flags & M_EXT) == 0) {
1751 m->m_pkthdr.rcvif = ifp;
1752 m->m_pkthdr.len = m->m_len = len;
1754 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1755 cas_rxcksum(m, CAS_GET(word4,
1759 (*ifp->if_input)(ifp, m);
1764 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 &&
1765 refcount_release(&rxds->rxds_refcount) != 0)
1766 cas_add_rxdesc(sc, idx);
1767 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) {
1768 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX);
1769 off = CAS_GET(word1, CAS_RC1_DATA_OFF);
1771 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d",
1772 __func__, idx, off, len);
1774 rxds = &sc->sc_rxdsoft[idx];
1775 MGETHDR(m, M_NOWAIT, MT_DATA);
1777 refcount_acquire(&rxds->rxds_refcount);
1779 m->m_len = min(CAS_PAGE_SIZE - off, len);
1780 bus_dmamap_sync(sc->sc_rdmatag,
1781 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1782 #if __FreeBSD_version < 800016
1783 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1784 m->m_len, cas_free, rxds, M_RDONLY,
1787 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1788 m->m_len, cas_free, sc,
1789 (void *)(uintptr_t)idx, M_RDONLY,
1792 if ((m->m_flags & M_EXT) == 0) {
1800 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) {
1801 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0,
1802 ("%s: split but no release next",
1805 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX);
1807 CTR2(KTR_CAS, "%s: split at idx %d",
1810 rxds2 = &sc->sc_rxdsoft[idx2];
1812 MGET(m2, M_NOWAIT, MT_DATA);
1815 &rxds2->rxds_refcount);
1816 m2->m_len = len - m->m_len;
1820 BUS_DMASYNC_POSTREAD);
1821 #if __FreeBSD_version < 800016
1823 (caddr_t)rxds2->rxds_buf,
1824 m2->m_len, cas_free,
1829 (caddr_t)rxds2->rxds_buf,
1830 m2->m_len, cas_free, sc,
1831 (void *)(uintptr_t)idx2,
1832 M_RDONLY, EXT_NET_DRV);
1834 if ((m2->m_flags & M_EXT) ==
1843 else if (m != NULL) {
1849 m->m_pkthdr.rcvif = ifp;
1850 m->m_pkthdr.len = len;
1852 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1853 cas_rxcksum(m, CAS_GET(word4,
1857 (*ifp->if_input)(ifp, m);
1862 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 &&
1863 refcount_release(&rxds->rxds_refcount) != 0)
1864 cas_add_rxdesc(sc, idx);
1865 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 &&
1866 refcount_release(&rxds2->rxds_refcount) != 0)
1867 cas_add_rxdesc(sc, idx2);
1870 skip = CAS_GET(word1, CAS_RC1_SKIP);
1873 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]);
1874 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1877 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1878 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1885 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1886 __func__, sc->sc_rxcptr, sc->sc_rxdptr,
1887 CAS_READ_4(sc, CAS_RX_COMP_HEAD));
1892 cas_free(struct mbuf *m, void *arg1, void *arg2)
1894 struct cas_rxdsoft *rxds;
1895 struct cas_softc *sc;
1898 #if __FreeBSD_version < 800016
1901 idx = rxds->rxds_idx;
1904 idx = (uintptr_t)arg2;
1905 rxds = &sc->sc_rxdsoft[idx];
1907 if (refcount_release(&rxds->rxds_refcount) == 0)
1908 return (EXT_FREE_OK);
1911 * NB: this function can be called via m_freem(9) within
1914 if ((locked = CAS_LOCK_OWNED(sc)) == 0)
1916 cas_add_rxdesc(sc, idx);
1919 return (EXT_FREE_OK);
1923 cas_add_rxdesc(struct cas_softc *sc, u_int idx)
1926 CAS_LOCK_ASSERT(sc, MA_OWNED);
1928 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap,
1929 BUS_DMASYNC_PREREAD);
1930 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx);
1931 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr);
1934 * Update the RX kick register. This register has to point to the
1935 * descriptor after the last valid one (before the current batch)
1936 * and for optimum performance should be incremented in multiples
1937 * of 4 (the DMA engine fetches/updates descriptors in batches of 4).
1939 if ((sc->sc_rxdptr % 4) == 0) {
1940 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1941 CAS_WRITE_4(sc, CAS_RX_KICK,
1942 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK);
1947 cas_eint(struct cas_softc *sc, u_int status)
1949 struct ifnet *ifp = sc->sc_ifp;
1951 CAS_LOCK_ASSERT(sc, MA_OWNED);
1955 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1956 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) {
1957 status = CAS_READ_4(sc, CAS_ERROR_STATUS);
1958 printf(", PCI bus error 0x%x", status);
1959 if ((status & CAS_ERROR_OTHER) != 0) {
1960 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
1961 printf(", PCI status 0x%x", status);
1962 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
1967 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1968 cas_init_locked(sc);
1969 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1970 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
1976 struct cas_softc *sc = v;
1978 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) &
1979 CAS_INTR_SUMMARY) == 0))
1980 return (FILTER_STRAY);
1982 /* Disable interrupts. */
1983 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
1984 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1986 return (FILTER_HANDLED);
1990 cas_intr_task(void *arg, int pending __unused)
1992 struct cas_softc *sc = arg;
1993 struct ifnet *ifp = sc->sc_ifp;
1994 uint32_t status, status2;
1996 CAS_LOCK_ASSERT(sc, MA_NOTOWNED);
1998 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
2001 status = CAS_READ_4(sc, CAS_STATUS);
2002 if (__predict_false((status & CAS_INTR_SUMMARY) == 0))
2007 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x",
2008 device_get_name(sc->sc_dev), __func__,
2009 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status);
2012 * PCS interrupts must be cleared, otherwise no traffic is passed!
2014 if ((status & CAS_INTR_PCS_INT) != 0) {
2016 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) |
2017 CAS_READ_4(sc, CAS_PCS_INTR_STATUS);
2018 if ((status2 & CAS_PCS_INTR_LINK) != 0)
2019 device_printf(sc->sc_dev,
2020 "%s: PCS link status changed\n", __func__);
2022 if ((status & CAS_MAC_CTRL_STATUS) != 0) {
2023 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS);
2024 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2025 device_printf(sc->sc_dev,
2026 "%s: PAUSE received (PAUSE time %d slots)\n",
2028 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >>
2029 CAS_MAC_CTRL_STATUS_PT_SHFT);
2030 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2031 device_printf(sc->sc_dev,
2032 "%s: transited to PAUSE state\n", __func__);
2033 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0)
2034 device_printf(sc->sc_dev,
2035 "%s: transited to non-PAUSE state\n", __func__);
2037 if ((status & CAS_INTR_MIF) != 0)
2038 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
2041 if (__predict_false((status &
2042 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
2043 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) {
2044 cas_eint(sc, status);
2049 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) {
2050 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS);
2052 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0)
2054 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0)
2055 device_printf(sc->sc_dev,
2056 "MAC TX fault, status %x\n", status2);
2059 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) {
2060 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS);
2061 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0)
2063 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0)
2064 device_printf(sc->sc_dev,
2065 "MAC RX fault, status %x\n", status2);
2069 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2070 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) {
2073 if (__predict_false((status &
2074 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2075 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0))
2076 device_printf(sc->sc_dev,
2077 "RX fault, status %x\n", status);
2082 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0)
2085 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2088 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2089 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2092 status = CAS_READ_4(sc, CAS_STATUS_ALIAS);
2093 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) {
2094 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
2099 /* Re-enable interrupts. */
2100 CAS_WRITE_4(sc, CAS_INTMASK,
2101 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
2102 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
2103 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
2104 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
2105 CAS_INTR_PCI_ERROR_INT
2107 | CAS_INTR_PCS_INT | CAS_INTR_MIF
2113 cas_watchdog(struct cas_softc *sc)
2115 struct ifnet *ifp = sc->sc_ifp;
2117 CAS_LOCK_ASSERT(sc, MA_OWNED);
2121 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x",
2122 __func__, CAS_READ_4(sc, CAS_RX_CONF),
2123 CAS_READ_4(sc, CAS_MAC_RX_STATUS),
2124 CAS_READ_4(sc, CAS_MAC_RX_CONF));
2126 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x",
2127 __func__, CAS_READ_4(sc, CAS_TX_CONF),
2128 CAS_READ_4(sc, CAS_MAC_TX_STATUS),
2129 CAS_READ_4(sc, CAS_MAC_TX_CONF));
2132 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
2135 if ((sc->sc_flags & CAS_LINK) != 0)
2136 device_printf(sc->sc_dev, "device timeout\n");
2137 else if (bootverbose)
2138 device_printf(sc->sc_dev, "device timeout (no link)\n");
2141 /* Try to get more packets going. */
2142 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2143 cas_init_locked(sc);
2144 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2145 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2149 cas_mifinit(struct cas_softc *sc)
2152 /* Configure the MIF in frame mode. */
2153 CAS_WRITE_4(sc, CAS_MIF_CONF,
2154 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE);
2155 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
2156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2162 * The MII interface supports at least three different operating modes:
2164 * Bitbang mode is implemented using data, clock and output enable registers.
2166 * Frame mode is implemented by loading a complete frame into the frame
2167 * register and polling the valid bit for completion.
2169 * Polling mode uses the frame register but completion is indicated by
2174 cas_mii_readreg(device_t dev, int phy, int reg)
2176 struct cas_softc *sc;
2180 #ifdef CAS_DEBUG_PHY
2181 printf("%s: phy %d reg %d\n", __func__, phy, reg);
2184 sc = device_get_softc(dev);
2185 if ((sc->sc_flags & CAS_SERDES) != 0) {
2191 reg = CAS_PCS_STATUS;
2200 reg = CAS_PCS_ANLPAR;
2203 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
2205 device_printf(sc->sc_dev,
2206 "%s: unhandled register %d\n", __func__, reg);
2209 return (CAS_READ_4(sc, reg));
2212 /* Construct the frame command. */
2213 v = CAS_MIF_FRAME_READ |
2214 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2215 (reg << CAS_MIF_FRAME_REG_SHFT);
2217 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2218 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2219 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2220 for (n = 0; n < 100; n++) {
2222 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2223 if (v & CAS_MIF_FRAME_TA_LSB)
2224 return (v & CAS_MIF_FRAME_DATA);
2227 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2232 cas_mii_writereg(device_t dev, int phy, int reg, int val)
2234 struct cas_softc *sc;
2238 #ifdef CAS_DEBUG_PHY
2239 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
2242 sc = device_get_softc(dev);
2243 if ((sc->sc_flags & CAS_SERDES) != 0) {
2246 reg = CAS_PCS_STATUS;
2250 if ((val & CAS_PCS_CTRL_RESET) == 0)
2252 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2253 CAS_BARRIER(sc, CAS_PCS_CTRL, 4,
2254 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2255 if (!cas_bitwait(sc, CAS_PCS_CTRL,
2256 CAS_PCS_CTRL_RESET, 0))
2257 device_printf(sc->sc_dev,
2258 "cannot reset PCS\n");
2261 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2262 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2263 BUS_SPACE_BARRIER_WRITE);
2264 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2265 CAS_BARRIER(sc, CAS_PCS_ANAR, 4,
2266 BUS_SPACE_BARRIER_WRITE);
2267 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2268 CAS_PCS_SERDES_CTRL_ESD);
2269 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2270 BUS_SPACE_BARRIER_WRITE);
2271 CAS_WRITE_4(sc, CAS_PCS_CONF,
2273 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2274 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2277 reg = CAS_PCS_ANLPAR;
2280 device_printf(sc->sc_dev,
2281 "%s: unhandled register %d\n", __func__, reg);
2284 CAS_WRITE_4(sc, reg, val);
2285 CAS_BARRIER(sc, reg, 4,
2286 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2290 /* Construct the frame command. */
2291 v = CAS_MIF_FRAME_WRITE |
2292 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2293 (reg << CAS_MIF_FRAME_REG_SHFT) |
2294 (val & CAS_MIF_FRAME_DATA);
2296 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2297 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2298 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2299 for (n = 0; n < 100; n++) {
2301 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2302 if (v & CAS_MIF_FRAME_TA_LSB)
2306 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2311 cas_mii_statchg(device_t dev)
2313 struct cas_softc *sc;
2316 uint32_t rxcfg, txcfg, v;
2318 sc = device_get_softc(dev);
2321 CAS_LOCK_ASSERT(sc, MA_OWNED);
2324 if ((ifp->if_flags & IFF_DEBUG) != 0)
2325 device_printf(sc->sc_dev, "%s: status changen", __func__);
2328 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2329 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2330 sc->sc_flags |= CAS_LINK;
2332 sc->sc_flags &= ~CAS_LINK;
2334 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2346 * The configuration done here corresponds to the steps F) and
2347 * G) and as far as enabling of RX and TX MAC goes also step H)
2348 * of the initialization sequence outlined in section 11.2.1 of
2349 * the Cassini+ ASIC Specification.
2352 rxcfg = sc->sc_mac_rxcfg;
2353 rxcfg &= ~CAS_MAC_RX_CONF_CARR;
2354 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU |
2355 CAS_MAC_TX_CONF_NGUL;
2356 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2357 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS;
2358 else if (gigabit != 0) {
2359 rxcfg |= CAS_MAC_RX_CONF_CARR;
2360 txcfg |= CAS_MAC_TX_CONF_CARR;
2362 (void)cas_disable_tx(sc);
2363 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2364 (void)cas_disable_rx(sc);
2365 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2367 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) &
2368 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP);
2369 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2370 IFM_ETH_RXPAUSE) != 0)
2371 v |= CAS_MAC_CTRL_CONF_RXP;
2372 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2373 IFM_ETH_TXPAUSE) != 0)
2374 v |= CAS_MAC_CTRL_CONF_TXP;
2375 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2378 * All supported chips have a bug causing incorrect checksum
2379 * to be calculated when letting them strip the FCS in half-
2380 * duplex mode. In theory we could disable FCS stripping and
2381 * manually adjust the checksum accordingly. It seems to make
2382 * more sense to optimze for the common case and just disable
2383 * hardware checksumming in half-duplex mode though.
2385 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) {
2386 ifp->if_capenable &= ~IFCAP_HWCSUM;
2387 ifp->if_hwassist = 0;
2388 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
2389 ifp->if_capenable = ifp->if_capabilities;
2390 ifp->if_hwassist = CAS_CSUM_FEATURES;
2393 if (sc->sc_variant == CAS_SATURN) {
2394 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2395 /* silicon bug workaround */
2396 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2398 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2401 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2403 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2404 CAS_MAC_SLOT_TIME_CARR);
2406 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2407 CAS_MAC_SLOT_TIME_NORM);
2409 /* XIF Configuration */
2410 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED;
2411 if ((sc->sc_flags & CAS_SERDES) == 0) {
2412 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2413 v |= CAS_MAC_XIF_CONF_NOECHO;
2414 v |= CAS_MAC_XIF_CONF_BUF_OE;
2417 v |= CAS_MAC_XIF_CONF_GMII;
2418 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2419 v |= CAS_MAC_XIF_CONF_FDXLED;
2420 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2422 sc->sc_mac_rxcfg = rxcfg;
2423 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2424 (sc->sc_flags & CAS_LINK) != 0) {
2425 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2426 txcfg | CAS_MAC_TX_CONF_EN);
2427 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2428 rxcfg | CAS_MAC_RX_CONF_EN);
2433 cas_mediachange(struct ifnet *ifp)
2435 struct cas_softc *sc = ifp->if_softc;
2438 /* XXX add support for serial media. */
2441 error = mii_mediachg(sc->sc_mii);
2447 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2449 struct cas_softc *sc = ifp->if_softc;
2452 if ((ifp->if_flags & IFF_UP) == 0) {
2457 mii_pollstat(sc->sc_mii);
2458 ifmr->ifm_active = sc->sc_mii->mii_media_active;
2459 ifmr->ifm_status = sc->sc_mii->mii_media_status;
2464 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2466 struct cas_softc *sc = ifp->if_softc;
2467 struct ifreq *ifr = (struct ifreq *)data;
2474 if ((ifp->if_flags & IFF_UP) != 0) {
2475 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2476 ((ifp->if_flags ^ sc->sc_ifflags) &
2477 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2480 cas_init_locked(sc);
2481 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2483 sc->sc_ifflags = ifp->if_flags;
2488 if ((sc->sc_flags & CAS_NO_CSUM) != 0) {
2493 ifp->if_capenable = ifr->ifr_reqcap;
2494 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2495 ifp->if_hwassist = CAS_CSUM_FEATURES;
2497 ifp->if_hwassist = 0;
2503 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2508 if ((ifr->ifr_mtu < ETHERMIN) ||
2509 (ifr->ifr_mtu > ETHERMTU_JUMBO))
2512 ifp->if_mtu = ifr->ifr_mtu;
2516 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
2519 error = ether_ioctl(ifp, cmd, data);
2527 cas_setladrf(struct cas_softc *sc)
2529 struct ifnet *ifp = sc->sc_ifp;
2530 struct ifmultiaddr *inm;
2535 CAS_LOCK_ASSERT(sc, MA_OWNED);
2538 * Turn off the RX MAC and the hash filter as required by the Sun
2539 * Cassini programming restrictions.
2541 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER |
2542 CAS_MAC_RX_CONF_EN);
2543 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2544 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
2545 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2546 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER |
2547 CAS_MAC_RX_CONF_EN, 0))
2548 device_printf(sc->sc_dev,
2549 "cannot disable RX MAC or hash filter\n");
2551 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP);
2552 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2553 v |= CAS_MAC_RX_CONF_PROMISC;
2556 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2557 v |= CAS_MAC_RX_CONF_PGRP;
2562 * Set up multicast address filter by passing all multicast
2563 * addresses through a crc generator, and then using the high
2564 * order 8 bits as an index into the 256 bit logical address
2565 * filter. The high order 4 bits selects the word, while the
2566 * other 4 bits select the bit within the word (where bit 0
2570 /* Clear the hash table. */
2571 memset(hash, 0, sizeof(hash));
2573 if_maddr_rlock(ifp);
2574 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
2575 if (inm->ifma_addr->sa_family != AF_LINK)
2577 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2578 inm->ifma_addr), ETHER_ADDR_LEN);
2580 /* We just want the 8 most significant bits. */
2583 /* Set the corresponding bit in the filter. */
2584 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2586 if_maddr_runlock(ifp);
2588 v |= CAS_MAC_RX_CONF_HFILTER;
2590 /* Now load the hash table into the chip (if we are using it). */
2591 for (i = 0; i < 16; i++)
2593 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
2597 sc->sc_mac_rxcfg = v;
2598 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2601 static int cas_pci_attach(device_t dev);
2602 static int cas_pci_detach(device_t dev);
2603 static int cas_pci_probe(device_t dev);
2604 static int cas_pci_resume(device_t dev);
2605 static int cas_pci_suspend(device_t dev);
2607 static device_method_t cas_pci_methods[] = {
2608 /* Device interface */
2609 DEVMETHOD(device_probe, cas_pci_probe),
2610 DEVMETHOD(device_attach, cas_pci_attach),
2611 DEVMETHOD(device_detach, cas_pci_detach),
2612 DEVMETHOD(device_suspend, cas_pci_suspend),
2613 DEVMETHOD(device_resume, cas_pci_resume),
2614 /* Use the suspend handler here, it is all that is required. */
2615 DEVMETHOD(device_shutdown, cas_pci_suspend),
2618 DEVMETHOD(miibus_readreg, cas_mii_readreg),
2619 DEVMETHOD(miibus_writereg, cas_mii_writereg),
2620 DEVMETHOD(miibus_statchg, cas_mii_statchg),
2625 static driver_t cas_pci_driver = {
2628 sizeof(struct cas_softc)
2631 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0);
2632 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0);
2633 MODULE_DEPEND(cas, pci, 1, 1, 1);
2635 static const struct cas_pci_dev {
2639 const char *cpd_desc;
2640 } cas_pci_devlist[] = {
2641 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" },
2642 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" },
2643 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" },
2648 cas_pci_probe(device_t dev)
2652 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2653 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2654 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2655 device_set_desc(dev, cas_pci_devlist[i].cpd_desc);
2656 return (BUS_PROBE_DEFAULT);
2663 static struct resource_spec cas_pci_res_spec[] = {
2664 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */
2665 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */
2669 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address"
2670 #define CAS_PHY_INTERFACE "phy-interface"
2671 #define CAS_PHY_TYPE "phy-type"
2672 #define CAS_PHY_TYPE_PCS "pcs"
2675 cas_pci_attach(device_t dev)
2677 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)];
2678 struct cas_softc *sc;
2680 #if !(defined(__powerpc__) || defined(__sparc64__))
2681 u_char enaddr[4][ETHER_ADDR_LEN];
2682 u_int j, k, lma, pcs[4], phy;
2685 sc = device_get_softc(dev);
2686 sc->sc_variant = CAS_UNKNOWN;
2687 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2688 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2689 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2690 sc->sc_variant = cas_pci_devlist[i].cpd_variant;
2694 if (sc->sc_variant == CAS_UNKNOWN) {
2695 device_printf(dev, "unknown adaptor\n");
2699 /* PCI configuration */
2700 pci_write_config(dev, PCIR_COMMAND,
2701 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN |
2702 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2);
2705 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02)
2706 /* Hardware checksumming may hang TX. */
2707 sc->sc_flags |= CAS_NO_CSUM;
2708 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN)
2709 sc->sc_flags |= CAS_REG_PLUS;
2710 if (sc->sc_variant == CAS_CAS ||
2711 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11))
2712 sc->sc_flags |= CAS_TABORT;
2714 device_printf(dev, "flags=0x%x\n", sc->sc_flags);
2716 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) {
2717 device_printf(dev, "failed to allocate resources\n");
2718 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2722 CAS_LOCK_INIT(sc, device_get_nameunit(dev));
2724 #if defined(__powerpc__) || defined(__sparc64__)
2725 OF_getetheraddr(dev, sc->sc_enaddr);
2726 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf,
2727 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev),
2728 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) {
2729 buf[sizeof(buf) - 1] = '\0';
2730 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2731 sc->sc_flags |= CAS_SERDES;
2735 * Dig out VPD (vital product data) and read the MAC address as well
2736 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI
2737 * FCode) and can't be accessed via the PCI capability pointer.
2738 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described
2739 * in the free US Patent 7149820.
2742 #define PCI_ROMHDR_SIZE 0x1c
2743 #define PCI_ROMHDR_SIG 0x00
2744 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
2745 #define PCI_ROMHDR_PTR_DATA 0x18
2746 #define PCI_ROM_SIZE 0x18
2747 #define PCI_ROM_SIG 0x00
2748 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
2750 #define PCI_ROM_VENDOR 0x04
2751 #define PCI_ROM_DEVICE 0x06
2752 #define PCI_ROM_PTR_VPD 0x08
2753 #define PCI_VPDRES_BYTE0 0x00
2754 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
2755 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
2756 #define PCI_VPDRES_LARGE_LEN_LSB 0x01
2757 #define PCI_VPDRES_LARGE_LEN_MSB 0x02
2758 #define PCI_VPDRES_LARGE_SIZE 0x03
2759 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */
2760 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
2761 #define PCI_VPD_KEY0 0x00
2762 #define PCI_VPD_KEY1 0x01
2763 #define PCI_VPD_LEN 0x02
2764 #define PCI_VPD_SIZE 0x03
2766 #define CAS_ROM_READ_1(sc, offs) \
2767 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs))
2768 #define CAS_ROM_READ_2(sc, offs) \
2769 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs))
2770 #define CAS_ROM_READ_4(sc, offs) \
2771 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs))
2774 memset(enaddr, 0, sizeof(enaddr));
2775 memset(pcs, 0, sizeof(pcs));
2777 /* Enable PCI Expansion ROM access. */
2778 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2779 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM);
2781 /* Read PCI Expansion ROM header. */
2782 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
2783 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
2785 device_printf(dev, "unexpected PCI Expansion ROM header\n");
2789 /* Read PCI Expansion ROM data. */
2790 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
2791 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
2792 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
2793 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
2795 device_printf(dev, "unexpected PCI Expansion ROM data\n");
2801 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc,
2802 j + PCI_VPDRES_BYTE0)) == 0) {
2803 device_printf(dev, "no large PCI VPD\n");
2807 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) |
2808 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB);
2809 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc,
2810 j + PCI_VPDRES_BYTE0))) {
2811 case PCI_VPDRES_TYPE_ID_STRING:
2812 /* Skip identifier string. */
2813 j += PCI_VPDRES_LARGE_SIZE + i;
2815 case PCI_VPDRES_TYPE_VPD:
2816 for (j += PCI_VPDRES_LARGE_SIZE; i > 0;
2817 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN),
2818 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) {
2819 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z')
2820 /* no Enhanced VPD */
2822 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I')
2823 /* no instance property */
2825 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') {
2827 if (CAS_ROM_READ_1(sc,
2828 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN)
2830 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2831 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2833 buf[sizeof(buf) - 1] = '\0';
2834 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0)
2836 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2837 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2838 5 + sizeof(CAS_LOCAL_MAC_ADDRESS),
2839 enaddr[lma], sizeof(enaddr[lma]));
2841 if (lma == 4 && phy == 4)
2843 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) ==
2846 if (CAS_ROM_READ_1(sc,
2847 j + PCI_VPD_SIZE + 4) !=
2848 sizeof(CAS_PHY_TYPE_PCS))
2850 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2851 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2853 buf[sizeof(buf) - 1] = '\0';
2854 if (strcmp(buf, CAS_PHY_INTERFACE) == 0)
2855 k = sizeof(CAS_PHY_INTERFACE);
2856 else if (strcmp(buf, CAS_PHY_TYPE) == 0)
2857 k = sizeof(CAS_PHY_TYPE);
2860 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2861 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2862 5 + k, buf, sizeof(buf));
2863 buf[sizeof(buf) - 1] = '\0';
2864 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2867 if (lma == 4 && phy == 4)
2873 device_printf(dev, "unexpected PCI VPD\n");
2878 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);
2881 device_printf(dev, "could not determine Ethernet address\n");
2885 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr))
2886 i = pci_get_slot(dev);
2887 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN);
2890 device_printf(dev, "could not determine PHY type\n");
2894 if (phy > 1 && pci_get_slot(dev) < nitems(pcs))
2895 i = pci_get_slot(dev);
2897 sc->sc_flags |= CAS_SERDES;
2900 if (cas_attach(sc) != 0) {
2901 device_printf(dev, "could not be attached\n");
2905 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET |
2906 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) {
2907 device_printf(dev, "failed to set up interrupt\n");
2914 CAS_LOCK_DESTROY(sc);
2915 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2920 cas_pci_detach(device_t dev)
2922 struct cas_softc *sc;
2924 sc = device_get_softc(dev);
2925 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih);
2927 CAS_LOCK_DESTROY(sc);
2928 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2933 cas_pci_suspend(device_t dev)
2936 cas_suspend(device_get_softc(dev));
2941 cas_pci_resume(device_t dev)
2944 cas_resume(device_get_softc(dev));