2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2001 Eduardo Horvath.
5 * Copyright (c) 2001-2003 Thomas Moestl
6 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
31 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
38 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065
39 * Saturn Gigabit Ethernet controllers
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/callout.h>
50 #include <sys/endian.h>
52 #include <sys/malloc.h>
53 #include <sys/kernel.h>
55 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/refcount.h>
58 #include <sys/resource.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/taskqueue.h>
65 #include <net/ethernet.h>
67 #include <net/if_var.h>
68 #include <net/if_arp.h>
69 #include <net/if_dl.h>
70 #include <net/if_media.h>
71 #include <net/if_types.h>
72 #include <net/if_vlan_var.h>
74 #include <netinet/in.h>
75 #include <netinet/in_systm.h>
76 #include <netinet/ip.h>
77 #include <netinet/tcp.h>
78 #include <netinet/udp.h>
80 #include <machine/bus.h>
81 #if defined(__powerpc__) || defined(__sparc64__)
82 #include <dev/ofw/ofw_bus.h>
83 #include <dev/ofw/openfirm.h>
84 #include <machine/ofw_machdep.h>
86 #include <machine/resource.h>
88 #include <dev/mii/mii.h>
89 #include <dev/mii/miivar.h>
91 #include <dev/cas/if_casreg.h>
92 #include <dev/cas/if_casvar.h>
94 #include <dev/pci/pcireg.h>
95 #include <dev/pci/pcivar.h>
97 #include "miibus_if.h"
99 #define RINGASSERT(n , min, max) \
100 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max))
102 RINGASSERT(CAS_NRXCOMP, 128, 32768);
103 RINGASSERT(CAS_NRXDESC, 32, 8192);
104 RINGASSERT(CAS_NRXDESC2, 32, 8192);
105 RINGASSERT(CAS_NTXDESC, 32, 8192);
109 #define CCDASSERT(m, a) \
110 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0)
112 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN);
113 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN);
114 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN);
118 #define CAS_TRIES 10000
121 * According to documentation, the hardware has support for basic TCP
122 * checksum offloading only, in practice this can be also used for UDP
123 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0
124 * is not converted to 0xffff no longer exists).
126 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
128 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx);
129 static int cas_attach(struct cas_softc *sc);
130 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr,
132 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs,
133 int nsegs, int error);
134 static void cas_detach(struct cas_softc *sc);
135 static int cas_disable_rx(struct cas_softc *sc);
136 static int cas_disable_tx(struct cas_softc *sc);
137 static void cas_eint(struct cas_softc *sc, u_int status);
138 static void cas_free(struct mbuf *m);
139 static void cas_init(void *xsc);
140 static void cas_init_locked(struct cas_softc *sc);
141 static void cas_init_regs(struct cas_softc *sc);
142 static int cas_intr(void *v);
143 static void cas_intr_task(void *arg, int pending __unused);
144 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
145 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head);
146 static int cas_mediachange(struct ifnet *ifp);
147 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
148 static void cas_meminit(struct cas_softc *sc);
149 static void cas_mifinit(struct cas_softc *sc);
150 static int cas_mii_readreg(device_t dev, int phy, int reg);
151 static void cas_mii_statchg(device_t dev);
152 static int cas_mii_writereg(device_t dev, int phy, int reg, int val);
153 static void cas_reset(struct cas_softc *sc);
154 static int cas_reset_rx(struct cas_softc *sc);
155 static int cas_reset_tx(struct cas_softc *sc);
156 static void cas_resume(struct cas_softc *sc);
157 static u_int cas_descsize(u_int sz);
158 static void cas_rint(struct cas_softc *sc);
159 static void cas_rint_timeout(void *arg);
160 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum);
161 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp);
162 static u_int cas_rxcompsize(u_int sz);
163 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs,
164 int nsegs, int error);
165 static void cas_setladrf(struct cas_softc *sc);
166 static void cas_start(struct ifnet *ifp);
167 static void cas_stop(struct ifnet *ifp);
168 static void cas_suspend(struct cas_softc *sc);
169 static void cas_tick(void *arg);
170 static void cas_tint(struct cas_softc *sc);
171 static void cas_tx_task(void *arg, int pending __unused);
172 static inline void cas_txkick(struct cas_softc *sc);
173 static void cas_watchdog(struct cas_softc *sc);
175 static devclass_t cas_devclass;
177 MODULE_DEPEND(cas, ether, 1, 1, 1);
178 MODULE_DEPEND(cas, miibus, 1, 1, 1);
182 #define KTR_CAS KTR_SPARE2
186 cas_attach(struct cas_softc *sc)
188 struct cas_txsoft *txs;
193 /* Set up ifnet structure. */
194 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
198 if_initname(ifp, device_get_name(sc->sc_dev),
199 device_get_unit(sc->sc_dev));
200 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
201 ifp->if_start = cas_start;
202 ifp->if_ioctl = cas_ioctl;
203 ifp->if_init = cas_init;
204 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN);
205 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN;
206 IFQ_SET_READY(&ifp->if_snd);
208 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
209 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
210 /* Create local taskq. */
211 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc);
212 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp);
213 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK,
214 taskqueue_thread_enqueue, &sc->sc_tq);
215 if (sc->sc_tq == NULL) {
216 device_printf(sc->sc_dev, "could not create taskqueue\n");
220 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
221 device_get_nameunit(sc->sc_dev));
223 device_printf(sc->sc_dev, "could not start threads\n");
227 /* Make sure the chip is stopped. */
230 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
232 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL,
237 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
238 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
239 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag);
243 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
245 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES,
246 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
250 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0,
251 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
252 sizeof(struct cas_control_data), 1,
253 sizeof(struct cas_control_data), 0,
254 NULL, NULL, &sc->sc_cdmatag);
259 * Allocate the control data structures, create and load the
262 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
263 (void **)&sc->sc_control_data,
264 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
265 &sc->sc_cddmamap)) != 0) {
266 device_printf(sc->sc_dev,
267 "unable to allocate control data, error = %d\n", error);
272 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
273 sc->sc_control_data, sizeof(struct cas_control_data),
274 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
275 device_printf(sc->sc_dev,
276 "unable to load control data DMA map, error = %d\n",
282 * Initialize the transmit job descriptors.
284 STAILQ_INIT(&sc->sc_txfreeq);
285 STAILQ_INIT(&sc->sc_txdirtyq);
288 * Create the transmit buffer DMA maps.
291 for (i = 0; i < CAS_TXQUEUELEN; i++) {
292 txs = &sc->sc_txsoft[i];
293 txs->txs_mbuf = NULL;
295 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
296 &txs->txs_dmamap)) != 0) {
297 device_printf(sc->sc_dev,
298 "unable to create TX DMA map %d, error = %d\n",
302 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
306 * Allocate the receive buffers, create and load the DMA maps
309 for (i = 0; i < CAS_NRXDESC; i++) {
310 if ((error = bus_dmamem_alloc(sc->sc_rdmatag,
311 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK,
312 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) {
313 device_printf(sc->sc_dev,
314 "unable to allocate RX buffer %d, error = %d\n",
320 sc->sc_rxdsoft[i].rxds_paddr = 0;
321 if ((error = bus_dmamap_load(sc->sc_rdmatag,
322 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf,
323 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 ||
324 sc->sc_rxdsoft[i].rxds_paddr == 0) {
325 device_printf(sc->sc_dev,
326 "unable to load RX DMA map %d, error = %d\n",
332 if ((sc->sc_flags & CAS_SERDES) == 0) {
333 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
334 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4,
335 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
338 * Look for an external PHY.
341 v = CAS_READ_4(sc, CAS_MIF_CONF);
342 if ((v & CAS_MIF_CONF_MDI1) != 0) {
343 v |= CAS_MIF_CONF_PHY_SELECT;
344 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
345 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
346 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
347 /* Enable/unfreeze the GMII pins of Saturn. */
348 if (sc->sc_variant == CAS_SATURN) {
349 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
350 CAS_READ_4(sc, CAS_SATURN_PCFG) &
351 ~CAS_SATURN_PCFG_FSI);
352 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
353 BUS_SPACE_BARRIER_READ |
354 BUS_SPACE_BARRIER_WRITE);
357 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
358 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
359 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
362 * Fall back on an internal PHY if no external PHY was found.
364 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) {
365 v &= ~CAS_MIF_CONF_PHY_SELECT;
366 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
367 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
368 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
369 /* Freeze the GMII pins of Saturn for saving power. */
370 if (sc->sc_variant == CAS_SATURN) {
371 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
372 CAS_READ_4(sc, CAS_SATURN_PCFG) |
373 CAS_SATURN_PCFG_FSI);
374 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
375 BUS_SPACE_BARRIER_READ |
376 BUS_SPACE_BARRIER_WRITE);
379 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
380 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
381 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
385 * Use the external PCS SERDES.
387 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
388 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE);
389 /* Enable/unfreeze the SERDES pins of Saturn. */
390 if (sc->sc_variant == CAS_SATURN) {
391 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
392 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
393 BUS_SPACE_BARRIER_WRITE);
395 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
396 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4,
397 BUS_SPACE_BARRIER_WRITE);
398 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
399 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
400 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
401 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
402 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
403 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
406 device_printf(sc->sc_dev, "attaching PHYs failed\n");
409 sc->sc_mii = device_get_softc(sc->sc_miibus);
412 * From this point forward, the attachment cannot fail. A failure
413 * before this point releases all resources that may have been
417 /* Announce FIFO sizes. */
418 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE);
419 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
420 CAS_RX_FIFO_SIZE / 1024, v / 16);
422 /* Attach the interface. */
423 ether_ifattach(ifp, sc->sc_enaddr);
426 * Tell the upper layer(s) we support long frames/checksum offloads.
428 ifp->if_hdrlen = sizeof(struct ether_vlan_header);
429 ifp->if_capabilities = IFCAP_VLAN_MTU;
430 if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
431 ifp->if_capabilities |= IFCAP_HWCSUM;
432 ifp->if_hwassist = CAS_CSUM_FEATURES;
434 ifp->if_capenable = ifp->if_capabilities;
439 * Free any resources we've allocated during the failed attach
440 * attempt. Do this in reverse order and fall through.
443 for (i = 0; i < CAS_NRXDESC; i++)
444 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
445 bus_dmamap_unload(sc->sc_rdmatag,
446 sc->sc_rxdsoft[i].rxds_dmamap);
448 for (i = 0; i < CAS_NRXDESC; i++)
449 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
450 bus_dmamem_free(sc->sc_rdmatag,
451 sc->sc_rxdsoft[i].rxds_buf,
452 sc->sc_rxdsoft[i].rxds_dmamap);
454 for (i = 0; i < CAS_TXQUEUELEN; i++)
455 if (sc->sc_txsoft[i].txs_dmamap != NULL)
456 bus_dmamap_destroy(sc->sc_tdmatag,
457 sc->sc_txsoft[i].txs_dmamap);
458 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
460 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
463 bus_dma_tag_destroy(sc->sc_cdmatag);
465 bus_dma_tag_destroy(sc->sc_tdmatag);
467 bus_dma_tag_destroy(sc->sc_rdmatag);
469 bus_dma_tag_destroy(sc->sc_pdmatag);
471 taskqueue_free(sc->sc_tq);
478 cas_detach(struct cas_softc *sc)
480 struct ifnet *ifp = sc->sc_ifp;
487 callout_drain(&sc->sc_tick_ch);
488 callout_drain(&sc->sc_rx_ch);
489 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task);
490 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task);
492 taskqueue_free(sc->sc_tq);
493 device_delete_child(sc->sc_dev, sc->sc_miibus);
495 for (i = 0; i < CAS_NRXDESC; i++)
496 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL)
497 bus_dmamap_sync(sc->sc_rdmatag,
498 sc->sc_rxdsoft[i].rxds_dmamap,
499 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
500 for (i = 0; i < CAS_NRXDESC; i++)
501 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
502 bus_dmamap_unload(sc->sc_rdmatag,
503 sc->sc_rxdsoft[i].rxds_dmamap);
504 for (i = 0; i < CAS_NRXDESC; i++)
505 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
506 bus_dmamem_free(sc->sc_rdmatag,
507 sc->sc_rxdsoft[i].rxds_buf,
508 sc->sc_rxdsoft[i].rxds_dmamap);
509 for (i = 0; i < CAS_TXQUEUELEN; i++)
510 if (sc->sc_txsoft[i].txs_dmamap != NULL)
511 bus_dmamap_destroy(sc->sc_tdmatag,
512 sc->sc_txsoft[i].txs_dmamap);
513 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
514 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
515 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
517 bus_dma_tag_destroy(sc->sc_cdmatag);
518 bus_dma_tag_destroy(sc->sc_tdmatag);
519 bus_dma_tag_destroy(sc->sc_rdmatag);
520 bus_dma_tag_destroy(sc->sc_pdmatag);
524 cas_suspend(struct cas_softc *sc)
526 struct ifnet *ifp = sc->sc_ifp;
534 cas_resume(struct cas_softc *sc)
536 struct ifnet *ifp = sc->sc_ifp;
540 * On resume all registers have to be initialized again like
543 sc->sc_flags &= ~CAS_INITED;
544 if (ifp->if_flags & IFF_UP)
550 cas_rxcksum(struct mbuf *m, uint16_t cksum)
552 struct ether_header *eh;
556 int32_t hlen, len, pktlen;
559 pktlen = m->m_pkthdr.len;
560 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
562 eh = mtod(m, struct ether_header *);
563 if (eh->ether_type != htons(ETHERTYPE_IP))
565 ip = (struct ip *)(eh + 1);
566 if (ip->ip_v != IPVERSION)
569 hlen = ip->ip_hl << 2;
570 pktlen -= sizeof(struct ether_header);
571 if (hlen < sizeof(struct ip))
573 if (ntohs(ip->ip_len) < hlen)
575 if (ntohs(ip->ip_len) != pktlen)
577 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
578 return; /* Cannot handle fragmented packet. */
582 if (pktlen < (hlen + sizeof(struct tcphdr)))
586 if (pktlen < (hlen + sizeof(struct udphdr)))
588 uh = (struct udphdr *)((uint8_t *)ip + hlen);
590 return; /* no checksum */
597 /* checksum fixup for IP options */
598 len = hlen - sizeof(struct ip);
600 opts = (uint16_t *)(ip + 1);
601 for (; len > 0; len -= sizeof(uint16_t), opts++) {
602 temp32 = cksum - *opts;
603 temp32 = (temp32 >> 16) + (temp32 & 65535);
604 cksum = temp32 & 65535;
607 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
608 m->m_pkthdr.csum_data = cksum;
612 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
614 struct cas_softc *sc = xsc;
619 panic("%s: bad control buffer segment count", __func__);
620 sc->sc_cddma = segs[0].ds_addr;
624 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
626 struct cas_softc *sc = xsc;
631 panic("%s: bad RX buffer segment count", __func__);
632 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr;
638 struct cas_softc *sc = arg;
639 struct ifnet *ifp = sc->sc_ifp;
642 CAS_LOCK_ASSERT(sc, MA_OWNED);
645 * Unload collision and error counters.
647 if_inc_counter(ifp, IFCOUNTER_COLLISIONS,
648 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) +
649 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT));
650 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) +
651 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT);
652 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v);
653 if_inc_counter(ifp, IFCOUNTER_OERRORS, v);
654 if_inc_counter(ifp, IFCOUNTER_IERRORS,
655 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) +
656 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) +
657 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) +
658 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL));
661 * Then clear the hardware counters.
663 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
664 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
665 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
666 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
667 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
668 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
669 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
670 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
672 mii_tick(sc->sc_mii);
674 if (sc->sc_txfree != CAS_MAXTXFREE)
679 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
683 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
688 for (i = CAS_TRIES; i--; DELAY(100)) {
689 reg = CAS_READ_4(sc, r);
690 if ((reg & clr) == 0 && (reg & set) == set)
697 cas_reset(struct cas_softc *sc)
701 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
703 /* Disable all interrupts in order to avoid spurious ones. */
704 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
710 * Do a full reset modulo the result of the last auto-negotiation
711 * when using the SERDES.
713 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
714 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
715 CAS_BARRIER(sc, CAS_RESET, 4,
716 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
718 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
719 device_printf(sc->sc_dev, "cannot reset device\n");
723 cas_stop(struct ifnet *ifp)
725 struct cas_softc *sc = ifp->if_softc;
726 struct cas_txsoft *txs;
729 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
732 callout_stop(&sc->sc_tick_ch);
733 callout_stop(&sc->sc_rx_ch);
735 /* Disable all interrupts in order to avoid spurious ones. */
736 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
742 * Release any queued transmit buffers.
744 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
745 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
746 if (txs->txs_ndescs != 0) {
747 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
748 BUS_DMASYNC_POSTWRITE);
749 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
750 if (txs->txs_mbuf != NULL) {
751 m_freem(txs->txs_mbuf);
752 txs->txs_mbuf = NULL;
755 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
759 * Mark the interface down and cancel the watchdog timer.
761 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
762 sc->sc_flags &= ~CAS_LINK;
763 sc->sc_wdog_timer = 0;
767 cas_reset_rx(struct cas_softc *sc)
771 * Resetting while DMA is in progress can cause a bus hang, so we
774 (void)cas_disable_rx(sc);
775 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
776 CAS_BARRIER(sc, CAS_RX_CONF, 4,
777 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
778 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0))
779 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
781 /* Finally, reset the ERX. */
782 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
783 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
784 CAS_BARRIER(sc, CAS_RESET, 4,
785 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
786 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) {
787 device_printf(sc->sc_dev, "cannot reset receiver\n");
794 cas_reset_tx(struct cas_softc *sc)
798 * Resetting while DMA is in progress can cause a bus hang, so we
801 (void)cas_disable_tx(sc);
802 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
803 CAS_BARRIER(sc, CAS_TX_CONF, 4,
804 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
805 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0))
806 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
808 /* Finally, reset the ETX. */
809 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
810 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
811 CAS_BARRIER(sc, CAS_RESET, 4,
812 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
813 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) {
814 device_printf(sc->sc_dev, "cannot reset transmitter\n");
821 cas_disable_rx(struct cas_softc *sc)
824 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
825 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN);
826 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
827 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
828 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
831 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
836 cas_disable_tx(struct cas_softc *sc)
839 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
840 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN);
841 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
842 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
843 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
846 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
851 cas_rxcompinit(struct cas_rx_comp *rxcomp)
854 rxcomp->crc_word1 = 0;
855 rxcomp->crc_word2 = 0;
857 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO));
858 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO);
862 cas_meminit(struct cas_softc *sc)
866 CAS_LOCK_ASSERT(sc, MA_OWNED);
869 * Initialize the transmit descriptor ring.
871 for (i = 0; i < CAS_NTXDESC; i++) {
872 sc->sc_txdescs[i].cd_flags = 0;
873 sc->sc_txdescs[i].cd_buf_ptr = 0;
875 sc->sc_txfree = CAS_MAXTXFREE;
880 * Initialize the receive completion ring.
882 for (i = 0; i < CAS_NRXCOMP; i++)
883 cas_rxcompinit(&sc->sc_rxcomps[i]);
887 * Initialize the first receive descriptor ring. We leave
888 * the second one zeroed as we don't actually use it.
890 for (i = 0; i < CAS_NRXDESC; i++)
891 CAS_INIT_RXDESC(sc, i, i);
894 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
898 cas_descsize(u_int sz)
903 return (CAS_DESC_32);
905 return (CAS_DESC_64);
907 return (CAS_DESC_128);
909 return (CAS_DESC_256);
911 return (CAS_DESC_512);
913 return (CAS_DESC_1K);
915 return (CAS_DESC_2K);
917 return (CAS_DESC_4K);
919 return (CAS_DESC_8K);
921 printf("%s: invalid descriptor ring size %d\n", __func__, sz);
922 return (CAS_DESC_32);
927 cas_rxcompsize(u_int sz)
932 return (CAS_RX_CONF_COMP_128);
934 return (CAS_RX_CONF_COMP_256);
936 return (CAS_RX_CONF_COMP_512);
938 return (CAS_RX_CONF_COMP_1K);
940 return (CAS_RX_CONF_COMP_2K);
942 return (CAS_RX_CONF_COMP_4K);
944 return (CAS_RX_CONF_COMP_8K);
946 return (CAS_RX_CONF_COMP_16K);
948 return (CAS_RX_CONF_COMP_32K);
950 printf("%s: invalid dcompletion ring size %d\n", __func__, sz);
951 return (CAS_RX_CONF_COMP_128);
958 struct cas_softc *sc = xsc;
966 * Initialization of interface; set up initialization block
967 * and transmit/receive descriptor rings.
970 cas_init_locked(struct cas_softc *sc)
972 struct ifnet *ifp = sc->sc_ifp;
975 CAS_LOCK_ASSERT(sc, MA_OWNED);
977 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
981 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev),
985 * Initialization sequence. The numbered steps below correspond
986 * to the sequence outlined in section 6.3.5.1 in the Ethernet
987 * Channel Engine manual (part of the PCIO manual).
988 * See also the STP2002-STQ document from Sun Microsystems.
991 /* step 1 & 2. Reset the Ethernet Channel. */
995 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev),
999 if ((sc->sc_flags & CAS_SERDES) == 0)
1000 /* Re-initialize the MIF. */
1003 /* step 3. Setup data structures in host memory. */
1006 /* step 4. TX MAC registers & counters */
1009 /* step 5. RX MAC registers & counters */
1011 /* step 6 & 7. Program Ring Base Addresses. */
1012 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
1013 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32));
1014 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1015 CAS_CDTXDADDR(sc, 0) & 0xffffffff);
1017 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1018 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
1019 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1020 CAS_CDRXCADDR(sc, 0) & 0xffffffff);
1022 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1023 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32));
1024 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1025 CAS_CDRXDADDR(sc, 0) & 0xffffffff);
1027 if ((sc->sc_flags & CAS_REG_PLUS) != 0) {
1028 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1029 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32));
1030 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1031 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff);
1036 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx",
1037 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0),
1038 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma);
1041 /* step 8. Global Configuration & Interrupt Masks */
1043 /* Disable weighted round robin. */
1044 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1047 * Enable infinite bursts for revisions without PCI issues if
1048 * applicable. Doing so greatly improves the TX performance on
1049 * !__sparc64__ (on sparc64, setting CAS_INF_BURST improves TX
1050 * performance only marginally but hurts RX throughput quite a bit).
1052 CAS_WRITE_4(sc, CAS_INF_BURST,
1053 #if !defined(__sparc64__)
1054 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN :
1058 /* Set up interrupts. */
1059 CAS_WRITE_4(sc, CAS_INTMASK,
1060 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
1061 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
1062 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
1063 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
1064 CAS_INTR_PCI_ERROR_INT
1066 | CAS_INTR_PCS_INT | CAS_INTR_MIF
1069 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */
1070 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1071 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1072 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1073 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR));
1075 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1076 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1077 CAS_MAC_CTRL_NON_PAUSE));
1079 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1080 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1081 CAS_MAC_CTRL_NON_PAUSE);
1084 /* Enable PCI error interrupts. */
1085 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1086 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO |
1087 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO));
1089 /* Enable PCI error interrupts in BIM configuration. */
1090 CAS_WRITE_4(sc, CAS_BIM_CONF,
1091 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN);
1094 * step 9. ETX Configuration: encode receive descriptor ring size,
1095 * enable DMA and disable pre-interrupt writeback completion.
1097 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT;
1098 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1099 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS);
1101 /* step 10. ERX Configuration */
1104 * Encode receive completion and descriptor ring sizes, set the
1107 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT;
1108 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT;
1109 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1110 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT;
1111 CAS_WRITE_4(sc, CAS_RX_CONF,
1112 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT));
1114 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */
1115 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1116 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT));
1119 CAS_WRITE_4(sc, CAS_RX_BLANK,
1120 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT));
1122 /* Set RX_COMP_AFULL threshold to half of the RX completions. */
1123 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1124 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT);
1126 /* Initialize the RX page size register as appropriate for 8k. */
1127 CAS_WRITE_4(sc, CAS_RX_PSZ,
1128 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) |
1129 (4 << CAS_RX_PSZ_MB_CNT_SHFT) |
1130 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) |
1131 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT));
1133 /* Disable RX random early detection. */
1134 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1136 /* Zero the RX reassembly DMA table. */
1137 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) {
1138 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1139 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1140 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1141 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1144 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */
1145 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1146 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1148 /* Finally, enable RX DMA. */
1149 CAS_WRITE_4(sc, CAS_RX_CONF,
1150 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN);
1152 /* step 11. Configure Media. */
1154 /* step 12. RX_MAC Configuration Register */
1155 v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
1156 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN);
1157 v |= CAS_MAC_RX_CONF_STRPFCS;
1158 sc->sc_mac_rxcfg = v;
1160 * Clear the RX filter and reprogram it. This will also set the
1161 * current RX MAC configuration and enable it.
1165 /* step 13. TX_MAC Configuration Register */
1166 v = CAS_READ_4(sc, CAS_MAC_TX_CONF);
1167 v |= CAS_MAC_TX_CONF_EN;
1168 (void)cas_disable_tx(sc);
1169 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1171 /* step 14. Issue Transmit Pending command. */
1173 /* step 15. Give the receiver a swift kick. */
1174 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1175 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1176 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1177 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1179 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1180 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1182 mii_mediachg(sc->sc_mii);
1184 /* Start the one second timer. */
1185 sc->sc_wdog_timer = 0;
1186 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
1190 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head)
1192 bus_dma_segment_t txsegs[CAS_NTXSEGS];
1193 struct cas_txsoft *txs;
1197 int error, nexttx, nsegs, offset, seg;
1199 CAS_LOCK_ASSERT(sc, MA_OWNED);
1201 /* Get a work queue entry. */
1202 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1203 /* Ran out of descriptors. */
1208 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) {
1209 if (M_WRITABLE(*m_head) == 0) {
1210 m = m_dup(*m_head, M_NOWAIT);
1216 offset = sizeof(struct ether_header);
1217 m = m_pullup(*m_head, offset + sizeof(struct ip));
1222 ip = (struct ip *)(mtod(m, caddr_t) + offset);
1223 offset += (ip->ip_hl << 2);
1224 cflags = (offset << CAS_TD_CKSUM_START_SHFT) |
1225 ((offset + m->m_pkthdr.csum_data) <<
1226 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN;
1230 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
1231 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1232 if (error == EFBIG) {
1233 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS);
1240 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag,
1241 txs->txs_dmamap, *m_head, txsegs, &nsegs,
1248 } else if (error != 0)
1250 /* If nsegs is wrong then the stack is corrupt. */
1251 KASSERT(nsegs <= CAS_NTXSEGS,
1252 ("%s: too many DMA segments (%d)", __func__, nsegs));
1260 * Ensure we have enough descriptors free to describe
1261 * the packet. Note, we always reserve one descriptor
1262 * at the end of the ring as a termination point, in
1263 * order to prevent wrap-around.
1265 if (nsegs > sc->sc_txfree - 1) {
1266 txs->txs_ndescs = 0;
1267 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1271 txs->txs_ndescs = nsegs;
1272 txs->txs_firstdesc = sc->sc_txnext;
1273 nexttx = txs->txs_firstdesc;
1274 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) {
1277 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1278 __func__, seg, nexttx, txsegs[seg].ds_len,
1279 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr));
1281 sc->sc_txdescs[nexttx].cd_buf_ptr =
1282 htole64(txsegs[seg].ds_addr);
1283 KASSERT(txsegs[seg].ds_len <
1284 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT,
1285 ("%s: segment size too large!", __func__));
1286 sc->sc_txdescs[nexttx].cd_flags =
1287 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT);
1288 txs->txs_lastdesc = nexttx;
1291 /* Set EOF on the last descriptor. */
1293 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d",
1294 __func__, seg, nexttx);
1296 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |=
1297 htole64(CAS_TD_END_OF_FRAME);
1299 /* Lastly set SOF on the first descriptor. */
1301 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d",
1302 __func__, seg, nexttx);
1304 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) {
1306 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1307 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME);
1309 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1310 htole64(cflags | CAS_TD_START_OF_FRAME);
1312 /* Sync the DMA map. */
1313 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1314 BUS_DMASYNC_PREWRITE);
1317 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1318 __func__, txs->txs_firstdesc, txs->txs_lastdesc,
1321 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1322 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1323 txs->txs_mbuf = *m_head;
1325 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc);
1326 sc->sc_txfree -= txs->txs_ndescs;
1332 cas_init_regs(struct cas_softc *sc)
1335 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1337 CAS_LOCK_ASSERT(sc, MA_OWNED);
1339 /* These registers are not cleared on reset. */
1340 if ((sc->sc_flags & CAS_INITED) == 0) {
1342 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1343 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1344 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1346 /* min frame length */
1347 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1348 /* max frame length and max burst size */
1349 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1350 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) <<
1351 CAS_MAC_MAX_BF_FRM_SHFT) |
1352 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT));
1354 /* more magic values */
1355 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1356 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1357 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1358 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1360 /* random number seed */
1361 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1362 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1364 /* secondary MAC addresses: 0:0:0:0:0:0 */
1365 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41;
1366 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3)
1367 CAS_WRITE_4(sc, i, 0);
1369 /* MAC control address: 01:80:c2:00:00:01 */
1370 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1371 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1372 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1374 /* MAC filter address: 0:0:0:0:0:0 */
1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1376 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1377 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1378 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1379 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1381 /* Zero the hash table. */
1382 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15;
1383 i += CAS_MAC_HASH1 - CAS_MAC_HASH0)
1384 CAS_WRITE_4(sc, i, 0);
1386 sc->sc_flags |= CAS_INITED;
1389 /* Counters need to be zeroed. */
1390 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1391 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1392 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1393 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1394 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1395 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1396 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1397 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1398 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1399 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1400 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1402 /* Set XOFF PAUSE time. */
1403 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1405 /* Set the station address. */
1406 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1407 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1408 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1410 /* Enable MII outputs. */
1411 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1415 cas_tx_task(void *arg, int pending __unused)
1419 ifp = (struct ifnet *)arg;
1424 cas_txkick(struct cas_softc *sc)
1428 * Update the TX kick register. This register has to point to the
1429 * descriptor after the last valid one and for optimum performance
1430 * should be incremented in multiples of 4 (the DMA engine fetches/
1431 * updates descriptors in batches of 4).
1434 CTR3(KTR_CAS, "%s: %s: kicking TX %d",
1435 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1437 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1438 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1442 cas_start(struct ifnet *ifp)
1444 struct cas_softc *sc = ifp->if_softc;
1450 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1451 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) {
1456 if (sc->sc_txfree < CAS_MAXTXFREE / 4)
1460 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d",
1461 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1466 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1467 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1470 if (cas_load_txmbuf(sc, &m) != 0) {
1473 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1474 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1477 if ((sc->sc_txnext % 4) == 0) {
1490 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d",
1491 device_get_name(sc->sc_dev), sc->sc_txnext);
1494 /* Set a watchdog timer in case the chip flakes out. */
1495 sc->sc_wdog_timer = 5;
1497 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1498 device_get_name(sc->sc_dev), __func__,
1507 cas_tint(struct cas_softc *sc)
1509 struct ifnet *ifp = sc->sc_ifp;
1510 struct cas_txsoft *txs;
1516 CAS_LOCK_ASSERT(sc, MA_OWNED);
1518 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1522 * Go through our TX list and free mbufs for those
1523 * frames that have been transmitted.
1526 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1527 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1529 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1530 printf(" txsoft %p transmit chain:\n", txs);
1531 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) {
1532 printf("descriptor %d: ", i);
1533 printf("cd_flags: 0x%016llx\t",
1535 sc->sc_txdescs[i].cd_flags));
1536 printf("cd_buf_ptr: 0x%016llx\n",
1538 sc->sc_txdescs[i].cd_buf_ptr));
1539 if (i == txs->txs_lastdesc)
1546 * In theory, we could harvest some descriptors before
1547 * the ring is empty, but that's a bit complicated.
1549 * CAS_TX_COMPn points to the last descriptor
1552 txlast = CAS_READ_4(sc, CAS_TX_COMP3);
1554 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, "
1555 "txs->txs_lastdesc = %d, txlast = %d",
1556 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1558 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1559 if ((txlast >= txs->txs_firstdesc) &&
1560 (txlast <= txs->txs_lastdesc))
1563 /* Ick -- this command wraps. */
1564 if ((txlast >= txs->txs_firstdesc) ||
1565 (txlast <= txs->txs_lastdesc))
1570 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__);
1572 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1574 sc->sc_txfree += txs->txs_ndescs;
1576 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1577 BUS_DMASYNC_POSTWRITE);
1578 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1579 if (txs->txs_mbuf != NULL) {
1580 m_freem(txs->txs_mbuf);
1581 txs->txs_mbuf = NULL;
1584 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1586 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
1591 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx "
1593 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2),
1594 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) |
1595 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO),
1596 CAS_READ_4(sc, CAS_TX_COMP3));
1600 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */
1601 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1602 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1603 sc->sc_wdog_timer = 0;
1607 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1608 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1613 cas_rint_timeout(void *arg)
1615 struct cas_softc *sc = arg;
1617 CAS_LOCK_ASSERT(sc, MA_OWNED);
1623 cas_rint(struct cas_softc *sc)
1625 struct cas_rxdsoft *rxds, *rxds2;
1626 struct ifnet *ifp = sc->sc_ifp;
1627 struct mbuf *m, *m2;
1628 uint64_t word1, word2, word3, word4;
1630 u_int idx, idx2, len, off, skip;
1632 CAS_LOCK_ASSERT(sc, MA_OWNED);
1634 callout_stop(&sc->sc_rx_ch);
1637 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1640 #define PRINTWORD(n, delimiter) \
1641 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter)
1643 #define SKIPASSERT(n) \
1644 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \
1645 ("%s: word ## n not 0", __func__))
1647 #define WORDTOH(n) \
1648 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n)
1651 * Read the completion head register once. This limits
1652 * how long the following loop can execute.
1654 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD);
1656 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1657 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead);
1660 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1661 for (; sc->sc_rxcptr != rxhead;
1662 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) {
1678 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1679 printf(" completion %d: ", sc->sc_rxcptr);
1687 if (__predict_false(
1688 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW ||
1689 (word4 & CAS_RC4_ZERO) != 0)) {
1691 * The descriptor is still marked as owned, although
1692 * it is supposed to have completed. This has been
1693 * observed on some machines. Just exiting here
1694 * might leave the packet sitting around until another
1695 * one arrives to trigger a new interrupt, which is
1696 * generally undesirable, so set up a timeout.
1698 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS,
1699 cas_rint_timeout, sc);
1703 if (__predict_false(
1704 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) {
1705 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1706 device_printf(sc->sc_dev,
1707 "receive error: CRC error\n");
1711 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1712 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1713 ("%s: data and header present", __func__));
1714 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 ||
1715 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1716 ("%s: split and header present", __func__));
1717 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1718 (word1 & CAS_RC1_RELEASE_HDR) == 0,
1719 ("%s: data present but header release", __func__));
1720 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 ||
1721 (word1 & CAS_RC1_RELEASE_DATA) == 0,
1722 ("%s: header present but data release", __func__));
1724 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) {
1725 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX);
1726 off = CAS_GET(word2, CAS_RC2_HDR_OFF);
1728 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d",
1729 __func__, idx, off, len);
1731 rxds = &sc->sc_rxdsoft[idx];
1732 MGETHDR(m, M_NOWAIT, MT_DATA);
1734 refcount_acquire(&rxds->rxds_refcount);
1735 bus_dmamap_sync(sc->sc_rdmatag,
1736 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1737 m_extadd(m, (char *)rxds->rxds_buf +
1738 off * 256 + ETHER_ALIGN, len, cas_free,
1739 sc, (void *)(uintptr_t)idx,
1740 M_RDONLY, EXT_NET_DRV);
1741 if ((m->m_flags & M_EXT) == 0) {
1747 m->m_pkthdr.rcvif = ifp;
1748 m->m_pkthdr.len = m->m_len = len;
1749 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1750 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1751 cas_rxcksum(m, CAS_GET(word4,
1755 (*ifp->if_input)(ifp, m);
1758 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1760 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 &&
1761 refcount_release(&rxds->rxds_refcount) != 0)
1762 cas_add_rxdesc(sc, idx);
1763 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) {
1764 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX);
1765 off = CAS_GET(word1, CAS_RC1_DATA_OFF);
1767 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d",
1768 __func__, idx, off, len);
1770 rxds = &sc->sc_rxdsoft[idx];
1771 MGETHDR(m, M_NOWAIT, MT_DATA);
1773 refcount_acquire(&rxds->rxds_refcount);
1775 m->m_len = min(CAS_PAGE_SIZE - off, len);
1776 bus_dmamap_sync(sc->sc_rdmatag,
1777 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1778 m_extadd(m, (char *)rxds->rxds_buf + off,
1779 m->m_len, cas_free, sc,
1780 (void *)(uintptr_t)idx, M_RDONLY,
1782 if ((m->m_flags & M_EXT) == 0) {
1790 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) {
1791 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0,
1792 ("%s: split but no release next",
1795 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX);
1797 CTR2(KTR_CAS, "%s: split at idx %d",
1800 rxds2 = &sc->sc_rxdsoft[idx2];
1802 MGET(m2, M_NOWAIT, MT_DATA);
1805 &rxds2->rxds_refcount);
1806 m2->m_len = len - m->m_len;
1810 BUS_DMASYNC_POSTREAD);
1812 (char *)rxds2->rxds_buf,
1813 m2->m_len, cas_free, sc,
1814 (void *)(uintptr_t)idx2,
1815 M_RDONLY, EXT_NET_DRV);
1816 if ((m2->m_flags & M_EXT) ==
1825 else if (m != NULL) {
1831 m->m_pkthdr.rcvif = ifp;
1832 m->m_pkthdr.len = len;
1833 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
1834 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1835 cas_rxcksum(m, CAS_GET(word4,
1839 (*ifp->if_input)(ifp, m);
1842 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
1844 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 &&
1845 refcount_release(&rxds->rxds_refcount) != 0)
1846 cas_add_rxdesc(sc, idx);
1847 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 &&
1848 refcount_release(&rxds2->rxds_refcount) != 0)
1849 cas_add_rxdesc(sc, idx2);
1852 skip = CAS_GET(word1, CAS_RC1_SKIP);
1855 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]);
1856 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1859 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1860 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1867 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1868 __func__, sc->sc_rxcptr, sc->sc_rxdptr,
1869 CAS_READ_4(sc, CAS_RX_COMP_HEAD));
1874 cas_free(struct mbuf *m)
1876 struct cas_rxdsoft *rxds;
1877 struct cas_softc *sc;
1880 sc = m->m_ext.ext_arg1;
1881 idx = (uintptr_t)m->m_ext.ext_arg2;
1882 rxds = &sc->sc_rxdsoft[idx];
1883 if (refcount_release(&rxds->rxds_refcount) == 0)
1887 * NB: this function can be called via m_freem(9) within
1890 if ((locked = CAS_LOCK_OWNED(sc)) == 0)
1892 cas_add_rxdesc(sc, idx);
1898 cas_add_rxdesc(struct cas_softc *sc, u_int idx)
1901 CAS_LOCK_ASSERT(sc, MA_OWNED);
1903 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap,
1904 BUS_DMASYNC_PREREAD);
1905 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx);
1906 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr);
1909 * Update the RX kick register. This register has to point to the
1910 * descriptor after the last valid one (before the current batch)
1911 * and for optimum performance should be incremented in multiples
1912 * of 4 (the DMA engine fetches/updates descriptors in batches of 4).
1914 if ((sc->sc_rxdptr % 4) == 0) {
1915 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1916 CAS_WRITE_4(sc, CAS_RX_KICK,
1917 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK);
1922 cas_eint(struct cas_softc *sc, u_int status)
1924 struct ifnet *ifp = sc->sc_ifp;
1926 CAS_LOCK_ASSERT(sc, MA_OWNED);
1928 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
1930 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1931 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) {
1932 status = CAS_READ_4(sc, CAS_ERROR_STATUS);
1933 printf(", PCI bus error 0x%x", status);
1934 if ((status & CAS_ERROR_OTHER) != 0) {
1935 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
1936 printf(", PCI status 0x%x", status);
1937 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
1942 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1943 cas_init_locked(sc);
1944 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1945 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
1951 struct cas_softc *sc = v;
1953 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) &
1954 CAS_INTR_SUMMARY) == 0))
1955 return (FILTER_STRAY);
1957 /* Disable interrupts. */
1958 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
1959 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1961 return (FILTER_HANDLED);
1965 cas_intr_task(void *arg, int pending __unused)
1967 struct cas_softc *sc = arg;
1968 struct ifnet *ifp = sc->sc_ifp;
1969 uint32_t status, status2;
1971 CAS_LOCK_ASSERT(sc, MA_NOTOWNED);
1973 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1976 status = CAS_READ_4(sc, CAS_STATUS);
1977 if (__predict_false((status & CAS_INTR_SUMMARY) == 0))
1982 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x",
1983 device_get_name(sc->sc_dev), __func__,
1984 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status);
1987 * PCS interrupts must be cleared, otherwise no traffic is passed!
1989 if ((status & CAS_INTR_PCS_INT) != 0) {
1991 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) |
1992 CAS_READ_4(sc, CAS_PCS_INTR_STATUS);
1993 if ((status2 & CAS_PCS_INTR_LINK) != 0)
1994 device_printf(sc->sc_dev,
1995 "%s: PCS link status changed\n", __func__);
1997 if ((status & CAS_MAC_CTRL_STATUS) != 0) {
1998 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS);
1999 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2000 device_printf(sc->sc_dev,
2001 "%s: PAUSE received (PAUSE time %d slots)\n",
2003 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >>
2004 CAS_MAC_CTRL_STATUS_PT_SHFT);
2005 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2006 device_printf(sc->sc_dev,
2007 "%s: transited to PAUSE state\n", __func__);
2008 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0)
2009 device_printf(sc->sc_dev,
2010 "%s: transited to non-PAUSE state\n", __func__);
2012 if ((status & CAS_INTR_MIF) != 0)
2013 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
2016 if (__predict_false((status &
2017 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
2018 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) {
2019 cas_eint(sc, status);
2024 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) {
2025 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS);
2027 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0)
2028 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2029 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0)
2030 device_printf(sc->sc_dev,
2031 "MAC TX fault, status %x\n", status2);
2034 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) {
2035 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS);
2036 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0)
2037 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
2038 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0)
2039 device_printf(sc->sc_dev,
2040 "MAC RX fault, status %x\n", status2);
2044 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2045 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) {
2048 if (__predict_false((status &
2049 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2050 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0))
2051 device_printf(sc->sc_dev,
2052 "RX fault, status %x\n", status);
2057 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0)
2060 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2063 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2064 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2067 status = CAS_READ_4(sc, CAS_STATUS_ALIAS);
2068 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) {
2069 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
2074 /* Re-enable interrupts. */
2075 CAS_WRITE_4(sc, CAS_INTMASK,
2076 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
2077 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
2078 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
2079 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
2080 CAS_INTR_PCI_ERROR_INT
2082 | CAS_INTR_PCS_INT | CAS_INTR_MIF
2088 cas_watchdog(struct cas_softc *sc)
2090 struct ifnet *ifp = sc->sc_ifp;
2092 CAS_LOCK_ASSERT(sc, MA_OWNED);
2096 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x",
2097 __func__, CAS_READ_4(sc, CAS_RX_CONF),
2098 CAS_READ_4(sc, CAS_MAC_RX_STATUS),
2099 CAS_READ_4(sc, CAS_MAC_RX_CONF));
2101 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x",
2102 __func__, CAS_READ_4(sc, CAS_TX_CONF),
2103 CAS_READ_4(sc, CAS_MAC_TX_STATUS),
2104 CAS_READ_4(sc, CAS_MAC_TX_CONF));
2107 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
2110 if ((sc->sc_flags & CAS_LINK) != 0)
2111 device_printf(sc->sc_dev, "device timeout\n");
2112 else if (bootverbose)
2113 device_printf(sc->sc_dev, "device timeout (no link)\n");
2114 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
2116 /* Try to get more packets going. */
2117 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2118 cas_init_locked(sc);
2119 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2120 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2124 cas_mifinit(struct cas_softc *sc)
2127 /* Configure the MIF in frame mode. */
2128 CAS_WRITE_4(sc, CAS_MIF_CONF,
2129 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE);
2130 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
2131 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2137 * The MII interface supports at least three different operating modes:
2139 * Bitbang mode is implemented using data, clock and output enable registers.
2141 * Frame mode is implemented by loading a complete frame into the frame
2142 * register and polling the valid bit for completion.
2144 * Polling mode uses the frame register but completion is indicated by
2149 cas_mii_readreg(device_t dev, int phy, int reg)
2151 struct cas_softc *sc;
2155 #ifdef CAS_DEBUG_PHY
2156 printf("%s: phy %d reg %d\n", __func__, phy, reg);
2159 sc = device_get_softc(dev);
2160 if ((sc->sc_flags & CAS_SERDES) != 0) {
2166 reg = CAS_PCS_STATUS;
2175 reg = CAS_PCS_ANLPAR;
2178 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
2180 device_printf(sc->sc_dev,
2181 "%s: unhandled register %d\n", __func__, reg);
2184 return (CAS_READ_4(sc, reg));
2187 /* Construct the frame command. */
2188 v = CAS_MIF_FRAME_READ |
2189 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2190 (reg << CAS_MIF_FRAME_REG_SHFT);
2192 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2193 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2194 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2195 for (n = 0; n < 100; n++) {
2197 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2198 if (v & CAS_MIF_FRAME_TA_LSB)
2199 return (v & CAS_MIF_FRAME_DATA);
2202 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2207 cas_mii_writereg(device_t dev, int phy, int reg, int val)
2209 struct cas_softc *sc;
2213 #ifdef CAS_DEBUG_PHY
2214 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
2217 sc = device_get_softc(dev);
2218 if ((sc->sc_flags & CAS_SERDES) != 0) {
2221 reg = CAS_PCS_STATUS;
2225 if ((val & CAS_PCS_CTRL_RESET) == 0)
2227 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2228 CAS_BARRIER(sc, CAS_PCS_CTRL, 4,
2229 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2230 if (!cas_bitwait(sc, CAS_PCS_CTRL,
2231 CAS_PCS_CTRL_RESET, 0))
2232 device_printf(sc->sc_dev,
2233 "cannot reset PCS\n");
2236 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2237 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2238 BUS_SPACE_BARRIER_WRITE);
2239 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2240 CAS_BARRIER(sc, CAS_PCS_ANAR, 4,
2241 BUS_SPACE_BARRIER_WRITE);
2242 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2243 CAS_PCS_SERDES_CTRL_ESD);
2244 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2245 BUS_SPACE_BARRIER_WRITE);
2246 CAS_WRITE_4(sc, CAS_PCS_CONF,
2248 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2249 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2252 reg = CAS_PCS_ANLPAR;
2255 device_printf(sc->sc_dev,
2256 "%s: unhandled register %d\n", __func__, reg);
2259 CAS_WRITE_4(sc, reg, val);
2260 CAS_BARRIER(sc, reg, 4,
2261 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2265 /* Construct the frame command. */
2266 v = CAS_MIF_FRAME_WRITE |
2267 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2268 (reg << CAS_MIF_FRAME_REG_SHFT) |
2269 (val & CAS_MIF_FRAME_DATA);
2271 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2272 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2273 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2274 for (n = 0; n < 100; n++) {
2276 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2277 if (v & CAS_MIF_FRAME_TA_LSB)
2281 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2286 cas_mii_statchg(device_t dev)
2288 struct cas_softc *sc;
2291 uint32_t rxcfg, txcfg, v;
2293 sc = device_get_softc(dev);
2296 CAS_LOCK_ASSERT(sc, MA_OWNED);
2299 if ((ifp->if_flags & IFF_DEBUG) != 0)
2300 device_printf(sc->sc_dev, "%s: status changen", __func__);
2303 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2304 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2305 sc->sc_flags |= CAS_LINK;
2307 sc->sc_flags &= ~CAS_LINK;
2309 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2321 * The configuration done here corresponds to the steps F) and
2322 * G) and as far as enabling of RX and TX MAC goes also step H)
2323 * of the initialization sequence outlined in section 11.2.1 of
2324 * the Cassini+ ASIC Specification.
2327 rxcfg = sc->sc_mac_rxcfg;
2328 rxcfg &= ~CAS_MAC_RX_CONF_CARR;
2329 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU |
2330 CAS_MAC_TX_CONF_NGUL;
2331 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2332 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS;
2333 else if (gigabit != 0) {
2334 rxcfg |= CAS_MAC_RX_CONF_CARR;
2335 txcfg |= CAS_MAC_TX_CONF_CARR;
2337 (void)cas_disable_tx(sc);
2338 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2339 (void)cas_disable_rx(sc);
2340 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2342 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) &
2343 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP);
2344 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2345 IFM_ETH_RXPAUSE) != 0)
2346 v |= CAS_MAC_CTRL_CONF_RXP;
2347 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2348 IFM_ETH_TXPAUSE) != 0)
2349 v |= CAS_MAC_CTRL_CONF_TXP;
2350 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2353 * All supported chips have a bug causing incorrect checksum
2354 * to be calculated when letting them strip the FCS in half-
2355 * duplex mode. In theory we could disable FCS stripping and
2356 * manually adjust the checksum accordingly. It seems to make
2357 * more sense to optimze for the common case and just disable
2358 * hardware checksumming in half-duplex mode though.
2360 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) {
2361 ifp->if_capenable &= ~IFCAP_HWCSUM;
2362 ifp->if_hwassist = 0;
2363 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
2364 ifp->if_capenable = ifp->if_capabilities;
2365 ifp->if_hwassist = CAS_CSUM_FEATURES;
2368 if (sc->sc_variant == CAS_SATURN) {
2369 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2370 /* silicon bug workaround */
2371 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2373 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2376 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2378 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2379 CAS_MAC_SLOT_TIME_CARR);
2381 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2382 CAS_MAC_SLOT_TIME_NORM);
2384 /* XIF Configuration */
2385 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED;
2386 if ((sc->sc_flags & CAS_SERDES) == 0) {
2387 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2388 v |= CAS_MAC_XIF_CONF_NOECHO;
2389 v |= CAS_MAC_XIF_CONF_BUF_OE;
2392 v |= CAS_MAC_XIF_CONF_GMII;
2393 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2394 v |= CAS_MAC_XIF_CONF_FDXLED;
2395 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2397 sc->sc_mac_rxcfg = rxcfg;
2398 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2399 (sc->sc_flags & CAS_LINK) != 0) {
2400 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2401 txcfg | CAS_MAC_TX_CONF_EN);
2402 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2403 rxcfg | CAS_MAC_RX_CONF_EN);
2408 cas_mediachange(struct ifnet *ifp)
2410 struct cas_softc *sc = ifp->if_softc;
2413 /* XXX add support for serial media. */
2416 error = mii_mediachg(sc->sc_mii);
2422 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2424 struct cas_softc *sc = ifp->if_softc;
2427 if ((ifp->if_flags & IFF_UP) == 0) {
2432 mii_pollstat(sc->sc_mii);
2433 ifmr->ifm_active = sc->sc_mii->mii_media_active;
2434 ifmr->ifm_status = sc->sc_mii->mii_media_status;
2439 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2441 struct cas_softc *sc = ifp->if_softc;
2442 struct ifreq *ifr = (struct ifreq *)data;
2449 if ((ifp->if_flags & IFF_UP) != 0) {
2450 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2451 ((ifp->if_flags ^ sc->sc_ifflags) &
2452 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2455 cas_init_locked(sc);
2456 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2458 sc->sc_ifflags = ifp->if_flags;
2463 if ((sc->sc_flags & CAS_NO_CSUM) != 0) {
2468 ifp->if_capenable = ifr->ifr_reqcap;
2469 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2470 ifp->if_hwassist = CAS_CSUM_FEATURES;
2472 ifp->if_hwassist = 0;
2478 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2483 if ((ifr->ifr_mtu < ETHERMIN) ||
2484 (ifr->ifr_mtu > ETHERMTU_JUMBO))
2487 ifp->if_mtu = ifr->ifr_mtu;
2491 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
2494 error = ether_ioctl(ifp, cmd, data);
2502 cas_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
2504 uint32_t crc, *hash = arg;
2506 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN);
2507 /* We just want the 8 most significant bits. */
2509 /* Set the corresponding bit in the filter. */
2510 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2516 cas_setladrf(struct cas_softc *sc)
2518 struct ifnet *ifp = sc->sc_ifp;
2523 CAS_LOCK_ASSERT(sc, MA_OWNED);
2526 * Turn off the RX MAC and the hash filter as required by the Sun
2527 * Cassini programming restrictions.
2529 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER |
2530 CAS_MAC_RX_CONF_EN);
2531 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2532 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
2533 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2534 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER |
2535 CAS_MAC_RX_CONF_EN, 0))
2536 device_printf(sc->sc_dev,
2537 "cannot disable RX MAC or hash filter\n");
2539 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP);
2540 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2541 v |= CAS_MAC_RX_CONF_PROMISC;
2544 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2545 v |= CAS_MAC_RX_CONF_PGRP;
2550 * Set up multicast address filter by passing all multicast
2551 * addresses through a crc generator, and then using the high
2552 * order 8 bits as an index into the 256 bit logical address
2553 * filter. The high order 4 bits selects the word, while the
2554 * other 4 bits select the bit within the word (where bit 0
2558 memset(hash, 0, sizeof(hash));
2559 if_foreach_llmaddr(ifp, cas_hash_maddr, &hash);
2561 v |= CAS_MAC_RX_CONF_HFILTER;
2563 /* Now load the hash table into the chip (if we are using it). */
2564 for (i = 0; i < 16; i++)
2566 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
2570 sc->sc_mac_rxcfg = v;
2571 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2574 static int cas_pci_attach(device_t dev);
2575 static int cas_pci_detach(device_t dev);
2576 static int cas_pci_probe(device_t dev);
2577 static int cas_pci_resume(device_t dev);
2578 static int cas_pci_suspend(device_t dev);
2580 static device_method_t cas_pci_methods[] = {
2581 /* Device interface */
2582 DEVMETHOD(device_probe, cas_pci_probe),
2583 DEVMETHOD(device_attach, cas_pci_attach),
2584 DEVMETHOD(device_detach, cas_pci_detach),
2585 DEVMETHOD(device_suspend, cas_pci_suspend),
2586 DEVMETHOD(device_resume, cas_pci_resume),
2587 /* Use the suspend handler here, it is all that is required. */
2588 DEVMETHOD(device_shutdown, cas_pci_suspend),
2591 DEVMETHOD(miibus_readreg, cas_mii_readreg),
2592 DEVMETHOD(miibus_writereg, cas_mii_writereg),
2593 DEVMETHOD(miibus_statchg, cas_mii_statchg),
2598 static driver_t cas_pci_driver = {
2601 sizeof(struct cas_softc)
2604 static const struct cas_pci_dev {
2608 const char *cpd_desc;
2609 } cas_pci_devlist[] = {
2610 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" },
2611 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" },
2612 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" },
2616 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0);
2617 MODULE_PNP_INFO("W32:vendor/device", pci, cas, cas_pci_devlist,
2618 nitems(cas_pci_devlist) - 1);
2619 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0);
2620 MODULE_DEPEND(cas, pci, 1, 1, 1);
2623 cas_pci_probe(device_t dev)
2627 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2628 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2629 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2630 device_set_desc(dev, cas_pci_devlist[i].cpd_desc);
2631 return (BUS_PROBE_DEFAULT);
2638 static struct resource_spec cas_pci_res_spec[] = {
2639 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */
2640 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */
2644 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address"
2645 #define CAS_PHY_INTERFACE "phy-interface"
2646 #define CAS_PHY_TYPE "phy-type"
2647 #define CAS_PHY_TYPE_PCS "pcs"
2650 cas_pci_attach(device_t dev)
2652 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)];
2653 struct cas_softc *sc;
2655 #if !(defined(__powerpc__) || defined(__sparc64__))
2656 u_char enaddr[4][ETHER_ADDR_LEN];
2657 u_int j, k, lma, pcs[4], phy;
2660 sc = device_get_softc(dev);
2661 sc->sc_variant = CAS_UNKNOWN;
2662 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2663 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2664 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2665 sc->sc_variant = cas_pci_devlist[i].cpd_variant;
2669 if (sc->sc_variant == CAS_UNKNOWN) {
2670 device_printf(dev, "unknown adaptor\n");
2674 /* PCI configuration */
2675 pci_write_config(dev, PCIR_COMMAND,
2676 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN |
2677 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2);
2680 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02)
2681 /* Hardware checksumming may hang TX. */
2682 sc->sc_flags |= CAS_NO_CSUM;
2683 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN)
2684 sc->sc_flags |= CAS_REG_PLUS;
2685 if (sc->sc_variant == CAS_CAS ||
2686 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11))
2687 sc->sc_flags |= CAS_TABORT;
2689 device_printf(dev, "flags=0x%x\n", sc->sc_flags);
2691 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) {
2692 device_printf(dev, "failed to allocate resources\n");
2693 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2697 CAS_LOCK_INIT(sc, device_get_nameunit(dev));
2699 #if defined(__powerpc__) || defined(__sparc64__)
2700 OF_getetheraddr(dev, sc->sc_enaddr);
2701 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf,
2702 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev),
2703 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) {
2704 buf[sizeof(buf) - 1] = '\0';
2705 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2706 sc->sc_flags |= CAS_SERDES;
2710 * Dig out VPD (vital product data) and read the MAC address as well
2711 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI
2712 * FCode) and can't be accessed via the PCI capability pointer.
2713 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described
2714 * in the free US Patent 7149820.
2717 #define PCI_ROMHDR_SIZE 0x1c
2718 #define PCI_ROMHDR_SIG 0x00
2719 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
2720 #define PCI_ROMHDR_PTR_DATA 0x18
2721 #define PCI_ROM_SIZE 0x18
2722 #define PCI_ROM_SIG 0x00
2723 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
2725 #define PCI_ROM_VENDOR 0x04
2726 #define PCI_ROM_DEVICE 0x06
2727 #define PCI_ROM_PTR_VPD 0x08
2728 #define PCI_VPDRES_BYTE0 0x00
2729 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
2730 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
2731 #define PCI_VPDRES_LARGE_LEN_LSB 0x01
2732 #define PCI_VPDRES_LARGE_LEN_MSB 0x02
2733 #define PCI_VPDRES_LARGE_SIZE 0x03
2734 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */
2735 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
2736 #define PCI_VPD_KEY0 0x00
2737 #define PCI_VPD_KEY1 0x01
2738 #define PCI_VPD_LEN 0x02
2739 #define PCI_VPD_SIZE 0x03
2741 #define CAS_ROM_READ_1(sc, offs) \
2742 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs))
2743 #define CAS_ROM_READ_2(sc, offs) \
2744 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs))
2745 #define CAS_ROM_READ_4(sc, offs) \
2746 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs))
2749 memset(enaddr, 0, sizeof(enaddr));
2750 memset(pcs, 0, sizeof(pcs));
2752 /* Enable PCI Expansion ROM access. */
2753 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2754 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM);
2756 /* Read PCI Expansion ROM header. */
2757 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
2758 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
2760 device_printf(dev, "unexpected PCI Expansion ROM header\n");
2764 /* Read PCI Expansion ROM data. */
2765 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
2766 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
2767 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
2768 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
2770 device_printf(dev, "unexpected PCI Expansion ROM data\n");
2776 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc,
2777 j + PCI_VPDRES_BYTE0)) == 0) {
2778 device_printf(dev, "no large PCI VPD\n");
2782 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) |
2783 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB);
2784 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc,
2785 j + PCI_VPDRES_BYTE0))) {
2786 case PCI_VPDRES_TYPE_ID_STRING:
2787 /* Skip identifier string. */
2788 j += PCI_VPDRES_LARGE_SIZE + i;
2790 case PCI_VPDRES_TYPE_VPD:
2791 for (j += PCI_VPDRES_LARGE_SIZE; i > 0;
2792 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN),
2793 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) {
2794 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z')
2795 /* no Enhanced VPD */
2797 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I')
2798 /* no instance property */
2800 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') {
2802 if (CAS_ROM_READ_1(sc,
2803 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN)
2805 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2806 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2808 buf[sizeof(buf) - 1] = '\0';
2809 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0)
2811 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2812 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2813 5 + sizeof(CAS_LOCAL_MAC_ADDRESS),
2814 enaddr[lma], sizeof(enaddr[lma]));
2816 if (lma == 4 && phy == 4)
2818 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) ==
2821 if (CAS_ROM_READ_1(sc,
2822 j + PCI_VPD_SIZE + 4) !=
2823 sizeof(CAS_PHY_TYPE_PCS))
2825 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2826 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2828 buf[sizeof(buf) - 1] = '\0';
2829 if (strcmp(buf, CAS_PHY_INTERFACE) == 0)
2830 k = sizeof(CAS_PHY_INTERFACE);
2831 else if (strcmp(buf, CAS_PHY_TYPE) == 0)
2832 k = sizeof(CAS_PHY_TYPE);
2835 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2836 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2837 5 + k, buf, sizeof(buf));
2838 buf[sizeof(buf) - 1] = '\0';
2839 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2842 if (lma == 4 && phy == 4)
2848 device_printf(dev, "unexpected PCI VPD\n");
2853 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);
2856 device_printf(dev, "could not determine Ethernet address\n");
2860 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr))
2861 i = pci_get_slot(dev);
2862 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN);
2865 device_printf(dev, "could not determine PHY type\n");
2869 if (phy > 1 && pci_get_slot(dev) < nitems(pcs))
2870 i = pci_get_slot(dev);
2872 sc->sc_flags |= CAS_SERDES;
2875 if (cas_attach(sc) != 0) {
2876 device_printf(dev, "could not be attached\n");
2880 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET |
2881 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) {
2882 device_printf(dev, "failed to set up interrupt\n");
2889 CAS_LOCK_DESTROY(sc);
2890 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2895 cas_pci_detach(device_t dev)
2897 struct cas_softc *sc;
2899 sc = device_get_softc(dev);
2900 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih);
2902 CAS_LOCK_DESTROY(sc);
2903 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2908 cas_pci_suspend(device_t dev)
2911 cas_suspend(device_get_softc(dev));
2916 cas_pci_resume(device_t dev)
2919 cas_resume(device_get_softc(dev));