2 * Copyright (C) 2001 Eduardo Horvath.
3 * Copyright (c) 2001-2003 Thomas Moestl
4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065
37 * Saturn Gigabit Ethernet controllers
44 #include <sys/param.h>
45 #include <sys/systm.h>
47 #include <sys/callout.h>
48 #include <sys/endian.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
55 #include <sys/refcount.h>
56 #include <sys/resource.h>
58 #include <sys/socket.h>
59 #include <sys/sockio.h>
60 #include <sys/taskqueue.h>
63 #include <net/ethernet.h>
65 #include <net/if_arp.h>
66 #include <net/if_dl.h>
67 #include <net/if_media.h>
68 #include <net/if_types.h>
69 #include <net/if_vlan_var.h>
71 #include <netinet/in.h>
72 #include <netinet/in_systm.h>
73 #include <netinet/ip.h>
74 #include <netinet/tcp.h>
75 #include <netinet/udp.h>
77 #include <machine/bus.h>
78 #if defined(__powerpc__) || defined(__sparc64__)
79 #include <dev/ofw/ofw_bus.h>
80 #include <dev/ofw/openfirm.h>
81 #include <machine/ofw_machdep.h>
83 #include <machine/resource.h>
85 #include <dev/mii/mii.h>
86 #include <dev/mii/miivar.h>
88 #include <dev/cas/if_casreg.h>
89 #include <dev/cas/if_casvar.h>
91 #include <dev/pci/pcireg.h>
92 #include <dev/pci/pcivar.h>
94 #include "miibus_if.h"
96 #define RINGASSERT(n , min, max) \
97 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max))
99 RINGASSERT(CAS_NRXCOMP, 128, 32768);
100 RINGASSERT(CAS_NRXDESC, 32, 8192);
101 RINGASSERT(CAS_NRXDESC2, 32, 8192);
102 RINGASSERT(CAS_NTXDESC, 32, 8192);
106 #define CCDASSERT(m, a) \
107 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0)
109 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN);
110 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN);
111 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN);
115 #define CAS_TRIES 10000
118 * According to documentation, the hardware has support for basic TCP
119 * checksum offloading only, in practice this can be also used for UDP
120 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0
121 * is not converted to 0xffff no longer exists).
123 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP)
125 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx);
126 static int cas_attach(struct cas_softc *sc);
127 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr,
129 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs,
130 int nsegs, int error);
131 static void cas_detach(struct cas_softc *sc);
132 static int cas_disable_rx(struct cas_softc *sc);
133 static int cas_disable_tx(struct cas_softc *sc);
134 static void cas_eint(struct cas_softc *sc, u_int status);
135 static void cas_free(void *arg1, void* arg2);
136 static void cas_init(void *xsc);
137 static void cas_init_locked(struct cas_softc *sc);
138 static void cas_init_regs(struct cas_softc *sc);
139 static int cas_intr(void *v);
140 static void cas_intr_task(void *arg, int pending __unused);
141 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
142 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head);
143 static int cas_mediachange(struct ifnet *ifp);
144 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr);
145 static void cas_meminit(struct cas_softc *sc);
146 static void cas_mifinit(struct cas_softc *sc);
147 static int cas_mii_readreg(device_t dev, int phy, int reg);
148 static void cas_mii_statchg(device_t dev);
149 static int cas_mii_writereg(device_t dev, int phy, int reg, int val);
150 static void cas_reset(struct cas_softc *sc);
151 static int cas_reset_rx(struct cas_softc *sc);
152 static int cas_reset_tx(struct cas_softc *sc);
153 static void cas_resume(struct cas_softc *sc);
154 static u_int cas_descsize(u_int sz);
155 static void cas_rint(struct cas_softc *sc);
156 static void cas_rint_timeout(void *arg);
157 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum);
158 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp);
159 static u_int cas_rxcompsize(u_int sz);
160 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs,
161 int nsegs, int error);
162 static void cas_setladrf(struct cas_softc *sc);
163 static void cas_start(struct ifnet *ifp);
164 static void cas_stop(struct ifnet *ifp);
165 static void cas_suspend(struct cas_softc *sc);
166 static void cas_tick(void *arg);
167 static void cas_tint(struct cas_softc *sc);
168 static void cas_tx_task(void *arg, int pending __unused);
169 static inline void cas_txkick(struct cas_softc *sc);
170 static void cas_watchdog(struct cas_softc *sc);
172 static devclass_t cas_devclass;
174 MODULE_DEPEND(cas, ether, 1, 1, 1);
175 MODULE_DEPEND(cas, miibus, 1, 1, 1);
179 #define KTR_CAS KTR_SPARE2
183 cas_attach(struct cas_softc *sc)
185 struct cas_txsoft *txs;
190 /* Set up ifnet structure. */
191 ifp = sc->sc_ifp = if_alloc(IFT_ETHER);
195 if_initname(ifp, device_get_name(sc->sc_dev),
196 device_get_unit(sc->sc_dev));
197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
198 ifp->if_start = cas_start;
199 ifp->if_ioctl = cas_ioctl;
200 ifp->if_init = cas_init;
201 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN);
202 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN;
203 IFQ_SET_READY(&ifp->if_snd);
205 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0);
206 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0);
207 /* Create local taskq. */
208 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc);
209 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp);
210 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK,
211 taskqueue_thread_enqueue, &sc->sc_tq);
212 if (sc->sc_tq == NULL) {
213 device_printf(sc->sc_dev, "could not create taskqueue\n");
217 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
218 device_get_nameunit(sc->sc_dev));
220 /* Make sure the chip is stopped. */
223 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
225 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL,
230 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
232 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag);
236 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0,
237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
238 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES,
239 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag);
243 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0,
244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
245 sizeof(struct cas_control_data), 1,
246 sizeof(struct cas_control_data), 0,
247 NULL, NULL, &sc->sc_cdmatag);
252 * Allocate the control data structures, create and load the
255 if ((error = bus_dmamem_alloc(sc->sc_cdmatag,
256 (void **)&sc->sc_control_data,
257 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
258 &sc->sc_cddmamap)) != 0) {
259 device_printf(sc->sc_dev,
260 "unable to allocate control data, error = %d\n", error);
265 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap,
266 sc->sc_control_data, sizeof(struct cas_control_data),
267 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) {
268 device_printf(sc->sc_dev,
269 "unable to load control data DMA map, error = %d\n",
275 * Initialize the transmit job descriptors.
277 STAILQ_INIT(&sc->sc_txfreeq);
278 STAILQ_INIT(&sc->sc_txdirtyq);
281 * Create the transmit buffer DMA maps.
284 for (i = 0; i < CAS_TXQUEUELEN; i++) {
285 txs = &sc->sc_txsoft[i];
286 txs->txs_mbuf = NULL;
288 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0,
289 &txs->txs_dmamap)) != 0) {
290 device_printf(sc->sc_dev,
291 "unable to create TX DMA map %d, error = %d\n",
295 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
299 * Allocate the receive buffers, create and load the DMA maps
302 for (i = 0; i < CAS_NRXDESC; i++) {
303 if ((error = bus_dmamem_alloc(sc->sc_rdmatag,
304 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK,
305 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) {
306 device_printf(sc->sc_dev,
307 "unable to allocate RX buffer %d, error = %d\n",
313 sc->sc_rxdsoft[i].rxds_paddr = 0;
314 if ((error = bus_dmamap_load(sc->sc_rdmatag,
315 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf,
316 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 ||
317 sc->sc_rxdsoft[i].rxds_paddr == 0) {
318 device_printf(sc->sc_dev,
319 "unable to load RX DMA map %d, error = %d\n",
325 if ((sc->sc_flags & CAS_SERDES) == 0) {
326 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
327 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4,
328 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
331 * Look for an external PHY.
334 v = CAS_READ_4(sc, CAS_MIF_CONF);
335 if ((v & CAS_MIF_CONF_MDI1) != 0) {
336 v |= CAS_MIF_CONF_PHY_SELECT;
337 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
338 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
339 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
340 /* Enable/unfreeze the GMII pins of Saturn. */
341 if (sc->sc_variant == CAS_SATURN) {
342 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
343 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
344 BUS_SPACE_BARRIER_READ |
345 BUS_SPACE_BARRIER_WRITE);
347 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
348 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
349 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
352 * Fall back on an internal PHY if no external PHY was found.
354 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) {
355 v &= ~CAS_MIF_CONF_PHY_SELECT;
356 CAS_WRITE_4(sc, CAS_MIF_CONF, v);
357 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
358 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
359 /* Freeze the GMII pins of Saturn for saving power. */
360 if (sc->sc_variant == CAS_SATURN) {
361 CAS_WRITE_4(sc, CAS_SATURN_PCFG,
362 CAS_SATURN_PCFG_FSI);
363 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
364 BUS_SPACE_BARRIER_READ |
365 BUS_SPACE_BARRIER_WRITE);
367 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
368 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
369 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE);
373 * Use the external PCS SERDES.
375 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
376 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE);
377 /* Enable/unfreeze the SERDES pins of Saturn. */
378 if (sc->sc_variant == CAS_SATURN) {
379 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
380 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4,
381 BUS_SPACE_BARRIER_WRITE);
383 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
384 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4,
385 BUS_SPACE_BARRIER_WRITE);
386 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
387 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
389 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp,
390 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK,
391 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE);
394 device_printf(sc->sc_dev, "attaching PHYs failed\n");
397 sc->sc_mii = device_get_softc(sc->sc_miibus);
400 * From this point forward, the attachment cannot fail. A failure
401 * before this point releases all resources that may have been
405 /* Announce FIFO sizes. */
406 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE);
407 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n",
408 CAS_RX_FIFO_SIZE / 1024, v / 16);
410 /* Attach the interface. */
411 ether_ifattach(ifp, sc->sc_enaddr);
414 * Tell the upper layer(s) we support long frames/checksum offloads.
416 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
417 ifp->if_capabilities = IFCAP_VLAN_MTU;
418 if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
419 ifp->if_capabilities |= IFCAP_HWCSUM;
420 ifp->if_hwassist = CAS_CSUM_FEATURES;
422 ifp->if_capenable = ifp->if_capabilities;
427 * Free any resources we've allocated during the failed attach
428 * attempt. Do this in reverse order and fall through.
431 for (i = 0; i < CAS_NRXDESC; i++)
432 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
433 bus_dmamap_unload(sc->sc_rdmatag,
434 sc->sc_rxdsoft[i].rxds_dmamap);
436 for (i = 0; i < CAS_NRXDESC; i++)
437 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
438 bus_dmamem_free(sc->sc_rdmatag,
439 sc->sc_rxdsoft[i].rxds_buf,
440 sc->sc_rxdsoft[i].rxds_dmamap);
442 for (i = 0; i < CAS_TXQUEUELEN; i++)
443 if (sc->sc_txsoft[i].txs_dmamap != NULL)
444 bus_dmamap_destroy(sc->sc_tdmatag,
445 sc->sc_txsoft[i].txs_dmamap);
446 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
448 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
451 bus_dma_tag_destroy(sc->sc_cdmatag);
453 bus_dma_tag_destroy(sc->sc_tdmatag);
455 bus_dma_tag_destroy(sc->sc_rdmatag);
457 bus_dma_tag_destroy(sc->sc_pdmatag);
459 taskqueue_free(sc->sc_tq);
466 cas_detach(struct cas_softc *sc)
468 struct ifnet *ifp = sc->sc_ifp;
475 callout_drain(&sc->sc_tick_ch);
476 callout_drain(&sc->sc_rx_ch);
477 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task);
478 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task);
480 taskqueue_free(sc->sc_tq);
481 device_delete_child(sc->sc_dev, sc->sc_miibus);
483 for (i = 0; i < CAS_NRXDESC; i++)
484 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL)
485 bus_dmamap_sync(sc->sc_rdmatag,
486 sc->sc_rxdsoft[i].rxds_dmamap,
487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
488 for (i = 0; i < CAS_NRXDESC; i++)
489 if (sc->sc_rxdsoft[i].rxds_paddr != 0)
490 bus_dmamap_unload(sc->sc_rdmatag,
491 sc->sc_rxdsoft[i].rxds_dmamap);
492 for (i = 0; i < CAS_NRXDESC; i++)
493 if (sc->sc_rxdsoft[i].rxds_buf != NULL)
494 bus_dmamem_free(sc->sc_rdmatag,
495 sc->sc_rxdsoft[i].rxds_buf,
496 sc->sc_rxdsoft[i].rxds_dmamap);
497 for (i = 0; i < CAS_TXQUEUELEN; i++)
498 if (sc->sc_txsoft[i].txs_dmamap != NULL)
499 bus_dmamap_destroy(sc->sc_tdmatag,
500 sc->sc_txsoft[i].txs_dmamap);
501 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
502 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap);
503 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data,
505 bus_dma_tag_destroy(sc->sc_cdmatag);
506 bus_dma_tag_destroy(sc->sc_tdmatag);
507 bus_dma_tag_destroy(sc->sc_rdmatag);
508 bus_dma_tag_destroy(sc->sc_pdmatag);
512 cas_suspend(struct cas_softc *sc)
514 struct ifnet *ifp = sc->sc_ifp;
522 cas_resume(struct cas_softc *sc)
524 struct ifnet *ifp = sc->sc_ifp;
528 * On resume all registers have to be initialized again like
531 sc->sc_flags &= ~CAS_INITED;
532 if (ifp->if_flags & IFF_UP)
538 cas_rxcksum(struct mbuf *m, uint16_t cksum)
540 struct ether_header *eh;
544 int32_t hlen, len, pktlen;
547 pktlen = m->m_pkthdr.len;
548 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
550 eh = mtod(m, struct ether_header *);
551 if (eh->ether_type != htons(ETHERTYPE_IP))
553 ip = (struct ip *)(eh + 1);
554 if (ip->ip_v != IPVERSION)
557 hlen = ip->ip_hl << 2;
558 pktlen -= sizeof(struct ether_header);
559 if (hlen < sizeof(struct ip))
561 if (ntohs(ip->ip_len) < hlen)
563 if (ntohs(ip->ip_len) != pktlen)
565 if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
566 return; /* Cannot handle fragmented packet. */
570 if (pktlen < (hlen + sizeof(struct tcphdr)))
574 if (pktlen < (hlen + sizeof(struct udphdr)))
576 uh = (struct udphdr *)((uint8_t *)ip + hlen);
578 return; /* no checksum */
585 /* checksum fixup for IP options */
586 len = hlen - sizeof(struct ip);
588 opts = (uint16_t *)(ip + 1);
589 for (; len > 0; len -= sizeof(uint16_t), opts++) {
590 temp32 = cksum - *opts;
591 temp32 = (temp32 >> 16) + (temp32 & 65535);
592 cksum = temp32 & 65535;
595 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
596 m->m_pkthdr.csum_data = cksum;
600 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
602 struct cas_softc *sc = xsc;
607 panic("%s: bad control buffer segment count", __func__);
608 sc->sc_cddma = segs[0].ds_addr;
612 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
614 struct cas_softc *sc = xsc;
619 panic("%s: bad RX buffer segment count", __func__);
620 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr;
626 struct cas_softc *sc = arg;
627 struct ifnet *ifp = sc->sc_ifp;
630 CAS_LOCK_ASSERT(sc, MA_OWNED);
633 * Unload collision and error counters.
635 ifp->if_collisions +=
636 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) +
637 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT);
638 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) +
639 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT);
640 ifp->if_collisions += v;
641 ifp->if_oerrors += v;
643 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) +
644 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) +
645 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) +
646 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL);
649 * Then clear the hardware counters.
651 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
652 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
653 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
654 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
655 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
656 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
657 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
658 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
660 mii_tick(sc->sc_mii);
662 if (sc->sc_txfree != CAS_MAXTXFREE)
667 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
671 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set)
676 for (i = CAS_TRIES; i--; DELAY(100)) {
677 reg = CAS_READ_4(sc, r);
678 if ((reg & clr) == 0 && (reg & set) == set)
685 cas_reset(struct cas_softc *sc)
689 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
691 /* Disable all interrupts in order to avoid spurious ones. */
692 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
698 * Do a full reset modulo the result of the last auto-negotiation
699 * when using the SERDES.
701 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
702 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
703 CAS_BARRIER(sc, CAS_RESET, 4,
704 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
706 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0))
707 device_printf(sc->sc_dev, "cannot reset device\n");
711 cas_stop(struct ifnet *ifp)
713 struct cas_softc *sc = ifp->if_softc;
714 struct cas_txsoft *txs;
717 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
720 callout_stop(&sc->sc_tick_ch);
721 callout_stop(&sc->sc_rx_ch);
723 /* Disable all interrupts in order to avoid spurious ones. */
724 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
730 * Release any queued transmit buffers.
732 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
733 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
734 if (txs->txs_ndescs != 0) {
735 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
736 BUS_DMASYNC_POSTWRITE);
737 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
738 if (txs->txs_mbuf != NULL) {
739 m_freem(txs->txs_mbuf);
740 txs->txs_mbuf = NULL;
743 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
747 * Mark the interface down and cancel the watchdog timer.
749 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
750 sc->sc_flags &= ~CAS_LINK;
751 sc->sc_wdog_timer = 0;
755 cas_reset_rx(struct cas_softc *sc)
759 * Resetting while DMA is in progress can cause a bus hang, so we
762 (void)cas_disable_rx(sc);
763 CAS_WRITE_4(sc, CAS_RX_CONF, 0);
764 CAS_BARRIER(sc, CAS_RX_CONF, 4,
765 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
766 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0))
767 device_printf(sc->sc_dev, "cannot disable RX DMA\n");
769 /* Finally, reset the ERX. */
770 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
771 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
772 CAS_BARRIER(sc, CAS_RESET, 4,
773 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
774 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) {
775 device_printf(sc->sc_dev, "cannot reset receiver\n");
782 cas_reset_tx(struct cas_softc *sc)
786 * Resetting while DMA is in progress can cause a bus hang, so we
789 (void)cas_disable_tx(sc);
790 CAS_WRITE_4(sc, CAS_TX_CONF, 0);
791 CAS_BARRIER(sc, CAS_TX_CONF, 4,
792 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
793 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0))
794 device_printf(sc->sc_dev, "cannot disable TX DMA\n");
796 /* Finally, reset the ETX. */
797 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
798 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0));
799 CAS_BARRIER(sc, CAS_RESET, 4,
800 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
801 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) {
802 device_printf(sc->sc_dev, "cannot reset transmitter\n");
809 cas_disable_rx(struct cas_softc *sc)
812 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
813 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN);
814 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
815 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
816 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0))
818 device_printf(sc->sc_dev, "cannot disable RX MAC\n");
823 cas_disable_tx(struct cas_softc *sc)
826 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
827 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN);
828 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4,
829 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
830 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0))
832 device_printf(sc->sc_dev, "cannot disable TX MAC\n");
837 cas_rxcompinit(struct cas_rx_comp *rxcomp)
840 rxcomp->crc_word1 = 0;
841 rxcomp->crc_word2 = 0;
843 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO));
844 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO);
848 cas_meminit(struct cas_softc *sc)
852 CAS_LOCK_ASSERT(sc, MA_OWNED);
855 * Initialize the transmit descriptor ring.
857 for (i = 0; i < CAS_NTXDESC; i++) {
858 sc->sc_txdescs[i].cd_flags = 0;
859 sc->sc_txdescs[i].cd_buf_ptr = 0;
861 sc->sc_txfree = CAS_MAXTXFREE;
866 * Initialize the receive completion ring.
868 for (i = 0; i < CAS_NRXCOMP; i++)
869 cas_rxcompinit(&sc->sc_rxcomps[i]);
873 * Initialize the first receive descriptor ring. We leave
874 * the second one zeroed as we don't actually use it.
876 for (i = 0; i < CAS_NRXDESC; i++)
877 CAS_INIT_RXDESC(sc, i, i);
880 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
884 cas_descsize(u_int sz)
889 return (CAS_DESC_32);
891 return (CAS_DESC_64);
893 return (CAS_DESC_128);
895 return (CAS_DESC_256);
897 return (CAS_DESC_512);
899 return (CAS_DESC_1K);
901 return (CAS_DESC_2K);
903 return (CAS_DESC_4K);
905 return (CAS_DESC_8K);
907 printf("%s: invalid descriptor ring size %d\n", __func__, sz);
908 return (CAS_DESC_32);
913 cas_rxcompsize(u_int sz)
918 return (CAS_RX_CONF_COMP_128);
920 return (CAS_RX_CONF_COMP_256);
922 return (CAS_RX_CONF_COMP_512);
924 return (CAS_RX_CONF_COMP_1K);
926 return (CAS_RX_CONF_COMP_2K);
928 return (CAS_RX_CONF_COMP_4K);
930 return (CAS_RX_CONF_COMP_8K);
932 return (CAS_RX_CONF_COMP_16K);
934 return (CAS_RX_CONF_COMP_32K);
936 printf("%s: invalid dcompletion ring size %d\n", __func__, sz);
937 return (CAS_RX_CONF_COMP_128);
944 struct cas_softc *sc = xsc;
952 * Initialization of interface; set up initialization block
953 * and transmit/receive descriptor rings.
956 cas_init_locked(struct cas_softc *sc)
958 struct ifnet *ifp = sc->sc_ifp;
961 CAS_LOCK_ASSERT(sc, MA_OWNED);
963 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
967 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev),
971 * Initialization sequence. The numbered steps below correspond
972 * to the sequence outlined in section 6.3.5.1 in the Ethernet
973 * Channel Engine manual (part of the PCIO manual).
974 * See also the STP2002-STQ document from Sun Microsystems.
977 /* step 1 & 2. Reset the Ethernet Channel. */
981 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev),
985 if ((sc->sc_flags & CAS_SERDES) == 0)
986 /* Re-initialize the MIF. */
989 /* step 3. Setup data structures in host memory. */
992 /* step 4. TX MAC registers & counters */
995 /* step 5. RX MAC registers & counters */
997 /* step 6 & 7. Program Ring Base Addresses. */
998 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,
999 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32));
1000 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
1001 CAS_CDTXDADDR(sc, 0) & 0xffffffff);
1003 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
1004 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32));
1005 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
1006 CAS_CDRXCADDR(sc, 0) & 0xffffffff);
1008 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
1009 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32));
1010 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
1011 CAS_CDRXDADDR(sc, 0) & 0xffffffff);
1013 if ((sc->sc_flags & CAS_REG_PLUS) != 0) {
1014 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
1015 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32));
1016 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
1017 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff);
1022 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx",
1023 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0),
1024 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma);
1027 /* step 8. Global Configuration & Interrupt Masks */
1029 /* Disable weighted round robin. */
1030 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
1033 * Enable infinite bursts for revisions without PCI issues if
1034 * applicable. Doing so greatly improves the TX performance on
1037 CAS_WRITE_4(sc, CAS_INF_BURST,
1038 #if !defined(__sparc64__)
1039 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN :
1043 /* Set up interrupts. */
1044 CAS_WRITE_4(sc, CAS_INTMASK,
1045 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
1046 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
1047 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
1048 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
1049 CAS_INTR_PCI_ERROR_INT
1051 | CAS_INTR_PCS_INT | CAS_INTR_MIF
1054 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */
1055 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
1056 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
1057 CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
1058 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR));
1060 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1061 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1062 CAS_MAC_CTRL_NON_PAUSE));
1064 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
1065 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE |
1066 CAS_MAC_CTRL_NON_PAUSE);
1069 /* Enable PCI error interrupts. */
1070 CAS_WRITE_4(sc, CAS_ERROR_MASK,
1071 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO |
1072 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO));
1074 /* Enable PCI error interrupts in BIM configuration. */
1075 CAS_WRITE_4(sc, CAS_BIM_CONF,
1076 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN);
1079 * step 9. ETX Configuration: encode receive descriptor ring size,
1080 * enable DMA and disable pre-interrupt writeback completion.
1082 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT;
1083 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
1084 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS);
1086 /* step 10. ERX Configuration */
1089 * Encode receive completion and descriptor ring sizes, set the
1092 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT;
1093 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT;
1094 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1095 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT;
1096 CAS_WRITE_4(sc, CAS_RX_CONF,
1097 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT));
1099 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */
1100 CAS_WRITE_4(sc, CAS_RX_PTHRS,
1101 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT));
1104 CAS_WRITE_4(sc, CAS_RX_BLANK,
1105 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT));
1107 /* Set RX_COMP_AFULL threshold to half of the RX completions. */
1108 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
1109 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT);
1111 /* Initialize the RX page size register as appropriate for 8k. */
1112 CAS_WRITE_4(sc, CAS_RX_PSZ,
1113 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) |
1114 (4 << CAS_RX_PSZ_MB_CNT_SHFT) |
1115 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) |
1116 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT));
1118 /* Disable RX random early detection. */
1119 CAS_WRITE_4(sc, CAS_RX_RED, 0);
1121 /* Zero the RX reassembly DMA table. */
1122 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) {
1123 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
1124 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
1125 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
1126 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
1129 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */
1130 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
1131 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
1133 /* Finally, enable RX DMA. */
1134 CAS_WRITE_4(sc, CAS_RX_CONF,
1135 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN);
1137 /* step 11. Configure Media. */
1139 /* step 12. RX_MAC Configuration Register */
1140 v = CAS_READ_4(sc, CAS_MAC_RX_CONF);
1141 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN);
1142 v |= CAS_MAC_RX_CONF_STRPFCS;
1143 sc->sc_mac_rxcfg = v;
1145 * Clear the RX filter and reprogram it. This will also set the
1146 * current RX MAC configuration and enable it.
1150 /* step 13. TX_MAC Configuration Register */
1151 v = CAS_READ_4(sc, CAS_MAC_TX_CONF);
1152 v |= CAS_MAC_TX_CONF_EN;
1153 (void)cas_disable_tx(sc);
1154 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
1156 /* step 14. Issue Transmit Pending command. */
1158 /* step 15. Give the receiver a swift kick. */
1159 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
1160 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
1161 if ((sc->sc_flags & CAS_REG_PLUS) != 0)
1162 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
1164 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1165 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1167 mii_mediachg(sc->sc_mii);
1169 /* Start the one second timer. */
1170 sc->sc_wdog_timer = 0;
1171 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc);
1175 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head)
1177 bus_dma_segment_t txsegs[CAS_NTXSEGS];
1178 struct cas_txsoft *txs;
1182 int error, nexttx, nsegs, offset, seg;
1184 CAS_LOCK_ASSERT(sc, MA_OWNED);
1186 /* Get a work queue entry. */
1187 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) {
1188 /* Ran out of descriptors. */
1193 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) {
1194 if (M_WRITABLE(*m_head) == 0) {
1195 m = m_dup(*m_head, M_DONTWAIT);
1201 offset = sizeof(struct ether_header);
1202 m = m_pullup(*m_head, offset + sizeof(struct ip));
1207 ip = (struct ip *)(mtod(m, caddr_t) + offset);
1208 offset += (ip->ip_hl << 2);
1209 cflags = (offset << CAS_TD_CKSUM_START_SHFT) |
1210 ((offset + m->m_pkthdr.csum_data) <<
1211 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN;
1215 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap,
1216 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
1217 if (error == EFBIG) {
1218 m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS);
1225 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag,
1226 txs->txs_dmamap, *m_head, txsegs, &nsegs,
1233 } else if (error != 0)
1235 /* If nsegs is wrong then the stack is corrupt. */
1236 KASSERT(nsegs <= CAS_NTXSEGS,
1237 ("%s: too many DMA segments (%d)", __func__, nsegs));
1245 * Ensure we have enough descriptors free to describe
1246 * the packet. Note, we always reserve one descriptor
1247 * at the end of the ring as a termination point, in
1248 * order to prevent wrap-around.
1250 if (nsegs > sc->sc_txfree - 1) {
1251 txs->txs_ndescs = 0;
1252 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1256 txs->txs_ndescs = nsegs;
1257 txs->txs_firstdesc = sc->sc_txnext;
1258 nexttx = txs->txs_firstdesc;
1259 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) {
1262 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)",
1263 __func__, seg, nexttx, txsegs[seg].ds_len,
1264 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr));
1266 sc->sc_txdescs[nexttx].cd_buf_ptr =
1267 htole64(txsegs[seg].ds_addr);
1268 KASSERT(txsegs[seg].ds_len <
1269 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT,
1270 ("%s: segment size too large!", __func__));
1271 sc->sc_txdescs[nexttx].cd_flags =
1272 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT);
1273 txs->txs_lastdesc = nexttx;
1276 /* Set EOF on the last descriptor. */
1278 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d",
1279 __func__, seg, nexttx);
1281 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |=
1282 htole64(CAS_TD_END_OF_FRAME);
1284 /* Lastly set SOF on the first descriptor. */
1286 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d",
1287 __func__, seg, nexttx);
1289 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) {
1291 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1292 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME);
1294 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |=
1295 htole64(cflags | CAS_TD_START_OF_FRAME);
1297 /* Sync the DMA map. */
1298 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1299 BUS_DMASYNC_PREWRITE);
1302 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d",
1303 __func__, txs->txs_firstdesc, txs->txs_lastdesc,
1306 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q);
1307 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q);
1308 txs->txs_mbuf = *m_head;
1310 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc);
1311 sc->sc_txfree -= txs->txs_ndescs;
1317 cas_init_regs(struct cas_softc *sc)
1320 const u_char *laddr = IF_LLADDR(sc->sc_ifp);
1322 CAS_LOCK_ASSERT(sc, MA_OWNED);
1324 /* These registers are not cleared on reset. */
1325 if ((sc->sc_flags & CAS_INITED) == 0) {
1327 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
1328 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
1329 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
1331 /* min frame length */
1332 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
1333 /* max frame length and max burst size */
1334 CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
1335 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) <<
1336 CAS_MAC_MAX_BF_FRM_SHFT) |
1337 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT));
1339 /* more magic values */
1340 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
1341 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
1342 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
1343 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
1345 /* random number seed */
1346 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
1347 ((laddr[5] << 8) | laddr[4]) & 0x3ff);
1349 /* secondary MAC addresses: 0:0:0:0:0:0 */
1350 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41;
1351 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3)
1352 CAS_WRITE_4(sc, i, 0);
1354 /* MAC control address: 01:80:c2:00:00:01 */
1355 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
1356 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
1357 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
1359 /* MAC filter address: 0:0:0:0:0:0 */
1360 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
1361 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
1362 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
1363 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
1364 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
1366 /* Zero the hash table. */
1367 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15;
1368 i += CAS_MAC_HASH1 - CAS_MAC_HASH0)
1369 CAS_WRITE_4(sc, i, 0);
1371 sc->sc_flags |= CAS_INITED;
1374 /* Counters need to be zeroed. */
1375 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
1376 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
1377 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
1378 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
1379 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
1380 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
1381 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
1382 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
1383 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
1384 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
1385 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
1387 /* Set XOFF PAUSE time. */
1388 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
1390 /* Set the station address. */
1391 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
1392 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
1393 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
1395 /* Enable MII outputs. */
1396 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
1400 cas_tx_task(void *arg, int pending __unused)
1404 ifp = (struct ifnet *)arg;
1409 cas_txkick(struct cas_softc *sc)
1413 * Update the TX kick register. This register has to point to the
1414 * descriptor after the last valid one and for optimum performance
1415 * should be incremented in multiples of 4 (the DMA engine fetches/
1416 * updates descriptors in batches of 4).
1419 CTR3(KTR_CAS, "%s: %s: kicking TX %d",
1420 device_get_name(sc->sc_dev), __func__, sc->sc_txnext);
1422 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1423 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
1427 cas_start(struct ifnet *ifp)
1429 struct cas_softc *sc = ifp->if_softc;
1435 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1436 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) {
1441 if (sc->sc_txfree < CAS_MAXTXFREE / 4)
1445 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d",
1446 device_get_name(sc->sc_dev), __func__, sc->sc_txfree,
1451 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) {
1452 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1455 if (cas_load_txmbuf(sc, &m) != 0) {
1458 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1459 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1462 if ((sc->sc_txnext % 4) == 0) {
1475 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d",
1476 device_get_name(sc->sc_dev), sc->sc_txnext);
1479 /* Set a watchdog timer in case the chip flakes out. */
1480 sc->sc_wdog_timer = 5;
1482 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1483 device_get_name(sc->sc_dev), __func__,
1492 cas_tint(struct cas_softc *sc)
1494 struct ifnet *ifp = sc->sc_ifp;
1495 struct cas_txsoft *txs;
1501 CAS_LOCK_ASSERT(sc, MA_OWNED);
1503 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1507 * Go through our TX list and free mbufs for those
1508 * frames that have been transmitted.
1511 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD);
1512 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) {
1514 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1515 printf(" txsoft %p transmit chain:\n", txs);
1516 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) {
1517 printf("descriptor %d: ", i);
1518 printf("cd_flags: 0x%016llx\t",
1520 sc->sc_txdescs[i].cd_flags));
1521 printf("cd_buf_ptr: 0x%016llx\n",
1523 sc->sc_txdescs[i].cd_buf_ptr));
1524 if (i == txs->txs_lastdesc)
1531 * In theory, we could harvest some descriptors before
1532 * the ring is empty, but that's a bit complicated.
1534 * CAS_TX_COMPn points to the last descriptor
1537 txlast = CAS_READ_4(sc, CAS_TX_COMP3);
1539 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, "
1540 "txs->txs_lastdesc = %d, txlast = %d",
1541 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast);
1543 if (txs->txs_firstdesc <= txs->txs_lastdesc) {
1544 if ((txlast >= txs->txs_firstdesc) &&
1545 (txlast <= txs->txs_lastdesc))
1548 /* Ick -- this command wraps. */
1549 if ((txlast >= txs->txs_firstdesc) ||
1550 (txlast <= txs->txs_lastdesc))
1555 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__);
1557 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q);
1559 sc->sc_txfree += txs->txs_ndescs;
1561 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap,
1562 BUS_DMASYNC_POSTWRITE);
1563 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap);
1564 if (txs->txs_mbuf != NULL) {
1565 m_freem(txs->txs_mbuf);
1566 txs->txs_mbuf = NULL;
1569 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
1576 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx "
1578 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2),
1579 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) |
1580 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO),
1581 CAS_READ_4(sc, CAS_TX_COMP3));
1585 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */
1586 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1587 if (STAILQ_EMPTY(&sc->sc_txdirtyq))
1588 sc->sc_wdog_timer = 0;
1592 CTR3(KTR_CAS, "%s: %s: watchdog %d",
1593 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer);
1598 cas_rint_timeout(void *arg)
1600 struct cas_softc *sc = arg;
1602 CAS_LOCK_ASSERT(sc, MA_OWNED);
1608 cas_rint(struct cas_softc *sc)
1610 struct cas_rxdsoft *rxds, *rxds2;
1611 struct ifnet *ifp = sc->sc_ifp;
1612 struct mbuf *m, *m2;
1613 uint64_t word1, word2, word3, word4;
1615 u_int idx, idx2, len, off, skip;
1617 CAS_LOCK_ASSERT(sc, MA_OWNED);
1619 callout_stop(&sc->sc_rx_ch);
1622 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__);
1625 #define PRINTWORD(n, delimiter) \
1626 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter)
1628 #define SKIPASSERT(n) \
1629 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \
1630 ("%s: word ## n not 0", __func__))
1632 #define WORDTOH(n) \
1633 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n)
1636 * Read the completion head register once. This limits
1637 * how long the following loop can execute.
1639 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD);
1641 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1642 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead);
1645 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1646 for (; sc->sc_rxcptr != rxhead;
1647 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) {
1663 if ((ifp->if_flags & IFF_DEBUG) != 0) {
1664 printf(" completion %d: ", sc->sc_rxcptr);
1672 if (__predict_false(
1673 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW ||
1674 (word4 & CAS_RC4_ZERO) != 0)) {
1676 * The descriptor is still marked as owned, although
1677 * it is supposed to have completed. This has been
1678 * observed on some machines. Just exiting here
1679 * might leave the packet sitting around until another
1680 * one arrives to trigger a new interrupt, which is
1681 * generally undesirable, so set up a timeout.
1683 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS,
1684 cas_rint_timeout, sc);
1688 if (__predict_false(
1689 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) {
1691 device_printf(sc->sc_dev,
1692 "receive error: CRC error\n");
1696 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1697 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1698 ("%s: data and header present", __func__));
1699 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 ||
1700 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0,
1701 ("%s: split and header present", __func__));
1702 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 ||
1703 (word1 & CAS_RC1_RELEASE_HDR) == 0,
1704 ("%s: data present but header release", __func__));
1705 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 ||
1706 (word1 & CAS_RC1_RELEASE_DATA) == 0,
1707 ("%s: header present but data release", __func__));
1709 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) {
1710 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX);
1711 off = CAS_GET(word2, CAS_RC2_HDR_OFF);
1713 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d",
1714 __func__, idx, off, len);
1716 rxds = &sc->sc_rxdsoft[idx];
1717 MGETHDR(m, M_DONTWAIT, MT_DATA);
1719 refcount_acquire(&rxds->rxds_refcount);
1720 bus_dmamap_sync(sc->sc_rdmatag,
1721 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1722 #if __FreeBSD_version < 800016
1723 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1724 off * 256 + ETHER_ALIGN, len, cas_free,
1725 rxds, M_RDONLY, EXT_NET_DRV);
1727 MEXTADD(m, (caddr_t)rxds->rxds_buf +
1728 off * 256 + ETHER_ALIGN, len, cas_free,
1729 sc, (void *)(uintptr_t)idx,
1730 M_RDONLY, EXT_NET_DRV);
1732 if ((m->m_flags & M_EXT) == 0) {
1738 m->m_pkthdr.rcvif = ifp;
1739 m->m_pkthdr.len = m->m_len = len;
1741 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1742 cas_rxcksum(m, CAS_GET(word4,
1746 (*ifp->if_input)(ifp, m);
1751 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 &&
1752 refcount_release(&rxds->rxds_refcount) != 0)
1753 cas_add_rxdesc(sc, idx);
1754 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) {
1755 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX);
1756 off = CAS_GET(word1, CAS_RC1_DATA_OFF);
1758 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d",
1759 __func__, idx, off, len);
1761 rxds = &sc->sc_rxdsoft[idx];
1762 MGETHDR(m, M_DONTWAIT, MT_DATA);
1764 refcount_acquire(&rxds->rxds_refcount);
1766 m->m_len = min(CAS_PAGE_SIZE - off, len);
1767 bus_dmamap_sync(sc->sc_rdmatag,
1768 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD);
1769 #if __FreeBSD_version < 800016
1770 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1771 m->m_len, cas_free, rxds, M_RDONLY,
1774 MEXTADD(m, (caddr_t)rxds->rxds_buf + off,
1775 m->m_len, cas_free, sc,
1776 (void *)(uintptr_t)idx, M_RDONLY,
1779 if ((m->m_flags & M_EXT) == 0) {
1787 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) {
1788 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0,
1789 ("%s: split but no release next",
1792 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX);
1794 CTR2(KTR_CAS, "%s: split at idx %d",
1797 rxds2 = &sc->sc_rxdsoft[idx2];
1799 MGET(m2, M_DONTWAIT, MT_DATA);
1802 &rxds2->rxds_refcount);
1803 m2->m_len = len - m->m_len;
1807 BUS_DMASYNC_POSTREAD);
1808 #if __FreeBSD_version < 800016
1810 (caddr_t)rxds2->rxds_buf,
1811 m2->m_len, cas_free,
1816 (caddr_t)rxds2->rxds_buf,
1817 m2->m_len, cas_free, sc,
1818 (void *)(uintptr_t)idx2,
1819 M_RDONLY, EXT_NET_DRV);
1821 if ((m2->m_flags & M_EXT) ==
1830 else if (m != NULL) {
1836 m->m_pkthdr.rcvif = ifp;
1837 m->m_pkthdr.len = len;
1839 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1840 cas_rxcksum(m, CAS_GET(word4,
1844 (*ifp->if_input)(ifp, m);
1849 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 &&
1850 refcount_release(&rxds->rxds_refcount) != 0)
1851 cas_add_rxdesc(sc, idx);
1852 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 &&
1853 refcount_release(&rxds2->rxds_refcount) != 0)
1854 cas_add_rxdesc(sc, idx2);
1857 skip = CAS_GET(word1, CAS_RC1_SKIP);
1860 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]);
1861 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1864 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1865 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
1872 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d",
1873 __func__, sc->sc_rxcptr, sc->sc_rxdptr,
1874 CAS_READ_4(sc, CAS_RX_COMP_HEAD));
1879 cas_free(void *arg1, void *arg2)
1881 struct cas_rxdsoft *rxds;
1882 struct cas_softc *sc;
1885 #if __FreeBSD_version < 800016
1888 idx = rxds->rxds_idx;
1891 idx = (uintptr_t)arg2;
1892 rxds = &sc->sc_rxdsoft[idx];
1894 if (refcount_release(&rxds->rxds_refcount) == 0)
1898 * NB: this function can be called via m_freem(9) within
1901 if ((locked = CAS_LOCK_OWNED(sc)) == 0)
1903 cas_add_rxdesc(sc, idx);
1909 cas_add_rxdesc(struct cas_softc *sc, u_int idx)
1912 CAS_LOCK_ASSERT(sc, MA_OWNED);
1914 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap,
1915 BUS_DMASYNC_PREREAD);
1916 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx);
1917 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr);
1920 * Update the RX kick register. This register has to point to the
1921 * descriptor after the last valid one (before the current batch)
1922 * and for optimum performance should be incremented in multiples
1923 * of 4 (the DMA engine fetches/updates descriptors in batches of 4).
1925 if ((sc->sc_rxdptr % 4) == 0) {
1926 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1927 CAS_WRITE_4(sc, CAS_RX_KICK,
1928 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK);
1933 cas_eint(struct cas_softc *sc, u_int status)
1935 struct ifnet *ifp = sc->sc_ifp;
1937 CAS_LOCK_ASSERT(sc, MA_OWNED);
1941 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status);
1942 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) {
1943 status = CAS_READ_4(sc, CAS_ERROR_STATUS);
1944 printf(", PCI bus error 0x%x", status);
1945 if ((status & CAS_ERROR_OTHER) != 0) {
1946 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
1947 printf(", PCI status 0x%x", status);
1948 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
1953 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1954 cas_init_locked(sc);
1955 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1956 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
1962 struct cas_softc *sc = v;
1964 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) &
1965 CAS_INTR_SUMMARY) == 0))
1966 return (FILTER_STRAY);
1968 /* Disable interrupts. */
1969 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
1970 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
1972 return (FILTER_HANDLED);
1976 cas_intr_task(void *arg, int pending __unused)
1978 struct cas_softc *sc = arg;
1979 struct ifnet *ifp = sc->sc_ifp;
1980 uint32_t status, status2;
1982 CAS_LOCK_ASSERT(sc, MA_NOTOWNED);
1984 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1987 status = CAS_READ_4(sc, CAS_STATUS);
1988 if (__predict_false((status & CAS_INTR_SUMMARY) == 0))
1993 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x",
1994 device_get_name(sc->sc_dev), __func__,
1995 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status);
1998 * PCS interrupts must be cleared, otherwise no traffic is passed!
2000 if ((status & CAS_INTR_PCS_INT) != 0) {
2002 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) |
2003 CAS_READ_4(sc, CAS_PCS_INTR_STATUS);
2004 if ((status2 & CAS_PCS_INTR_LINK) != 0)
2005 device_printf(sc->sc_dev,
2006 "%s: PCS link status changed\n", __func__);
2008 if ((status & CAS_MAC_CTRL_STATUS) != 0) {
2009 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS);
2010 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2011 device_printf(sc->sc_dev,
2012 "%s: PAUSE received (PAUSE time %d slots)\n",
2014 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >>
2015 CAS_MAC_CTRL_STATUS_PT_SHFT);
2016 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0)
2017 device_printf(sc->sc_dev,
2018 "%s: transited to PAUSE state\n", __func__);
2019 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0)
2020 device_printf(sc->sc_dev,
2021 "%s: transited to non-PAUSE state\n", __func__);
2023 if ((status & CAS_INTR_MIF) != 0)
2024 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__);
2027 if (__predict_false((status &
2028 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR |
2029 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) {
2030 cas_eint(sc, status);
2035 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) {
2036 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS);
2038 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0)
2040 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0)
2041 device_printf(sc->sc_dev,
2042 "MAC TX fault, status %x\n", status2);
2045 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) {
2046 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS);
2047 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0)
2049 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0)
2050 device_printf(sc->sc_dev,
2051 "MAC RX fault, status %x\n", status2);
2055 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2056 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) {
2059 if (__predict_false((status &
2060 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL |
2061 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0))
2062 device_printf(sc->sc_dev,
2063 "RX fault, status %x\n", status);
2068 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0)
2071 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2074 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2075 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2078 status = CAS_READ_4(sc, CAS_STATUS_ALIAS);
2079 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) {
2080 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task);
2085 /* Re-enable interrupts. */
2086 CAS_WRITE_4(sc, CAS_INTMASK,
2087 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR |
2088 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR |
2089 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY |
2090 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH |
2091 CAS_INTR_PCI_ERROR_INT
2093 | CAS_INTR_PCS_INT | CAS_INTR_MIF
2099 cas_watchdog(struct cas_softc *sc)
2101 struct ifnet *ifp = sc->sc_ifp;
2103 CAS_LOCK_ASSERT(sc, MA_OWNED);
2107 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x",
2108 __func__, CAS_READ_4(sc, CAS_RX_CONF),
2109 CAS_READ_4(sc, CAS_MAC_RX_STATUS),
2110 CAS_READ_4(sc, CAS_MAC_RX_CONF));
2112 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x",
2113 __func__, CAS_READ_4(sc, CAS_TX_CONF),
2114 CAS_READ_4(sc, CAS_MAC_TX_STATUS),
2115 CAS_READ_4(sc, CAS_MAC_TX_CONF));
2118 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0)
2121 if ((sc->sc_flags & CAS_LINK) != 0)
2122 device_printf(sc->sc_dev, "device timeout\n");
2123 else if (bootverbose)
2124 device_printf(sc->sc_dev, "device timeout (no link)\n");
2127 /* Try to get more packets going. */
2128 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2129 cas_init_locked(sc);
2130 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2131 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task);
2135 cas_mifinit(struct cas_softc *sc)
2138 /* Configure the MIF in frame mode. */
2139 CAS_WRITE_4(sc, CAS_MIF_CONF,
2140 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE);
2141 CAS_BARRIER(sc, CAS_MIF_CONF, 4,
2142 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2148 * The MII interface supports at least three different operating modes:
2150 * Bitbang mode is implemented using data, clock and output enable registers.
2152 * Frame mode is implemented by loading a complete frame into the frame
2153 * register and polling the valid bit for completion.
2155 * Polling mode uses the frame register but completion is indicated by
2160 cas_mii_readreg(device_t dev, int phy, int reg)
2162 struct cas_softc *sc;
2166 #ifdef CAS_DEBUG_PHY
2167 printf("%s: phy %d reg %d\n", __func__, phy, reg);
2170 sc = device_get_softc(dev);
2171 if ((sc->sc_flags & CAS_SERDES) != 0) {
2177 reg = CAS_PCS_STATUS;
2186 reg = CAS_PCS_ANLPAR;
2189 return (EXTSR_1000XFDX | EXTSR_1000XHDX);
2191 device_printf(sc->sc_dev,
2192 "%s: unhandled register %d\n", __func__, reg);
2195 return (CAS_READ_4(sc, reg));
2198 /* Construct the frame command. */
2199 v = CAS_MIF_FRAME_READ |
2200 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2201 (reg << CAS_MIF_FRAME_REG_SHFT);
2203 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2204 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2205 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2206 for (n = 0; n < 100; n++) {
2208 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2209 if (v & CAS_MIF_FRAME_TA_LSB)
2210 return (v & CAS_MIF_FRAME_DATA);
2213 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2218 cas_mii_writereg(device_t dev, int phy, int reg, int val)
2220 struct cas_softc *sc;
2224 #ifdef CAS_DEBUG_PHY
2225 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__);
2228 sc = device_get_softc(dev);
2229 if ((sc->sc_flags & CAS_SERDES) != 0) {
2232 reg = CAS_PCS_STATUS;
2236 if ((val & CAS_PCS_CTRL_RESET) == 0)
2238 CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
2239 CAS_BARRIER(sc, CAS_PCS_CTRL, 4,
2240 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2241 if (!cas_bitwait(sc, CAS_PCS_CTRL,
2242 CAS_PCS_CTRL_RESET, 0))
2243 device_printf(sc->sc_dev,
2244 "cannot reset PCS\n");
2247 CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
2248 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2249 BUS_SPACE_BARRIER_WRITE);
2250 CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
2251 CAS_BARRIER(sc, CAS_PCS_ANAR, 4,
2252 BUS_SPACE_BARRIER_WRITE);
2253 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
2254 CAS_PCS_SERDES_CTRL_ESD);
2255 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2256 BUS_SPACE_BARRIER_WRITE);
2257 CAS_WRITE_4(sc, CAS_PCS_CONF,
2259 CAS_BARRIER(sc, CAS_PCS_CONF, 4,
2260 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2263 reg = CAS_PCS_ANLPAR;
2266 device_printf(sc->sc_dev,
2267 "%s: unhandled register %d\n", __func__, reg);
2270 CAS_WRITE_4(sc, reg, val);
2271 CAS_BARRIER(sc, reg, 4,
2272 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2276 /* Construct the frame command. */
2277 v = CAS_MIF_FRAME_WRITE |
2278 (phy << CAS_MIF_FRAME_PHY_SHFT) |
2279 (reg << CAS_MIF_FRAME_REG_SHFT) |
2280 (val & CAS_MIF_FRAME_DATA);
2282 CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
2283 CAS_BARRIER(sc, CAS_MIF_FRAME, 4,
2284 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2285 for (n = 0; n < 100; n++) {
2287 v = CAS_READ_4(sc, CAS_MIF_FRAME);
2288 if (v & CAS_MIF_FRAME_TA_LSB)
2292 device_printf(sc->sc_dev, "%s: timed out\n", __func__);
2297 cas_mii_statchg(device_t dev)
2299 struct cas_softc *sc;
2302 uint32_t rxcfg, txcfg, v;
2304 sc = device_get_softc(dev);
2307 CAS_LOCK_ASSERT(sc, MA_OWNED);
2310 if ((ifp->if_flags & IFF_DEBUG) != 0)
2311 device_printf(sc->sc_dev, "%s: status changen", __func__);
2314 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 &&
2315 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE)
2316 sc->sc_flags |= CAS_LINK;
2318 sc->sc_flags &= ~CAS_LINK;
2320 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) {
2332 * The configuration done here corresponds to the steps F) and
2333 * G) and as far as enabling of RX and TX MAC goes also step H)
2334 * of the initialization sequence outlined in section 11.2.1 of
2335 * the Cassini+ ASIC Specification.
2338 rxcfg = sc->sc_mac_rxcfg;
2339 rxcfg &= ~CAS_MAC_RX_CONF_CARR;
2340 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU |
2341 CAS_MAC_TX_CONF_NGUL;
2342 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2343 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS;
2344 else if (gigabit != 0) {
2345 rxcfg |= CAS_MAC_RX_CONF_CARR;
2346 txcfg |= CAS_MAC_TX_CONF_CARR;
2348 (void)cas_disable_tx(sc);
2349 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
2350 (void)cas_disable_rx(sc);
2351 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
2353 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) &
2354 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP);
2355 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2356 IFM_ETH_RXPAUSE) != 0)
2357 v |= CAS_MAC_CTRL_CONF_RXP;
2358 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
2359 IFM_ETH_TXPAUSE) != 0)
2360 v |= CAS_MAC_CTRL_CONF_TXP;
2361 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
2364 * All supported chips have a bug causing incorrect checksum
2365 * to be calculated when letting them strip the FCS in half-
2366 * duplex mode. In theory we could disable FCS stripping and
2367 * manually adjust the checksum accordingly. It seems to make
2368 * more sense to optimze for the common case and just disable
2369 * hardware checksumming in half-duplex mode though.
2371 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) {
2372 ifp->if_capenable &= ~IFCAP_HWCSUM;
2373 ifp->if_hwassist = 0;
2374 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) {
2375 ifp->if_capenable = ifp->if_capabilities;
2376 ifp->if_hwassist = CAS_CSUM_FEATURES;
2379 if (sc->sc_variant == CAS_SATURN) {
2380 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2381 /* silicon bug workaround */
2382 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
2384 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
2387 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 &&
2389 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2390 CAS_MAC_SLOT_TIME_CARR);
2392 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
2393 CAS_MAC_SLOT_TIME_NORM);
2395 /* XIF Configuration */
2396 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED;
2397 if ((sc->sc_flags & CAS_SERDES) == 0) {
2398 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0)
2399 v |= CAS_MAC_XIF_CONF_NOECHO;
2400 v |= CAS_MAC_XIF_CONF_BUF_OE;
2403 v |= CAS_MAC_XIF_CONF_GMII;
2404 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
2405 v |= CAS_MAC_XIF_CONF_FDXLED;
2406 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
2408 sc->sc_mac_rxcfg = rxcfg;
2409 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2410 (sc->sc_flags & CAS_LINK) != 0) {
2411 CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
2412 txcfg | CAS_MAC_TX_CONF_EN);
2413 CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
2414 rxcfg | CAS_MAC_RX_CONF_EN);
2419 cas_mediachange(struct ifnet *ifp)
2421 struct cas_softc *sc = ifp->if_softc;
2424 /* XXX add support for serial media. */
2427 error = mii_mediachg(sc->sc_mii);
2433 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
2435 struct cas_softc *sc = ifp->if_softc;
2438 if ((ifp->if_flags & IFF_UP) == 0) {
2443 mii_pollstat(sc->sc_mii);
2444 ifmr->ifm_active = sc->sc_mii->mii_media_active;
2445 ifmr->ifm_status = sc->sc_mii->mii_media_status;
2450 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
2452 struct cas_softc *sc = ifp->if_softc;
2453 struct ifreq *ifr = (struct ifreq *)data;
2460 if ((ifp->if_flags & IFF_UP) != 0) {
2461 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
2462 ((ifp->if_flags ^ sc->sc_ifflags) &
2463 (IFF_ALLMULTI | IFF_PROMISC)) != 0)
2466 cas_init_locked(sc);
2467 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2469 sc->sc_ifflags = ifp->if_flags;
2474 if ((sc->sc_flags & CAS_NO_CSUM) != 0) {
2479 ifp->if_capenable = ifr->ifr_reqcap;
2480 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2481 ifp->if_hwassist = CAS_CSUM_FEATURES;
2483 ifp->if_hwassist = 0;
2489 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2494 if ((ifr->ifr_mtu < ETHERMIN) ||
2495 (ifr->ifr_mtu > ETHERMTU_JUMBO))
2498 ifp->if_mtu = ifr->ifr_mtu;
2502 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd);
2505 error = ether_ioctl(ifp, cmd, data);
2513 cas_setladrf(struct cas_softc *sc)
2515 struct ifnet *ifp = sc->sc_ifp;
2516 struct ifmultiaddr *inm;
2521 CAS_LOCK_ASSERT(sc, MA_OWNED);
2524 * Turn off the RX MAC and the hash filter as required by the Sun
2525 * Cassini programming restrictions.
2527 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER |
2528 CAS_MAC_RX_CONF_EN);
2529 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
2530 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4,
2531 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
2532 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER |
2533 CAS_MAC_RX_CONF_EN, 0))
2534 device_printf(sc->sc_dev,
2535 "cannot disable RX MAC or hash filter\n");
2537 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP);
2538 if ((ifp->if_flags & IFF_PROMISC) != 0) {
2539 v |= CAS_MAC_RX_CONF_PROMISC;
2542 if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
2543 v |= CAS_MAC_RX_CONF_PGRP;
2548 * Set up multicast address filter by passing all multicast
2549 * addresses through a crc generator, and then using the high
2550 * order 8 bits as an index into the 256 bit logical address
2551 * filter. The high order 4 bits selects the word, while the
2552 * other 4 bits select the bit within the word (where bit 0
2556 /* Clear the hash table. */
2557 memset(hash, 0, sizeof(hash));
2559 if_maddr_rlock(ifp);
2560 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) {
2561 if (inm->ifma_addr->sa_family != AF_LINK)
2563 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2564 inm->ifma_addr), ETHER_ADDR_LEN);
2566 /* We just want the 8 most significant bits. */
2569 /* Set the corresponding bit in the filter. */
2570 hash[crc >> 4] |= 1 << (15 - (crc & 15));
2572 if_maddr_runlock(ifp);
2574 v |= CAS_MAC_RX_CONF_HFILTER;
2576 /* Now load the hash table into the chip (if we are using it). */
2577 for (i = 0; i < 16; i++)
2579 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0),
2583 sc->sc_mac_rxcfg = v;
2584 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
2587 static int cas_pci_attach(device_t dev);
2588 static int cas_pci_detach(device_t dev);
2589 static int cas_pci_probe(device_t dev);
2590 static int cas_pci_resume(device_t dev);
2591 static int cas_pci_suspend(device_t dev);
2593 static device_method_t cas_pci_methods[] = {
2594 /* Device interface */
2595 DEVMETHOD(device_probe, cas_pci_probe),
2596 DEVMETHOD(device_attach, cas_pci_attach),
2597 DEVMETHOD(device_detach, cas_pci_detach),
2598 DEVMETHOD(device_suspend, cas_pci_suspend),
2599 DEVMETHOD(device_resume, cas_pci_resume),
2600 /* Use the suspend handler here, it is all that is required. */
2601 DEVMETHOD(device_shutdown, cas_pci_suspend),
2604 DEVMETHOD(miibus_readreg, cas_mii_readreg),
2605 DEVMETHOD(miibus_writereg, cas_mii_writereg),
2606 DEVMETHOD(miibus_statchg, cas_mii_statchg),
2611 static driver_t cas_pci_driver = {
2614 sizeof(struct cas_softc)
2617 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0);
2618 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0);
2619 MODULE_DEPEND(cas, pci, 1, 1, 1);
2621 static const struct cas_pci_dev {
2625 const char *cpd_desc;
2626 } cas_pci_devlist[] = {
2627 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" },
2628 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" },
2629 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" },
2634 cas_pci_probe(device_t dev)
2638 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2639 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2640 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2641 device_set_desc(dev, cas_pci_devlist[i].cpd_desc);
2642 return (BUS_PROBE_DEFAULT);
2649 static struct resource_spec cas_pci_res_spec[] = {
2650 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */
2651 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */
2655 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address"
2656 #define CAS_PHY_INTERFACE "phy-interface"
2657 #define CAS_PHY_TYPE "phy-type"
2658 #define CAS_PHY_TYPE_PCS "pcs"
2661 cas_pci_attach(device_t dev)
2663 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)];
2664 struct cas_softc *sc;
2666 #if !(defined(__powerpc__) || defined(__sparc64__))
2667 u_char enaddr[4][ETHER_ADDR_LEN];
2668 u_int j, k, lma, pcs[4], phy;
2671 sc = device_get_softc(dev);
2672 sc->sc_variant = CAS_UNKNOWN;
2673 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) {
2674 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid &&
2675 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) {
2676 sc->sc_variant = cas_pci_devlist[i].cpd_variant;
2680 if (sc->sc_variant == CAS_UNKNOWN) {
2681 device_printf(dev, "unknown adaptor\n");
2685 pci_enable_busmaster(dev);
2688 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02)
2689 /* Hardware checksumming may hang TX. */
2690 sc->sc_flags |= CAS_NO_CSUM;
2691 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN)
2692 sc->sc_flags |= CAS_REG_PLUS;
2693 if (sc->sc_variant == CAS_CAS ||
2694 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11))
2695 sc->sc_flags |= CAS_TABORT;
2697 device_printf(dev, "flags=0x%x\n", sc->sc_flags);
2699 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) {
2700 device_printf(dev, "failed to allocate resources\n");
2701 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2705 CAS_LOCK_INIT(sc, device_get_nameunit(dev));
2707 #if defined(__powerpc__) || defined(__sparc64__)
2708 OF_getetheraddr(dev, sc->sc_enaddr);
2709 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf,
2710 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev),
2711 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) {
2712 buf[sizeof(buf) - 1] = '\0';
2713 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2714 sc->sc_flags |= CAS_SERDES;
2718 * Dig out VPD (vital product data) and read the MAC address as well
2719 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI
2720 * FCode) and can't be accessed via the PCI capability pointer.
2721 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described
2722 * in the free US Patent 7149820.
2725 #define PCI_ROMHDR_SIZE 0x1c
2726 #define PCI_ROMHDR_SIG 0x00
2727 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */
2728 #define PCI_ROMHDR_PTR_DATA 0x18
2729 #define PCI_ROM_SIZE 0x18
2730 #define PCI_ROM_SIG 0x00
2731 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */
2733 #define PCI_ROM_VENDOR 0x04
2734 #define PCI_ROM_DEVICE 0x06
2735 #define PCI_ROM_PTR_VPD 0x08
2736 #define PCI_VPDRES_BYTE0 0x00
2737 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80)
2738 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f)
2739 #define PCI_VPDRES_LARGE_LEN_LSB 0x01
2740 #define PCI_VPDRES_LARGE_LEN_MSB 0x02
2741 #define PCI_VPDRES_LARGE_SIZE 0x03
2742 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */
2743 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */
2744 #define PCI_VPD_KEY0 0x00
2745 #define PCI_VPD_KEY1 0x01
2746 #define PCI_VPD_LEN 0x02
2747 #define PCI_VPD_SIZE 0x03
2749 #define CAS_ROM_READ_1(sc, offs) \
2750 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs))
2751 #define CAS_ROM_READ_2(sc, offs) \
2752 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs))
2753 #define CAS_ROM_READ_4(sc, offs) \
2754 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs))
2757 memset(enaddr, 0, sizeof(enaddr));
2758 memset(pcs, 0, sizeof(pcs));
2760 /* Enable PCI Expansion ROM access. */
2761 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
2762 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM);
2764 /* Read PCI Expansion ROM header. */
2765 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC ||
2766 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) <
2768 device_printf(dev, "unexpected PCI Expansion ROM header\n");
2772 /* Read PCI Expansion ROM data. */
2773 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC ||
2774 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) ||
2775 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) ||
2776 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) <
2778 device_printf(dev, "unexpected PCI Expansion ROM data\n");
2784 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc,
2785 j + PCI_VPDRES_BYTE0)) == 0) {
2786 device_printf(dev, "no large PCI VPD\n");
2790 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) |
2791 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB);
2792 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc,
2793 j + PCI_VPDRES_BYTE0))) {
2794 case PCI_VPDRES_TYPE_ID_STRING:
2795 /* Skip identifier string. */
2796 j += PCI_VPDRES_LARGE_SIZE + i;
2798 case PCI_VPDRES_TYPE_VPD:
2799 for (j += PCI_VPDRES_LARGE_SIZE; i > 0;
2800 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN),
2801 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) {
2802 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z')
2803 /* no Enhanced VPD */
2805 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I')
2806 /* no instance property */
2808 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') {
2810 if (CAS_ROM_READ_1(sc,
2811 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN)
2813 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2814 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2816 buf[sizeof(buf) - 1] = '\0';
2817 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0)
2819 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2820 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2821 5 + sizeof(CAS_LOCAL_MAC_ADDRESS),
2822 enaddr[lma], sizeof(enaddr[lma]));
2824 if (lma == 4 && phy == 4)
2826 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) ==
2829 if (CAS_ROM_READ_1(sc,
2830 j + PCI_VPD_SIZE + 4) !=
2831 sizeof(CAS_PHY_TYPE_PCS))
2833 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2834 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5,
2836 buf[sizeof(buf) - 1] = '\0';
2837 if (strcmp(buf, CAS_PHY_INTERFACE) == 0)
2838 k = sizeof(CAS_PHY_INTERFACE);
2839 else if (strcmp(buf, CAS_PHY_TYPE) == 0)
2840 k = sizeof(CAS_PHY_TYPE);
2843 bus_read_region_1(sc->sc_res[CAS_RES_MEM],
2844 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE +
2845 5 + k, buf, sizeof(buf));
2846 buf[sizeof(buf) - 1] = '\0';
2847 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0)
2850 if (lma == 4 && phy == 4)
2856 device_printf(dev, "unexpected PCI VPD\n");
2861 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);
2864 device_printf(dev, "could not determine Ethernet address\n");
2868 if (lma > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr))
2869 i = pci_get_slot(dev);
2870 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN);
2873 device_printf(dev, "could not determine PHY type\n");
2877 if (phy > 1 && pci_get_slot(dev) < sizeof(pcs) / sizeof(*pcs))
2878 i = pci_get_slot(dev);
2880 sc->sc_flags |= CAS_SERDES;
2883 if (cas_attach(sc) != 0) {
2884 device_printf(dev, "could not be attached\n");
2888 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET |
2889 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) {
2890 device_printf(dev, "failed to set up interrupt\n");
2897 CAS_LOCK_DESTROY(sc);
2898 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2903 cas_pci_detach(device_t dev)
2905 struct cas_softc *sc;
2907 sc = device_get_softc(dev);
2908 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih);
2910 CAS_LOCK_DESTROY(sc);
2911 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res);
2916 cas_pci_suspend(device_t dev)
2919 cas_suspend(device_get_softc(dev));
2924 cas_pci_resume(device_t dev)
2927 cas_resume(device_get_softc(dev));