2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (C) 2009-2011 Semihalf.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * CESA SRAM Memory Map:
32 * +------------------------+ <= sc->sc_sram_base_va + CESA_SRAM_SIZE
36 * +------------------------+ <= sc->sc_sram_base_va + CESA_DATA(0)
37 * | struct cesa_sa_data |
38 * +------------------------+
39 * | struct cesa_sa_hdesc |
40 * +------------------------+ <= sc->sc_sram_base_va
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
46 #include <sys/param.h>
47 #include <sys/systm.h>
49 #include <sys/endian.h>
50 #include <sys/kernel.h>
53 #include <sys/module.h>
54 #include <sys/mutex.h>
57 #include <machine/bus.h>
58 #include <machine/intr.h>
59 #include <machine/resource.h>
60 #include <machine/fdt.h>
62 #include <dev/fdt/simplebus.h>
63 #include <dev/fdt/fdt_common.h>
64 #include <dev/ofw/ofw_bus.h>
65 #include <dev/ofw/ofw_bus_subr.h>
68 #include <crypto/sha1.h>
69 #include <crypto/sha2/sha256.h>
70 #include <crypto/rijndael/rijndael.h>
71 #include <opencrypto/cryptodev.h>
72 #include "cryptodev_if.h"
74 #include <arm/mv/mvreg.h>
75 #include <arm/mv/mvvar.h>
78 static int cesa_probe(device_t);
79 static int cesa_attach(device_t);
80 static int cesa_attach_late(device_t);
81 static int cesa_detach(device_t);
82 static void cesa_intr(void *);
83 static int cesa_newsession(device_t, u_int32_t *, struct cryptoini *);
84 static int cesa_freesession(device_t, u_int64_t);
85 static int cesa_process(device_t, struct cryptop *, int);
87 static struct resource_spec cesa_res_spec[] = {
88 { SYS_RES_MEMORY, 0, RF_ACTIVE },
89 { SYS_RES_MEMORY, 1, RF_ACTIVE },
90 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
94 static device_method_t cesa_methods[] = {
95 /* Device interface */
96 DEVMETHOD(device_probe, cesa_probe),
97 DEVMETHOD(device_attach, cesa_attach),
98 DEVMETHOD(device_detach, cesa_detach),
100 /* Crypto device methods */
101 DEVMETHOD(cryptodev_newsession, cesa_newsession),
102 DEVMETHOD(cryptodev_freesession,cesa_freesession),
103 DEVMETHOD(cryptodev_process, cesa_process),
108 static driver_t cesa_driver = {
111 sizeof (struct cesa_softc)
113 static devclass_t cesa_devclass;
115 DRIVER_MODULE(cesa, simplebus, cesa_driver, cesa_devclass, 0, 0);
116 MODULE_DEPEND(cesa, crypto, 1, 1, 1);
119 cesa_dump_cshd(struct cesa_softc *sc, struct cesa_sa_hdesc *cshd)
125 device_printf(dev, "CESA SA Hardware Descriptor:\n");
126 device_printf(dev, "\t\tconfig: 0x%08X\n", cshd->cshd_config);
127 device_printf(dev, "\t\te_src: 0x%08X\n", cshd->cshd_enc_src);
128 device_printf(dev, "\t\te_dst: 0x%08X\n", cshd->cshd_enc_dst);
129 device_printf(dev, "\t\te_dlen: 0x%08X\n", cshd->cshd_enc_dlen);
130 device_printf(dev, "\t\te_key: 0x%08X\n", cshd->cshd_enc_key);
131 device_printf(dev, "\t\te_iv_1: 0x%08X\n", cshd->cshd_enc_iv);
132 device_printf(dev, "\t\te_iv_2: 0x%08X\n", cshd->cshd_enc_iv_buf);
133 device_printf(dev, "\t\tm_src: 0x%08X\n", cshd->cshd_mac_src);
134 device_printf(dev, "\t\tm_dst: 0x%08X\n", cshd->cshd_mac_dst);
135 device_printf(dev, "\t\tm_dlen: 0x%08X\n", cshd->cshd_mac_dlen);
136 device_printf(dev, "\t\tm_tlen: 0x%08X\n", cshd->cshd_mac_total_dlen);
137 device_printf(dev, "\t\tm_iv_i: 0x%08X\n", cshd->cshd_mac_iv_in);
138 device_printf(dev, "\t\tm_iv_o: 0x%08X\n", cshd->cshd_mac_iv_out);
143 cesa_alloc_dma_mem_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
145 struct cesa_dma_mem *cdm;
150 KASSERT(nseg == 1, ("Got wrong number of DMA segments, should be 1."));
152 cdm->cdm_paddr = segs->ds_addr;
156 cesa_alloc_dma_mem(struct cesa_softc *sc, struct cesa_dma_mem *cdm,
161 KASSERT(cdm->cdm_vaddr == NULL,
162 ("%s(): DMA memory descriptor in use.", __func__));
164 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
165 PAGE_SIZE, 0, /* alignment, boundary */
166 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
167 BUS_SPACE_MAXADDR, /* highaddr */
168 NULL, NULL, /* filtfunc, filtfuncarg */
169 size, 1, /* maxsize, nsegments */
170 size, 0, /* maxsegsz, flags */
171 NULL, NULL, /* lockfunc, lockfuncarg */
172 &cdm->cdm_tag); /* dmat */
174 device_printf(sc->sc_dev, "failed to allocate busdma tag, error"
180 error = bus_dmamem_alloc(cdm->cdm_tag, &cdm->cdm_vaddr,
181 BUS_DMA_NOWAIT | BUS_DMA_ZERO, &cdm->cdm_map);
183 device_printf(sc->sc_dev, "failed to allocate DMA safe"
184 " memory, error %i!\n", error);
189 error = bus_dmamap_load(cdm->cdm_tag, cdm->cdm_map, cdm->cdm_vaddr,
190 size, cesa_alloc_dma_mem_cb, cdm, BUS_DMA_NOWAIT);
192 device_printf(sc->sc_dev, "cannot get address of the DMA"
193 " memory, error %i\n", error);
200 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map);
202 bus_dma_tag_destroy(cdm->cdm_tag);
204 cdm->cdm_vaddr = NULL;
209 cesa_free_dma_mem(struct cesa_dma_mem *cdm)
212 bus_dmamap_unload(cdm->cdm_tag, cdm->cdm_map);
213 bus_dmamem_free(cdm->cdm_tag, cdm->cdm_vaddr, cdm->cdm_map);
214 bus_dma_tag_destroy(cdm->cdm_tag);
215 cdm->cdm_vaddr = NULL;
219 cesa_sync_dma_mem(struct cesa_dma_mem *cdm, bus_dmasync_op_t op)
222 /* Sync only if dma memory is valid */
223 if (cdm->cdm_vaddr != NULL)
224 bus_dmamap_sync(cdm->cdm_tag, cdm->cdm_map, op);
228 cesa_sync_desc(struct cesa_softc *sc, bus_dmasync_op_t op)
231 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, op);
232 cesa_sync_dma_mem(&sc->sc_sdesc_cdm, op);
233 cesa_sync_dma_mem(&sc->sc_requests_cdm, op);
236 static struct cesa_session *
237 cesa_alloc_session(struct cesa_softc *sc)
239 struct cesa_session *cs;
241 CESA_GENERIC_ALLOC_LOCKED(sc, cs, sessions);
246 static struct cesa_session *
247 cesa_get_session(struct cesa_softc *sc, uint32_t sid)
250 if (sid >= CESA_SESSIONS)
253 return (&sc->sc_sessions[sid]);
257 cesa_free_session(struct cesa_softc *sc, struct cesa_session *cs)
260 CESA_GENERIC_FREE_LOCKED(sc, cs, sessions);
263 static struct cesa_request *
264 cesa_alloc_request(struct cesa_softc *sc)
266 struct cesa_request *cr;
268 CESA_GENERIC_ALLOC_LOCKED(sc, cr, requests);
272 STAILQ_INIT(&cr->cr_tdesc);
273 STAILQ_INIT(&cr->cr_sdesc);
279 cesa_free_request(struct cesa_softc *sc, struct cesa_request *cr)
282 /* Free TDMA descriptors assigned to this request */
283 CESA_LOCK(sc, tdesc);
284 STAILQ_CONCAT(&sc->sc_free_tdesc, &cr->cr_tdesc);
285 CESA_UNLOCK(sc, tdesc);
287 /* Free SA descriptors assigned to this request */
288 CESA_LOCK(sc, sdesc);
289 STAILQ_CONCAT(&sc->sc_free_sdesc, &cr->cr_sdesc);
290 CESA_UNLOCK(sc, sdesc);
292 /* Unload DMA memory associated with request */
293 if (cr->cr_dmap_loaded) {
294 bus_dmamap_unload(sc->sc_data_dtag, cr->cr_dmap);
295 cr->cr_dmap_loaded = 0;
298 CESA_GENERIC_FREE_LOCKED(sc, cr, requests);
302 cesa_enqueue_request(struct cesa_softc *sc, struct cesa_request *cr)
305 CESA_LOCK(sc, requests);
306 STAILQ_INSERT_TAIL(&sc->sc_ready_requests, cr, cr_stq);
307 CESA_UNLOCK(sc, requests);
310 static struct cesa_tdma_desc *
311 cesa_alloc_tdesc(struct cesa_softc *sc)
313 struct cesa_tdma_desc *ctd;
315 CESA_GENERIC_ALLOC_LOCKED(sc, ctd, tdesc);
318 device_printf(sc->sc_dev, "TDMA descriptors pool exhaused. "
319 "Consider increasing CESA_TDMA_DESCRIPTORS.\n");
324 static struct cesa_sa_desc *
325 cesa_alloc_sdesc(struct cesa_softc *sc, struct cesa_request *cr)
327 struct cesa_sa_desc *csd;
329 CESA_GENERIC_ALLOC_LOCKED(sc, csd, sdesc);
331 device_printf(sc->sc_dev, "SA descriptors pool exhaused. "
332 "Consider increasing CESA_SA_DESCRIPTORS.\n");
336 STAILQ_INSERT_TAIL(&cr->cr_sdesc, csd, csd_stq);
338 /* Fill-in SA descriptor with default values */
339 csd->csd_cshd->cshd_enc_key = CESA_SA_DATA(csd_key);
340 csd->csd_cshd->cshd_enc_iv = CESA_SA_DATA(csd_iv);
341 csd->csd_cshd->cshd_enc_iv_buf = CESA_SA_DATA(csd_iv);
342 csd->csd_cshd->cshd_enc_src = 0;
343 csd->csd_cshd->cshd_enc_dst = 0;
344 csd->csd_cshd->cshd_enc_dlen = 0;
345 csd->csd_cshd->cshd_mac_dst = CESA_SA_DATA(csd_hash);
346 csd->csd_cshd->cshd_mac_iv_in = CESA_SA_DATA(csd_hiv_in);
347 csd->csd_cshd->cshd_mac_iv_out = CESA_SA_DATA(csd_hiv_out);
348 csd->csd_cshd->cshd_mac_src = 0;
349 csd->csd_cshd->cshd_mac_dlen = 0;
354 static struct cesa_tdma_desc *
355 cesa_tdma_copy(struct cesa_softc *sc, bus_addr_t dst, bus_addr_t src,
358 struct cesa_tdma_desc *ctd;
360 ctd = cesa_alloc_tdesc(sc);
364 ctd->ctd_cthd->cthd_dst = dst;
365 ctd->ctd_cthd->cthd_src = src;
366 ctd->ctd_cthd->cthd_byte_count = size;
368 /* Handle special control packet */
370 ctd->ctd_cthd->cthd_flags = CESA_CTHD_OWNED;
372 ctd->ctd_cthd->cthd_flags = 0;
377 static struct cesa_tdma_desc *
378 cesa_tdma_copyin_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
381 return (cesa_tdma_copy(sc, sc->sc_sram_base_pa +
382 sizeof(struct cesa_sa_hdesc), cr->cr_csd_paddr,
383 sizeof(struct cesa_sa_data)));
386 static struct cesa_tdma_desc *
387 cesa_tdma_copyout_sa_data(struct cesa_softc *sc, struct cesa_request *cr)
390 return (cesa_tdma_copy(sc, cr->cr_csd_paddr, sc->sc_sram_base_pa +
391 sizeof(struct cesa_sa_hdesc), sizeof(struct cesa_sa_data)));
394 static struct cesa_tdma_desc *
395 cesa_tdma_copy_sdesc(struct cesa_softc *sc, struct cesa_sa_desc *csd)
398 return (cesa_tdma_copy(sc, sc->sc_sram_base_pa, csd->csd_cshd_paddr,
399 sizeof(struct cesa_sa_hdesc)));
403 cesa_append_tdesc(struct cesa_request *cr, struct cesa_tdma_desc *ctd)
405 struct cesa_tdma_desc *ctd_prev;
407 if (!STAILQ_EMPTY(&cr->cr_tdesc)) {
408 ctd_prev = STAILQ_LAST(&cr->cr_tdesc, cesa_tdma_desc, ctd_stq);
409 ctd_prev->ctd_cthd->cthd_next = ctd->ctd_cthd_paddr;
412 ctd->ctd_cthd->cthd_next = 0;
413 STAILQ_INSERT_TAIL(&cr->cr_tdesc, ctd, ctd_stq);
417 cesa_append_packet(struct cesa_softc *sc, struct cesa_request *cr,
418 struct cesa_packet *cp, struct cesa_sa_desc *csd)
420 struct cesa_tdma_desc *ctd, *tmp;
422 /* Copy SA descriptor for this packet */
423 ctd = cesa_tdma_copy_sdesc(sc, csd);
427 cesa_append_tdesc(cr, ctd);
429 /* Copy data to be processed */
430 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyin, ctd_stq, tmp)
431 cesa_append_tdesc(cr, ctd);
432 STAILQ_INIT(&cp->cp_copyin);
434 /* Insert control descriptor */
435 ctd = cesa_tdma_copy(sc, 0, 0, 0);
439 cesa_append_tdesc(cr, ctd);
441 /* Copy back results */
442 STAILQ_FOREACH_SAFE(ctd, &cp->cp_copyout, ctd_stq, tmp)
443 cesa_append_tdesc(cr, ctd);
444 STAILQ_INIT(&cp->cp_copyout);
450 cesa_set_mkey(struct cesa_session *cs, int alg, const uint8_t *mkey, int mklen)
452 uint8_t ipad[CESA_MAX_HMAC_BLOCK_LEN];
453 uint8_t opad[CESA_MAX_HMAC_BLOCK_LEN];
455 SHA256_CTX sha256ctx;
461 memset(ipad, HMAC_IPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN);
462 memset(opad, HMAC_OPAD_VAL, CESA_MAX_HMAC_BLOCK_LEN);
463 for (i = 0; i < mklen; i++) {
468 hin = (uint32_t *)cs->cs_hiv_in;
469 hout = (uint32_t *)cs->cs_hiv_out;
472 case CRYPTO_MD5_HMAC:
474 MD5Update(&md5ctx, ipad, MD5_HMAC_BLOCK_LEN);
475 memcpy(hin, md5ctx.state, sizeof(md5ctx.state));
477 MD5Update(&md5ctx, opad, MD5_HMAC_BLOCK_LEN);
478 memcpy(hout, md5ctx.state, sizeof(md5ctx.state));
480 case CRYPTO_SHA1_HMAC:
482 SHA1Update(&sha1ctx, ipad, SHA1_HMAC_BLOCK_LEN);
483 memcpy(hin, sha1ctx.h.b32, sizeof(sha1ctx.h.b32));
485 SHA1Update(&sha1ctx, opad, SHA1_HMAC_BLOCK_LEN);
486 memcpy(hout, sha1ctx.h.b32, sizeof(sha1ctx.h.b32));
488 case CRYPTO_SHA2_256_HMAC:
489 SHA256_Init(&sha256ctx);
490 SHA256_Update(&sha256ctx, ipad, SHA2_256_HMAC_BLOCK_LEN);
491 memcpy(hin, sha256ctx.state, sizeof(sha256ctx.state));
492 SHA256_Init(&sha256ctx);
493 SHA256_Update(&sha256ctx, opad, SHA2_256_HMAC_BLOCK_LEN);
494 memcpy(hout, sha256ctx.state, sizeof(sha256ctx.state));
500 for (i = 0; i < CESA_MAX_HASH_LEN / sizeof(uint32_t); i++) {
501 hin[i] = htobe32(hin[i]);
502 hout[i] = htobe32(hout[i]);
509 cesa_prep_aes_key(struct cesa_session *cs)
511 uint32_t ek[4 * (RIJNDAEL_MAXNR + 1)];
515 rijndaelKeySetupEnc(ek, cs->cs_key, cs->cs_klen * 8);
517 cs->cs_config &= ~CESA_CSH_AES_KLEN_MASK;
518 dkey = (uint32_t *)cs->cs_aes_dkey;
520 switch (cs->cs_klen) {
522 cs->cs_config |= CESA_CSH_AES_KLEN_128;
523 for (i = 0; i < 4; i++)
524 *dkey++ = htobe32(ek[4 * 10 + i]);
527 cs->cs_config |= CESA_CSH_AES_KLEN_192;
528 for (i = 0; i < 4; i++)
529 *dkey++ = htobe32(ek[4 * 12 + i]);
530 for (i = 0; i < 2; i++)
531 *dkey++ = htobe32(ek[4 * 11 + 2 + i]);
534 cs->cs_config |= CESA_CSH_AES_KLEN_256;
535 for (i = 0; i < 4; i++)
536 *dkey++ = htobe32(ek[4 * 14 + i]);
537 for (i = 0; i < 4; i++)
538 *dkey++ = htobe32(ek[4 * 13 + i]);
548 cesa_is_hash(int alg)
553 case CRYPTO_MD5_HMAC:
555 case CRYPTO_SHA1_HMAC:
556 case CRYPTO_SHA2_256_HMAC:
564 cesa_start_packet(struct cesa_packet *cp, unsigned int size)
569 STAILQ_INIT(&cp->cp_copyin);
570 STAILQ_INIT(&cp->cp_copyout);
574 cesa_fill_packet(struct cesa_softc *sc, struct cesa_packet *cp,
575 bus_dma_segment_t *seg)
577 struct cesa_tdma_desc *ctd;
580 /* Calculate size of block copy */
581 bsize = MIN(seg->ds_len, cp->cp_size - cp->cp_offset);
584 ctd = cesa_tdma_copy(sc, sc->sc_sram_base_pa +
585 CESA_DATA(cp->cp_offset), seg->ds_addr, bsize);
589 STAILQ_INSERT_TAIL(&cp->cp_copyin, ctd, ctd_stq);
591 ctd = cesa_tdma_copy(sc, seg->ds_addr, sc->sc_sram_base_pa +
592 CESA_DATA(cp->cp_offset), bsize);
596 STAILQ_INSERT_TAIL(&cp->cp_copyout, ctd, ctd_stq);
598 seg->ds_len -= bsize;
599 seg->ds_addr += bsize;
600 cp->cp_offset += bsize;
607 cesa_create_chain_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
609 unsigned int mpsize, fragmented;
610 unsigned int mlen, mskip, tmlen;
611 struct cesa_chain_info *cci;
612 unsigned int elen, eskip;
613 unsigned int skip, len;
614 struct cesa_sa_desc *csd;
615 struct cesa_request *cr;
616 struct cesa_softc *sc;
617 struct cesa_packet cp;
618 bus_dma_segment_t seg;
627 cci->cci_error = error;
631 elen = cci->cci_enc ? cci->cci_enc->crd_len : 0;
632 eskip = cci->cci_enc ? cci->cci_enc->crd_skip : 0;
633 mlen = cci->cci_mac ? cci->cci_mac->crd_len : 0;
634 mskip = cci->cci_mac ? cci->cci_mac->crd_skip : 0;
637 ((eskip > mskip && ((eskip - mskip) & (cr->cr_cs->cs_ivlen - 1))) ||
638 (mskip > eskip && ((mskip - eskip) & (cr->cr_cs->cs_mblen - 1))) ||
639 (eskip > (mskip + mlen)) || (mskip > (eskip + elen)))) {
641 * Data alignment in the request does not meet CESA requiremnts
642 * for combined encryption/decryption and hashing. We have to
643 * split the request to separate operations and process them
646 config = cci->cci_config;
647 if ((config & CESA_CSHD_OP_MASK) == CESA_CSHD_MAC_AND_ENC) {
648 config &= ~CESA_CSHD_OP_MASK;
650 cci->cci_config = config | CESA_CSHD_MAC;
652 cci->cci_mac = cr->cr_mac;
653 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
655 cci->cci_config = config | CESA_CSHD_ENC;
656 cci->cci_enc = cr->cr_enc;
658 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
660 config &= ~CESA_CSHD_OP_MASK;
662 cci->cci_config = config | CESA_CSHD_ENC;
663 cci->cci_enc = cr->cr_enc;
665 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
667 cci->cci_config = config | CESA_CSHD_MAC;
669 cci->cci_mac = cr->cr_mac;
670 cesa_create_chain_cb(cci, segs, nseg, cci->cci_error);
678 mpsize = CESA_MAX_PACKET_SIZE;
679 mpsize &= ~((cr->cr_cs->cs_ivlen - 1) | (cr->cr_cs->cs_mblen - 1));
682 skip = MIN(eskip, mskip);
683 len = MAX(elen + eskip, mlen + mskip) - skip;
692 /* Start first packet in chain */
693 cesa_start_packet(&cp, MIN(mpsize, len));
695 while (nseg-- && len > 0) {
699 * Skip data in buffer on which neither ENC nor MAC operation
703 size = MIN(skip, seg.ds_len);
721 * Fill in current packet with data. Break if there is
722 * no more data in current DMA segment or an error
725 size = cesa_fill_packet(sc, &cp, &seg);
733 /* If packet is full, append it to the chain */
734 if (cp.cp_size == cp.cp_offset) {
735 csd = cesa_alloc_sdesc(sc, cr);
741 /* Create SA descriptor for this packet */
742 csd->csd_cshd->cshd_config = cci->cci_config;
743 csd->csd_cshd->cshd_mac_total_dlen = tmlen;
746 * Enable fragmentation if request will not fit
752 csd->csd_cshd->cshd_config |=
753 CESA_CSHD_FRAG_FIRST;
755 csd->csd_cshd->cshd_config |=
756 CESA_CSHD_FRAG_MIDDLE;
757 } else if (fragmented)
758 csd->csd_cshd->cshd_config |=
761 if (eskip < cp.cp_size && elen > 0) {
762 csd->csd_cshd->cshd_enc_src =
764 csd->csd_cshd->cshd_enc_dst =
766 csd->csd_cshd->cshd_enc_dlen =
767 MIN(elen, cp.cp_size - eskip);
770 if (mskip < cp.cp_size && mlen > 0) {
771 csd->csd_cshd->cshd_mac_src =
773 csd->csd_cshd->cshd_mac_dlen =
774 MIN(mlen, cp.cp_size - mskip);
777 elen -= csd->csd_cshd->cshd_enc_dlen;
778 eskip -= MIN(eskip, cp.cp_size);
779 mlen -= csd->csd_cshd->cshd_mac_dlen;
780 mskip -= MIN(mskip, cp.cp_size);
782 cesa_dump_cshd(sc, csd->csd_cshd);
784 /* Append packet to the request */
785 error = cesa_append_packet(sc, cr, &cp, csd);
789 /* Start a new packet, as current is full */
790 cesa_start_packet(&cp, MIN(mpsize, len));
800 * Move all allocated resources to the request. They will be
803 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyin);
804 STAILQ_CONCAT(&cr->cr_tdesc, &cp.cp_copyout);
805 cci->cci_error = error;
810 cesa_create_chain_cb2(void *arg, bus_dma_segment_t *segs, int nseg,
811 bus_size_t size, int error)
814 cesa_create_chain_cb(arg, segs, nseg, error);
818 cesa_create_chain(struct cesa_softc *sc, struct cesa_request *cr)
820 struct cesa_chain_info cci;
821 struct cesa_tdma_desc *ctd;
826 CESA_LOCK_ASSERT(sc, sessions);
828 /* Create request metadata */
830 if (cr->cr_enc->crd_alg == CRYPTO_AES_CBC &&
831 (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0)
832 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_aes_dkey,
835 memcpy(cr->cr_csd->csd_key, cr->cr_cs->cs_key,
840 memcpy(cr->cr_csd->csd_hiv_in, cr->cr_cs->cs_hiv_in,
842 memcpy(cr->cr_csd->csd_hiv_out, cr->cr_cs->cs_hiv_out,
846 ctd = cesa_tdma_copyin_sa_data(sc, cr);
850 cesa_append_tdesc(cr, ctd);
852 /* Prepare SA configuration */
853 config = cr->cr_cs->cs_config;
855 if (cr->cr_enc && (cr->cr_enc->crd_flags & CRD_F_ENCRYPT) == 0)
856 config |= CESA_CSHD_DECRYPT;
857 if (cr->cr_enc && !cr->cr_mac)
858 config |= CESA_CSHD_ENC;
859 if (!cr->cr_enc && cr->cr_mac)
860 config |= CESA_CSHD_MAC;
861 if (cr->cr_enc && cr->cr_mac)
862 config |= (config & CESA_CSHD_DECRYPT) ? CESA_CSHD_MAC_AND_ENC :
863 CESA_CSHD_ENC_AND_MAC;
865 /* Create data packets */
868 cci.cci_enc = cr->cr_enc;
869 cci.cci_mac = cr->cr_mac;
870 cci.cci_config = config;
873 if (cr->cr_crp->crp_flags & CRYPTO_F_IOV)
874 error = bus_dmamap_load_uio(sc->sc_data_dtag,
875 cr->cr_dmap, (struct uio *)cr->cr_crp->crp_buf,
876 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT);
877 else if (cr->cr_crp->crp_flags & CRYPTO_F_IMBUF)
878 error = bus_dmamap_load_mbuf(sc->sc_data_dtag,
879 cr->cr_dmap, (struct mbuf *)cr->cr_crp->crp_buf,
880 cesa_create_chain_cb2, &cci, BUS_DMA_NOWAIT);
882 error = bus_dmamap_load(sc->sc_data_dtag,
883 cr->cr_dmap, cr->cr_crp->crp_buf,
884 cr->cr_crp->crp_ilen, cesa_create_chain_cb, &cci,
888 cr->cr_dmap_loaded = 1;
891 error = cci.cci_error;
896 /* Read back request metadata */
897 ctd = cesa_tdma_copyout_sa_data(sc, cr);
901 cesa_append_tdesc(cr, ctd);
907 cesa_execute(struct cesa_softc *sc)
909 struct cesa_tdma_desc *prev_ctd, *ctd;
910 struct cesa_request *prev_cr, *cr;
912 CESA_LOCK(sc, requests);
915 * If ready list is empty, there is nothing to execute. If queued list
916 * is not empty, the hardware is busy and we cannot start another
919 if (STAILQ_EMPTY(&sc->sc_ready_requests) ||
920 !STAILQ_EMPTY(&sc->sc_queued_requests)) {
921 CESA_UNLOCK(sc, requests);
925 /* Move all ready requests to queued list */
926 STAILQ_CONCAT(&sc->sc_queued_requests, &sc->sc_ready_requests);
927 STAILQ_INIT(&sc->sc_ready_requests);
929 /* Create one execution chain from all requests on the list */
930 if (STAILQ_FIRST(&sc->sc_queued_requests) !=
931 STAILQ_LAST(&sc->sc_queued_requests, cesa_request, cr_stq)) {
933 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_POSTREAD |
934 BUS_DMASYNC_POSTWRITE);
936 STAILQ_FOREACH(cr, &sc->sc_queued_requests, cr_stq) {
938 ctd = STAILQ_FIRST(&cr->cr_tdesc);
939 prev_ctd = STAILQ_LAST(&prev_cr->cr_tdesc,
940 cesa_tdma_desc, ctd_stq);
942 prev_ctd->ctd_cthd->cthd_next =
949 cesa_sync_dma_mem(&sc->sc_tdesc_cdm, BUS_DMASYNC_PREREAD |
950 BUS_DMASYNC_PREWRITE);
953 /* Start chain execution in hardware */
954 cr = STAILQ_FIRST(&sc->sc_queued_requests);
955 ctd = STAILQ_FIRST(&cr->cr_tdesc);
957 CESA_TDMA_WRITE(sc, CESA_TDMA_ND, ctd->ctd_cthd_paddr);
959 if (sc->sc_soc_id == MV_DEV_88F6828 ||
960 sc->sc_soc_id == MV_DEV_88F6820 ||
961 sc->sc_soc_id == MV_DEV_88F6810)
962 CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE | CESA_SA_CMD_SHA2);
964 CESA_REG_WRITE(sc, CESA_SA_CMD, CESA_SA_CMD_ACTVATE);
966 CESA_UNLOCK(sc, requests);
970 cesa_setup_sram(struct cesa_softc *sc)
973 ihandle_t sram_ihandle;
974 pcell_t sram_handle, sram_reg[2];
978 rv = OF_getencprop(ofw_bus_get_node(sc->sc_dev), "sram-handle",
979 (void *)&sram_handle, sizeof(sram_handle));
983 sram_ihandle = (ihandle_t)sram_handle;
984 sram_node = OF_instance_to_package(sram_ihandle);
986 rv = OF_getencprop(sram_node, "reg", (void *)sram_reg, sizeof(sram_reg));
990 sc->sc_sram_base_pa = sram_reg[0];
991 /* Store SRAM size to be able to unmap in detach() */
992 sc->sc_sram_size = sram_reg[1];
994 if (sc->sc_soc_id != MV_DEV_88F6828 &&
995 sc->sc_soc_id != MV_DEV_88F6820 &&
996 sc->sc_soc_id != MV_DEV_88F6810)
999 /* SRAM memory was not mapped in platform_sram_devmap(), map it now */
1000 sram_va = pmap_mapdev(sc->sc_sram_base_pa, sc->sc_sram_size);
1001 if (sram_va == NULL)
1003 sc->sc_sram_base_va = (vm_offset_t)sram_va;
1009 * Function: device_from_node
1010 * This function returns appropriate device_t to phandle_t
1012 * root - device where you want to start search
1013 * if you provide NULL here, function will take
1014 * "root0" device as root.
1015 * node - we are checking every device_t to be
1016 * appropriate with this.
1019 device_from_node(device_t root, phandle_t node)
1021 device_t *children, retval;
1024 /* Nothing matches no node */
1029 /* Get root of device tree */
1030 if ((root = device_lookup_by_name("root0")) == NULL)
1033 if (device_get_children(root, &children, &nkid) != 0)
1037 for (i = 0; i < nkid; i++) {
1038 /* Check if device and node matches */
1039 if (OFW_BUS_GET_NODE(root, children[i]) == node) {
1040 retval = children[i];
1044 if ((retval = device_from_node(children[i], node)) != NULL)
1047 free(children, M_TEMP);
1053 cesa_setup_sram_armada(struct cesa_softc *sc)
1055 phandle_t sram_node;
1056 ihandle_t sram_ihandle;
1057 pcell_t sram_handle[2];
1060 struct resource_list rl;
1061 struct resource_list_entry *rle;
1062 struct simplebus_softc *ssc;
1065 /* Get refs to SRAMS from CESA node */
1066 rv = OF_getencprop(ofw_bus_get_node(sc->sc_dev), "marvell,crypto-srams",
1067 (void *)sram_handle, sizeof(sram_handle));
1071 if (sc->sc_cesa_engine_id >= 2)
1074 /* Get SRAM node on the basis of sc_cesa_engine_id */
1075 sram_ihandle = (ihandle_t)sram_handle[sc->sc_cesa_engine_id];
1076 sram_node = OF_instance_to_package(sram_ihandle);
1078 /* Get device_t of simplebus (sram_node parent) */
1079 sdev = device_from_node(NULL, OF_parent(sram_node));
1083 ssc = device_get_softc(sdev);
1085 resource_list_init(&rl);
1086 /* Parse reg property to resource list */
1087 ofw_bus_reg_to_rl(sdev, sram_node, ssc->acells,
1090 /* We expect only one resource */
1091 rle = resource_list_find(&rl, SYS_RES_MEMORY, 0);
1095 /* Remap through ranges property */
1096 for (j = 0; j < ssc->nranges; j++) {
1097 if (rle->start >= ssc->ranges[j].bus &&
1098 rle->end < ssc->ranges[j].bus + ssc->ranges[j].size) {
1099 rle->start -= ssc->ranges[j].bus;
1100 rle->start += ssc->ranges[j].host;
1101 rle->end -= ssc->ranges[j].bus;
1102 rle->end += ssc->ranges[j].host;
1106 sc->sc_sram_base_pa = rle->start;
1107 sc->sc_sram_size = rle->count;
1109 /* SRAM memory was not mapped in platform_sram_devmap(), map it now */
1110 sram_va = pmap_mapdev(sc->sc_sram_base_pa, sc->sc_sram_size);
1111 if (sram_va == NULL)
1113 sc->sc_sram_base_va = (vm_offset_t)sram_va;
1118 struct ofw_compat_data cesa_devices[] = {
1119 { "mrvl,cesa", (uintptr_t)true },
1120 { "marvell,armada-38x-crypto", (uintptr_t)true },
1125 cesa_probe(device_t dev)
1128 if (!ofw_bus_status_okay(dev))
1131 if (!ofw_bus_search_compatible(dev, cesa_devices)->ocd_data)
1134 device_set_desc(dev, "Marvell Cryptographic Engine and Security "
1137 return (BUS_PROBE_DEFAULT);
1141 cesa_attach(device_t dev)
1143 static int engine_idx = 0;
1144 struct simplebus_devinfo *ndi;
1145 struct resource_list *rl;
1146 struct cesa_softc *sc;
1148 if (!ofw_bus_is_compatible(dev, "marvell,armada-38x-crypto"))
1149 return (cesa_attach_late(dev));
1152 * Get simplebus_devinfo which contains
1153 * resource list filled with adresses and
1154 * interrupts read form FDT.
1155 * Let's correct it by splitting resources
1158 if ((ndi = device_get_ivars(dev)) == NULL)
1163 switch (engine_idx) {
1165 /* Update regs values */
1166 resource_list_add(rl, SYS_RES_MEMORY, 0, CESA0_TDMA_ADDR,
1167 CESA0_TDMA_ADDR + CESA_TDMA_SIZE - 1, CESA_TDMA_SIZE);
1168 resource_list_add(rl, SYS_RES_MEMORY, 1, CESA0_CESA_ADDR,
1169 CESA0_CESA_ADDR + CESA_CESA_SIZE - 1, CESA_CESA_SIZE);
1171 /* Remove unused interrupt */
1172 resource_list_delete(rl, SYS_RES_IRQ, 1);
1176 /* Update regs values */
1177 resource_list_add(rl, SYS_RES_MEMORY, 0, CESA1_TDMA_ADDR,
1178 CESA1_TDMA_ADDR + CESA_TDMA_SIZE - 1, CESA_TDMA_SIZE);
1179 resource_list_add(rl, SYS_RES_MEMORY, 1, CESA1_CESA_ADDR,
1180 CESA1_CESA_ADDR + CESA_CESA_SIZE - 1, CESA_CESA_SIZE);
1182 /* Remove unused interrupt */
1183 resource_list_delete(rl, SYS_RES_IRQ, 0);
1184 resource_list_find(rl, SYS_RES_IRQ, 1)->rid = 0;
1188 device_printf(dev, "Bad cesa engine_idx\n");
1192 sc = device_get_softc(dev);
1193 sc->sc_cesa_engine_id = engine_idx;
1196 * Call simplebus_add_device only once.
1197 * It will create second cesa driver instance
1198 * with the same FDT node as first instance.
1199 * When second driver reach this function,
1200 * it will be configured to use second cesa engine
1202 if (engine_idx == 0)
1203 simplebus_add_device(device_get_parent(dev), ofw_bus_get_node(dev),
1204 0, "cesa", 1, NULL);
1208 return (cesa_attach_late(dev));
1212 cesa_attach_late(device_t dev)
1214 struct cesa_softc *sc;
1219 sc = device_get_softc(dev);
1227 case MV_DEV_88F6281:
1228 case MV_DEV_88F6282:
1229 /* Check if CESA peripheral device has power turned on */
1230 if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) ==
1231 CPU_PM_CTRL_CRYPTO) {
1232 device_printf(dev, "not powered on\n");
1237 case MV_DEV_88F6828:
1238 case MV_DEV_88F6820:
1239 case MV_DEV_88F6810:
1242 case MV_DEV_MV78100:
1243 case MV_DEV_MV78100_Z0:
1244 /* Check if CESA peripheral device has power turned on */
1245 if (soc_power_ctrl_get(CPU_PM_CTRL_CRYPTO) !=
1246 CPU_PM_CTRL_CRYPTO) {
1247 device_printf(dev, "not powered on\n");
1250 sc->sc_tperr = CESA_ICR_TPERR;
1258 /* Initialize mutexes */
1259 mtx_init(&sc->sc_sc_lock, device_get_nameunit(dev),
1260 "CESA Shared Data", MTX_DEF);
1261 mtx_init(&sc->sc_tdesc_lock, device_get_nameunit(dev),
1262 "CESA TDMA Descriptors Pool", MTX_DEF);
1263 mtx_init(&sc->sc_sdesc_lock, device_get_nameunit(dev),
1264 "CESA SA Descriptors Pool", MTX_DEF);
1265 mtx_init(&sc->sc_requests_lock, device_get_nameunit(dev),
1266 "CESA Requests Pool", MTX_DEF);
1267 mtx_init(&sc->sc_sessions_lock, device_get_nameunit(dev),
1268 "CESA Sessions Pool", MTX_DEF);
1270 /* Allocate I/O and IRQ resources */
1271 error = bus_alloc_resources(dev, cesa_res_spec, sc->sc_res);
1273 device_printf(dev, "could not allocate resources\n");
1277 /* Acquire SRAM base address */
1278 if (!ofw_bus_is_compatible(dev, "marvell,armada-38x-crypto"))
1279 error = cesa_setup_sram(sc);
1281 error = cesa_setup_sram_armada(sc);
1284 device_printf(dev, "could not setup SRAM\n");
1288 /* Setup interrupt handler */
1289 error = bus_setup_intr(dev, sc->sc_res[RES_CESA_IRQ], INTR_TYPE_NET |
1290 INTR_MPSAFE, NULL, cesa_intr, sc, &(sc->sc_icookie));
1292 device_printf(dev, "could not setup engine completion irq\n");
1296 /* Create DMA tag for processed data */
1297 error = bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */
1298 1, 0, /* alignment, boundary */
1299 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
1300 BUS_SPACE_MAXADDR, /* highaddr */
1301 NULL, NULL, /* filtfunc, filtfuncarg */
1302 CESA_MAX_REQUEST_SIZE, /* maxsize */
1303 CESA_MAX_FRAGMENTS, /* nsegments */
1304 CESA_MAX_REQUEST_SIZE, 0, /* maxsegsz, flags */
1305 NULL, NULL, /* lockfunc, lockfuncarg */
1306 &sc->sc_data_dtag); /* dmat */
1310 /* Initialize data structures: TDMA Descriptors Pool */
1311 error = cesa_alloc_dma_mem(sc, &sc->sc_tdesc_cdm,
1312 CESA_TDMA_DESCRIPTORS * sizeof(struct cesa_tdma_hdesc));
1316 STAILQ_INIT(&sc->sc_free_tdesc);
1317 for (i = 0; i < CESA_TDMA_DESCRIPTORS; i++) {
1318 sc->sc_tdesc[i].ctd_cthd =
1319 (struct cesa_tdma_hdesc *)(sc->sc_tdesc_cdm.cdm_vaddr) + i;
1320 sc->sc_tdesc[i].ctd_cthd_paddr = sc->sc_tdesc_cdm.cdm_paddr +
1321 (i * sizeof(struct cesa_tdma_hdesc));
1322 STAILQ_INSERT_TAIL(&sc->sc_free_tdesc, &sc->sc_tdesc[i],
1326 /* Initialize data structures: SA Descriptors Pool */
1327 error = cesa_alloc_dma_mem(sc, &sc->sc_sdesc_cdm,
1328 CESA_SA_DESCRIPTORS * sizeof(struct cesa_sa_hdesc));
1332 STAILQ_INIT(&sc->sc_free_sdesc);
1333 for (i = 0; i < CESA_SA_DESCRIPTORS; i++) {
1334 sc->sc_sdesc[i].csd_cshd =
1335 (struct cesa_sa_hdesc *)(sc->sc_sdesc_cdm.cdm_vaddr) + i;
1336 sc->sc_sdesc[i].csd_cshd_paddr = sc->sc_sdesc_cdm.cdm_paddr +
1337 (i * sizeof(struct cesa_sa_hdesc));
1338 STAILQ_INSERT_TAIL(&sc->sc_free_sdesc, &sc->sc_sdesc[i],
1342 /* Initialize data structures: Requests Pool */
1343 error = cesa_alloc_dma_mem(sc, &sc->sc_requests_cdm,
1344 CESA_REQUESTS * sizeof(struct cesa_sa_data));
1348 STAILQ_INIT(&sc->sc_free_requests);
1349 STAILQ_INIT(&sc->sc_ready_requests);
1350 STAILQ_INIT(&sc->sc_queued_requests);
1351 for (i = 0; i < CESA_REQUESTS; i++) {
1352 sc->sc_requests[i].cr_csd =
1353 (struct cesa_sa_data *)(sc->sc_requests_cdm.cdm_vaddr) + i;
1354 sc->sc_requests[i].cr_csd_paddr =
1355 sc->sc_requests_cdm.cdm_paddr +
1356 (i * sizeof(struct cesa_sa_data));
1358 /* Preallocate DMA maps */
1359 error = bus_dmamap_create(sc->sc_data_dtag, 0,
1360 &sc->sc_requests[i].cr_dmap);
1361 if (error && i > 0) {
1364 bus_dmamap_destroy(sc->sc_data_dtag,
1365 sc->sc_requests[i].cr_dmap);
1371 STAILQ_INSERT_TAIL(&sc->sc_free_requests, &sc->sc_requests[i],
1375 /* Initialize data structures: Sessions Pool */
1376 STAILQ_INIT(&sc->sc_free_sessions);
1377 for (i = 0; i < CESA_SESSIONS; i++) {
1378 sc->sc_sessions[i].cs_sid = i;
1379 STAILQ_INSERT_TAIL(&sc->sc_free_sessions, &sc->sc_sessions[i],
1385 * - Burst limit: 128 bytes,
1386 * - Outstanding reads enabled,
1389 val = CESA_TDMA_CR_DBL128 | CESA_TDMA_CR_SBL128 |
1390 CESA_TDMA_CR_ORDEN | CESA_TDMA_CR_NBS | CESA_TDMA_CR_ENABLE;
1392 if (sc->sc_soc_id == MV_DEV_88F6828 ||
1393 sc->sc_soc_id == MV_DEV_88F6820 ||
1394 sc->sc_soc_id == MV_DEV_88F6810)
1395 val |= CESA_TDMA_NUM_OUTSTAND;
1397 CESA_TDMA_WRITE(sc, CESA_TDMA_CR, val);
1401 * - SA descriptor is present at beginning of CESA SRAM,
1402 * - Multi-packet chain mode,
1403 * - Cooperation with TDMA enabled.
1405 CESA_REG_WRITE(sc, CESA_SA_DPR, 0);
1406 CESA_REG_WRITE(sc, CESA_SA_CR, CESA_SA_CR_ACTIVATE_TDMA |
1407 CESA_SA_CR_WAIT_FOR_TDMA | CESA_SA_CR_MULTI_MODE);
1409 /* Unmask interrupts */
1410 CESA_REG_WRITE(sc, CESA_ICR, 0);
1411 CESA_REG_WRITE(sc, CESA_ICM, CESA_ICM_ACCTDMA | sc->sc_tperr);
1412 CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0);
1413 CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, CESA_TDMA_EMR_MISS |
1414 CESA_TDMA_EMR_DOUBLE_HIT | CESA_TDMA_EMR_BOTH_HIT |
1415 CESA_TDMA_EMR_DATA_ERROR);
1417 /* Register in OCF */
1418 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
1419 if (sc->sc_cid < 0) {
1420 device_printf(dev, "could not get crypto driver id\n");
1424 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
1425 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
1426 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
1427 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
1428 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
1429 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
1430 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
1431 if (sc->sc_soc_id == MV_DEV_88F6828 ||
1432 sc->sc_soc_id == MV_DEV_88F6820 ||
1433 sc->sc_soc_id == MV_DEV_88F6810)
1434 crypto_register(sc->sc_cid, CRYPTO_SHA2_256_HMAC, 0, 0);
1438 for (i = 0; i < CESA_REQUESTS; i++)
1439 bus_dmamap_destroy(sc->sc_data_dtag,
1440 sc->sc_requests[i].cr_dmap);
1442 cesa_free_dma_mem(&sc->sc_requests_cdm);
1444 cesa_free_dma_mem(&sc->sc_sdesc_cdm);
1446 cesa_free_dma_mem(&sc->sc_tdesc_cdm);
1448 bus_dma_tag_destroy(sc->sc_data_dtag);
1450 bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie);
1452 if (sc->sc_soc_id == MV_DEV_88F6828 ||
1453 sc->sc_soc_id == MV_DEV_88F6820 ||
1454 sc->sc_soc_id == MV_DEV_88F6810)
1455 pmap_unmapdev(sc->sc_sram_base_va, sc->sc_sram_size);
1457 bus_release_resources(dev, cesa_res_spec, sc->sc_res);
1459 mtx_destroy(&sc->sc_sessions_lock);
1460 mtx_destroy(&sc->sc_requests_lock);
1461 mtx_destroy(&sc->sc_sdesc_lock);
1462 mtx_destroy(&sc->sc_tdesc_lock);
1463 mtx_destroy(&sc->sc_sc_lock);
1468 cesa_detach(device_t dev)
1470 struct cesa_softc *sc;
1473 sc = device_get_softc(dev);
1475 /* TODO: Wait for queued requests completion before shutdown. */
1477 /* Mask interrupts */
1478 CESA_REG_WRITE(sc, CESA_ICM, 0);
1479 CESA_TDMA_WRITE(sc, CESA_TDMA_EMR, 0);
1481 /* Unregister from OCF */
1482 crypto_unregister_all(sc->sc_cid);
1485 for (i = 0; i < CESA_REQUESTS; i++)
1486 bus_dmamap_destroy(sc->sc_data_dtag,
1487 sc->sc_requests[i].cr_dmap);
1489 /* Free DMA Memory */
1490 cesa_free_dma_mem(&sc->sc_requests_cdm);
1491 cesa_free_dma_mem(&sc->sc_sdesc_cdm);
1492 cesa_free_dma_mem(&sc->sc_tdesc_cdm);
1495 bus_dma_tag_destroy(sc->sc_data_dtag);
1497 /* Stop interrupt */
1498 bus_teardown_intr(dev, sc->sc_res[RES_CESA_IRQ], sc->sc_icookie);
1500 /* Relase I/O and IRQ resources */
1501 bus_release_resources(dev, cesa_res_spec, sc->sc_res);
1503 /* Unmap SRAM memory */
1504 if (sc->sc_soc_id == MV_DEV_88F6828 ||
1505 sc->sc_soc_id == MV_DEV_88F6820 ||
1506 sc->sc_soc_id == MV_DEV_88F6810)
1507 pmap_unmapdev(sc->sc_sram_base_va, sc->sc_sram_size);
1509 /* Destroy mutexes */
1510 mtx_destroy(&sc->sc_sessions_lock);
1511 mtx_destroy(&sc->sc_requests_lock);
1512 mtx_destroy(&sc->sc_sdesc_lock);
1513 mtx_destroy(&sc->sc_tdesc_lock);
1514 mtx_destroy(&sc->sc_sc_lock);
1520 cesa_intr(void *arg)
1522 STAILQ_HEAD(, cesa_request) requests;
1523 struct cesa_request *cr, *tmp;
1524 struct cesa_softc *sc;
1531 ecr = CESA_TDMA_READ(sc, CESA_TDMA_ECR);
1532 CESA_TDMA_WRITE(sc, CESA_TDMA_ECR, 0);
1533 icr = CESA_REG_READ(sc, CESA_ICR);
1534 CESA_REG_WRITE(sc, CESA_ICR, 0);
1536 /* Check for TDMA errors */
1537 if (ecr & CESA_TDMA_ECR_MISS) {
1538 device_printf(sc->sc_dev, "TDMA Miss error detected!\n");
1542 if (ecr & CESA_TDMA_ECR_DOUBLE_HIT) {
1543 device_printf(sc->sc_dev, "TDMA Double Hit error detected!\n");
1547 if (ecr & CESA_TDMA_ECR_BOTH_HIT) {
1548 device_printf(sc->sc_dev, "TDMA Both Hit error detected!\n");
1552 if (ecr & CESA_TDMA_ECR_DATA_ERROR) {
1553 device_printf(sc->sc_dev, "TDMA Data error detected!\n");
1557 /* Check for CESA errors */
1558 if (icr & sc->sc_tperr) {
1559 device_printf(sc->sc_dev, "CESA SRAM Parity error detected!\n");
1563 /* If there is nothing more to do, return */
1564 if ((icr & CESA_ICR_ACCTDMA) == 0)
1567 /* Get all finished requests */
1568 CESA_LOCK(sc, requests);
1569 STAILQ_INIT(&requests);
1570 STAILQ_CONCAT(&requests, &sc->sc_queued_requests);
1571 STAILQ_INIT(&sc->sc_queued_requests);
1572 CESA_UNLOCK(sc, requests);
1574 /* Execute all ready requests */
1577 /* Process completed requests */
1578 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_POSTREAD |
1579 BUS_DMASYNC_POSTWRITE);
1581 STAILQ_FOREACH_SAFE(cr, &requests, cr_stq, tmp) {
1582 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap,
1583 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1585 cr->cr_crp->crp_etype = sc->sc_error;
1587 crypto_copyback(cr->cr_crp->crp_flags,
1588 cr->cr_crp->crp_buf, cr->cr_mac->crd_inject,
1589 cr->cr_cs->cs_hlen, cr->cr_csd->csd_hash);
1591 crypto_done(cr->cr_crp);
1592 cesa_free_request(sc, cr);
1595 cesa_sync_dma_mem(&sc->sc_requests_cdm, BUS_DMASYNC_PREREAD |
1596 BUS_DMASYNC_PREWRITE);
1600 /* Unblock driver if it ran out of resources */
1602 blocked = sc->sc_blocked;
1604 CESA_UNLOCK(sc, sc);
1607 crypto_unblock(sc->sc_cid, blocked);
1611 cesa_newsession(device_t dev, uint32_t *sidp, struct cryptoini *cri)
1613 struct cesa_session *cs;
1614 struct cesa_softc *sc;
1615 struct cryptoini *enc;
1616 struct cryptoini *mac;
1619 sc = device_get_softc(dev);
1624 /* Check and parse input */
1625 if (cesa_is_hash(cri->cri_alg))
1630 cri = cri->cri_next;
1633 if (!enc && !cesa_is_hash(cri->cri_alg))
1636 if (!mac && cesa_is_hash(cri->cri_alg))
1639 if (cri->cri_next || !(enc && mac))
1643 if ((enc && (enc->cri_klen / 8) > CESA_MAX_KEY_LEN) ||
1644 (mac && (mac->cri_klen / 8) > CESA_MAX_MKEY_LEN))
1647 /* Allocate session */
1648 cs = cesa_alloc_session(sc);
1652 /* Prepare CESA configuration */
1658 switch (enc->cri_alg) {
1659 case CRYPTO_AES_CBC:
1660 cs->cs_config |= CESA_CSHD_AES | CESA_CSHD_CBC;
1661 cs->cs_ivlen = AES_BLOCK_LEN;
1663 case CRYPTO_DES_CBC:
1664 cs->cs_config |= CESA_CSHD_DES | CESA_CSHD_CBC;
1665 cs->cs_ivlen = DES_BLOCK_LEN;
1667 case CRYPTO_3DES_CBC:
1668 cs->cs_config |= CESA_CSHD_3DES | CESA_CSHD_3DES_EDE |
1670 cs->cs_ivlen = DES3_BLOCK_LEN;
1678 if (!error && mac) {
1679 switch (mac->cri_alg) {
1682 cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN :
1684 cs->cs_config |= CESA_CSHD_MD5;
1686 case CRYPTO_MD5_HMAC:
1687 cs->cs_mblen = MD5_HMAC_BLOCK_LEN;
1688 cs->cs_hlen = (mac->cri_mlen == 0) ? MD5_HASH_LEN :
1690 cs->cs_config |= CESA_CSHD_MD5_HMAC;
1691 if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN)
1692 cs->cs_config |= CESA_CSHD_96_BIT_HMAC;
1696 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN :
1698 cs->cs_config |= CESA_CSHD_SHA1;
1700 case CRYPTO_SHA1_HMAC:
1701 cs->cs_mblen = SHA1_HMAC_BLOCK_LEN;
1702 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA1_HASH_LEN :
1704 cs->cs_config |= CESA_CSHD_SHA1_HMAC;
1705 if (cs->cs_hlen == CESA_HMAC_TRUNC_LEN)
1706 cs->cs_config |= CESA_CSHD_96_BIT_HMAC;
1708 case CRYPTO_SHA2_256_HMAC:
1709 cs->cs_mblen = SHA2_256_HMAC_BLOCK_LEN;
1710 cs->cs_hlen = (mac->cri_mlen == 0) ? SHA2_256_HASH_LEN :
1712 cs->cs_config |= CESA_CSHD_SHA2_256_HMAC;
1720 /* Save cipher key */
1721 if (!error && enc && enc->cri_key) {
1722 cs->cs_klen = enc->cri_klen / 8;
1723 memcpy(cs->cs_key, enc->cri_key, cs->cs_klen);
1724 if (enc->cri_alg == CRYPTO_AES_CBC)
1725 error = cesa_prep_aes_key(cs);
1728 /* Save digest key */
1729 if (!error && mac && mac->cri_key)
1730 error = cesa_set_mkey(cs, mac->cri_alg, mac->cri_key,
1734 cesa_free_session(sc, cs);
1744 cesa_freesession(device_t dev, uint64_t tid)
1746 struct cesa_session *cs;
1747 struct cesa_softc *sc;
1749 sc = device_get_softc(dev);
1750 cs = cesa_get_session(sc, CRYPTO_SESID2LID(tid));
1755 cesa_free_session(sc, cs);
1761 cesa_process(device_t dev, struct cryptop *crp, int hint)
1763 struct cesa_request *cr;
1764 struct cesa_session *cs;
1765 struct cryptodesc *crd;
1766 struct cryptodesc *enc;
1767 struct cryptodesc *mac;
1768 struct cesa_softc *sc;
1771 sc = device_get_softc(dev);
1772 crd = crp->crp_desc;
1777 /* Check session ID */
1778 cs = cesa_get_session(sc, CRYPTO_SESID2LID(crp->crp_sid));
1780 crp->crp_etype = EINVAL;
1785 /* Check and parse input */
1786 if (crp->crp_ilen > CESA_MAX_REQUEST_SIZE) {
1787 crp->crp_etype = E2BIG;
1792 if (cesa_is_hash(crd->crd_alg))
1797 crd = crd->crd_next;
1800 if (!enc && !cesa_is_hash(crd->crd_alg))
1803 if (!mac && cesa_is_hash(crd->crd_alg))
1806 if (crd->crd_next || !(enc && mac)) {
1807 crp->crp_etype = EINVAL;
1814 * Get request descriptor. Block driver if there is no free
1815 * descriptors in pool.
1817 cr = cesa_alloc_request(sc);
1820 sc->sc_blocked = CRYPTO_SYMQ;
1821 CESA_UNLOCK(sc, sc);
1825 /* Prepare request */
1831 CESA_LOCK(sc, sessions);
1832 cesa_sync_desc(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1834 if (enc && enc->crd_flags & CRD_F_ENCRYPT) {
1835 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1836 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen);
1838 arc4rand(cr->cr_csd->csd_iv, cs->cs_ivlen, 0);
1840 if ((enc->crd_flags & CRD_F_IV_PRESENT) == 0)
1841 crypto_copyback(crp->crp_flags, crp->crp_buf,
1842 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv);
1844 if (enc->crd_flags & CRD_F_IV_EXPLICIT)
1845 memcpy(cr->cr_csd->csd_iv, enc->crd_iv, cs->cs_ivlen);
1847 crypto_copydata(crp->crp_flags, crp->crp_buf,
1848 enc->crd_inject, cs->cs_ivlen, cr->cr_csd->csd_iv);
1851 if (enc && enc->crd_flags & CRD_F_KEY_EXPLICIT) {
1852 if ((enc->crd_klen / 8) <= CESA_MAX_KEY_LEN) {
1853 cs->cs_klen = enc->crd_klen / 8;
1854 memcpy(cs->cs_key, enc->crd_key, cs->cs_klen);
1855 if (enc->crd_alg == CRYPTO_AES_CBC)
1856 error = cesa_prep_aes_key(cs);
1861 if (!error && mac && mac->crd_flags & CRD_F_KEY_EXPLICIT) {
1862 if ((mac->crd_klen / 8) <= CESA_MAX_MKEY_LEN)
1863 error = cesa_set_mkey(cs, mac->crd_alg, mac->crd_key,
1869 /* Convert request to chain of TDMA and SA descriptors */
1871 error = cesa_create_chain(sc, cr);
1873 cesa_sync_desc(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1874 CESA_UNLOCK(sc, sessions);
1877 cesa_free_request(sc, cr);
1878 crp->crp_etype = error;
1883 bus_dmamap_sync(sc->sc_data_dtag, cr->cr_dmap, BUS_DMASYNC_PREREAD |
1884 BUS_DMASYNC_PREWRITE);
1886 /* Enqueue request to execution */
1887 cesa_enqueue_request(sc, cr);
1889 /* Start execution, if we have no more requests in queue */
1890 if ((hint & CRYPTO_HINT_MORE) == 0)