2 * Copyright (C) 2009-2011 Semihalf.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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12 * documentation and/or other materials provided with the distribution.
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32 /* Maximum number of allocated sessions */
33 #define CESA_SESSIONS 64
35 /* Maximum number of queued requests */
36 #define CESA_REQUESTS 256
39 * CESA is able to process data only in CESA SRAM, which is quite small (2 kB).
40 * We have to fit a packet there, which contains SA descriptor, keys, IV
41 * and data to be processed. Every request must be converted into chain of
42 * packets and each packet can hold about 1.75 kB of data.
44 * To process each packet we need at least 1 SA descriptor and at least 4 TDMA
45 * descriptors. However there are cases when we use 2 SA and 8 TDMA descriptors
46 * per packet. Number of used TDMA descriptors can increase beyond given values
47 * if data in the request is fragmented in physical memory.
49 * The driver uses preallocated SA and TDMA descriptors pools to get best
50 * performace. Size of these pools should match expected request size. Example:
52 * Expected average request size: 1.5 kB (Ethernet MTU)
53 * Packets per average request: (1.5 kB / 1.75 kB) = 1
54 * SA decriptors per average request (worst case): 1 * 2 = 2
55 * TDMA desctiptors per average request (worst case): 1 * 8 = 8
57 * More TDMA descriptors should be allocated, if data fragmentation is expected
58 * (for example while processing mbufs larger than MCLBYTES). The driver may use
59 * 2 additional TDMA descriptors per each discontinuity in the physical data
63 /* Values below are optimized for requests containing about 1.5 kB of data */
64 #define CESA_SA_DESC_PER_REQ 2
65 #define CESA_TDMA_DESC_PER_REQ 8
67 #define CESA_SA_DESCRIPTORS (CESA_SA_DESC_PER_REQ * CESA_REQUESTS)
68 #define CESA_TDMA_DESCRIPTORS (CESA_TDMA_DESC_PER_REQ * CESA_REQUESTS)
70 /* Useful constants */
71 #define CESA_HMAC_TRUNC_LEN 12
72 #define CESA_MAX_FRAGMENTS 64
73 #define CESA_SRAM_SIZE 2048
76 * CESA_MAX_HASH_LEN is maximum length of hash generated by CESA.
77 * As CESA supports MD5, SHA1 and SHA-256 this equals to 32 bytes.
79 #define CESA_MAX_HASH_LEN 32
80 #define CESA_MAX_KEY_LEN 32
81 #define CESA_MAX_IV_LEN 16
82 #define CESA_MAX_HMAC_BLOCK_LEN 64
83 #define CESA_MAX_MKEY_LEN CESA_MAX_HMAC_BLOCK_LEN
84 #define CESA_MAX_PACKET_SIZE (CESA_SRAM_SIZE - CESA_DATA(0))
85 #define CESA_MAX_REQUEST_SIZE 65535
88 #define CESA_LOCK(sc, what) mtx_lock(&(sc)->sc_ ## what ## _lock)
89 #define CESA_UNLOCK(sc, what) mtx_unlock(&(sc)->sc_ ## what ## _lock)
90 #define CESA_LOCK_ASSERT(sc, what) \
91 mtx_assert(&(sc)->sc_ ## what ## _lock, MA_OWNED)
93 /* Registers read/write macros */
94 #define CESA_REG_READ(sc, reg) \
95 bus_read_4((sc)->sc_res[RES_CESA_REGS], (reg))
96 #define CESA_REG_WRITE(sc, reg, val) \
97 bus_write_4((sc)->sc_res[RES_CESA_REGS], (reg), (val))
99 #define CESA_TDMA_READ(sc, reg) \
100 bus_read_4((sc)->sc_res[RES_TDMA_REGS], (reg))
101 #define CESA_TDMA_WRITE(sc, reg, val) \
102 bus_write_4((sc)->sc_res[RES_TDMA_REGS], (reg), (val))
104 /* Generic allocator for objects */
105 #define CESA_GENERIC_ALLOC_LOCKED(sc, obj, pool) do { \
106 CESA_LOCK(sc, pool); \
108 if (STAILQ_EMPTY(&(sc)->sc_free_ ## pool)) \
111 obj = STAILQ_FIRST(&(sc)->sc_free_ ## pool); \
112 STAILQ_REMOVE_HEAD(&(sc)->sc_free_ ## pool, \
116 CESA_UNLOCK(sc, pool); \
119 #define CESA_GENERIC_FREE_LOCKED(sc, obj, pool) do { \
120 CESA_LOCK(sc, pool); \
121 STAILQ_INSERT_TAIL(&(sc)->sc_free_ ## pool, obj, \
123 CESA_UNLOCK(sc, pool); \
126 /* CESA SRAM offset calculation macros */
127 #define CESA_SA_DATA(member) \
128 (sizeof(struct cesa_sa_hdesc) + offsetof(struct cesa_sa_data, member))
129 #define CESA_DATA(offset) \
130 (sizeof(struct cesa_sa_hdesc) + sizeof(struct cesa_sa_data) + offset)
132 /* CESA memory and IRQ resources */
140 struct cesa_tdma_hdesc {
141 uint16_t cthd_byte_count;
148 struct cesa_sa_hdesc {
149 uint32_t cshd_config;
150 uint16_t cshd_enc_src;
151 uint16_t cshd_enc_dst;
152 uint32_t cshd_enc_dlen;
153 uint32_t cshd_enc_key;
154 uint16_t cshd_enc_iv;
155 uint16_t cshd_enc_iv_buf;
156 uint16_t cshd_mac_src;
157 uint16_t cshd_mac_total_dlen;
158 uint16_t cshd_mac_dst;
159 uint16_t cshd_mac_dlen;
160 uint16_t cshd_mac_iv_in;
161 uint16_t cshd_mac_iv_out;
164 struct cesa_sa_data {
165 uint8_t csd_key[CESA_MAX_KEY_LEN];
166 uint8_t csd_iv[CESA_MAX_IV_LEN];
167 uint8_t csd_hiv_in[CESA_MAX_HASH_LEN];
168 uint8_t csd_hiv_out[CESA_MAX_HASH_LEN];
169 uint8_t csd_hash[CESA_MAX_HASH_LEN];
172 struct cesa_dma_mem {
174 bus_addr_t cdm_paddr;
175 bus_dma_tag_t cdm_tag;
176 bus_dmamap_t cdm_map;
179 struct cesa_tdma_desc {
180 struct cesa_tdma_hdesc *ctd_cthd;
181 bus_addr_t ctd_cthd_paddr;
183 STAILQ_ENTRY(cesa_tdma_desc) ctd_stq;
186 struct cesa_sa_desc {
187 struct cesa_sa_hdesc *csd_cshd;
188 bus_addr_t csd_cshd_paddr;
190 STAILQ_ENTRY(cesa_sa_desc) csd_stq;
193 struct cesa_session {
196 unsigned int cs_klen;
197 unsigned int cs_ivlen;
198 unsigned int cs_hlen;
199 unsigned int cs_mblen;
200 uint8_t cs_key[CESA_MAX_KEY_LEN];
201 uint8_t cs_aes_dkey[CESA_MAX_KEY_LEN];
202 uint8_t cs_hiv_in[CESA_MAX_HASH_LEN];
203 uint8_t cs_hiv_out[CESA_MAX_HASH_LEN];
205 STAILQ_ENTRY(cesa_session) cs_stq;
208 struct cesa_request {
209 struct cesa_sa_data *cr_csd;
210 bus_addr_t cr_csd_paddr;
211 struct cryptop *cr_crp;
212 struct cryptodesc *cr_enc;
213 struct cryptodesc *cr_mac;
214 struct cesa_session *cr_cs;
215 bus_dmamap_t cr_dmap;
218 STAILQ_HEAD(, cesa_tdma_desc) cr_tdesc;
219 STAILQ_HEAD(, cesa_sa_desc) cr_sdesc;
221 STAILQ_ENTRY(cesa_request) cr_stq;
225 STAILQ_HEAD(, cesa_tdma_desc) cp_copyin;
226 STAILQ_HEAD(, cesa_tdma_desc) cp_copyout;
227 unsigned int cp_size;
228 unsigned int cp_offset;
235 struct resource *sc_res[RES_CESA_NUM];
237 bus_dma_tag_t sc_data_dtag;
241 struct mtx sc_sc_lock;
244 /* TDMA descriptors pool */
245 struct mtx sc_tdesc_lock;
246 struct cesa_tdma_desc sc_tdesc[CESA_TDMA_DESCRIPTORS];
247 struct cesa_dma_mem sc_tdesc_cdm;
248 STAILQ_HEAD(, cesa_tdma_desc) sc_free_tdesc;
250 /* SA descriptors pool */
251 struct mtx sc_sdesc_lock;
252 struct cesa_sa_desc sc_sdesc[CESA_SA_DESCRIPTORS];
253 struct cesa_dma_mem sc_sdesc_cdm;
254 STAILQ_HEAD(, cesa_sa_desc) sc_free_sdesc;
257 struct mtx sc_requests_lock;
258 struct cesa_request sc_requests[CESA_REQUESTS];
259 struct cesa_dma_mem sc_requests_cdm;
260 STAILQ_HEAD(, cesa_request) sc_free_requests;
261 STAILQ_HEAD(, cesa_request) sc_ready_requests;
262 STAILQ_HEAD(, cesa_request) sc_queued_requests;
265 struct mtx sc_sessions_lock;
266 struct cesa_session sc_sessions[CESA_SESSIONS];
267 STAILQ_HEAD(, cesa_session) sc_free_sessions;
269 /* CESA SRAM Address */
270 bus_addr_t sc_sram_base_pa;
271 vm_offset_t sc_sram_base_va;
272 bus_size_t sc_sram_size;
275 struct cesa_chain_info {
276 struct cesa_softc *cci_sc;
277 struct cesa_request *cci_cr;
278 struct cryptodesc *cci_enc;
279 struct cryptodesc *cci_mac;
284 /* CESA descriptors flags definitions */
285 #define CESA_CTHD_OWNED (1 << 15)
287 #define CESA_CSHD_MAC (0 << 0)
288 #define CESA_CSHD_ENC (1 << 0)
289 #define CESA_CSHD_MAC_AND_ENC (2 << 0)
290 #define CESA_CSHD_ENC_AND_MAC (3 << 0)
291 #define CESA_CSHD_OP_MASK (3 << 0)
293 #define CESA_CSHD_MD5 (4 << 4)
294 #define CESA_CSHD_SHA1 (5 << 4)
295 #define CESA_CSHD_SHA2_256 (1 << 4)
296 #define CESA_CSHD_MD5_HMAC (6 << 4)
297 #define CESA_CSHD_SHA1_HMAC (7 << 4)
298 #define CESA_CSHD_SHA2_256_HMAC (3 << 4)
300 #define CESA_CSHD_96_BIT_HMAC (1 << 7)
302 #define CESA_CSHD_DES (1 << 8)
303 #define CESA_CSHD_3DES (2 << 8)
304 #define CESA_CSHD_AES (3 << 8)
306 #define CESA_CSHD_DECRYPT (1 << 12)
307 #define CESA_CSHD_CBC (1 << 16)
308 #define CESA_CSHD_3DES_EDE (1 << 20)
310 #define CESA_CSH_AES_KLEN_128 (0 << 24)
311 #define CESA_CSH_AES_KLEN_192 (1 << 24)
312 #define CESA_CSH_AES_KLEN_256 (2 << 24)
313 #define CESA_CSH_AES_KLEN_MASK (3 << 24)
315 #define CESA_CSHD_FRAG_FIRST (1 << 30)
316 #define CESA_CSHD_FRAG_LAST (2U << 30)
317 #define CESA_CSHD_FRAG_MIDDLE (3U << 30)
319 /* CESA registers definitions */
320 #define CESA_ICR 0x0E20
321 #define CESA_ICR_ACCTDMA (1 << 7)
322 #define CESA_ICR_TPERR (1 << 12)
324 #define CESA_ICM 0x0E24
325 #define CESA_ICM_ACCTDMA CESA_ICR_ACCTDMA
326 #define CESA_ICM_TPERR CESA_ICR_TPERR
328 /* CESA TDMA registers definitions */
329 #define CESA_TDMA_ND 0x0830
331 #define CESA_TDMA_CR 0x0840
332 #define CESA_TDMA_CR_DBL128 (4 << 0)
333 #define CESA_TDMA_CR_ORDEN (1 << 4)
334 #define CESA_TDMA_CR_SBL128 (4 << 6)
335 #define CESA_TDMA_CR_NBS (1 << 11)
336 #define CESA_TDMA_CR_ENABLE (1 << 12)
337 #define CESA_TDMA_CR_FETCHND (1 << 13)
338 #define CESA_TDMA_CR_ACTIVE (1 << 14)
339 #define CESA_TDMA_NUM_OUTSTAND (2 << 16)
341 #define CESA_TDMA_ECR 0x08C8
342 #define CESA_TDMA_ECR_MISS (1 << 0)
343 #define CESA_TDMA_ECR_DOUBLE_HIT (1 << 1)
344 #define CESA_TDMA_ECR_BOTH_HIT (1 << 2)
345 #define CESA_TDMA_ECR_DATA_ERROR (1 << 3)
347 #define CESA_TDMA_EMR 0x08CC
348 #define CESA_TDMA_EMR_MISS CESA_TDMA_ECR_MISS
349 #define CESA_TDMA_EMR_DOUBLE_HIT CESA_TDMA_ECR_DOUBLE_HIT
350 #define CESA_TDMA_EMR_BOTH_HIT CESA_TDMA_ECR_BOTH_HIT
351 #define CESA_TDMA_EMR_DATA_ERROR CESA_TDMA_ECR_DATA_ERROR
353 /* CESA SA registers definitions */
354 #define CESA_SA_CMD 0x0E00
355 #define CESA_SA_CMD_ACTVATE (1 << 0)
356 #define CESA_SA_CMD_SHA2 (1 << 31)
358 #define CESA_SA_DPR 0x0E04
360 #define CESA_SA_CR 0x0E08
361 #define CESA_SA_CR_WAIT_FOR_TDMA (1 << 7)
362 #define CESA_SA_CR_ACTIVATE_TDMA (1 << 9)
363 #define CESA_SA_CR_MULTI_MODE (1 << 11)
365 #define CESA_SA_SR 0x0E0C
366 #define CESA_SA_SR_ACTIVE (1 << 0)