2 * Copyright (c) 2007, Juniper Networks, Inc.
3 * Copyright (c) 2012-2013, SRI International
6 * Portions of this software were developed by SRI International and the
7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
8 * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
45 #include <sys/endian.h>
47 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
51 #include <sys/sysctl.h>
53 #include <machine/bus.h>
55 #include <dev/cfi/cfi_reg.h>
56 #include <dev/cfi/cfi_var.h>
58 static void cfi_add_sysctls(struct cfi_softc *);
60 extern struct cdevsw cfi_cdevsw;
62 char cfi_driver_name[] = "cfi";
63 devclass_t cfi_devclass;
64 devclass_t cfi_diskclass;
67 cfi_read_raw(struct cfi_softc *sc, u_int ofs)
71 ofs &= ~(sc->sc_width - 1);
72 switch (sc->sc_width) {
74 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
77 val = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
80 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
90 cfi_read(struct cfi_softc *sc, u_int ofs)
95 ofs &= ~(sc->sc_width - 1);
96 switch (sc->sc_width) {
98 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
101 sval = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
105 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
116 cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
119 ofs &= ~(sc->sc_width - 1);
120 switch (sc->sc_width) {
122 bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
125 bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, htole16(val));
128 bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, htole32(val));
134 cfi_read_qry(struct cfi_softc *sc, u_int ofs)
138 cfi_write(sc, CFI_QRY_CMD_ADDR * sc->sc_width, CFI_QRY_CMD_DATA);
139 val = cfi_read(sc, ofs * sc->sc_width);
140 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
145 cfi_amd_write(struct cfi_softc *sc, u_int ofs, u_int addr, u_int data)
148 cfi_write(sc, ofs + AMD_ADDR_START, CFI_AMD_UNLOCK);
149 cfi_write(sc, ofs + AMD_ADDR_ACK, CFI_AMD_UNLOCK_ACK);
150 cfi_write(sc, ofs + addr, data);
154 cfi_fmtsize(uint32_t sz)
157 static const char *sfx[] = { "", "K", "M", "G" };
161 while (sfxidx < 3 && sz > 1023) {
166 sprintf(buf, "%u%sB", sz, sfx[sfxidx]);
171 cfi_probe(device_t dev)
174 struct cfi_softc *sc;
177 uint16_t iface, vend;
179 sc = device_get_softc(dev);
183 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
185 if (sc->sc_res == NULL)
188 sc->sc_tag = rman_get_bustag(sc->sc_res);
189 sc->sc_handle = rman_get_bushandle(sc->sc_res);
191 if (sc->sc_width == 0) {
193 while (sc->sc_width <= 4) {
194 if (cfi_read_qry(sc, CFI_QRY_IDENT) == 'Q')
198 } else if (cfi_read_qry(sc, CFI_QRY_IDENT) != 'Q') {
202 if (sc->sc_width > 4) {
207 /* We got a Q. Check if we also have the R and the Y. */
208 if (cfi_read_qry(sc, CFI_QRY_IDENT + 1) != 'R' ||
209 cfi_read_qry(sc, CFI_QRY_IDENT + 2) != 'Y') {
214 /* Get the vendor and command set. */
215 vend = cfi_read_qry(sc, CFI_QRY_VEND) |
216 (cfi_read_qry(sc, CFI_QRY_VEND + 1) << 8);
218 sc->sc_cmdset = vend;
221 case CFI_VEND_AMD_ECS:
222 case CFI_VEND_AMD_SCS:
223 vend_str = "AMD/Fujitsu";
225 case CFI_VEND_INTEL_ECS:
226 vend_str = "Intel/Sharp";
228 case CFI_VEND_INTEL_SCS:
231 case CFI_VEND_MITSUBISHI_ECS:
232 case CFI_VEND_MITSUBISHI_SCS:
233 vend_str = "Mitsubishi";
236 vend_str = "Unknown vendor";
240 /* Get the device size. */
241 sc->sc_size = 1U << cfi_read_qry(sc, CFI_QRY_SIZE);
243 /* Sanity-check the I/F */
244 iface = cfi_read_qry(sc, CFI_QRY_IFACE) |
245 (cfi_read_qry(sc, CFI_QRY_IFACE + 1) << 8);
248 * Adding 1 to iface will give us a bit-wise "switch"
249 * that allows us to test for the interface width by
250 * testing a single bit.
254 error = (iface & sc->sc_width) ? 0 : EINVAL;
258 snprintf(desc, sizeof(desc), "%s - %s", vend_str,
259 cfi_fmtsize(sc->sc_size));
260 device_set_desc_copy(dev, desc);
263 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
268 cfi_attach(device_t dev)
270 struct cfi_softc *sc;
273 uint64_t mtoexp, ttoexp;
274 #ifdef CFI_SUPPORT_STRATAFLASH
276 char name[KENV_MNAMELEN], value[32];
279 sc = device_get_softc(dev);
283 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
284 #ifndef ATSE_CFI_HACK
287 RF_ACTIVE | RF_SHAREABLE);
289 if (sc->sc_res == NULL)
292 sc->sc_tag = rman_get_bustag(sc->sc_res);
293 sc->sc_handle = rman_get_bushandle(sc->sc_res);
295 /* Get time-out values for erase, write, and buffer write. */
296 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_ERASE);
297 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_ERASE);
299 device_printf(dev, "erase timeout == 0, using 2^16ms\n");
303 device_printf(dev, "insane timeout: 2^%jdms\n", ttoexp);
307 device_printf(dev, "max erase timeout == 0, using 2^%jdms\n",
311 if (ttoexp + mtoexp > 41) {
312 device_printf(dev, "insane max erase timeout: 2^%jd\n",
316 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] = SBT_1MS * (1ULL << ttoexp);
317 sc->sc_max_timeouts[CFI_TIMEOUT_ERASE] =
318 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] * (1ULL << mtoexp);
320 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_WRITE);
321 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_WRITE);
323 device_printf(dev, "write timeout == 0, using 2^18ns\n");
327 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
331 device_printf(dev, "max write timeout == 0, using 2^%jdms\n",
335 if (ttoexp + mtoexp > 51) {
336 device_printf(dev, "insane max write timeout: 2^%jdus\n",
340 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] = SBT_1US * (1ULL << ttoexp);
341 sc->sc_max_timeouts[CFI_TIMEOUT_WRITE] =
342 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] * (1ULL << mtoexp);
344 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE);
345 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE);
346 /* Don't check for 0, it means not-supported. */
348 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
351 if (ttoexp + mtoexp > 51) {
352 device_printf(dev, "insane max write timeout: 2^%jdus\n",
356 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] =
357 SBT_1US * (1ULL << cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE));
358 sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE] =
359 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] *
360 (1ULL << cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE));
362 /* Get the maximum size of a multibyte program */
363 if (sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] != 0)
364 sc->sc_maxbuf = 1 << (cfi_read_qry(sc, CFI_QRY_MAXBUF) |
365 cfi_read_qry(sc, CFI_QRY_MAXBUF) << 8);
369 /* Get erase regions. */
370 sc->sc_regions = cfi_read_qry(sc, CFI_QRY_NREGIONS);
371 sc->sc_region = malloc(sc->sc_regions * sizeof(struct cfi_region),
372 M_TEMP, M_WAITOK | M_ZERO);
373 for (r = 0; r < sc->sc_regions; r++) {
374 blocks = cfi_read_qry(sc, CFI_QRY_REGION(r)) |
375 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 1) << 8);
376 sc->sc_region[r].r_blocks = blocks + 1;
378 blksz = cfi_read_qry(sc, CFI_QRY_REGION(r) + 2) |
379 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 3) << 8);
380 sc->sc_region[r].r_blksz = (blksz == 0) ? 128 :
384 /* Reset the device to a default state. */
385 cfi_write(sc, 0, CFI_BCS_CLEAR_STATUS);
388 device_printf(dev, "[");
389 for (r = 0; r < sc->sc_regions; r++) {
390 printf("%ux%s%s", sc->sc_region[r].r_blocks,
391 cfi_fmtsize(sc->sc_region[r].r_blksz),
392 (r == sc->sc_regions - 1) ? "]\n" : ",");
396 u = device_get_unit(dev);
397 sc->sc_nod = make_dev(&cfi_cdevsw, u, UID_ROOT, GID_WHEEL, 0600,
398 "%s%u", cfi_driver_name, u);
399 sc->sc_nod->si_drv1 = sc;
403 #ifdef CFI_SUPPORT_STRATAFLASH
405 * Store the Intel factory PPR in the environment. In some
406 * cases it is the most unique ID on a board.
408 if (cfi_intel_get_factory_pr(sc, &ppr) == 0) {
409 if (snprintf(name, sizeof(name), "%s.factory_ppr",
410 device_get_nameunit(dev)) < (sizeof(name) - 1) &&
411 snprintf(value, sizeof(value), "0x%016jx", ppr) <
413 (void) setenv(name, value);
417 device_add_child(dev, "cfid", -1);
418 bus_generic_attach(dev);
424 cfi_add_sysctls(struct cfi_softc *sc)
426 struct sysctl_ctx_list *ctx;
427 struct sysctl_oid_list *children;
429 ctx = device_get_sysctl_ctx(sc->sc_dev);
430 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
432 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
433 "typical_erase_timout_count",
434 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_ERASE],
435 0, "Number of times the typical erase timeout was exceeded");
436 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
437 "max_erase_timout_count",
438 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_ERASE], 0,
439 "Number of times the maximum erase timeout was exceeded");
440 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
441 "typical_write_timout_count",
442 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_WRITE], 0,
443 "Number of times the typical write timeout was exceeded");
444 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
445 "max_write_timout_count",
446 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_WRITE], 0,
447 "Number of times the maximum write timeout was exceeded");
448 if (sc->sc_maxbuf > 0) {
449 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
450 "typical_bufwrite_timout_count",
451 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_BUFWRITE], 0,
452 "Number of times the typical buffered write timeout was "
454 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
455 "max_bufwrite_timout_count",
456 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_BUFWRITE], 0,
457 "Number of times the maximum buffered write timeout was "
463 cfi_detach(device_t dev)
465 struct cfi_softc *sc;
467 sc = device_get_softc(dev);
469 destroy_dev(sc->sc_nod);
470 free(sc->sc_region, M_TEMP);
471 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
476 cfi_wait_ready(struct cfi_softc *sc, u_int ofs, sbintime_t start,
477 enum cfi_wait_cmd cmd)
479 int done, error, tto_exceeded;
480 uint32_t st0 = 0, st = 0;
486 while (!done && !error) {
488 * Save time before we start so we always do one check
489 * after the timeout has expired.
493 switch (sc->sc_cmdset) {
494 case CFI_VEND_INTEL_ECS:
495 case CFI_VEND_INTEL_SCS:
496 st = cfi_read(sc, ofs);
497 done = (st & CFI_INTEL_STATUS_WSMS);
499 /* NB: bit 0 is reserved */
500 st &= ~(CFI_INTEL_XSTATUS_RSVD |
501 CFI_INTEL_STATUS_WSMS |
502 CFI_INTEL_STATUS_RSVD);
503 if (st & CFI_INTEL_STATUS_DPS)
505 else if (st & CFI_INTEL_STATUS_PSLBS)
507 else if (st & CFI_INTEL_STATUS_ECLBS)
513 case CFI_VEND_AMD_SCS:
514 case CFI_VEND_AMD_ECS:
515 st0 = cfi_read(sc, ofs);
516 st = cfi_read(sc, ofs);
517 done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
522 now > start + sc->sc_typical_timeouts[cmd]) {
525 sc->sc_tto_counts[cmd]++;
526 #ifdef CFI_DEBUG_TIMEOUT
527 device_printf(sc->sc_dev,
528 "typical timeout exceeded (cmd %d)", cmd);
531 if (now > start + sc->sc_max_timeouts[cmd]) {
532 sc->sc_mto_counts[cmd]++;
533 #ifdef CFI_DEBUG_TIMEOUT
534 device_printf(sc->sc_dev,
535 "max timeout exceeded (cmd %d)", cmd);
543 printf("\nerror=%d (st 0x%x st0 0x%x)\n", error, st, st0);
548 cfi_write_block(struct cfi_softc *sc)
556 int error, i, neederase = 0;
561 /* Intel flash must be unlocked before modification */
562 switch (sc->sc_cmdset) {
563 case CFI_VEND_INTEL_ECS:
564 case CFI_VEND_INTEL_SCS:
565 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
566 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_UB);
567 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
571 /* Check if an erase is required. */
572 for (i = 0; i < sc->sc_wrbufsz; i++)
573 if ((sc->sc_wrbuf[i] & sc->sc_wrbufcpy[i]) != sc->sc_wrbuf[i]) {
579 intr = intr_disable();
580 start = sbinuptime();
581 /* Erase the block. */
582 switch (sc->sc_cmdset) {
583 case CFI_VEND_INTEL_ECS:
584 case CFI_VEND_INTEL_SCS:
585 cfi_write(sc, sc->sc_wrofs, CFI_BCS_BLOCK_ERASE);
586 cfi_write(sc, sc->sc_wrofs, CFI_BCS_CONFIRM);
588 case CFI_VEND_AMD_SCS:
589 case CFI_VEND_AMD_ECS:
590 cfi_amd_write(sc, sc->sc_wrofs, AMD_ADDR_START,
591 CFI_AMD_ERASE_SECTOR);
592 cfi_amd_write(sc, sc->sc_wrofs, 0, CFI_AMD_BLOCK_ERASE);
595 /* Better safe than sorry... */
600 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
607 /* Write the block using a multibyte write if supported. */
608 ptr.x8 = sc->sc_wrbuf;
609 cpyprt.x8 = sc->sc_wrbufcpy;
610 if (sc->sc_maxbuf > sc->sc_width) {
611 switch (sc->sc_cmdset) {
612 case CFI_VEND_INTEL_ECS:
613 case CFI_VEND_INTEL_SCS:
614 for (i = 0; i < sc->sc_wrbufsz; i += wlen) {
615 wlen = MIN(sc->sc_maxbuf, sc->sc_wrbufsz - i);
617 intr = intr_disable();
619 start = sbinuptime();
621 cfi_write(sc, sc->sc_wrofs + i,
622 CFI_BCS_BUF_PROG_SETUP);
623 if (sbinuptime() > start + sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE]) {
627 st = cfi_read(sc, sc->sc_wrofs + i);
628 } while (! (st & CFI_INTEL_STATUS_WSMS));
630 cfi_write(sc, sc->sc_wrofs + i,
631 (wlen / sc->sc_width) - 1);
632 switch (sc->sc_width) {
634 bus_space_write_region_1(sc->sc_tag,
635 sc->sc_handle, sc->sc_wrofs + i,
639 bus_space_write_region_2(sc->sc_tag,
640 sc->sc_handle, sc->sc_wrofs + i,
641 ptr.x16 + i / 2, wlen / 2);
644 bus_space_write_region_4(sc->sc_tag,
645 sc->sc_handle, sc->sc_wrofs + i,
646 ptr.x32 + i / 4, wlen / 4);
650 cfi_write(sc, sc->sc_wrofs + i,
655 error = cfi_wait_ready(sc, sc->sc_wrofs + i,
656 start, CFI_TIMEOUT_BUFWRITE);
662 /* Fall through to single word case */
668 /* Write the block one byte/word at a time. */
669 for (i = 0; i < sc->sc_wrbufsz; i += sc->sc_width) {
671 /* Avoid writing unless we are actually changing bits */
673 switch (sc->sc_width) {
675 if(*(ptr.x8 + i) == *(cpyprt.x8 + i))
679 if(*(ptr.x16 + i / 2) == *(cpyprt.x16 + i / 2))
683 if(*(ptr.x32 + i / 4) == *(cpyprt.x32 + i / 4))
690 * Make sure the command to start a write and the
691 * actual write happens back-to-back without any
694 intr = intr_disable();
696 start = sbinuptime();
697 switch (sc->sc_cmdset) {
698 case CFI_VEND_INTEL_ECS:
699 case CFI_VEND_INTEL_SCS:
700 cfi_write(sc, sc->sc_wrofs + i, CFI_BCS_PROGRAM);
702 case CFI_VEND_AMD_SCS:
703 case CFI_VEND_AMD_ECS:
704 cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_PROGRAM);
707 switch (sc->sc_width) {
709 bus_space_write_1(sc->sc_tag, sc->sc_handle,
710 sc->sc_wrofs + i, *(ptr.x8 + i));
713 bus_space_write_2(sc->sc_tag, sc->sc_handle,
714 sc->sc_wrofs + i, *(ptr.x16 + i / 2));
717 bus_space_write_4(sc->sc_tag, sc->sc_handle,
718 sc->sc_wrofs + i, *(ptr.x32 + i / 4));
724 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
733 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
735 /* Relock Intel flash */
736 switch (sc->sc_cmdset) {
737 case CFI_VEND_INTEL_ECS:
738 case CFI_VEND_INTEL_SCS:
739 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
740 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LB);
741 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
747 #ifdef CFI_SUPPORT_STRATAFLASH
749 * Intel StrataFlash Protection Register Support.
751 * The memory includes a 128-bit Protection Register that can be
752 * used for security. There are two 64-bit segments; one is programmed
753 * at the factory with a unique 64-bit number which is immutable.
754 * The other segment is left blank for User (OEM) programming.
755 * The User/OEM segment is One Time Programmable (OTP). It can also
756 * be locked to prevent any further writes by setting bit 0 of the
757 * Protection Lock Register (PLR). The PLR can written only once.
761 cfi_get16(struct cfi_softc *sc, int off)
763 uint16_t v = bus_space_read_2(sc->sc_tag, sc->sc_handle, off<<1);
767 #ifdef CFI_ARMEDANDDANGEROUS
769 cfi_put16(struct cfi_softc *sc, int off, uint16_t v)
771 bus_space_write_2(sc->sc_tag, sc->sc_handle, off<<1, v);
776 * Read the factory-defined 64-bit segment of the PR.
779 cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *id)
781 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
783 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
785 cfi_write(sc, 0, CFI_INTEL_READ_ID);
786 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(0)))<<48 |
787 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(1)))<<32 |
788 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(2)))<<16 |
789 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(3)));
790 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
795 * Read the User/OEM 64-bit segment of the PR.
798 cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
800 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
802 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
804 cfi_write(sc, 0, CFI_INTEL_READ_ID);
805 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(4)))<<48 |
806 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(5)))<<32 |
807 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(6)))<<16 |
808 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(7)));
809 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
814 * Write the User/OEM 64-bit segment of the PR.
815 * XXX should allow writing individual words/bytes
818 cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
820 #ifdef CFI_ARMEDANDDANGEROUS
826 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
828 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
830 #ifdef CFI_ARMEDANDDANGEROUS
831 for (i = 7; i >= 4; i--, id >>= 16) {
832 intr = intr_disable();
833 start = sbinuptime();
834 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
835 cfi_put16(sc, CFI_INTEL_PR(i), id&0xffff);
837 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
842 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
845 device_printf(sc->sc_dev, "%s: OEM PR not set, "
846 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
852 * Read the contents of the Protection Lock Register.
855 cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *plr)
857 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
859 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
861 cfi_write(sc, 0, CFI_INTEL_READ_ID);
862 *plr = cfi_get16(sc, CFI_INTEL_PLR);
863 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
868 * Write the Protection Lock Register to lock down the
869 * user-settable segment of the Protection Register.
870 * NOTE: this operation is not reversible.
873 cfi_intel_set_plr(struct cfi_softc *sc)
875 #ifdef CFI_ARMEDANDDANGEROUS
880 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
882 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
884 #ifdef CFI_ARMEDANDDANGEROUS
885 /* worthy of console msg */
886 device_printf(sc->sc_dev, "set PLR\n");
887 intr = intr_disable();
889 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
890 cfi_put16(sc, CFI_INTEL_PLR, 0xFFFD);
892 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
894 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
897 device_printf(sc->sc_dev, "%s: PLR not set, "
898 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
902 #endif /* CFI_SUPPORT_STRATAFLASH */