2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 2007, Juniper Networks, Inc.
5 * Copyright (c) 2012-2013, SRI International
8 * Portions of this software were developed by SRI International and the
9 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
10 * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of the author nor the names of any co-contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
30 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
31 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
32 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
43 #include <sys/param.h>
44 #include <sys/systm.h>
47 #include <sys/endian.h>
49 #include <sys/kernel.h>
50 #include <sys/malloc.h>
51 #include <sys/module.h>
53 #include <sys/sysctl.h>
55 #include <machine/bus.h>
57 #include <dev/cfi/cfi_reg.h>
58 #include <dev/cfi/cfi_var.h>
60 static void cfi_add_sysctls(struct cfi_softc *);
62 extern struct cdevsw cfi_cdevsw;
64 char cfi_driver_name[] = "cfi";
65 devclass_t cfi_devclass;
66 devclass_t cfi_diskclass;
69 cfi_read_raw(struct cfi_softc *sc, u_int ofs)
73 ofs &= ~(sc->sc_width - 1);
74 switch (sc->sc_width) {
76 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
79 val = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
82 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
92 cfi_read(struct cfi_softc *sc, u_int ofs)
97 ofs &= ~(sc->sc_width - 1);
98 switch (sc->sc_width) {
100 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
103 sval = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
104 #ifdef CFI_HARDWAREBYTESWAP
111 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
112 #ifndef CFI_HARDWAREBYTESWAP
124 cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
127 ofs &= ~(sc->sc_width - 1);
128 switch (sc->sc_width) {
130 bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
133 #ifdef CFI_HARDWAREBYTESWAP
134 bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, val);
136 bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, htole16(val));
141 #ifdef CFI_HARDWAREBYTESWAP
142 bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, val);
144 bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, htole32(val));
151 * This is same workaound as NetBSD sys/dev/nor/cfi.c cfi_reset_default()
154 cfi_reset_default(struct cfi_softc *sc)
157 cfi_write(sc, 0, CFI_BCS_READ_ARRAY2);
158 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
162 cfi_read_qry(struct cfi_softc *sc, u_int ofs)
166 cfi_write(sc, CFI_QRY_CMD_ADDR * sc->sc_width, CFI_QRY_CMD_DATA);
167 val = cfi_read(sc, ofs * sc->sc_width);
168 cfi_reset_default(sc);
173 cfi_amd_write(struct cfi_softc *sc, u_int ofs, u_int addr, u_int data)
176 cfi_write(sc, ofs + AMD_ADDR_START, CFI_AMD_UNLOCK);
177 cfi_write(sc, ofs + AMD_ADDR_ACK, CFI_AMD_UNLOCK_ACK);
178 cfi_write(sc, ofs + addr, data);
182 cfi_fmtsize(uint32_t sz)
185 static const char *sfx[] = { "", "K", "M", "G" };
189 while (sfxidx < 3 && sz > 1023) {
194 sprintf(buf, "%u%sB", sz, sfx[sfxidx]);
199 cfi_probe(device_t dev)
202 struct cfi_softc *sc;
205 uint16_t iface, vend;
207 sc = device_get_softc(dev);
211 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
213 if (sc->sc_res == NULL)
216 sc->sc_tag = rman_get_bustag(sc->sc_res);
217 sc->sc_handle = rman_get_bushandle(sc->sc_res);
219 if (sc->sc_width == 0) {
221 while (sc->sc_width <= 4) {
222 if (cfi_read_qry(sc, CFI_QRY_IDENT) == 'Q')
226 } else if (cfi_read_qry(sc, CFI_QRY_IDENT) != 'Q') {
230 if (sc->sc_width > 4) {
235 /* We got a Q. Check if we also have the R and the Y. */
236 if (cfi_read_qry(sc, CFI_QRY_IDENT + 1) != 'R' ||
237 cfi_read_qry(sc, CFI_QRY_IDENT + 2) != 'Y') {
242 /* Get the vendor and command set. */
243 vend = cfi_read_qry(sc, CFI_QRY_VEND) |
244 (cfi_read_qry(sc, CFI_QRY_VEND + 1) << 8);
246 sc->sc_cmdset = vend;
249 case CFI_VEND_AMD_ECS:
250 case CFI_VEND_AMD_SCS:
251 vend_str = "AMD/Fujitsu";
253 case CFI_VEND_INTEL_ECS:
254 vend_str = "Intel/Sharp";
256 case CFI_VEND_INTEL_SCS:
259 case CFI_VEND_MITSUBISHI_ECS:
260 case CFI_VEND_MITSUBISHI_SCS:
261 vend_str = "Mitsubishi";
264 vend_str = "Unknown vendor";
268 /* Get the device size. */
269 sc->sc_size = 1U << cfi_read_qry(sc, CFI_QRY_SIZE);
271 /* Sanity-check the I/F */
272 iface = cfi_read_qry(sc, CFI_QRY_IFACE) |
273 (cfi_read_qry(sc, CFI_QRY_IFACE + 1) << 8);
276 * Adding 1 to iface will give us a bit-wise "switch"
277 * that allows us to test for the interface width by
278 * testing a single bit.
282 error = (iface & sc->sc_width) ? 0 : EINVAL;
286 snprintf(desc, sizeof(desc), "%s - %s", vend_str,
287 cfi_fmtsize(sc->sc_size));
288 device_set_desc_copy(dev, desc);
291 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
296 cfi_attach(device_t dev)
298 struct cfi_softc *sc;
301 uint64_t mtoexp, ttoexp;
302 #ifdef CFI_SUPPORT_STRATAFLASH
304 char name[KENV_MNAMELEN], value[32];
307 sc = device_get_softc(dev);
311 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
312 #ifndef ATSE_CFI_HACK
315 RF_ACTIVE | RF_SHAREABLE);
317 if (sc->sc_res == NULL)
320 sc->sc_tag = rman_get_bustag(sc->sc_res);
321 sc->sc_handle = rman_get_bushandle(sc->sc_res);
323 /* Get time-out values for erase, write, and buffer write. */
324 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_ERASE);
325 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_ERASE);
327 device_printf(dev, "erase timeout == 0, using 2^16ms\n");
331 device_printf(dev, "insane timeout: 2^%jdms\n", ttoexp);
335 device_printf(dev, "max erase timeout == 0, using 2^%jdms\n",
339 if (ttoexp + mtoexp > 41) {
340 device_printf(dev, "insane max erase timeout: 2^%jd\n",
344 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] = SBT_1MS * (1ULL << ttoexp);
345 sc->sc_max_timeouts[CFI_TIMEOUT_ERASE] =
346 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] * (1ULL << mtoexp);
348 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_WRITE);
349 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_WRITE);
351 device_printf(dev, "write timeout == 0, using 2^18ns\n");
355 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
359 device_printf(dev, "max write timeout == 0, using 2^%jdms\n",
363 if (ttoexp + mtoexp > 51) {
364 device_printf(dev, "insane max write timeout: 2^%jdus\n",
368 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] = SBT_1US * (1ULL << ttoexp);
369 sc->sc_max_timeouts[CFI_TIMEOUT_WRITE] =
370 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] * (1ULL << mtoexp);
372 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE);
373 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE);
374 /* Don't check for 0, it means not-supported. */
376 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
379 if (ttoexp + mtoexp > 51) {
380 device_printf(dev, "insane max write timeout: 2^%jdus\n",
384 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] =
385 SBT_1US * (1ULL << cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE));
386 sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE] =
387 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] *
388 (1ULL << cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE));
390 /* Get the maximum size of a multibyte program */
391 if (sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] != 0)
392 sc->sc_maxbuf = 1 << (cfi_read_qry(sc, CFI_QRY_MAXBUF) |
393 cfi_read_qry(sc, CFI_QRY_MAXBUF) << 8);
397 /* Get erase regions. */
398 sc->sc_regions = cfi_read_qry(sc, CFI_QRY_NREGIONS);
399 sc->sc_region = malloc(sc->sc_regions * sizeof(struct cfi_region),
400 M_TEMP, M_WAITOK | M_ZERO);
401 for (r = 0; r < sc->sc_regions; r++) {
402 blocks = cfi_read_qry(sc, CFI_QRY_REGION(r)) |
403 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 1) << 8);
404 sc->sc_region[r].r_blocks = blocks + 1;
406 blksz = cfi_read_qry(sc, CFI_QRY_REGION(r) + 2) |
407 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 3) << 8);
408 sc->sc_region[r].r_blksz = (blksz == 0) ? 128 :
412 /* Reset the device to a default state. */
413 cfi_write(sc, 0, CFI_BCS_CLEAR_STATUS);
416 device_printf(dev, "[");
417 for (r = 0; r < sc->sc_regions; r++) {
418 printf("%ux%s%s", sc->sc_region[r].r_blocks,
419 cfi_fmtsize(sc->sc_region[r].r_blksz),
420 (r == sc->sc_regions - 1) ? "]\n" : ",");
424 u = device_get_unit(dev);
425 sc->sc_nod = make_dev(&cfi_cdevsw, u, UID_ROOT, GID_WHEEL, 0600,
426 "%s%u", cfi_driver_name, u);
427 sc->sc_nod->si_drv1 = sc;
431 #ifdef CFI_SUPPORT_STRATAFLASH
433 * Store the Intel factory PPR in the environment. In some
434 * cases it is the most unique ID on a board.
436 if (cfi_intel_get_factory_pr(sc, &ppr) == 0) {
437 if (snprintf(name, sizeof(name), "%s.factory_ppr",
438 device_get_nameunit(dev)) < (sizeof(name) - 1) &&
439 snprintf(value, sizeof(value), "0x%016jx", ppr) <
441 (void) kern_setenv(name, value);
445 device_add_child(dev, "cfid", -1);
446 bus_generic_attach(dev);
452 cfi_add_sysctls(struct cfi_softc *sc)
454 struct sysctl_ctx_list *ctx;
455 struct sysctl_oid_list *children;
457 ctx = device_get_sysctl_ctx(sc->sc_dev);
458 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
460 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
461 "typical_erase_timout_count",
462 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_ERASE],
463 0, "Number of times the typical erase timeout was exceeded");
464 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
465 "max_erase_timout_count",
466 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_ERASE], 0,
467 "Number of times the maximum erase timeout was exceeded");
468 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
469 "typical_write_timout_count",
470 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_WRITE], 0,
471 "Number of times the typical write timeout was exceeded");
472 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
473 "max_write_timout_count",
474 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_WRITE], 0,
475 "Number of times the maximum write timeout was exceeded");
476 if (sc->sc_maxbuf > 0) {
477 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
478 "typical_bufwrite_timout_count",
479 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_BUFWRITE], 0,
480 "Number of times the typical buffered write timeout was "
482 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
483 "max_bufwrite_timout_count",
484 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_BUFWRITE], 0,
485 "Number of times the maximum buffered write timeout was "
491 cfi_detach(device_t dev)
493 struct cfi_softc *sc;
495 sc = device_get_softc(dev);
497 destroy_dev(sc->sc_nod);
498 free(sc->sc_region, M_TEMP);
499 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
504 cfi_wait_ready(struct cfi_softc *sc, u_int ofs, sbintime_t start,
505 enum cfi_wait_cmd cmd)
507 int done, error, tto_exceeded;
508 uint32_t st0 = 0, st = 0;
514 while (!done && !error) {
516 * Save time before we start so we always do one check
517 * after the timeout has expired.
521 switch (sc->sc_cmdset) {
522 case CFI_VEND_INTEL_ECS:
523 case CFI_VEND_INTEL_SCS:
524 st = cfi_read(sc, ofs);
525 done = (st & CFI_INTEL_STATUS_WSMS);
527 /* NB: bit 0 is reserved */
528 st &= ~(CFI_INTEL_XSTATUS_RSVD |
529 CFI_INTEL_STATUS_WSMS |
530 CFI_INTEL_STATUS_RSVD);
531 if (st & CFI_INTEL_STATUS_DPS)
533 else if (st & CFI_INTEL_STATUS_PSLBS)
535 else if (st & CFI_INTEL_STATUS_ECLBS)
541 case CFI_VEND_AMD_SCS:
542 case CFI_VEND_AMD_ECS:
543 st0 = cfi_read(sc, ofs);
544 st = cfi_read(sc, ofs);
545 done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
550 now > start + sc->sc_typical_timeouts[cmd]) {
553 sc->sc_tto_counts[cmd]++;
554 #ifdef CFI_DEBUG_TIMEOUT
555 device_printf(sc->sc_dev,
556 "typical timeout exceeded (cmd %d)", cmd);
559 if (now > start + sc->sc_max_timeouts[cmd]) {
560 sc->sc_mto_counts[cmd]++;
561 #ifdef CFI_DEBUG_TIMEOUT
562 device_printf(sc->sc_dev,
563 "max timeout exceeded (cmd %d)", cmd);
571 printf("\nerror=%d (st 0x%x st0 0x%x)\n", error, st, st0);
576 cfi_write_block(struct cfi_softc *sc)
584 int error, i, neederase = 0;
589 /* Intel flash must be unlocked before modification */
590 switch (sc->sc_cmdset) {
591 case CFI_VEND_INTEL_ECS:
592 case CFI_VEND_INTEL_SCS:
593 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
594 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_UB);
595 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
599 /* Check if an erase is required. */
600 for (i = 0; i < sc->sc_wrbufsz; i++)
601 if ((sc->sc_wrbuf[i] & sc->sc_wrbufcpy[i]) != sc->sc_wrbuf[i]) {
607 intr = intr_disable();
608 start = sbinuptime();
609 /* Erase the block. */
610 switch (sc->sc_cmdset) {
611 case CFI_VEND_INTEL_ECS:
612 case CFI_VEND_INTEL_SCS:
613 cfi_write(sc, sc->sc_wrofs, CFI_BCS_BLOCK_ERASE);
614 cfi_write(sc, sc->sc_wrofs, CFI_BCS_CONFIRM);
616 case CFI_VEND_AMD_SCS:
617 case CFI_VEND_AMD_ECS:
618 cfi_amd_write(sc, sc->sc_wrofs, AMD_ADDR_START,
619 CFI_AMD_ERASE_SECTOR);
620 cfi_amd_write(sc, sc->sc_wrofs, 0, CFI_AMD_BLOCK_ERASE);
623 /* Better safe than sorry... */
628 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
635 /* Write the block using a multibyte write if supported. */
636 ptr.x8 = sc->sc_wrbuf;
637 cpyprt.x8 = sc->sc_wrbufcpy;
638 if (sc->sc_maxbuf > sc->sc_width) {
639 switch (sc->sc_cmdset) {
640 case CFI_VEND_INTEL_ECS:
641 case CFI_VEND_INTEL_SCS:
642 for (i = 0; i < sc->sc_wrbufsz; i += wlen) {
643 wlen = MIN(sc->sc_maxbuf, sc->sc_wrbufsz - i);
645 intr = intr_disable();
647 start = sbinuptime();
649 cfi_write(sc, sc->sc_wrofs + i,
650 CFI_BCS_BUF_PROG_SETUP);
651 if (sbinuptime() > start + sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE]) {
655 st = cfi_read(sc, sc->sc_wrofs + i);
656 } while (! (st & CFI_INTEL_STATUS_WSMS));
658 cfi_write(sc, sc->sc_wrofs + i,
659 (wlen / sc->sc_width) - 1);
660 switch (sc->sc_width) {
662 bus_space_write_region_1(sc->sc_tag,
663 sc->sc_handle, sc->sc_wrofs + i,
667 bus_space_write_region_2(sc->sc_tag,
668 sc->sc_handle, sc->sc_wrofs + i,
669 ptr.x16 + i / 2, wlen / 2);
672 bus_space_write_region_4(sc->sc_tag,
673 sc->sc_handle, sc->sc_wrofs + i,
674 ptr.x32 + i / 4, wlen / 4);
678 cfi_write(sc, sc->sc_wrofs + i,
683 error = cfi_wait_ready(sc, sc->sc_wrofs + i,
684 start, CFI_TIMEOUT_BUFWRITE);
690 /* Fall through to single word case */
696 /* Write the block one byte/word at a time. */
697 for (i = 0; i < sc->sc_wrbufsz; i += sc->sc_width) {
699 /* Avoid writing unless we are actually changing bits */
701 switch (sc->sc_width) {
703 if(*(ptr.x8 + i) == *(cpyprt.x8 + i))
707 if(*(ptr.x16 + i / 2) == *(cpyprt.x16 + i / 2))
711 if(*(ptr.x32 + i / 4) == *(cpyprt.x32 + i / 4))
718 * Make sure the command to start a write and the
719 * actual write happens back-to-back without any
722 intr = intr_disable();
724 start = sbinuptime();
725 switch (sc->sc_cmdset) {
726 case CFI_VEND_INTEL_ECS:
727 case CFI_VEND_INTEL_SCS:
728 cfi_write(sc, sc->sc_wrofs + i, CFI_BCS_PROGRAM);
730 case CFI_VEND_AMD_SCS:
731 case CFI_VEND_AMD_ECS:
732 cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_PROGRAM);
735 switch (sc->sc_width) {
737 bus_space_write_1(sc->sc_tag, sc->sc_handle,
738 sc->sc_wrofs + i, *(ptr.x8 + i));
741 bus_space_write_2(sc->sc_tag, sc->sc_handle,
742 sc->sc_wrofs + i, *(ptr.x16 + i / 2));
745 bus_space_write_4(sc->sc_tag, sc->sc_handle,
746 sc->sc_wrofs + i, *(ptr.x32 + i / 4));
752 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
761 cfi_reset_default(sc);
763 /* Relock Intel flash */
764 switch (sc->sc_cmdset) {
765 case CFI_VEND_INTEL_ECS:
766 case CFI_VEND_INTEL_SCS:
767 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
768 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LB);
769 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
775 #ifdef CFI_SUPPORT_STRATAFLASH
777 * Intel StrataFlash Protection Register Support.
779 * The memory includes a 128-bit Protection Register that can be
780 * used for security. There are two 64-bit segments; one is programmed
781 * at the factory with a unique 64-bit number which is immutable.
782 * The other segment is left blank for User (OEM) programming.
783 * The User/OEM segment is One Time Programmable (OTP). It can also
784 * be locked to prevent any further writes by setting bit 0 of the
785 * Protection Lock Register (PLR). The PLR can written only once.
789 cfi_get16(struct cfi_softc *sc, int off)
791 uint16_t v = bus_space_read_2(sc->sc_tag, sc->sc_handle, off<<1);
795 #ifdef CFI_ARMEDANDDANGEROUS
797 cfi_put16(struct cfi_softc *sc, int off, uint16_t v)
799 bus_space_write_2(sc->sc_tag, sc->sc_handle, off<<1, v);
804 * Read the factory-defined 64-bit segment of the PR.
807 cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *id)
809 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
811 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
813 cfi_write(sc, 0, CFI_INTEL_READ_ID);
814 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(0)))<<48 |
815 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(1)))<<32 |
816 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(2)))<<16 |
817 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(3)));
818 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
823 * Read the User/OEM 64-bit segment of the PR.
826 cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
828 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
830 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
832 cfi_write(sc, 0, CFI_INTEL_READ_ID);
833 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(4)))<<48 |
834 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(5)))<<32 |
835 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(6)))<<16 |
836 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(7)));
837 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
842 * Write the User/OEM 64-bit segment of the PR.
843 * XXX should allow writing individual words/bytes
846 cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
848 #ifdef CFI_ARMEDANDDANGEROUS
854 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
856 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
858 #ifdef CFI_ARMEDANDDANGEROUS
859 for (i = 7; i >= 4; i--, id >>= 16) {
860 intr = intr_disable();
861 start = sbinuptime();
862 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
863 cfi_put16(sc, CFI_INTEL_PR(i), id&0xffff);
865 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
870 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
873 device_printf(sc->sc_dev, "%s: OEM PR not set, "
874 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
880 * Read the contents of the Protection Lock Register.
883 cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *plr)
885 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
887 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
889 cfi_write(sc, 0, CFI_INTEL_READ_ID);
890 *plr = cfi_get16(sc, CFI_INTEL_PLR);
891 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
896 * Write the Protection Lock Register to lock down the
897 * user-settable segment of the Protection Register.
898 * NOTE: this operation is not reversible.
901 cfi_intel_set_plr(struct cfi_softc *sc)
903 #ifdef CFI_ARMEDANDDANGEROUS
908 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
910 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
912 #ifdef CFI_ARMEDANDDANGEROUS
913 /* worthy of console msg */
914 device_printf(sc->sc_dev, "set PLR\n");
915 intr = intr_disable();
917 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
918 cfi_put16(sc, CFI_INTEL_PLR, 0xFFFD);
920 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
922 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
925 device_printf(sc->sc_dev, "%s: PLR not set, "
926 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
930 #endif /* CFI_SUPPORT_STRATAFLASH */