2 * Copyright (c) 2007, Juniper Networks, Inc.
3 * Copyright (c) 2012-2013, SRI International
6 * Portions of this software were developed by SRI International and the
7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
8 * (FA8750-10-C-0237) ("CTSRD"), as part of the DARPA CRASH research
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. Neither the name of the author nor the names of any co-contributors
20 * may be used to endorse or promote products derived from this software
21 * without specific prior written permission.
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
41 #include <sys/param.h>
42 #include <sys/systm.h>
45 #include <sys/endian.h>
47 #include <sys/kernel.h>
48 #include <sys/malloc.h>
49 #include <sys/module.h>
51 #include <sys/sysctl.h>
53 #include <machine/bus.h>
55 #include <dev/cfi/cfi_reg.h>
56 #include <dev/cfi/cfi_var.h>
58 static void cfi_add_sysctls(struct cfi_softc *);
60 extern struct cdevsw cfi_cdevsw;
62 char cfi_driver_name[] = "cfi";
63 devclass_t cfi_devclass;
64 devclass_t cfi_diskclass;
67 cfi_read_raw(struct cfi_softc *sc, u_int ofs)
71 ofs &= ~(sc->sc_width - 1);
72 switch (sc->sc_width) {
74 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
77 val = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
80 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
90 cfi_read(struct cfi_softc *sc, u_int ofs)
95 ofs &= ~(sc->sc_width - 1);
96 switch (sc->sc_width) {
98 val = bus_space_read_1(sc->sc_tag, sc->sc_handle, ofs);
101 sval = bus_space_read_2(sc->sc_tag, sc->sc_handle, ofs);
102 #ifdef CFI_HARDWAREBYTESWAP
109 val = bus_space_read_4(sc->sc_tag, sc->sc_handle, ofs);
110 #ifndef CFI_HARDWAREBYTESWAP
122 cfi_write(struct cfi_softc *sc, u_int ofs, u_int val)
125 ofs &= ~(sc->sc_width - 1);
126 switch (sc->sc_width) {
128 bus_space_write_1(sc->sc_tag, sc->sc_handle, ofs, val);
131 #ifdef CFI_HARDWAREBYTESWAP
132 bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, val);
134 bus_space_write_2(sc->sc_tag, sc->sc_handle, ofs, htole16(val));
139 #ifdef CFI_HARDWAREBYTESWAP
140 bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, val);
142 bus_space_write_4(sc->sc_tag, sc->sc_handle, ofs, htole32(val));
149 * This is same workaound as NetBSD sys/dev/nor/cfi.c cfi_reset_default()
152 cfi_reset_default(struct cfi_softc *sc)
155 cfi_write(sc, 0, CFI_BCS_READ_ARRAY2);
156 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
160 cfi_read_qry(struct cfi_softc *sc, u_int ofs)
164 cfi_write(sc, CFI_QRY_CMD_ADDR * sc->sc_width, CFI_QRY_CMD_DATA);
165 val = cfi_read(sc, ofs * sc->sc_width);
166 cfi_reset_default(sc);
171 cfi_amd_write(struct cfi_softc *sc, u_int ofs, u_int addr, u_int data)
174 cfi_write(sc, ofs + AMD_ADDR_START, CFI_AMD_UNLOCK);
175 cfi_write(sc, ofs + AMD_ADDR_ACK, CFI_AMD_UNLOCK_ACK);
176 cfi_write(sc, ofs + addr, data);
180 cfi_fmtsize(uint32_t sz)
183 static const char *sfx[] = { "", "K", "M", "G" };
187 while (sfxidx < 3 && sz > 1023) {
192 sprintf(buf, "%u%sB", sz, sfx[sfxidx]);
197 cfi_probe(device_t dev)
200 struct cfi_softc *sc;
203 uint16_t iface, vend;
205 sc = device_get_softc(dev);
209 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
211 if (sc->sc_res == NULL)
214 sc->sc_tag = rman_get_bustag(sc->sc_res);
215 sc->sc_handle = rman_get_bushandle(sc->sc_res);
217 if (sc->sc_width == 0) {
219 while (sc->sc_width <= 4) {
220 if (cfi_read_qry(sc, CFI_QRY_IDENT) == 'Q')
224 } else if (cfi_read_qry(sc, CFI_QRY_IDENT) != 'Q') {
228 if (sc->sc_width > 4) {
233 /* We got a Q. Check if we also have the R and the Y. */
234 if (cfi_read_qry(sc, CFI_QRY_IDENT + 1) != 'R' ||
235 cfi_read_qry(sc, CFI_QRY_IDENT + 2) != 'Y') {
240 /* Get the vendor and command set. */
241 vend = cfi_read_qry(sc, CFI_QRY_VEND) |
242 (cfi_read_qry(sc, CFI_QRY_VEND + 1) << 8);
244 sc->sc_cmdset = vend;
247 case CFI_VEND_AMD_ECS:
248 case CFI_VEND_AMD_SCS:
249 vend_str = "AMD/Fujitsu";
251 case CFI_VEND_INTEL_ECS:
252 vend_str = "Intel/Sharp";
254 case CFI_VEND_INTEL_SCS:
257 case CFI_VEND_MITSUBISHI_ECS:
258 case CFI_VEND_MITSUBISHI_SCS:
259 vend_str = "Mitsubishi";
262 vend_str = "Unknown vendor";
266 /* Get the device size. */
267 sc->sc_size = 1U << cfi_read_qry(sc, CFI_QRY_SIZE);
269 /* Sanity-check the I/F */
270 iface = cfi_read_qry(sc, CFI_QRY_IFACE) |
271 (cfi_read_qry(sc, CFI_QRY_IFACE + 1) << 8);
274 * Adding 1 to iface will give us a bit-wise "switch"
275 * that allows us to test for the interface width by
276 * testing a single bit.
280 error = (iface & sc->sc_width) ? 0 : EINVAL;
284 snprintf(desc, sizeof(desc), "%s - %s", vend_str,
285 cfi_fmtsize(sc->sc_size));
286 device_set_desc_copy(dev, desc);
289 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
294 cfi_attach(device_t dev)
296 struct cfi_softc *sc;
299 uint64_t mtoexp, ttoexp;
300 #ifdef CFI_SUPPORT_STRATAFLASH
302 char name[KENV_MNAMELEN], value[32];
305 sc = device_get_softc(dev);
309 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid,
310 #ifndef ATSE_CFI_HACK
313 RF_ACTIVE | RF_SHAREABLE);
315 if (sc->sc_res == NULL)
318 sc->sc_tag = rman_get_bustag(sc->sc_res);
319 sc->sc_handle = rman_get_bushandle(sc->sc_res);
321 /* Get time-out values for erase, write, and buffer write. */
322 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_ERASE);
323 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_ERASE);
325 device_printf(dev, "erase timeout == 0, using 2^16ms\n");
329 device_printf(dev, "insane timeout: 2^%jdms\n", ttoexp);
333 device_printf(dev, "max erase timeout == 0, using 2^%jdms\n",
337 if (ttoexp + mtoexp > 41) {
338 device_printf(dev, "insane max erase timeout: 2^%jd\n",
342 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] = SBT_1MS * (1ULL << ttoexp);
343 sc->sc_max_timeouts[CFI_TIMEOUT_ERASE] =
344 sc->sc_typical_timeouts[CFI_TIMEOUT_ERASE] * (1ULL << mtoexp);
346 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_WRITE);
347 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_WRITE);
349 device_printf(dev, "write timeout == 0, using 2^18ns\n");
353 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
357 device_printf(dev, "max write timeout == 0, using 2^%jdms\n",
361 if (ttoexp + mtoexp > 51) {
362 device_printf(dev, "insane max write timeout: 2^%jdus\n",
366 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] = SBT_1US * (1ULL << ttoexp);
367 sc->sc_max_timeouts[CFI_TIMEOUT_WRITE] =
368 sc->sc_typical_timeouts[CFI_TIMEOUT_WRITE] * (1ULL << mtoexp);
370 ttoexp = cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE);
371 mtoexp = cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE);
372 /* Don't check for 0, it means not-supported. */
374 device_printf(dev, "insane write timeout: 2^%jdus\n", ttoexp);
377 if (ttoexp + mtoexp > 51) {
378 device_printf(dev, "insane max write timeout: 2^%jdus\n",
382 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] =
383 SBT_1US * (1ULL << cfi_read_qry(sc, CFI_QRY_TTO_BUFWRITE));
384 sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE] =
385 sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] *
386 (1ULL << cfi_read_qry(sc, CFI_QRY_MTO_BUFWRITE));
388 /* Get the maximum size of a multibyte program */
389 if (sc->sc_typical_timeouts[CFI_TIMEOUT_BUFWRITE] != 0)
390 sc->sc_maxbuf = 1 << (cfi_read_qry(sc, CFI_QRY_MAXBUF) |
391 cfi_read_qry(sc, CFI_QRY_MAXBUF) << 8);
395 /* Get erase regions. */
396 sc->sc_regions = cfi_read_qry(sc, CFI_QRY_NREGIONS);
397 sc->sc_region = malloc(sc->sc_regions * sizeof(struct cfi_region),
398 M_TEMP, M_WAITOK | M_ZERO);
399 for (r = 0; r < sc->sc_regions; r++) {
400 blocks = cfi_read_qry(sc, CFI_QRY_REGION(r)) |
401 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 1) << 8);
402 sc->sc_region[r].r_blocks = blocks + 1;
404 blksz = cfi_read_qry(sc, CFI_QRY_REGION(r) + 2) |
405 (cfi_read_qry(sc, CFI_QRY_REGION(r) + 3) << 8);
406 sc->sc_region[r].r_blksz = (blksz == 0) ? 128 :
410 /* Reset the device to a default state. */
411 cfi_write(sc, 0, CFI_BCS_CLEAR_STATUS);
414 device_printf(dev, "[");
415 for (r = 0; r < sc->sc_regions; r++) {
416 printf("%ux%s%s", sc->sc_region[r].r_blocks,
417 cfi_fmtsize(sc->sc_region[r].r_blksz),
418 (r == sc->sc_regions - 1) ? "]\n" : ",");
422 u = device_get_unit(dev);
423 sc->sc_nod = make_dev(&cfi_cdevsw, u, UID_ROOT, GID_WHEEL, 0600,
424 "%s%u", cfi_driver_name, u);
425 sc->sc_nod->si_drv1 = sc;
429 #ifdef CFI_SUPPORT_STRATAFLASH
431 * Store the Intel factory PPR in the environment. In some
432 * cases it is the most unique ID on a board.
434 if (cfi_intel_get_factory_pr(sc, &ppr) == 0) {
435 if (snprintf(name, sizeof(name), "%s.factory_ppr",
436 device_get_nameunit(dev)) < (sizeof(name) - 1) &&
437 snprintf(value, sizeof(value), "0x%016jx", ppr) <
439 (void) kern_setenv(name, value);
443 device_add_child(dev, "cfid", -1);
444 bus_generic_attach(dev);
450 cfi_add_sysctls(struct cfi_softc *sc)
452 struct sysctl_ctx_list *ctx;
453 struct sysctl_oid_list *children;
455 ctx = device_get_sysctl_ctx(sc->sc_dev);
456 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
458 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
459 "typical_erase_timout_count",
460 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_ERASE],
461 0, "Number of times the typical erase timeout was exceeded");
462 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
463 "max_erase_timout_count",
464 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_ERASE], 0,
465 "Number of times the maximum erase timeout was exceeded");
466 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
467 "typical_write_timout_count",
468 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_WRITE], 0,
469 "Number of times the typical write timeout was exceeded");
470 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
471 "max_write_timout_count",
472 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_WRITE], 0,
473 "Number of times the maximum write timeout was exceeded");
474 if (sc->sc_maxbuf > 0) {
475 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
476 "typical_bufwrite_timout_count",
477 CTLFLAG_RD, &sc->sc_tto_counts[CFI_TIMEOUT_BUFWRITE], 0,
478 "Number of times the typical buffered write timeout was "
480 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
481 "max_bufwrite_timout_count",
482 CTLFLAG_RD, &sc->sc_mto_counts[CFI_TIMEOUT_BUFWRITE], 0,
483 "Number of times the maximum buffered write timeout was "
489 cfi_detach(device_t dev)
491 struct cfi_softc *sc;
493 sc = device_get_softc(dev);
495 destroy_dev(sc->sc_nod);
496 free(sc->sc_region, M_TEMP);
497 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res);
502 cfi_wait_ready(struct cfi_softc *sc, u_int ofs, sbintime_t start,
503 enum cfi_wait_cmd cmd)
505 int done, error, tto_exceeded;
506 uint32_t st0 = 0, st = 0;
512 while (!done && !error) {
514 * Save time before we start so we always do one check
515 * after the timeout has expired.
519 switch (sc->sc_cmdset) {
520 case CFI_VEND_INTEL_ECS:
521 case CFI_VEND_INTEL_SCS:
522 st = cfi_read(sc, ofs);
523 done = (st & CFI_INTEL_STATUS_WSMS);
525 /* NB: bit 0 is reserved */
526 st &= ~(CFI_INTEL_XSTATUS_RSVD |
527 CFI_INTEL_STATUS_WSMS |
528 CFI_INTEL_STATUS_RSVD);
529 if (st & CFI_INTEL_STATUS_DPS)
531 else if (st & CFI_INTEL_STATUS_PSLBS)
533 else if (st & CFI_INTEL_STATUS_ECLBS)
539 case CFI_VEND_AMD_SCS:
540 case CFI_VEND_AMD_ECS:
541 st0 = cfi_read(sc, ofs);
542 st = cfi_read(sc, ofs);
543 done = ((st & 0x40) == (st0 & 0x40)) ? 1 : 0;
548 now > start + sc->sc_typical_timeouts[cmd]) {
551 sc->sc_tto_counts[cmd]++;
552 #ifdef CFI_DEBUG_TIMEOUT
553 device_printf(sc->sc_dev,
554 "typical timeout exceeded (cmd %d)", cmd);
557 if (now > start + sc->sc_max_timeouts[cmd]) {
558 sc->sc_mto_counts[cmd]++;
559 #ifdef CFI_DEBUG_TIMEOUT
560 device_printf(sc->sc_dev,
561 "max timeout exceeded (cmd %d)", cmd);
569 printf("\nerror=%d (st 0x%x st0 0x%x)\n", error, st, st0);
574 cfi_write_block(struct cfi_softc *sc)
582 int error, i, neederase = 0;
587 /* Intel flash must be unlocked before modification */
588 switch (sc->sc_cmdset) {
589 case CFI_VEND_INTEL_ECS:
590 case CFI_VEND_INTEL_SCS:
591 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
592 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_UB);
593 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
597 /* Check if an erase is required. */
598 for (i = 0; i < sc->sc_wrbufsz; i++)
599 if ((sc->sc_wrbuf[i] & sc->sc_wrbufcpy[i]) != sc->sc_wrbuf[i]) {
605 intr = intr_disable();
606 start = sbinuptime();
607 /* Erase the block. */
608 switch (sc->sc_cmdset) {
609 case CFI_VEND_INTEL_ECS:
610 case CFI_VEND_INTEL_SCS:
611 cfi_write(sc, sc->sc_wrofs, CFI_BCS_BLOCK_ERASE);
612 cfi_write(sc, sc->sc_wrofs, CFI_BCS_CONFIRM);
614 case CFI_VEND_AMD_SCS:
615 case CFI_VEND_AMD_ECS:
616 cfi_amd_write(sc, sc->sc_wrofs, AMD_ADDR_START,
617 CFI_AMD_ERASE_SECTOR);
618 cfi_amd_write(sc, sc->sc_wrofs, 0, CFI_AMD_BLOCK_ERASE);
621 /* Better safe than sorry... */
626 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
633 /* Write the block using a multibyte write if supported. */
634 ptr.x8 = sc->sc_wrbuf;
635 cpyprt.x8 = sc->sc_wrbufcpy;
636 if (sc->sc_maxbuf > sc->sc_width) {
637 switch (sc->sc_cmdset) {
638 case CFI_VEND_INTEL_ECS:
639 case CFI_VEND_INTEL_SCS:
640 for (i = 0; i < sc->sc_wrbufsz; i += wlen) {
641 wlen = MIN(sc->sc_maxbuf, sc->sc_wrbufsz - i);
643 intr = intr_disable();
645 start = sbinuptime();
647 cfi_write(sc, sc->sc_wrofs + i,
648 CFI_BCS_BUF_PROG_SETUP);
649 if (sbinuptime() > start + sc->sc_max_timeouts[CFI_TIMEOUT_BUFWRITE]) {
653 st = cfi_read(sc, sc->sc_wrofs + i);
654 } while (! (st & CFI_INTEL_STATUS_WSMS));
656 cfi_write(sc, sc->sc_wrofs + i,
657 (wlen / sc->sc_width) - 1);
658 switch (sc->sc_width) {
660 bus_space_write_region_1(sc->sc_tag,
661 sc->sc_handle, sc->sc_wrofs + i,
665 bus_space_write_region_2(sc->sc_tag,
666 sc->sc_handle, sc->sc_wrofs + i,
667 ptr.x16 + i / 2, wlen / 2);
670 bus_space_write_region_4(sc->sc_tag,
671 sc->sc_handle, sc->sc_wrofs + i,
672 ptr.x32 + i / 4, wlen / 4);
676 cfi_write(sc, sc->sc_wrofs + i,
681 error = cfi_wait_ready(sc, sc->sc_wrofs + i,
682 start, CFI_TIMEOUT_BUFWRITE);
688 /* Fall through to single word case */
694 /* Write the block one byte/word at a time. */
695 for (i = 0; i < sc->sc_wrbufsz; i += sc->sc_width) {
697 /* Avoid writing unless we are actually changing bits */
699 switch (sc->sc_width) {
701 if(*(ptr.x8 + i) == *(cpyprt.x8 + i))
705 if(*(ptr.x16 + i / 2) == *(cpyprt.x16 + i / 2))
709 if(*(ptr.x32 + i / 4) == *(cpyprt.x32 + i / 4))
716 * Make sure the command to start a write and the
717 * actual write happens back-to-back without any
720 intr = intr_disable();
722 start = sbinuptime();
723 switch (sc->sc_cmdset) {
724 case CFI_VEND_INTEL_ECS:
725 case CFI_VEND_INTEL_SCS:
726 cfi_write(sc, sc->sc_wrofs + i, CFI_BCS_PROGRAM);
728 case CFI_VEND_AMD_SCS:
729 case CFI_VEND_AMD_ECS:
730 cfi_amd_write(sc, 0, AMD_ADDR_START, CFI_AMD_PROGRAM);
733 switch (sc->sc_width) {
735 bus_space_write_1(sc->sc_tag, sc->sc_handle,
736 sc->sc_wrofs + i, *(ptr.x8 + i));
739 bus_space_write_2(sc->sc_tag, sc->sc_handle,
740 sc->sc_wrofs + i, *(ptr.x16 + i / 2));
743 bus_space_write_4(sc->sc_tag, sc->sc_handle,
744 sc->sc_wrofs + i, *(ptr.x32 + i / 4));
750 error = cfi_wait_ready(sc, sc->sc_wrofs, start,
759 cfi_reset_default(sc);
761 /* Relock Intel flash */
762 switch (sc->sc_cmdset) {
763 case CFI_VEND_INTEL_ECS:
764 case CFI_VEND_INTEL_SCS:
765 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LBS);
766 cfi_write(sc, sc->sc_wrofs, CFI_INTEL_LB);
767 cfi_write(sc, sc->sc_wrofs, CFI_BCS_READ_ARRAY);
773 #ifdef CFI_SUPPORT_STRATAFLASH
775 * Intel StrataFlash Protection Register Support.
777 * The memory includes a 128-bit Protection Register that can be
778 * used for security. There are two 64-bit segments; one is programmed
779 * at the factory with a unique 64-bit number which is immutable.
780 * The other segment is left blank for User (OEM) programming.
781 * The User/OEM segment is One Time Programmable (OTP). It can also
782 * be locked to prevent any further writes by setting bit 0 of the
783 * Protection Lock Register (PLR). The PLR can written only once.
787 cfi_get16(struct cfi_softc *sc, int off)
789 uint16_t v = bus_space_read_2(sc->sc_tag, sc->sc_handle, off<<1);
793 #ifdef CFI_ARMEDANDDANGEROUS
795 cfi_put16(struct cfi_softc *sc, int off, uint16_t v)
797 bus_space_write_2(sc->sc_tag, sc->sc_handle, off<<1, v);
802 * Read the factory-defined 64-bit segment of the PR.
805 cfi_intel_get_factory_pr(struct cfi_softc *sc, uint64_t *id)
807 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
809 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
811 cfi_write(sc, 0, CFI_INTEL_READ_ID);
812 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(0)))<<48 |
813 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(1)))<<32 |
814 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(2)))<<16 |
815 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(3)));
816 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
821 * Read the User/OEM 64-bit segment of the PR.
824 cfi_intel_get_oem_pr(struct cfi_softc *sc, uint64_t *id)
826 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
828 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
830 cfi_write(sc, 0, CFI_INTEL_READ_ID);
831 *id = ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(4)))<<48 |
832 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(5)))<<32 |
833 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(6)))<<16 |
834 ((uint64_t)cfi_get16(sc, CFI_INTEL_PR(7)));
835 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
840 * Write the User/OEM 64-bit segment of the PR.
841 * XXX should allow writing individual words/bytes
844 cfi_intel_set_oem_pr(struct cfi_softc *sc, uint64_t id)
846 #ifdef CFI_ARMEDANDDANGEROUS
852 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
854 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
856 #ifdef CFI_ARMEDANDDANGEROUS
857 for (i = 7; i >= 4; i--, id >>= 16) {
858 intr = intr_disable();
859 start = sbinuptime();
860 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
861 cfi_put16(sc, CFI_INTEL_PR(i), id&0xffff);
863 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
868 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
871 device_printf(sc->sc_dev, "%s: OEM PR not set, "
872 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
878 * Read the contents of the Protection Lock Register.
881 cfi_intel_get_plr(struct cfi_softc *sc, uint32_t *plr)
883 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
885 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
887 cfi_write(sc, 0, CFI_INTEL_READ_ID);
888 *plr = cfi_get16(sc, CFI_INTEL_PLR);
889 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
894 * Write the Protection Lock Register to lock down the
895 * user-settable segment of the Protection Register.
896 * NOTE: this operation is not reversible.
899 cfi_intel_set_plr(struct cfi_softc *sc)
901 #ifdef CFI_ARMEDANDDANGEROUS
906 if (sc->sc_cmdset != CFI_VEND_INTEL_ECS)
908 KASSERT(sc->sc_width == 2, ("sc_width %d", sc->sc_width));
910 #ifdef CFI_ARMEDANDDANGEROUS
911 /* worthy of console msg */
912 device_printf(sc->sc_dev, "set PLR\n");
913 intr = intr_disable();
915 cfi_write(sc, 0, CFI_INTEL_PP_SETUP);
916 cfi_put16(sc, CFI_INTEL_PLR, 0xFFFD);
918 error = cfi_wait_ready(sc, CFI_BCS_READ_STATUS, start,
920 cfi_write(sc, 0, CFI_BCS_READ_ARRAY);
923 device_printf(sc->sc_dev, "%s: PLR not set, "
924 "CFI_ARMEDANDDANGEROUS not configured\n", __func__);
928 #endif /* CFI_SUPPORT_STRATAFLASH */