2 * Copyright (c) 2004-2005 Nate Lawson (SDG)
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
33 #include <sys/kernel.h>
34 #include <sys/malloc.h>
35 #include <sys/module.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
40 #include <dev/pci/pcivar.h>
41 #include <machine/bus.h>
42 #include <machine/clock.h>
43 #include <machine/resource.h>
46 #include "cpufreq_if.h"
49 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency
50 * transition available on the ICH2M, 3M, and 4M. It is different from
51 * the newer Pentium-M SpeedStep feature. It offers only two levels of
52 * frequency/voltage. Often, the BIOS will select one of the levels via
53 * SMM code during the power-on process (i.e., choose a lower level if the
54 * system is off AC power.)
59 int bm_rid; /* Bus-mastering control (PM2REG). */
60 struct resource *bm_reg;
61 int ctrl_rid; /* Control/status register. */
62 struct resource *ctrl_reg;
63 struct cf_setting sets[2]; /* Only two settings. */
66 /* Supported PCI IDs. */
67 #define PCI_VENDOR_INTEL 0x8086
68 #define PCI_DEV_82801BA 0x244c /* ICH2M */
69 #define PCI_DEV_82801CA 0x248c /* ICH3M */
70 #define PCI_DEV_82801DB 0x24cc /* ICH4M */
71 #define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */
73 /* PCI config registers for finding PMBASE and enabling SpeedStep. */
74 #define ICHSS_PMBASE_OFFSET 0x40
75 #define ICHSS_PMCFG_OFFSET 0xa0
77 /* Values and masks. */
78 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */
79 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */
80 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */
81 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */
82 #define ICHSS_BM_DISABLE 0x1
84 /* Offsets from PMBASE for various registers. */
85 #define ICHSS_BM_OFFSET 0x20
86 #define ICHSS_CTRL_OFFSET 0x50
88 #define ICH_GET_REG(reg) \
89 (bus_space_read_1(rman_get_bustag((reg)), \
90 rman_get_bushandle((reg)), 0))
91 #define ICH_SET_REG(reg, val) \
92 (bus_space_write_1(rman_get_bustag((reg)), \
93 rman_get_bushandle((reg)), 0, (val)))
95 static int ichss_pci_probe(device_t dev);
96 static int ichss_probe(device_t dev);
97 static int ichss_attach(device_t dev);
98 static int ichss_detach(device_t dev);
99 static int ichss_settings(device_t dev, struct cf_setting *sets,
101 static int ichss_set(device_t dev, const struct cf_setting *set);
102 static int ichss_get(device_t dev, struct cf_setting *set);
103 static int ichss_type(device_t dev, int *type);
105 static device_method_t ichss_methods[] = {
106 /* Device interface */
107 DEVMETHOD(device_probe, ichss_probe),
108 DEVMETHOD(device_attach, ichss_attach),
109 DEVMETHOD(device_detach, ichss_detach),
111 /* cpufreq interface */
112 DEVMETHOD(cpufreq_drv_set, ichss_set),
113 DEVMETHOD(cpufreq_drv_get, ichss_get),
114 DEVMETHOD(cpufreq_drv_type, ichss_type),
115 DEVMETHOD(cpufreq_drv_settings, ichss_settings),
118 static driver_t ichss_driver = {
119 "ichss", ichss_methods, sizeof(struct ichss_softc)
121 static devclass_t ichss_devclass;
122 DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0);
124 static device_method_t ichss_pci_methods[] = {
125 DEVMETHOD(device_probe, ichss_pci_probe),
128 static driver_t ichss_pci_driver = {
129 "ichss_pci", ichss_pci_methods, 0
131 static devclass_t ichss_pci_devclass;
132 DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0);
135 #define DPRINT(x...) printf(x)
141 * We detect the chipset by looking for its LPC bus ID during the PCI
142 * scan and reading its config registers during the probe. However,
143 * we add the ichss child under the cpu device since even though the
144 * chipset provides the control, it really affects the cpu only.
146 * XXX This approach does not work if the module is loaded after boot.
149 ichss_pci_probe(device_t dev)
151 device_t child, parent;
156 * TODO: add a quirk to disable if we see the 82815_MC along
157 * with the 82801BA and revision < 5.
159 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL ||
160 (pci_get_device(dev) != PCI_DEV_82801BA &&
161 pci_get_device(dev) != PCI_DEV_82801CA &&
162 pci_get_device(dev) != PCI_DEV_82801DB))
165 /* Only one CPU is supported for this hardware. */
166 if (devclass_get_device(ichss_devclass, 0))
170 * Add a child under the CPU parent. It appears that ICH SpeedStep
171 * only requires a single CPU to set the value (since the chipset
172 * is shared by all CPUs.) Thus, we only add a child to cpu 0.
174 parent = devclass_get_device(devclass_find("cpu"), 0);
175 KASSERT(parent != NULL, ("cpu parent is NULL"));
176 child = BUS_ADD_CHILD(parent, 0, "ichss", 0);
178 device_printf(parent, "add SpeedStep child failed\n");
182 /* Find the PMBASE register from our PCI config header. */
183 pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase));
184 if ((pmbase & ICHSS_IO_REG) == 0) {
185 printf("ichss: invalid PMBASE memory type\n");
188 pmbase &= ICHSS_PMBASE_MASK;
190 printf("ichss: invalid zero PMBASE address\n");
193 DPRINT("ichss: PMBASE is %#x\n", pmbase);
195 /* Add the bus master arbitration and control registers. */
196 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET,
198 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET,
201 /* Activate SpeedStep control if not already enabled. */
202 ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en));
203 if ((ss_en & ICHSS_ENABLE) == 0) {
204 printf("ichss: enabling SpeedStep support\n");
205 pci_write_config(dev, ICHSS_PMCFG_OFFSET,
206 ss_en | ICHSS_ENABLE, sizeof(ss_en));
209 /* Attach the new CPU child now. */
210 device_probe_and_attach(child);
216 ichss_probe(device_t dev)
218 device_t est_dev, perf_dev;
221 if (resource_disabled("ichss", 0))
225 * If the ACPI perf driver has attached and is not just offering
226 * info, let it manage things. Also, if Enhanced SpeedStep is
227 * available, don't attach.
229 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1);
230 if (perf_dev && device_is_attached(perf_dev)) {
231 error = CPUFREQ_DRV_TYPE(perf_dev, &type);
232 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0)
235 est_dev = device_find_child(device_get_parent(dev), "est", -1);
236 if (est_dev && device_is_attached(est_dev))
239 device_set_desc(dev, "SpeedStep ICH");
244 ichss_attach(device_t dev)
246 struct ichss_softc *sc;
248 sc = device_get_softc(dev);
252 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid,
254 if (sc->bm_reg == NULL) {
255 device_printf(dev, "failed to alloc BM arb register\n");
259 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
260 &sc->ctrl_rid, RF_ACTIVE);
261 if (sc->ctrl_reg == NULL) {
262 device_printf(dev, "failed to alloc control register\n");
263 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid,
268 /* Setup some defaults for our exported settings. */
269 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN;
270 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN;
271 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN;
272 sc->sets[0].lat = 1000;
273 sc->sets[0].dev = dev;
274 sc->sets[1] = sc->sets[0];
275 cpufreq_register(dev);
281 ichss_detach(device_t dev)
283 /* TODO: teardown BM and CTRL registers. */
288 ichss_settings(device_t dev, struct cf_setting *sets, int *count)
290 struct ichss_softc *sc;
291 struct cf_setting set;
294 if (sets == NULL || count == NULL)
300 sc = device_get_softc(dev);
303 * Estimate frequencies for both levels, temporarily switching to
304 * the other one if we haven't calibrated it yet.
306 ichss_get(dev, &set);
307 for (i = 0; i < 2; i++) {
308 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) {
309 first = (i == 0) ? 1 : 0;
310 ichss_set(dev, &sc->sets[i]);
311 ichss_set(dev, &sc->sets[first]);
315 bcopy(sc->sets, sets, sizeof(sc->sets));
322 ichss_set(device_t dev, const struct cf_setting *set)
324 struct ichss_softc *sc;
325 uint8_t bmval, new_val, old_val, req_val;
329 /* Look up appropriate bit value based on frequency. */
330 sc = device_get_softc(dev);
331 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq))
333 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq))
334 req_val = ICHSS_CTRL_BIT;
337 DPRINT("ichss: requested setting %d\n", req_val);
339 /* Disable interrupts and get the other register contents. */
340 regs = intr_disable();
341 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT;
344 * Disable bus master arbitration, write the new value to the control
345 * register, and then re-enable bus master arbitration.
347 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE;
348 ICH_SET_REG(sc->bm_reg, bmval);
349 ICH_SET_REG(sc->ctrl_reg, old_val | req_val);
350 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE);
352 /* Get the new value and re-enable interrupts. */
353 new_val = ICH_GET_REG(sc->ctrl_reg);
356 /* Check if the desired state was indeed selected. */
357 if (req_val != (new_val & ICHSS_CTRL_BIT)) {
358 device_printf(sc->dev, "transition to %d failed\n", req_val);
362 /* Re-initialize our cycle counter if we don't know this new state. */
363 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) {
364 cpu_est_clockrate(0, &rate);
365 sc->sets[req_val].freq = rate / 1000000;
366 DPRINT("ichss: set calibrated new rate of %d\n",
367 sc->sets[req_val].freq);
374 ichss_get(device_t dev, struct cf_setting *set)
376 struct ichss_softc *sc;
380 sc = device_get_softc(dev);
381 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT;
383 /* If we haven't changed settings yet, estimate the current value. */
384 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) {
385 cpu_est_clockrate(0, &rate);
386 sc->sets[state].freq = rate / 1000000;
387 DPRINT("ichss: get calibrated new rate of %d\n",
388 sc->sets[state].freq);
390 *set = sc->sets[state];
396 ichss_type(device_t dev, int *type)
402 *type = CPUFREQ_TYPE_ABSOLUTE;