1 /* $NecBSD: bshw_machdep.c,v 1.8.12.6 2001/06/29 06:28:05 honda Exp $ */
8 * [NetBSD for NEC PC-98 series]
9 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
10 * NetBSD/pc98 porting staff. All rights reserved.
12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
13 * Naofumi HONDA. All rights reserved.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. The name of the author may not be used to endorse or promote products
24 * derived from this software without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/kernel.h>
46 #include <sys/queue.h>
47 #include <sys/malloc.h>
48 #include <sys/errno.h>
52 #include <machine/bus.h>
53 #include <machine/md_var.h>
55 #include <compat/netbsd/dvcfg.h>
57 #include <cam/scsi/scsi_low.h>
59 #include <dev/ic/wd33c93reg.h>
60 #include <dev/ct/ctvar.h>
61 #include <dev/ct/ct_machdep.h>
62 #include <dev/ct/bshwvar.h>
66 #define BSHW_IO_CONTROL_FLAGS 0
68 u_int bshw_io_control = BSHW_IO_CONTROL_FLAGS;
69 int bshw_data_read_bytes = 4096;
70 int bshw_data_write_bytes = 4096;
72 /*********************************************************
74 *********************************************************/
75 typedef unsigned long vaddr_t;
77 /*********************************************************
78 * GENERIC MACHDEP FUNCTIONS
79 *********************************************************/
81 bshw_synch_setup(struct ct_softc *ct, struct targ_info *ti)
83 struct ct_bus_access_handle *chp = &ct->sc_ch;
84 struct ct_targ_info *cti = (void *) ti;
85 struct bshw_softc *bs = ct->ct_hw;
86 struct bshw *hw = bs->sc_hw;
88 if (hw->hw_sregaddr == 0)
91 ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id, cti->cti_syncreg);
92 if (hw->hw_flags & BSHW_DOUBLE_DMACHAN)
94 ct_cr_write_1(chp, hw->hw_sregaddr + ti->ti_id + 8,
100 bshw_bus_reset(struct ct_softc *ct)
102 struct scsi_low_softc *slp = &ct->sc_sclow;
103 struct ct_bus_access_handle *chp = &ct->sc_ch;
104 struct bshw_softc *bs = ct->ct_hw;
105 struct bshw *hw = bs->sc_hw;
110 /* open hardware busmaster mode */
111 if (hw->hw_dma_init != NULL && ((*hw->hw_dma_init)(ct)) != 0)
113 device_printf(slp->sl_dev,
114 "change mode using external DMA (%x)\n",
115 (u_int)ct_cr_read_1(chp, 0x37));
118 /* clear hardware synch registers */
119 offs = hw->hw_sregaddr;
122 for (i = 0; i < 8; i ++, offs ++)
124 ct_cr_write_1(chp, offs, 0);
125 if ((hw->hw_flags & BSHW_DOUBLE_DMACHAN) != 0)
126 ct_cr_write_1(chp, offs + 8, 0);
130 /* disable interrupt & assert reset */
131 regv = ct_cr_read_1(chp, wd3s_mbank);
134 ct_cr_write_1(chp, wd3s_mbank, regv);
138 /* reset signal off */
140 ct_cr_write_1(chp, wd3s_mbank, regv);
142 /* interrupt enable */
144 ct_cr_write_1(chp, wd3s_mbank, regv);
149 bshw_read_settings(struct ct_bus_access_handle *chp, struct bshw_softc *bs)
151 static int irq_tbl[] = { 3, 5, 6, 9, 12, 13 };
153 bs->sc_hostid = (ct_cr_read_1(chp, wd3s_auxc) & AUXCR_HIDM);
154 bs->sc_irq = irq_tbl[(ct_cr_read_1(chp, wd3s_auxc) >> 3) & 7];
155 bs->sc_drq = ct_cmdp_read_1(chp) & 3;
159 /*********************************************************
160 * DMA PIO TRANSFER (SMIT)
161 *********************************************************/
162 #define LC_SMIT_TIMEOUT 2 /* 2 sec: timeout for a fifo status ready */
163 #define LC_SMIT_OFFSET 0x1000
164 #define LC_FSZ DEV_BSIZE
166 #define LC_REST (LC_FSZ - LC_SFSZ)
168 #define BSHW_LC_FSET 0x36
169 #define BSHW_LC_FCTRL 0x44
170 #define FCTRL_EN 0x01
171 #define FCTRL_WRITE 0x02
173 #define SF_ABORT 0x08
176 static __inline void bshw_lc_smit_start(struct ct_softc *, int, u_int);
177 static __inline void bshw_lc_smit_stop(struct ct_softc *);
178 static int bshw_lc_smit_fstat(struct ct_softc *, int, int);
181 bshw_lc_smit_stop(struct ct_softc *ct)
183 struct ct_bus_access_handle *chp = &ct->sc_ch;
185 ct_cr_write_1(chp, BSHW_LC_FCTRL, 0);
186 ct_cmdp_write_1(chp, CMDP_DMER);
190 bshw_lc_smit_start(struct ct_softc *ct, int count, u_int direction)
192 struct ct_bus_access_handle *chp = &ct->sc_ch;
195 val = ct_cr_read_1(chp, BSHW_LC_FSET);
196 cthw_set_count(chp, count);
199 if (direction == SCSI_LOW_WRITE)
200 pval |= (val & 0xe0) | FCTRL_WRITE;
201 ct_cr_write_1(chp, BSHW_LC_FCTRL, pval);
202 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
206 bshw_lc_smit_fstat(struct ct_softc *ct, int wc, int read)
208 struct ct_bus_access_handle *chp = &ct->sc_ch;
213 chp->ch_bus_weight(chp);
214 stat = ct_cmdp_read_1(chp);
215 if (read == SCSI_LOW_READ)
217 if ((stat & SF_RDY) != 0)
219 if ((stat & SF_ABORT) != 0)
224 if ((stat & SF_ABORT) != 0)
226 if ((stat & SF_RDY) != 0)
231 device_printf(ct->sc_sclow.sl_dev, "SMIT fifo status timeout\n");
236 bshw_smit_xfer_stop(struct ct_softc *ct)
238 struct scsi_low_softc *slp = &ct->sc_sclow;
239 struct bshw_softc *bs = ct->ct_hw;
240 struct targ_info *ti;
241 struct sc_p *sp = &slp->sl_scp;
244 bshw_lc_smit_stop(ct);
250 if (ti->ti_phase == PH_DATA)
252 count = cthw_get_count(&ct->sc_ch);
253 if (count < bs->sc_sdatalen)
255 if (sp->scp_direction == SCSI_LOW_READ &&
256 count != bs->sc_edatalen)
259 count = bs->sc_sdatalen - count;
260 if (count > (u_int) sp->scp_datalen)
263 sp->scp_data += count;
264 sp->scp_datalen -= count;
266 else if (count > bs->sc_sdatalen)
269 device_printf(slp->sl_dev,
270 "smit_xfer_end: cnt error\n");
271 slp->sl_error |= PDMAERR;
273 scsi_low_data_finish(slp);
277 device_printf(slp->sl_dev, "smit_xfer_end: phase miss\n");
278 slp->sl_error |= PDMAERR;
283 bshw_smit_xfer_start(struct ct_softc *ct)
285 struct scsi_low_softc *slp = &ct->sc_sclow;
286 struct ct_bus_access_handle *chp = &ct->sc_ch;
287 struct bshw_softc *bs = ct->ct_hw;
288 struct sc_p *sp = &slp->sl_scp;
289 struct targ_info *ti = slp->sl_Tnexus;
290 struct ct_targ_info *cti = (void *) ti;
291 u_int datalen, count, io_control;
295 io_control = bs->sc_io_control | bshw_io_control;
296 if ((io_control & BSHW_SMIT_BLOCK) != 0)
299 if ((slp->sl_scp.scp_datalen % DEV_BSIZE) != 0)
302 datalen = sp->scp_datalen;
303 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
305 if ((io_control & BSHW_READ_INTERRUPT_DRIVEN) != 0 &&
306 datalen > bshw_data_read_bytes)
307 datalen = bshw_data_read_bytes;
311 if ((io_control & BSHW_WRITE_INTERRUPT_DRIVEN) != 0 &&
312 datalen > bshw_data_write_bytes)
313 datalen = bshw_data_write_bytes;
316 bs->sc_sdatalen = datalen;
318 wc = LC_SMIT_TIMEOUT * 1024 * 1024;
320 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
321 bshw_lc_smit_start(ct, datalen, sp->scp_direction);
323 if (sp->scp_direction == SCSI_LOW_READ)
327 if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_READ))
330 count = (datalen > LC_FSZ ? LC_FSZ : datalen);
331 bus_space_read_region_4(chp->ch_memt, chp->ch_memh,
332 LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
338 bs->sc_edatalen = datalen;
344 if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
346 if (cti->cti_syncreg == 0)
349 * If async transfer, reconfirm a scsi phase
350 * again. Unless C bus might hang up.
352 if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
356 count = (datalen > LC_SFSZ ? LC_SFSZ : datalen);
357 bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
358 LC_SMIT_OFFSET, (u_int32_t *) data, count >> 2);
362 if (bshw_lc_smit_fstat(ct, wc, SCSI_LOW_WRITE))
365 count = (datalen > LC_REST ? LC_REST : datalen);
366 bus_space_write_region_4(chp->ch_memt, chp->ch_memh,
367 LC_SMIT_OFFSET + LC_SFSZ,
368 (u_int32_t *) data, count >> 2);
377 /*********************************************************
379 *********************************************************/
380 static __inline void bshw_dma_write_1 \
381 (struct ct_bus_access_handle *, bus_addr_t, u_int8_t);
382 static void bshw_dmastart(struct ct_softc *);
383 static void bshw_dmadone(struct ct_softc *);
386 bshw_dma_xfer_start(struct ct_softc *ct)
388 struct scsi_low_softc *slp = &ct->sc_sclow;
389 struct sc_p *sp = &slp->sl_scp;
390 struct ct_bus_access_handle *chp = &ct->sc_ch;
391 struct bshw_softc *bs = ct->ct_hw;
392 vaddr_t va, endva, phys, nphys;
395 io_control = bs->sc_io_control | bshw_io_control;
396 if ((io_control & BSHW_DMA_BLOCK) != 0 && sp->scp_datalen < 256)
399 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
400 phys = vtophys((vaddr_t) sp->scp_data);
401 if (phys >= bs->sc_minphys)
404 bs->sc_segaddr = bs->sc_bounce_phys;
406 bs->sc_seglen = sp->scp_datalen;
407 if (bs->sc_seglen > bs->sc_bounce_size)
408 bs->sc_seglen = bs->sc_bounce_size;
410 bs->sc_bufp = bs->sc_bounce_addr;
411 if (sp->scp_direction == SCSI_LOW_WRITE)
412 bcopy(sp->scp_data, bs->sc_bufp, bs->sc_seglen);
417 bs->sc_segaddr = (u_int8_t *) phys;
419 endva = (vaddr_t) round_page((vaddr_t) sp->scp_data + sp->scp_datalen);
420 for (va = (vaddr_t) sp->scp_data; ; phys = nphys)
422 if ((va += PAGE_SIZE) >= endva)
424 bs->sc_seglen = sp->scp_datalen;
429 if (phys + PAGE_SIZE != nphys || nphys >= bs->sc_minphys)
432 (u_int8_t *) trunc_page(va) - sp->scp_data;
441 cthw_set_count(chp, bs->sc_seglen);
442 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
447 bshw_dma_xfer_stop(struct ct_softc *ct)
449 struct scsi_low_softc *slp = &ct->sc_sclow;
450 struct sc_p *sp = &slp->sl_scp;
451 struct bshw_softc *bs = ct->ct_hw;
452 struct targ_info *ti;
453 u_int count, transbytes;
461 if (ti->ti_phase == PH_DATA)
463 count = cthw_get_count(&ct->sc_ch);
464 if (count < (u_int) bs->sc_seglen)
466 transbytes = bs->sc_seglen - count;
467 if (bs->sc_bufp != NULL &&
468 sp->scp_direction == SCSI_LOW_READ)
469 bcopy(bs->sc_bufp, sp->scp_data, transbytes);
471 sp->scp_data += transbytes;
472 sp->scp_datalen -= transbytes;
474 else if (count > (u_int) bs->sc_seglen)
476 device_printf(slp->sl_dev,
477 "port data %x != seglen %x\n",
478 count, bs->sc_seglen);
479 slp->sl_error |= PDMAERR;
482 scsi_low_data_finish(slp);
486 device_printf(slp->sl_dev, "extra DMA interrupt\n");
487 slp->sl_error |= PDMAERR;
493 /* common dma settings */
495 #define DMA1_SMSK (0x15)
497 #define DMA1_MODE (0x17)
499 #define DMA1_FFC (0x19)
501 #define DMA1_CHN(c) (0x01 + ((c) << 2))
503 #define DMA37SM_SET 0x04
504 #define DMA37MD_WRITE 0x04
505 #define DMA37MD_READ 0x08
506 #define DMA37MD_SINGLE 0x40
508 static bus_addr_t dmapageport[4] = { 0x27, 0x21, 0x23, 0x25 };
511 bshw_dma_write_1(struct ct_bus_access_handle *chp, bus_addr_t port,
520 bshw_dmastart(struct ct_softc *ct)
522 struct scsi_low_softc *slp = &ct->sc_sclow;
523 struct bshw_softc *bs = ct->ct_hw;
524 struct ct_bus_access_handle *chp = &ct->sc_ch;
525 int chan = bs->sc_drq;
527 u_int8_t regv, *phys = bs->sc_segaddr;
528 u_int nbytes = bs->sc_seglen;
530 /* flush cpu cache */
531 (*bs->sc_dmasync_before) (ct);
534 * Program one of DMA channels 0..3. These are
535 * byte mode channels.
537 /* set dma channel mode, and reset address ff */
539 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
540 regv = DMA37MD_WRITE | DMA37MD_SINGLE | chan;
542 regv = DMA37MD_READ | DMA37MD_SINGLE | chan;
544 bshw_dma_write_1(chp, DMA1_MODE, regv);
545 bshw_dma_write_1(chp, DMA1_FFC, 0);
547 /* send start address */
548 waport = DMA1_CHN(chan);
549 bshw_dma_write_1(chp, waport, (u_int) phys);
550 bshw_dma_write_1(chp, waport, ((u_int) phys) >> 8);
551 bshw_dma_write_1(chp, dmapageport[chan], ((u_int) phys) >> 16);
554 bshw_dma_write_1(chp, waport + 2, --nbytes);
555 bshw_dma_write_1(chp, waport + 2, nbytes >> 8);
557 /* vendor unique hook */
558 if (bs->sc_hw->hw_dma_start)
559 (*bs->sc_hw->hw_dma_start)(ct);
561 bshw_dma_write_1(chp, DMA1_SMSK, chan);
562 ct_cmdp_write_1(chp, CMDP_DMES);
566 bshw_dmadone(struct ct_softc *ct)
568 struct bshw_softc *bs = ct->ct_hw;
569 struct ct_bus_access_handle *chp = &ct->sc_ch;
571 bshw_dma_write_1(chp, DMA1_SMSK, (bs->sc_drq | DMA37SM_SET));
572 ct_cmdp_write_1(chp, CMDP_DMER);
574 /* vendor unique hook */
575 if (bs->sc_hw->hw_dma_stop)
576 (*bs->sc_hw->hw_dma_stop) (ct);
578 /* flush cpu cache */
579 (*bs->sc_dmasync_after) (ct);
582 /**********************************************
583 * VENDOR UNIQUE DMA FUNCS
584 **********************************************/
585 static int bshw_dma_init_sc98(struct ct_softc *);
586 static void bshw_dma_start_sc98(struct ct_softc *);
587 static void bshw_dma_stop_sc98(struct ct_softc *);
588 static int bshw_dma_init_texa(struct ct_softc *);
589 static void bshw_dma_start_elecom(struct ct_softc *);
590 static void bshw_dma_stop_elecom(struct ct_softc *);
593 bshw_dma_init_texa(struct ct_softc *ct)
595 struct ct_bus_access_handle *chp = &ct->sc_ch;
598 if ((regval = ct_cr_read_1(chp, 0x37)) & 0x08)
601 ct_cr_write_1(chp, 0x37, regval | 0x08);
602 regval = ct_cr_read_1(chp, 0x3f);
603 ct_cr_write_1(chp, 0x3f, regval | 0x08);
608 bshw_dma_init_sc98(struct ct_softc *ct)
610 struct ct_bus_access_handle *chp = &ct->sc_ch;
612 if (ct_cr_read_1(chp, 0x37) & 0x08)
615 /* If your card is SC98 with bios ver 1.01 or 1.02 under no PCI */
616 ct_cr_write_1(chp, 0x37, 0x1a);
617 ct_cr_write_1(chp, 0x3f, 0x1a);
619 /* only valid for IO */
620 ct_cr_write_1(chp, 0x40, 0xf4);
621 ct_cr_write_1(chp, 0x41, 0x9);
622 ct_cr_write_1(chp, 0x43, 0xff);
623 ct_cr_write_1(chp, 0x46, 0x4e);
625 ct_cr_write_1(chp, 0x48, 0xf4);
626 ct_cr_write_1(chp, 0x49, 0x9);
627 ct_cr_write_1(chp, 0x4b, 0xff);
628 ct_cr_write_1(chp, 0x4e, 0x4e);
634 bshw_dma_start_sc98(struct ct_softc *ct)
636 struct ct_bus_access_handle *chp = &ct->sc_ch;
638 ct_cr_write_1(chp, 0x73, 0x32);
639 ct_cr_write_1(chp, 0x74, 0x23);
643 bshw_dma_stop_sc98(struct ct_softc *ct)
645 struct ct_bus_access_handle *chp = &ct->sc_ch;
647 ct_cr_write_1(chp, 0x73, 0x43);
648 ct_cr_write_1(chp, 0x74, 0x34);
652 bshw_dma_start_elecom(struct ct_softc *ct)
654 struct ct_bus_access_handle *chp = &ct->sc_ch;
655 u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
657 ct_cr_write_1(chp, 0x32, tmp & 0xdf);
661 bshw_dma_stop_elecom(struct ct_softc *ct)
663 struct ct_bus_access_handle *chp = &ct->sc_ch;
664 u_int8_t tmp = ct_cr_read_1(chp, 0x4c);
666 ct_cr_write_1(chp, 0x32, tmp | 0x20);
669 static struct bshw bshw_generic = {
679 static struct bshw bshw_sc98 = {
689 static struct bshw bshw_texa = {
699 static struct bshw bshw_elecom = {
705 bshw_dma_start_elecom,
706 bshw_dma_stop_elecom,
709 static struct bshw bshw_lc_smit = {
710 BSHW_SMFIFO | BSHW_DOUBLE_DMACHAN,
719 static struct bshw bshw_lha20X = {
730 static dvcfg_hw_t bshw_hwsel_array[] = {
731 /* 0x00 */ &bshw_generic,
732 /* 0x01 */ &bshw_sc98,
733 /* 0x02 */ &bshw_texa,
734 /* 0x03 */ &bshw_elecom,
735 /* 0x04 */ &bshw_lc_smit,
736 /* 0x05 */ &bshw_lha20X,
739 struct dvcfg_hwsel bshw_hwsel = {
740 DVCFG_HWSEL_SZ(bshw_hwsel_array),