2 /* $NecBSD: bshwvar.h,v 1.3.14.3 2001/06/21 04:07:37 honda Exp $ */
6 * [NetBSD for NEC PC-98 series]
7 * Copyright (c) 1994, 1995, 1996, 1997, 1998
8 * NetBSD/pc98 porting staff. All rights reserved.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
29 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
30 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
38 * NEC 55 compatible board specific definitions
41 #define BSHW_DEFAULT_CHIPCLK 20 /* 20MHz */
42 #define BSHW_DEFAULT_HOSTID 7
45 #define BSHW_SYNC_RELOAD 0x01
46 #define BSHW_SMFIFO 0x02
47 #define BSHW_DOUBLE_DMACHAN 0x04
51 int ((*hw_dma_init)(struct ct_softc *));
52 void ((*hw_dma_start)(struct ct_softc *));
53 void ((*hw_dma_stop)(struct ct_softc *));
65 u_int sc_sdatalen; /* SMIT */
66 u_int sc_edatalen; /* SMIT */
69 u_int8_t *sc_bounce_phys;
70 u_int8_t *sc_bounce_addr;
72 bus_addr_t sc_minphys;
75 #define BSHW_READ_INTERRUPT_DRIVEN 0x0001
76 #define BSHW_WRITE_INTERRUPT_DRIVEN 0x0002
77 #define BSHW_DMA_BLOCK 0x0010
78 #define BSHW_SMIT_BLOCK 0x0020
83 void ((*sc_dmasync_before))(struct ct_softc *);
84 void ((*sc_dmasync_after))(struct ct_softc *);
87 void bshw_synch_setup(struct ct_softc *, struct targ_info *);
88 void bshw_bus_reset(struct ct_softc *);
89 int bshw_read_settings(struct ct_bus_access_handle *, struct bshw_softc *);
90 int bshw_smit_xfer_start(struct ct_softc *);
91 void bshw_smit_xfer_stop(struct ct_softc *);
92 int bshw_dma_xfer_start(struct ct_softc *);
93 void bshw_dma_xfer_stop(struct ct_softc *);
95 extern struct dvcfg_hwsel bshw_hwsel;
96 #endif /* !_BSHWVAR_H_ */