1 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
8 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
11 * [NetBSD for NEC PC-98 series]
12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
13 * NetBSD/pc98 porting staff. All rights reserved.
15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
16 * Naofumi HONDA. All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #if defined(__FreeBSD__) && __FreeBSD_version > 500001
47 #endif /* __ FreeBSD__ */
49 #include <sys/queue.h>
50 #include <sys/malloc.h>
51 #include <sys/errno.h>
54 #include <sys/device.h>
56 #include <machine/bus.h>
57 #include <machine/intr.h>
59 #include <dev/scsipi/scsi_all.h>
60 #include <dev/scsipi/scsipi_all.h>
61 #include <dev/scsipi/scsiconf.h>
62 #include <dev/scsipi/scsi_disk.h>
64 #include <machine/dvcfg.h>
65 #include <machine/physio_proc.h>
67 #include <i386/Cbus/dev/scsi_low.h>
69 #include <dev/ic/wd33c93reg.h>
70 #include <i386/Cbus/dev/ct/ctvar.h>
71 #include <i386/Cbus/dev/ct/ct_machdep.h>
72 #endif /* __NetBSD__ */
75 #include <machine/bus.h>
77 #include <compat/netbsd/dvcfg.h>
78 #include <compat/netbsd/physio_proc.h>
80 #include <cam/scsi/scsi_low.h>
82 #include <dev/ic/wd33c93reg.h>
83 #include <dev/ct/ctvar.h>
84 #include <dev/ct/ct_machdep.h>
85 #endif /* __FreeBSD__ */
89 #define CT_RESET_DEFAULT 2000
90 #define CT_DELAY_MAX (2 * 1000 * 1000)
91 #define CT_DELAY_INTERVAL (1)
93 /***************************************************
95 ***************************************************/
100 /***************************************************
102 ***************************************************/
103 #define CT_USE_CCSEQ 0x0100
104 #define CT_FAST_INTR 0x0200
106 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
108 /***************************************************
110 ***************************************************/
111 u_int8_t cthw_cmdlevel[256] = {
112 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
113 /*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
114 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
115 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
116 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
117 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
118 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
119 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
120 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
121 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
122 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
123 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
124 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
125 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
126 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
127 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
128 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
132 /* default synch data table */
133 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
134 /* X 100 150 200 250 300 350 400 500 ns */
135 static struct ct_synch_data ct_synch_data_FSCSI[] = {
136 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
137 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
140 static struct ct_synch_data ct_synch_data_SCSI[] = {
141 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
144 /***************************************************
146 ***************************************************/
147 extern struct cfdriver ct_cd;
149 /*****************************************************************
150 * Interface functions
151 *****************************************************************/
152 static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
153 static void ct_io_xfer(struct ct_softc *);
154 static int ct_reselected(struct ct_softc *, u_int8_t);
155 static void ct_phase_error(struct ct_softc *, u_int8_t);
156 static int ct_start_selection(struct ct_softc *, struct slccb *);
157 static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
158 static int ct_world_start(struct ct_softc *, int);
159 static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
160 static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
161 static void cthw_bus_reset(struct ct_softc *);
162 static int ct_ccb_nexus_establish(struct ct_softc *);
163 static int ct_lun_nexus_establish(struct ct_softc *);
164 static int ct_target_nexus_establish(struct ct_softc *, int, int);
165 static void cthw_attention(struct ct_softc *);
166 static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
167 static int ct_unbusy(struct ct_softc *);
168 static void ct_attention(struct ct_softc *);
169 static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
170 static int ct_catch_intr(struct ct_softc *);
172 struct scsi_low_funcs ct_funcs = {
173 SC_LOW_INIT_T ct_world_start,
174 SC_LOW_BUSRST_T cthw_bus_reset,
175 SC_LOW_TARG_INIT_T ct_targ_init,
176 SC_LOW_LUN_INIT_T NULL,
178 SC_LOW_SELECT_T ct_start_selection,
179 SC_LOW_NEXUS_T ct_lun_nexus_establish,
180 SC_LOW_NEXUS_T ct_ccb_nexus_establish,
182 SC_LOW_ATTEN_T cthw_attention,
185 SC_LOW_TIMEOUT_T NULL,
186 SC_LOW_POLL_T ctintr,
188 NULL, /* SC_LOW_POWER_T cthw_power, */
191 /**************************************************
193 **************************************************/
195 cthw_phase_bypass(ct, ph)
199 struct ct_bus_access_handle *chp = &ct->sc_ch;
201 ct_cr_write_1(chp, wd3s_cph, ph);
202 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
211 * wd33c93 does not have bus reset function.
213 if (ct->ct_bus_reset != NULL)
214 ((*ct->ct_bus_reset) (ct));
218 cthw_chip_reset(chp, chiprevp, chipclk, hostid)
219 struct ct_bus_access_handle *chp;
223 #define CT_SELTIMEOUT_20MHz_REGV (0x80)
228 /* issue abort cmd */
229 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
230 SCSI_LOW_DELAY(1000); /* 1ms wait */
231 (void) ct_stat_read_1(chp);
232 (void) ct_cr_read_1(chp, wd3s_stat);
234 /* setup chip registers */
236 seltout = CT_SELTIMEOUT_20MHz_REGV;
241 seltout = (seltout * chipclk) / 20;
247 seltout = (seltout * chipclk) / 20;
253 seltout = (seltout * chipclk) / 20;
258 panic("ct: illegal chip clk rate");
262 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
263 ct_cr_write_1(chp, wd3s_oid, regv);
265 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
266 for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
268 aux = ct_stat_read_1(chp);
269 if (aux != 0xff && (aux & STR_INT))
271 regv = ct_cr_read_1(chp, wd3s_stat);
272 if (regv == BSR_RESET || regv == BSR_AFM_RESET)
275 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
282 ct_cr_write_1(chp, wd3s_tout, seltout);
283 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
284 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
285 ct_cr_write_1(chp, wd3s_synch, 0);
286 if (chiprevp != NULL)
288 *chiprevp = CT_WD33C93;
289 if (regv == BSR_RESET)
292 *chiprevp = CT_WD33C93_A;
293 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
294 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
296 ct_cr_write_1(chp, wd3s_qtag, 0x0);
299 ct_cr_write_1(chp, wd3s_qtag, 0x55);
300 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
302 ct_cr_write_1(chp, wd3s_qtag, 0x0);
305 ct_cr_write_1(chp, wd3s_qtag, 0x0);
306 *chiprevp = CT_WD33C93_B;
310 (void) ct_stat_read_1(chp);
311 (void) ct_cr_read_1(chp, wd3s_stat);
315 static struct ct_synch_data *
316 ct_make_synch_table(ct)
319 struct ct_synch_data *sdtp, *sdp;
320 u_int base, i, period;
322 sdtp = sdp = &ct->sc_default_sdt[0];
324 if ((ct->sc_chipclk % 5) == 0)
325 base = 1000 / (5 * 2); /* 5 MHz type */
327 base = 1000 / (4 * 2); /* 4 MHz type */
329 if (ct->sc_chiprev >= CT_WD33C93_B)
332 for (i = 2; i < 8; i ++, sdp ++)
334 period = (base * i) / 2;
335 if (period >= 200) /* 5 MHz */
337 sdp->cs_period = period / 4;
338 sdp->cs_syncr = (i * 0x10) | 0x80;
342 for (i = 2; i < 8; i ++, sdp ++)
345 if (period > 500) /* 2 MHz */
347 sdp->cs_period = period / 4;
348 sdp->cs_syncr = (i * 0x10);
356 /**************************************************
358 **************************************************/
360 ctprobesubr(chp, dvcfg, hsid, chipclk, chiprevp)
361 struct ct_bus_access_handle *chp;
362 u_int dvcfg, chipclk;
368 if ((ct_stat_read_1(chp) & STR_BSY) != 0)
371 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
383 printf("%s: scsibus ", name);
391 struct scsi_low_softc *slp = &ct->sc_sclow;
393 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
394 slp->sl_funcs = &ct_funcs;
395 slp->sl_flags |= HW_READ_PADDING;
396 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
397 sizeof(struct ct_targ_info), 0);
400 /**************************************************
401 * SCSI LOW interface functions
402 **************************************************/
407 struct ct_bus_access_handle *chp = &ct->sc_ch;
410 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
413 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
415 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
425 struct scsi_low_softc *slp = &ct->sc_sclow;
427 if (slp->sl_atten == 0)
430 scsi_low_attention(slp);
432 else if (ct->sc_atten != 0)
440 ct_targ_init(ct, ti, action)
442 struct targ_info *ti;
445 struct ct_targ_info *cti = (void *) ti;
447 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
449 if (ct->sc_sdp == NULL)
451 ct->sc_sdp = ct_make_synch_table(ct);
454 switch (ct->sc_chiprev)
457 ti->ti_maxsynch.offset = 5;
462 ti->ti_maxsynch.offset = 12;
467 ti->ti_maxsynch.offset = 12;
471 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
472 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
473 cti->cti_syncreg = 0;
480 ct_world_start(ct, fdone)
484 struct scsi_low_softc *slp = &ct->sc_sclow;
485 struct ct_bus_access_handle *chp = &ct->sc_ch;
487 if (ct->sc_sdp == NULL)
489 ct->sc_sdp = ct_make_synch_table(ct);
492 if (slp->sl_cfgflags & CFG_NOPARITY)
493 ct->sc_creg = CR_DEFAULT;
495 ct->sc_creg = CR_DEFAULT_HP;
497 if (ct->sc_dma & CT_DMA_DMASTART)
498 (*ct->ct_dma_xfer_stop) (ct);
499 if (ct->sc_dma & CT_DMA_PIOSTART)
500 (*ct->ct_pio_xfer_stop) (ct);
504 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
505 scsi_low_bus_reset(slp);
506 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
508 SOFT_INTR_REQUIRED(slp);
513 ct_start_selection(ct, cb)
517 struct scsi_low_softc *slp = &ct->sc_sclow;
518 struct ct_bus_access_handle *chp = &ct->sc_ch;
520 struct targ_info *ti = slp->sl_Tnexus;
521 struct lun_info *li = slp->sl_Lnexus;
525 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
529 if (scsi_low_is_disconnect_ok(cb) != 0)
531 if (ct->sc_chiprev >= CT_WD33C93_A)
533 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
538 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
540 cmd = WD3S_SELECT_ATN_TFR;
541 ct->sc_satgo = CT_SAT_GOING;
545 cmd = WD3S_SELECT_ATN;
549 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
550 return SCSI_LOW_START_FAIL;
552 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
554 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
555 scsi_low_cmd(slp, ti);
556 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
557 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
561 /* anyway attention assert */
562 SCSI_LOW_ASSERT_ATN(slp);
565 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
568 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
571 * Reload a lun again here.
573 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
574 ct_cr_write_1(chp, wd3s_cmd, cmd);
575 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
578 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
579 return SCSI_LOW_START_OK;
583 return SCSI_LOW_START_FAIL;
589 struct targ_info *ti;
592 struct ct_bus_access_handle *chp = &ct->sc_ch;
593 struct ct_targ_info *cti = (void *) ti;
594 struct ct_synch_data *csp = ct->sc_sdp;
595 u_int offset, period;
598 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
600 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
602 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
608 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
611 offset = ti->ti_maxsynch.offset;
612 period = ti->ti_maxsynch.period;
613 for ( ; csp->cs_period != 0; csp ++)
615 if (period == csp->cs_period)
619 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
621 ti->ti_maxsynch.period = 0;
622 ti->ti_maxsynch.offset = 0;
623 cti->cti_syncreg = 0;
628 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
632 if (ct->ct_synch_setup != 0)
633 (*ct->ct_synch_setup) (ct, ti);
634 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
638 /*************************************************
640 *************************************************/
642 ct_xfer(ct, data, len, direction, statp)
648 struct ct_bus_access_handle *chp = &ct->sc_ch;
650 register u_int8_t aux;
655 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
659 cthw_set_count(chp, len);
660 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
663 aux = ct_stat_read_1(chp);
664 if ((aux & STR_LCI) != 0)
666 cthw_set_count(chp, 0);
670 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
672 /* check data ready */
673 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
675 if (direction == SCSI_LOW_READ)
677 *data = ct_cr_read_1(chp, wd3s_data);
678 if ((aux & STR_PE) != 0)
679 *statp |= SCSI_LOW_DATA_PE;
683 ct_cr_write_1(chp, wd3s_data, *data);
695 /* check phase miss */
696 aux = ct_stat_read_1(chp);
697 if ((aux & STR_INT) != 0)
703 #define CT_PADDING_BUF_SIZE 32
709 struct scsi_low_softc *slp = &ct->sc_sclow;
710 struct ct_bus_access_handle *chp = &ct->sc_ch;
711 struct sc_p *sp = &slp->sl_scp;
714 u_int8_t pbuf[CT_PADDING_BUF_SIZE];
717 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
719 if (sp->scp_datalen <= 0)
721 slp->sl_error |= PDMAERR;
723 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
724 SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
725 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
726 sp->scp_direction, &stat);
730 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
731 sp->scp_direction, &stat);
732 sp->scp_data += (sp->scp_datalen - len);
733 sp->scp_datalen = len;
737 /**************************************************
739 **************************************************/
747 struct ct_err ct_cmderr[] = {
748 /*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
749 /*1*/ { "unexpected bus free", FATALIO, 0, 1},
750 /*2*/ { NULL, SELTIMEOUTIO, 0, 1},
751 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
752 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
753 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
754 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
755 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
759 ct_phase_error(ct, scsi_status)
761 u_int8_t scsi_status;
763 struct scsi_low_softc *slp = &ct->sc_sclow;
764 struct targ_info *ti = slp->sl_Tnexus;
768 if ((scsi_status & BSR_CM) == BSR_CMDERR &&
769 (scsi_status & BSR_PHVALID) == 0)
771 pep = &ct_cmderr[scsi_status & BSR_PM];
772 slp->sl_error |= pep->pe_err;
773 if ((pep->pe_err & PARITYERR) != 0)
775 if (ti->ti_phase == PH_MSGIN)
776 msg = SCSI_LOW_MSG_PARITY;
778 msg = SCSI_LOW_MSG_ERROR;
781 msg = pep->pe_errmsg;
784 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
786 if (pep->pe_msg != NULL)
788 printf("%s: phase error: %s",
789 slp->sl_xname, pep->pe_msg);
790 scsi_low_print(slp, slp->sl_Tnexus);
793 if (pep->pe_done != 0)
794 scsi_low_disconnected(slp, ti);
798 slp->sl_error |= FATALIO;
799 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
803 /**************************************************
804 * ### SCSI PHASE SEQUENCER ###
805 **************************************************/
807 ct_reselected(ct, scsi_status)
809 u_int8_t scsi_status;
811 struct scsi_low_softc *slp = &ct->sc_sclow;
812 struct ct_bus_access_handle *chp = &ct->sc_ch;
813 struct targ_info *ti;
818 ct->sc_satgo &= ~CT_SAT_GOING;
819 regv = ct_cr_read_1(chp, wd3s_sid);
820 if ((regv & SIDR_VALID) == 0)
823 sid = regv & SIDR_IDM;
824 if ((ti = scsi_low_reselected(slp, sid)) == NULL)
827 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
828 if (scsi_status != BSR_AFM_RESEL)
831 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
832 regv = ct_cr_read_1(chp, wd3s_data);
833 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
835 if (scsi_low_is_msgout_continue(ti, 0) != 0)
837 /* XXX: scsi_low_attetion */
838 scsi_low_attention(slp);
842 if (ct->sc_atten != 0)
847 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
852 ct_target_nexus_establish(ct, lun, dir)
856 struct scsi_low_softc *slp = &ct->sc_sclow;
857 struct ct_bus_access_handle *chp = &ct->sc_ch;
858 struct targ_info *ti = slp->sl_Tnexus;
859 struct ct_targ_info *cti = (void *) ti;
861 if (dir == SCSI_LOW_WRITE)
862 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
864 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
865 ct_cr_write_1(chp, wd3s_lun, lun);
866 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
867 ct_cr_write_1(chp, wd3s_cph, 0);
868 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
869 cthw_set_count(chp, 0);
874 ct_lun_nexus_establish(ct)
877 struct scsi_low_softc *slp = &ct->sc_sclow;
878 struct ct_bus_access_handle *chp = &ct->sc_ch;
879 struct lun_info *li = slp->sl_Lnexus;
881 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
886 ct_ccb_nexus_establish(ct)
889 struct scsi_low_softc *slp = &ct->sc_sclow;
890 struct ct_bus_access_handle *chp = &ct->sc_ch;
891 struct lun_info *li = slp->sl_Lnexus;
892 struct targ_info *ti = slp->sl_Tnexus;
893 struct ct_targ_info *cti = (void *) ti;
894 struct slccb *cb = slp->sl_Qnexus;
896 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
898 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
900 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
901 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
903 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
904 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
906 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
907 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
908 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
916 struct scsi_low_softc *slp = &ct->sc_sclow;
917 struct ct_bus_access_handle *chp = &ct->sc_ch;
919 register u_int8_t regv;
921 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
923 regv = ct_stat_read_1(chp);
924 if ((regv & (STR_BSY | STR_CIP)) == 0)
926 if (regv == (u_int8_t) -1)
929 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
932 printf("%s: unbusy timeout\n", slp->sl_xname);
940 struct ct_bus_access_handle *chp = &ct->sc_ch;
942 register u_int8_t regv;
944 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
946 regv = ct_stat_read_1(chp);
947 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
950 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
959 struct ct_softc *ct = arg;
960 struct scsi_low_softc *slp = &ct->sc_sclow;
961 struct ct_bus_access_handle *chp = &ct->sc_ch;
962 struct targ_info *ti;
963 struct physio_proc *pp;
966 int len, satgo, error;
967 u_int8_t scsi_status, regv;
970 if (slp->sl_flags & HW_INACTIVE)
973 /**************************************************
974 * Get status & bus phase
975 **************************************************/
976 if ((ct_stat_read_1(chp) & STR_INT) == 0)
979 scsi_status = ct_cr_read_1(chp, wd3s_stat);
980 if (scsi_status == ((u_int8_t) -1))
983 /**************************************************
984 * Check reselection, or nexus
985 **************************************************/
986 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
988 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
992 if ((ti = slp->sl_Tnexus) == NULL)
995 /**************************************************
997 **************************************************/
1001 scsi_low_print(slp, NULL);
1002 printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
1003 (u_int) scsi_status);
1006 SCSI_LOW_DEBUGGER("ct");
1009 #endif /* CT_DEBUG */
1011 /**************************************************
1012 * Internal scsi phase
1013 **************************************************/
1014 satgo = ct->sc_satgo;
1015 ct->sc_satgo &= ~CT_SAT_GOING;
1017 switch (ti->ti_phase)
1020 if ((satgo & CT_SAT_GOING) == 0)
1022 if (scsi_status != BSR_SELECTED)
1024 ct_phase_error(ct, scsi_status);
1027 scsi_low_arbit_win(slp);
1028 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
1033 scsi_low_arbit_win(slp);
1034 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
1039 if ((scsi_status & BSR_PHVALID) == 0 ||
1040 (scsi_status & BSR_PM) != BSR_MSGIN)
1042 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
1043 "phase miss after reselect");
1049 if (slp->sl_flags & HW_PDMASTART)
1051 slp->sl_flags &= ~HW_PDMASTART;
1052 if (ct->sc_dma & CT_DMA_DMASTART)
1054 (*ct->ct_dma_xfer_stop) (ct);
1055 ct->sc_dma &= ~CT_DMA_DMASTART;
1057 else if (ct->sc_dma & CT_DMA_PIOSTART)
1059 (*ct->ct_pio_xfer_stop) (ct);
1060 ct->sc_dma &= ~CT_DMA_PIOSTART;
1064 scsi_low_data_finish(slp);
1070 /**************************************************
1072 **************************************************/
1073 if (scsi_status & BSR_PHVALID)
1075 /**************************************************
1076 * Normal SCSI phase.
1077 **************************************************/
1078 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1080 ct_phase_error(ct, scsi_status);
1084 switch (scsi_status & BSR_PM)
1087 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1088 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1092 goto common_data_phase;
1095 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1096 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1102 if (slp->sl_scp.scp_datalen > 0)
1104 slp->sl_flags |= HW_PDMASTART;
1105 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1107 pp = physio_proc_enter(bp);
1108 error = (*ct->ct_pio_xfer_start) (ct);
1109 physio_proc_leave(pp);
1112 ct->sc_dma |= CT_DMA_PIOSTART;
1117 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1119 error = (*ct->ct_dma_xfer_start) (ct);
1122 ct->sc_dma |= CT_DMA_DMASTART;
1129 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1131 if (!(slp->sl_flags & HW_READ_PADDING))
1133 printf("%s: read padding required\n", slp->sl_xname);
1139 if (!(slp->sl_flags & HW_WRITE_PADDING))
1141 printf("%s: write padding required\n", slp->sl_xname);
1145 slp->sl_flags |= HW_PDMASTART;
1152 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1153 if (scsi_low_cmd(slp, ti) != 0)
1158 if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1159 slp->sl_scp.scp_cmdlen,
1160 SCSI_LOW_WRITE, &derror) != 0)
1162 printf("%s: scsi cmd xfer short\n",
1168 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1169 if ((ct_io_control & CT_USE_CCSEQ) != 0)
1171 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1174 ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
1176 scsi_low_statusin(slp, ti,
1181 ct->sc_satgo |= CT_SAT_GOING;
1182 cthw_set_count(chp, 0);
1183 cthw_phase_bypass(ct, 0x41);
1188 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1189 scsi_low_statusin(slp, ti, regv | derror);
1195 printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
1196 (u_int) scsi_status);
1197 scsi_low_print(slp, ti);
1201 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1202 flags = SCSI_LOW_MSGOUT_UNIFY;
1203 if (ti->ti_ophase != ti->ti_phase)
1204 flags |= SCSI_LOW_MSGOUT_INIT;
1205 len = scsi_low_msgout(slp, ti, flags);
1207 if (len > 1 && slp->sl_atten == 0)
1212 if (ct_xfer(ct, ti->ti_msgoutstr, len,
1213 SCSI_LOW_WRITE, &derror) != 0)
1215 printf("%s: scsi msgout xfer short\n",
1218 SCSI_LOW_DEASSERT_ATN(slp);
1222 case BSR_MSGIN:/* msg in */
1223 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1225 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1226 if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1228 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1230 /* XXX: scsi_low_attetion */
1231 scsi_low_attention(slp);
1235 if ((ct_io_control & CT_FAST_INTR) != 0)
1237 if (ct_catch_intr(ct) == 0)
1245 /**************************************************
1246 * Special SCSI phase
1247 **************************************************/
1248 switch (scsi_status)
1250 case BSR_SATSDP: /* SAT with save data pointer */
1251 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1252 ct->sc_satgo |= CT_SAT_GOING;
1253 scsi_low_msgin(slp, ti, MSG_SAVESP);
1254 cthw_phase_bypass(ct, 0x41);
1257 case BSR_SATFIN: /* SAT COMPLETE */
1259 * emulate statusin => msgin
1261 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1262 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1264 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1265 scsi_low_msgin(slp, ti, MSG_COMP);
1267 scsi_low_disconnected(slp, ti);
1270 case BSR_ACKREQ: /* negate ACK */
1271 if (ct->sc_atten != 0)
1276 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1277 if ((ct_io_control & CT_FAST_INTR) != 0)
1280 * Should clear a pending interrupt and
1281 * sync with a next interrupt!
1287 case BSR_DISC: /* disconnect */
1288 if (slp->sl_msgphase == MSGPH_NULL &&
1289 (satgo & CT_SAT_GOING) != 0)
1292 * emulate disconnect msg
1294 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1295 scsi_low_msgin(slp, ti, MSG_DISCON);
1297 scsi_low_disconnected(slp, ti);
1305 ct_phase_error(ct, scsi_status);