1 /**************************************************************************
3 Copyright (c) 2007-2008, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
30 ***************************************************************************/
31 #ifndef __CHELSIO_COMMON_H
32 #define __CHELSIO_COMMON_H
34 #include <cxgb_osdep.h>
37 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
38 EEPROMSIZE = 8192, /* Serial EEPROM size */
39 SERNUM_LEN = 16, /* Serial # length */
40 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
41 TCB_SIZE = 128, /* TCB size */
42 NMTUS = 16, /* size of MTU table */
43 NCCTRL_WIN = 32, /* # of congestion control windows */
44 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
45 PROTO_SRAM_LINES = 128, /* size of protocol sram */
46 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */
49 #define MAX_RX_COALESCING_LEN 12288U
54 PAUSE_AUTONEG = 1 << 2
58 SUPPORTED_IRQ = 1 << 24
61 enum { /* adapter interrupt-maintained statistics */
66 IRQ_NUM_STATS /* keep last */
75 #define S_TP_VERSION_MAJOR 16
76 #define M_TP_VERSION_MAJOR 0xFF
77 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR)
78 #define G_TP_VERSION_MAJOR(x) \
79 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
81 #define S_TP_VERSION_MINOR 8
82 #define M_TP_VERSION_MINOR 0xFF
83 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR)
84 #define G_TP_VERSION_MINOR(x) \
85 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
87 #define S_TP_VERSION_MICRO 0
88 #define M_TP_VERSION_MICRO 0xFF
89 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO)
90 #define G_TP_VERSION_MICRO(x) \
91 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
100 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
101 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
102 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
105 enum sge_context_type { /* SGE egress context types */
113 AN_PKT_SIZE = 32, /* async notification packet size */
114 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
117 struct sg_ent { /* SGE scatter/gather entry */
122 #ifndef SGE_NUM_GENBITS
124 # define SGE_NUM_GENBITS 2
127 #define TX_DESC_FLITS 16U
128 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
130 #define MAX_PHYINTRS 4
135 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
136 int reg_addr, unsigned int *val);
137 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
138 int reg_addr, unsigned int val);
141 struct adapter_info {
142 unsigned char nports0; /* # of ports on channel 0 */
143 unsigned char nports1; /* # of ports on channel 1 */
144 unsigned char phy_base_addr; /* MDIO PHY base address */
145 unsigned char mdien:1;
146 unsigned char mdiinv:1;
147 unsigned int gpio_out; /* GPIO output settings */
148 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */
149 unsigned long caps; /* adapter capabilities */
150 const struct mdio_ops *mdio_ops; /* MDIO operations */
151 const char *desc; /* product description */
155 unsigned long parity_err;
156 unsigned long active_rgn_full;
157 unsigned long nfa_srch_err;
158 unsigned long unknown_cmd;
159 unsigned long reqq_parity_err;
160 unsigned long dispq_parity_err;
161 unsigned long del_act_empty;
165 unsigned long corr_err;
166 unsigned long uncorr_err;
167 unsigned long parity_err;
168 unsigned long addr_err;
172 u64 tx_octets; /* total # of octets in good frames */
173 u64 tx_octets_bad; /* total # of octets in error frames */
174 u64 tx_frames; /* all good frames */
175 u64 tx_mcast_frames; /* good multicast frames */
176 u64 tx_bcast_frames; /* good broadcast frames */
177 u64 tx_pause; /* # of transmitted pause frames */
178 u64 tx_deferred; /* frames with deferred transmissions */
179 u64 tx_late_collisions; /* # of late collisions */
180 u64 tx_total_collisions; /* # of total collisions */
181 u64 tx_excess_collisions; /* frame errors from excessive collissions */
182 u64 tx_underrun; /* # of Tx FIFO underruns */
183 u64 tx_len_errs; /* # of Tx length errors */
184 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
185 u64 tx_excess_deferral; /* # of frames with excessive deferral */
186 u64 tx_fcs_errs; /* # of frames with bad FCS */
188 u64 tx_frames_64; /* # of Tx frames in a particular range */
189 u64 tx_frames_65_127;
190 u64 tx_frames_128_255;
191 u64 tx_frames_256_511;
192 u64 tx_frames_512_1023;
193 u64 tx_frames_1024_1518;
194 u64 tx_frames_1519_max;
196 u64 rx_octets; /* total # of octets in good frames */
197 u64 rx_octets_bad; /* total # of octets in error frames */
198 u64 rx_frames; /* all good frames */
199 u64 rx_mcast_frames; /* good multicast frames */
200 u64 rx_bcast_frames; /* good broadcast frames */
201 u64 rx_pause; /* # of received pause frames */
202 u64 rx_fcs_errs; /* # of received frames with bad FCS */
203 u64 rx_align_errs; /* alignment errors */
204 u64 rx_symbol_errs; /* symbol errors */
205 u64 rx_data_errs; /* data errors */
206 u64 rx_sequence_errs; /* sequence errors */
207 u64 rx_runt; /* # of runt frames */
208 u64 rx_jabber; /* # of jabber frames */
209 u64 rx_short; /* # of short frames */
210 u64 rx_too_long; /* # of oversized frames */
211 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
213 u64 rx_frames_64; /* # of Rx frames in a particular range */
214 u64 rx_frames_65_127;
215 u64 rx_frames_128_255;
216 u64 rx_frames_256_511;
217 u64 rx_frames_512_1023;
218 u64 rx_frames_1024_1518;
219 u64 rx_frames_1519_max;
221 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
223 unsigned long tx_fifo_parity_err;
224 unsigned long rx_fifo_parity_err;
225 unsigned long tx_fifo_urun;
226 unsigned long rx_fifo_ovfl;
227 unsigned long serdes_signal_loss;
228 unsigned long xaui_pcs_ctc_err;
229 unsigned long xaui_pcs_align_change;
231 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
232 unsigned long num_resets; /* # times reset due to stuck TX */
235 struct tp_mib_stats {
238 u32 ipInHdrErrors_hi;
239 u32 ipInHdrErrors_lo;
240 u32 ipInAddrErrors_hi;
241 u32 ipInAddrErrors_lo;
242 u32 ipInUnknownProtos_hi;
243 u32 ipInUnknownProtos_lo;
248 u32 ipOutRequests_hi;
249 u32 ipOutRequests_lo;
250 u32 ipOutDiscards_hi;
251 u32 ipOutDiscards_lo;
252 u32 ipOutNoRoutes_hi;
253 u32 ipOutNoRoutes_lo;
271 u32 tcpRetransSeg_hi;
272 u32 tcpRetransSeg_lo;
280 unsigned int nchan; /* # of channels */
281 unsigned int pmrx_size; /* total PMRX capacity */
282 unsigned int pmtx_size; /* total PMTX capacity */
283 unsigned int cm_size; /* total CM capacity */
284 unsigned int chan_rx_size; /* per channel Rx size */
285 unsigned int chan_tx_size; /* per channel Tx size */
286 unsigned int rx_pg_size; /* Rx page size */
287 unsigned int tx_pg_size; /* Tx page size */
288 unsigned int rx_num_pgs; /* # of Rx pages */
289 unsigned int tx_num_pgs; /* # of Tx pages */
290 unsigned int ntimer_qs; /* # of timer queues */
291 unsigned int tre; /* log2 of core clocks per TP tick */
292 unsigned int dack_re; /* DACK timer resolution */
295 struct qset_params { /* SGE queue set parameters */
296 unsigned int polling; /* polling/interrupt service for rspq */
297 unsigned int lro; /* large receive offload */
298 unsigned int coalesce_usecs; /* irq coalescing timer */
299 unsigned int rspq_size; /* # of entries in response queue */
300 unsigned int fl_size; /* # of entries in regular free list */
301 unsigned int jumbo_size; /* # of entries in jumbo free list */
302 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
303 unsigned int cong_thres; /* FL congestion threshold */
304 unsigned int vector; /* Interrupt (line or vector) number */
308 unsigned int max_pkt_size; /* max offload pkt size */
309 struct qset_params qset[SGE_QSETS];
313 unsigned int mode; /* selects MC5 width */
314 unsigned int nservers; /* size of server region */
315 unsigned int nfilters; /* size of filter region */
316 unsigned int nroutes; /* size of routing region */
319 /* Default MC5 region sizes */
321 DEFAULT_NSERVERS = 512,
322 DEFAULT_NFILTERS = 128
325 /* MC5 modes, these must be non-0 */
327 MC5_MODE_144_BIT = 1,
331 /* MC5 min active region size */
332 enum { MC5_MIN_TIDS = 16 };
339 unsigned int mem_timing;
340 u8 sn[SERNUM_LEN + 1];
342 u8 port_type[MAX_NPORTS];
343 unsigned short xauicfg[2];
347 unsigned int vpd_cap_addr;
348 unsigned int pcie_cap_addr;
349 unsigned short speed;
351 unsigned char variant;
356 PCI_VARIANT_PCIX_MODE1_PARITY,
357 PCI_VARIANT_PCIX_MODE1_ECC,
358 PCI_VARIANT_PCIX_266_MODE2,
362 struct adapter_params {
363 struct sge_params sge;
364 struct mc5_params mc5;
366 struct vpd_params vpd;
367 struct pci_params pci;
369 const struct adapter_info *info;
371 #ifdef CONFIG_CHELSIO_T3_CORE
372 unsigned short mtus[NMTUS];
373 unsigned short a_wnd[NCCTRL_WIN];
374 unsigned short b_wnd[NCCTRL_WIN];
376 unsigned int nports; /* # of ethernet ports */
377 unsigned int chan_map; /* bitmap of in-use Tx channels */
378 unsigned int stats_update_period; /* MAC stats accumulation period */
379 unsigned int linkpoll_period; /* link poll period in 0.1s */
380 unsigned int rev; /* chip revision */
381 unsigned int offload;
384 enum { /* chip revisions */
391 struct trace_params {
409 unsigned int supported; /* link capabilities */
410 unsigned int advertising; /* advertised capabilities */
411 unsigned short requested_speed; /* speed user has requested */
412 unsigned short speed; /* actual link speed */
413 unsigned char requested_duplex; /* duplex user has requested */
414 unsigned char duplex; /* actual link duplex */
415 unsigned char requested_fc; /* flow control user has requested */
416 unsigned char fc; /* actual link flow control */
417 unsigned char autoneg; /* autonegotiating? */
418 unsigned int link_ok; /* link up? */
421 #define SPEED_INVALID 0xffff
422 #define DUPLEX_INVALID 0xff
426 unsigned int tcam_size;
427 unsigned char part_type;
428 unsigned char parity_enabled;
430 struct mc5_stats stats;
433 static inline unsigned int t3_mc5_size(const struct mc5 *p)
439 adapter_t *adapter; /* backpointer to adapter */
440 unsigned int size; /* memory size in bytes */
441 unsigned int width; /* MC7 interface width */
442 unsigned int offset; /* register address offset for MC7 instance */
443 const char *name; /* name of MC7 instance */
444 struct mc7_stats stats; /* MC7 statistics */
447 static inline unsigned int t3_mc7_size(const struct mc7 *p)
455 unsigned char nucast; /* # of address filters for unicast MACs */
456 unsigned char multiport; /* multiple ports connected to this MAC */
457 unsigned char ext_port; /* external MAC port */
458 unsigned char promisc_map; /* which external ports are promiscuous */
459 unsigned int tx_tcnt;
460 unsigned int tx_xcnt;
462 unsigned int rx_xcnt;
463 unsigned int rx_ocnt;
465 unsigned int toggle_cnt;
468 struct mac_stats stats;
472 MAC_DIRECTION_RX = 1,
473 MAC_DIRECTION_TX = 2,
474 MAC_RXFIFO_SIZE = 32768
477 /* IEEE 802.3 specified MDIO devices */
479 MDIO_DEV_PMA_PMD = 1,
488 /* LASI control and status registers */
490 RX_ALARM_CTRL = 0x9000,
491 TX_ALARM_CTRL = 0x9001,
493 RX_ALARM_STAT = 0x9003,
494 TX_ALARM_STAT = 0x9004,
498 /* PHY loopback direction */
504 /* PHY interrupt types */
506 cphy_cause_link_change = 1,
507 cphy_cause_fifo_error = 2,
508 cphy_cause_module_change = 4,
511 /* PHY module types */
518 phy_modtype_twinax_long,
524 int (*reset)(struct cphy *phy, int wait);
526 int (*intr_enable)(struct cphy *phy);
527 int (*intr_disable)(struct cphy *phy);
528 int (*intr_clear)(struct cphy *phy);
529 int (*intr_handler)(struct cphy *phy);
531 int (*autoneg_enable)(struct cphy *phy);
532 int (*autoneg_restart)(struct cphy *phy);
534 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
535 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
536 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
537 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
538 int *duplex, int *fc);
539 int (*power_down)(struct cphy *phy, int enable);
544 u8 addr; /* PHY address */
545 u8 modtype; /* PHY module type */
546 short priv; /* scratch pad */
547 unsigned int caps; /* PHY capabilities */
548 adapter_t *adapter; /* associated adapter */
549 const char *desc; /* PHY description */
550 unsigned long fifo_errors; /* FIFO over/under-flows */
551 const struct cphy_ops *ops; /* PHY operations */
552 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
553 int reg_addr, unsigned int *val);
554 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
555 int reg_addr, unsigned int val);
558 /* Convenience MDIO read/write wrappers */
559 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
562 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
565 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
568 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
571 /* Convenience initializer */
572 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
573 int phy_addr, struct cphy_ops *phy_ops,
574 const struct mdio_ops *mdio_ops, unsigned int caps,
577 phy->addr = (u8)phy_addr;
579 phy->adapter = adapter;
583 phy->mdio_read = mdio_ops->read;
584 phy->mdio_write = mdio_ops->write;
588 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
589 #define MAC_STATS_ACCUM_SECS 180
591 /* The external MAC needs accumulation every 30 seconds */
592 #define VSC_STATS_ACCUM_SECS 30
594 #define XGM_REG(reg_addr, idx) \
595 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
597 struct addr_val_pair {
598 unsigned int reg_addr;
602 #include <cxgb_adapter.h>
604 #ifndef PCI_VENDOR_ID_CHELSIO
605 # define PCI_VENDOR_ID_CHELSIO 0x1425
608 #define for_each_port(adapter, iter) \
609 for (iter = 0; iter < (adapter)->params.nports; ++iter)
611 #define adapter_info(adap) ((adap)->params.info)
613 static inline int uses_xaui(const adapter_t *adap)
615 return adapter_info(adap)->caps & SUPPORTED_AUI;
618 static inline int is_10G(const adapter_t *adap)
620 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
623 static inline int is_offload(const adapter_t *adap)
625 #if defined(CONFIG_CHELSIO_T3_CORE)
626 return adap->params.offload;
632 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
634 return adap->params.vpd.cclk / 1000;
637 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
640 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
643 static inline unsigned int is_pcie(const adapter_t *adap)
645 return adap->params.pci.variant == PCI_VARIANT_PCIE;
648 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
649 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
650 unsigned int offset);
651 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
652 int attempts, int delay, u32 *valp);
654 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
655 int polarity, int attempts, int delay)
657 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
661 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
663 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
664 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
665 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert);
666 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
667 int t3_phy_lasi_intr_enable(struct cphy *phy);
668 int t3_phy_lasi_intr_disable(struct cphy *phy);
669 int t3_phy_lasi_intr_clear(struct cphy *phy);
670 int t3_phy_lasi_intr_handler(struct cphy *phy);
672 void t3_intr_enable(adapter_t *adapter);
673 void t3_intr_disable(adapter_t *adapter);
674 void t3_intr_clear(adapter_t *adapter);
675 void t3_port_intr_enable(adapter_t *adapter, int idx);
676 void t3_port_intr_disable(adapter_t *adapter, int idx);
677 void t3_port_intr_clear(adapter_t *adapter, int idx);
678 int t3_slow_intr_handler(adapter_t *adapter);
679 int t3_phy_intr_handler(adapter_t *adapter);
681 void t3_link_changed(adapter_t *adapter, int port_id);
682 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
683 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
684 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
685 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
686 int t3_seeprom_wp(adapter_t *adapter, int enable);
687 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
688 u32 *data, int byte_oriented);
689 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
690 int t3_check_tpsram_version(adapter_t *adapter, int *must_load);
691 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
692 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
693 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
694 int t3_check_fw_version(adapter_t *adapter, int *must_load);
695 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size);
696 int t3_init_hw(adapter_t *adapter, u32 fw_params);
697 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
698 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
699 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
700 int t3_reinit_adapter(adapter_t *adap);
701 void t3_led_ready(adapter_t *adapter);
702 void t3_fatal_err(adapter_t *adapter);
703 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
704 void t3_enable_filters(adapter_t *adap);
705 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
706 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
708 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
709 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
710 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
711 void t3_port_failover(adapter_t *adapter, int port);
712 void t3_failover_done(adapter_t *adapter, int port);
713 void t3_failover_clear(adapter_t *adapter);
714 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
716 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
719 int t3_mac_reset(struct cmac *mac);
720 void t3b_pcs_reset(struct cmac *mac);
721 int t3_mac_enable(struct cmac *mac, int which);
722 int t3_mac_disable(struct cmac *mac, int which);
723 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
724 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
725 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
726 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
727 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
728 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
730 int t3b2_mac_watchdog_task(struct cmac *mac);
732 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
733 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
734 unsigned int nroutes);
735 void t3_mc5_intr_handler(struct mc5 *mc5);
736 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
739 #ifdef CONFIG_CHELSIO_T3_CORE
740 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
741 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
742 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
743 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
744 unsigned short alpha[NCCTRL_WIN],
745 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
746 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
747 void t3_get_cong_cntl_tab(adapter_t *adap,
748 unsigned short incr[NMTUS][NCCTRL_WIN]);
749 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
750 int filter_index, int invert, int enable);
751 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
752 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
753 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
755 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
756 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
757 unsigned int start, unsigned int n);
760 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
761 void t3_sge_init(adapter_t *adap, struct sge_params *p);
762 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
763 enum sge_context_type type, int respq, u64 base_addr,
764 unsigned int size, unsigned int token, int gen,
766 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
767 u64 base_addr, unsigned int size, unsigned int esize,
768 unsigned int cong_thres, int gen, unsigned int cidx);
769 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
770 u64 base_addr, unsigned int size,
771 unsigned int fl_thres, int gen, unsigned int cidx);
772 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
773 unsigned int size, int rspq, int ovfl_mode,
774 unsigned int credits, unsigned int credit_thres);
775 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
776 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
777 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
778 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
779 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
780 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
781 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
782 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
783 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
784 unsigned int credits);
786 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
787 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
788 int t3_vsc7323_init(adapter_t *adap, int nports);
789 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
790 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
791 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
792 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
793 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
794 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
796 int t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
797 const struct mdio_ops *mdio_ops);
798 int t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
799 const struct mdio_ops *mdio_ops);
800 int t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
801 const struct mdio_ops *mdio_ops);
802 int t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
803 const struct mdio_ops *mdio_ops);
804 int t3_ael2005_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
805 const struct mdio_ops *mdio_ops);
806 int t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
807 const struct mdio_ops *mdio_ops);
808 int t3_tn1010_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
809 const struct mdio_ops *mdio_ops);
810 int t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
811 const struct mdio_ops *mdio_ops);
812 #endif /* __CHELSIO_COMMON_H */