1 /**************************************************************************
3 Copyright (c) 2007, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Chelsio Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
34 ***************************************************************************/
35 #ifndef __CHELSIO_COMMON_H
36 #define __CHELSIO_COMMON_H
38 #include <dev/cxgb/cxgb_osdep.h>
41 MAX_NPORTS = 2, /* max # of ports */
42 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */
43 EEPROMSIZE = 8192, /* Serial EEPROM size */
44 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
45 TCB_SIZE = 128, /* TCB size */
46 NMTUS = 16, /* size of MTU table */
47 NCCTRL_WIN = 32, /* # of congestion control windows */
50 #define MAX_RX_COALESCING_LEN 16224U
55 PAUSE_AUTONEG = 1 << 2
59 SUPPORTED_OFFLOAD = 1 << 24,
60 SUPPORTED_IRQ = 1 << 25
63 enum { /* adapter interrupt-maintained statistics */
68 IRQ_NUM_STATS /* keep last */
72 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */
73 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */
74 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */
77 enum sge_context_type { /* SGE egress context types */
85 AN_PKT_SIZE = 32, /* async notification packet size */
86 IMMED_PKT_SIZE = 48 /* packet size for immediate data */
89 struct sg_ent { /* SGE scatter/gather entry */
94 #ifndef SGE_NUM_GENBITS
96 # define SGE_NUM_GENBITS 2
99 #define TX_DESC_FLITS 16U
100 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
105 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
106 int reg_addr, unsigned int *val);
107 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
108 int reg_addr, unsigned int val);
111 struct adapter_info {
112 unsigned char nports; /* # of ports */
113 unsigned char phy_base_addr; /* MDIO PHY base address */
115 unsigned char mdiinv;
116 unsigned int gpio_out; /* GPIO output settings */
117 unsigned int gpio_intr; /* GPIO IRQ enable mask */
118 unsigned long caps; /* adapter capabilities */
119 const struct mdio_ops *mdio_ops; /* MDIO operations */
120 const char *desc; /* product description */
123 struct port_type_info {
124 void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
125 const struct mdio_ops *ops);
131 unsigned long parity_err;
132 unsigned long active_rgn_full;
133 unsigned long nfa_srch_err;
134 unsigned long unknown_cmd;
135 unsigned long reqq_parity_err;
136 unsigned long dispq_parity_err;
137 unsigned long del_act_empty;
141 unsigned long corr_err;
142 unsigned long uncorr_err;
143 unsigned long parity_err;
144 unsigned long addr_err;
148 u64 tx_octets; /* total # of octets in good frames */
149 u64 tx_octets_bad; /* total # of octets in error frames */
150 u64 tx_frames; /* all good frames */
151 u64 tx_mcast_frames; /* good multicast frames */
152 u64 tx_bcast_frames; /* good broadcast frames */
153 u64 tx_pause; /* # of transmitted pause frames */
154 u64 tx_deferred; /* frames with deferred transmissions */
155 u64 tx_late_collisions; /* # of late collisions */
156 u64 tx_total_collisions; /* # of total collisions */
157 u64 tx_excess_collisions; /* frame errors from excessive collissions */
158 u64 tx_underrun; /* # of Tx FIFO underruns */
159 u64 tx_len_errs; /* # of Tx length errors */
160 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
161 u64 tx_excess_deferral; /* # of frames with excessive deferral */
162 u64 tx_fcs_errs; /* # of frames with bad FCS */
164 u64 tx_frames_64; /* # of Tx frames in a particular range */
165 u64 tx_frames_65_127;
166 u64 tx_frames_128_255;
167 u64 tx_frames_256_511;
168 u64 tx_frames_512_1023;
169 u64 tx_frames_1024_1518;
170 u64 tx_frames_1519_max;
172 u64 rx_octets; /* total # of octets in good frames */
173 u64 rx_octets_bad; /* total # of octets in error frames */
174 u64 rx_frames; /* all good frames */
175 u64 rx_mcast_frames; /* good multicast frames */
176 u64 rx_bcast_frames; /* good broadcast frames */
177 u64 rx_pause; /* # of received pause frames */
178 u64 rx_fcs_errs; /* # of received frames with bad FCS */
179 u64 rx_align_errs; /* alignment errors */
180 u64 rx_symbol_errs; /* symbol errors */
181 u64 rx_data_errs; /* data errors */
182 u64 rx_sequence_errs; /* sequence errors */
183 u64 rx_runt; /* # of runt frames */
184 u64 rx_jabber; /* # of jabber frames */
185 u64 rx_short; /* # of short frames */
186 u64 rx_too_long; /* # of oversized frames */
187 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
189 u64 rx_frames_64; /* # of Rx frames in a particular range */
190 u64 rx_frames_65_127;
191 u64 rx_frames_128_255;
192 u64 rx_frames_256_511;
193 u64 rx_frames_512_1023;
194 u64 rx_frames_1024_1518;
195 u64 rx_frames_1519_max;
197 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */
199 unsigned long tx_fifo_parity_err;
200 unsigned long rx_fifo_parity_err;
201 unsigned long tx_fifo_urun;
202 unsigned long rx_fifo_ovfl;
203 unsigned long serdes_signal_loss;
204 unsigned long xaui_pcs_ctc_err;
205 unsigned long xaui_pcs_align_change;
208 struct tp_mib_stats {
211 u32 ipInHdrErrors_hi;
212 u32 ipInHdrErrors_lo;
213 u32 ipInAddrErrors_hi;
214 u32 ipInAddrErrors_lo;
215 u32 ipInUnknownProtos_hi;
216 u32 ipInUnknownProtos_lo;
221 u32 ipOutRequests_hi;
222 u32 ipOutRequests_lo;
223 u32 ipOutDiscards_hi;
224 u32 ipOutDiscards_lo;
225 u32 ipOutNoRoutes_hi;
226 u32 ipOutNoRoutes_lo;
244 u32 tcpRetransSeg_hi;
245 u32 tcpRetransSeg_lo;
253 unsigned int nchan; /* # of channels */
254 unsigned int pmrx_size; /* total PMRX capacity */
255 unsigned int pmtx_size; /* total PMTX capacity */
256 unsigned int cm_size; /* total CM capacity */
257 unsigned int chan_rx_size; /* per channel Rx size */
258 unsigned int chan_tx_size; /* per channel Tx size */
259 unsigned int rx_pg_size; /* Rx page size */
260 unsigned int tx_pg_size; /* Tx page size */
261 unsigned int rx_num_pgs; /* # of Rx pages */
262 unsigned int tx_num_pgs; /* # of Tx pages */
263 unsigned int ntimer_qs; /* # of timer queues */
266 struct qset_params { /* SGE queue set parameters */
267 unsigned int polling; /* polling/interrupt service for rspq */
268 unsigned int coalesce_nsecs; /* irq coalescing timer */
269 unsigned int rspq_size; /* # of entries in response queue */
270 unsigned int fl_size; /* # of entries in regular free list */
271 unsigned int jumbo_size; /* # of entries in jumbo free list */
272 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */
273 unsigned int cong_thres; /* FL congestion threshold */
277 unsigned int max_pkt_size; /* max offload pkt size */
278 struct qset_params qset[SGE_QSETS];
282 unsigned int mode; /* selects MC5 width */
283 unsigned int nservers; /* size of server region */
284 unsigned int nfilters; /* size of filter region */
285 unsigned int nroutes; /* size of routing region */
288 /* Default MC5 region sizes */
290 DEFAULT_NSERVERS = 512,
291 DEFAULT_NFILTERS = 128
294 /* MC5 modes, these must be non-0 */
296 MC5_MODE_144_BIT = 1,
305 unsigned int mem_timing;
307 u8 port_type[MAX_NPORTS];
308 unsigned short xauicfg[2];
312 unsigned int vpd_cap_addr;
313 unsigned int pcie_cap_addr;
314 unsigned short speed;
316 unsigned char variant;
321 PCI_VARIANT_PCIX_MODE1_PARITY,
322 PCI_VARIANT_PCIX_MODE1_ECC,
323 PCI_VARIANT_PCIX_266_MODE2,
327 struct adapter_params {
328 struct sge_params sge;
329 struct mc5_params mc5;
331 struct vpd_params vpd;
332 struct pci_params pci;
334 const struct adapter_info *info;
336 #ifdef CONFIG_CHELSIO_T3_CORE
337 unsigned short mtus[NMTUS];
338 unsigned short a_wnd[NCCTRL_WIN];
339 unsigned short b_wnd[NCCTRL_WIN];
341 unsigned int nports; /* # of ethernet ports */
342 unsigned int stats_update_period; /* MAC stats accumulation period */
343 unsigned int linkpoll_period; /* link poll period in 0.1s */
344 unsigned int rev; /* chip revision */
347 struct trace_params {
365 unsigned int supported; /* link capabilities */
366 unsigned int advertising; /* advertised capabilities */
367 unsigned short requested_speed; /* speed user has requested */
368 unsigned short speed; /* actual link speed */
369 unsigned char requested_duplex; /* duplex user has requested */
370 unsigned char duplex; /* actual link duplex */
371 unsigned char requested_fc; /* flow control user has requested */
372 unsigned char fc; /* actual link flow control */
373 unsigned char autoneg; /* autonegotiating? */
374 unsigned int link_ok; /* link up? */
377 #define SPEED_INVALID 0xffff
378 #define DUPLEX_INVALID 0xff
382 unsigned int tcam_size;
383 unsigned char part_type;
384 unsigned char parity_enabled;
386 struct mc5_stats stats;
389 static inline unsigned int t3_mc5_size(const struct mc5 *p)
395 adapter_t *adapter; /* backpointer to adapter */
396 unsigned int size; /* memory size in bytes */
397 unsigned int width; /* MC7 interface width */
398 unsigned int offset; /* register address offset for MC7 instance */
399 const char *name; /* name of MC7 instance */
400 struct mc7_stats stats; /* MC7 statistics */
403 static inline unsigned int t3_mc7_size(const struct mc7 *p)
411 unsigned int nucast; /* # of address filters for unicast MACs */
412 struct mac_stats stats;
416 MAC_DIRECTION_RX = 1,
417 MAC_DIRECTION_TX = 2,
418 MAC_RXFIFO_SIZE = 32768
421 /* IEEE 802.3ae specified MDIO devices */
423 MDIO_DEV_PMA_PMD = 1,
429 /* PHY loopback direction */
435 /* PHY interrupt types */
437 cphy_cause_link_change = 1,
438 cphy_cause_fifo_error = 2
443 void (*destroy)(struct cphy *phy);
444 int (*reset)(struct cphy *phy, int wait);
446 int (*intr_enable)(struct cphy *phy);
447 int (*intr_disable)(struct cphy *phy);
448 int (*intr_clear)(struct cphy *phy);
449 int (*intr_handler)(struct cphy *phy);
451 int (*autoneg_enable)(struct cphy *phy);
452 int (*autoneg_restart)(struct cphy *phy);
454 int (*advertise)(struct cphy *phy, unsigned int advertise_map);
455 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
456 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
457 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
458 int *duplex, int *fc);
459 int (*power_down)(struct cphy *phy, int enable);
464 int addr; /* PHY address */
465 adapter_t *adapter; /* associated adapter */
466 unsigned long fifo_errors; /* FIFO over/under-flows */
467 const struct cphy_ops *ops; /* PHY operations */
468 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
469 int reg_addr, unsigned int *val);
470 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
471 int reg_addr, unsigned int val);
474 /* Convenience MDIO read/write wrappers */
475 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
478 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
481 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
484 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
487 /* Convenience initializer */
488 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
489 int phy_addr, struct cphy_ops *phy_ops,
490 const struct mdio_ops *mdio_ops)
492 phy->adapter = adapter;
493 phy->addr = phy_addr;
496 phy->mdio_read = mdio_ops->read;
497 phy->mdio_write = mdio_ops->write;
501 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
502 #define MAC_STATS_ACCUM_SECS 180
504 #define XGM_REG(reg_addr, idx) \
505 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
507 struct addr_val_pair {
508 unsigned int reg_addr;
512 #include <dev/cxgb/cxgb_adapter.h>
514 #ifndef PCI_VENDOR_ID_CHELSIO
515 # define PCI_VENDOR_ID_CHELSIO 0x1425
518 #define for_each_port(adapter, iter) \
519 for (iter = 0; iter < (adapter)->params.nports; ++iter)
521 #define adapter_info(adap) ((adap)->params.info)
523 static inline int uses_xaui(const adapter_t *adap)
525 return adapter_info(adap)->caps & SUPPORTED_AUI;
528 static inline int is_10G(const adapter_t *adap)
530 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
533 static inline int is_offload(const adapter_t *adap)
535 #ifdef CONFIG_CHELSIO_T3_CORE
536 return adapter_info(adap)->caps & SUPPORTED_OFFLOAD;
542 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
544 return adap->params.vpd.cclk / 1000;
547 static inline unsigned int is_pcie(const adapter_t *adap)
549 return adap->params.pci.variant == PCI_VARIANT_PCIE;
552 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
553 void t3_read_indirect(adapter_t *adap, unsigned int addr_reg,
554 unsigned int data_reg, u32 *vals, unsigned int nregs,
555 unsigned int start_idx);
556 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
557 unsigned int offset);
558 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
559 int attempts, int delay, u32 *valp);
561 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
562 int polarity, int attempts, int delay)
564 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
568 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
570 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
571 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
572 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
574 void t3_intr_enable(adapter_t *adapter);
575 void t3_intr_disable(adapter_t *adapter);
576 void t3_intr_clear(adapter_t *adapter);
577 void t3_port_intr_enable(adapter_t *adapter, int idx);
578 void t3_port_intr_disable(adapter_t *adapter, int idx);
579 void t3_port_intr_clear(adapter_t *adapter, int idx);
580 int t3_slow_intr_handler(adapter_t *adapter);
581 int t3_phy_intr_handler(adapter_t *adapter);
583 void t3_link_changed(adapter_t *adapter, int port_id);
584 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
585 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
586 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
587 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
588 int t3_seeprom_wp(adapter_t *adapter, int enable);
589 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
590 u32 *data, int byte_oriented);
591 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
592 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
593 int t3_check_fw_version(adapter_t *adapter);
594 int t3_init_hw(adapter_t *adapter, u32 fw_params);
595 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
596 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
597 int t3_reset_adapter(adapter_t *adapter);
598 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
599 void t3_led_ready(adapter_t *adapter);
600 void t3_fatal_err(adapter_t *adapter);
601 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
602 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
604 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
605 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
606 void t3_port_failover(adapter_t *adapter, int port);
607 void t3_failover_done(adapter_t *adapter, int port);
608 void t3_failover_clear(adapter_t *adapter);
609 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
611 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
614 int t3_mac_reset(struct cmac *mac);
615 void t3b_pcs_reset(struct cmac *mac);
616 int t3_mac_enable(struct cmac *mac, int which);
617 int t3_mac_disable(struct cmac *mac, int which);
618 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
619 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
620 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
621 int t3_mac_set_num_ucast(struct cmac *mac, int n);
622 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
623 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
626 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
627 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
628 unsigned int nroutes);
629 void t3_mc5_intr_handler(struct mc5 *mc5);
630 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
633 #ifdef CONFIG_CHELSIO_T3_CORE
634 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
635 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
636 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
637 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
638 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
639 unsigned short alpha[NCCTRL_WIN],
640 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
641 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
642 void t3_get_cong_cntl_tab(adapter_t *adap,
643 unsigned short incr[NMTUS][NCCTRL_WIN]);
644 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
645 int filter_index, int invert, int enable);
646 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
649 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
650 void t3_sge_init(adapter_t *adap, struct sge_params *p);
651 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
652 enum sge_context_type type, int respq, u64 base_addr,
653 unsigned int size, unsigned int token, int gen,
655 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
656 u64 base_addr, unsigned int size, unsigned int esize,
657 unsigned int cong_thres, int gen, unsigned int cidx);
658 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
659 u64 base_addr, unsigned int size,
660 unsigned int fl_thres, int gen, unsigned int cidx);
661 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
662 unsigned int size, int rspq, int ovfl_mode,
663 unsigned int credits, unsigned int credit_thres);
664 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
665 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
666 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
667 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
668 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
669 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
670 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
671 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
672 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
673 unsigned int credits);
675 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
676 const struct mdio_ops *mdio_ops);
677 void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
678 const struct mdio_ops *mdio_ops);
679 void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
680 const struct mdio_ops *mdio_ops);
681 void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
682 const struct mdio_ops *mdio_ops);
683 void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
684 const struct mdio_ops *mdio_ops);
685 void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
686 const struct mdio_ops *mdio_ops);
687 #endif /* __CHELSIO_COMMON_H */