1 /**************************************************************************
3 Copyright (c) 2007, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
28 ***************************************************************************/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include <common/cxgb_common.h>
35 #include <common/cxgb_regs.h>
37 #include <dev/cxgb/common/cxgb_common.h>
38 #include <dev/cxgb/common/cxgb_regs.h>
46 /* DBGI command mode */
49 DBGI_MODE_IDT52100 = 5
52 /* IDT 75P52100 commands */
53 #define IDT_CMD_READ 0
54 #define IDT_CMD_WRITE 1
55 #define IDT_CMD_SEARCH 2
56 #define IDT_CMD_LEARN 3
58 /* IDT LAR register address and value for 144-bit mode (low 32 bits) */
59 #define IDT_LAR_ADR0 0x180006
60 #define IDT_LAR_MODE144 0xffff0000
62 /* IDT SCR and SSR addresses (low 32 bits) */
63 #define IDT_SCR_ADR0 0x180000
64 #define IDT_SSR0_ADR0 0x180002
65 #define IDT_SSR1_ADR0 0x180004
67 /* IDT GMR base address (low 32 bits) */
68 #define IDT_GMR_BASE_ADR0 0x180020
70 /* IDT data and mask array base addresses (low 32 bits) */
71 #define IDT_DATARY_BASE_ADR0 0
72 #define IDT_MSKARY_BASE_ADR0 0x80000
74 /* IDT 75N43102 commands */
75 #define IDT4_CMD_SEARCH144 3
76 #define IDT4_CMD_WRITE 4
77 #define IDT4_CMD_READ 5
79 /* IDT 75N43102 SCR address (low 32 bits) */
80 #define IDT4_SCR_ADR0 0x3
82 /* IDT 75N43102 GMR base addresses (low 32 bits) */
83 #define IDT4_GMR_BASE0 0x10
84 #define IDT4_GMR_BASE1 0x20
85 #define IDT4_GMR_BASE2 0x30
87 /* IDT 75N43102 data and mask array base addresses (low 32 bits) */
88 #define IDT4_DATARY_BASE_ADR0 0x1000000
89 #define IDT4_MSKARY_BASE_ADR0 0x2000000
91 #define MAX_WRITE_ATTEMPTS 5
93 #define MAX_ROUTES 2048
96 * Issue a command to the TCAM and wait for its completion. The address and
97 * any data required by the command must have been setup by the caller.
99 static int mc5_cmd_write(adapter_t *adapter, u32 cmd)
101 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd);
102 return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS,
103 F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1);
106 static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
108 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1);
109 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2);
110 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3);
113 static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3)
115 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1);
116 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2);
117 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3);
120 static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3)
122 *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0);
123 *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1);
124 *v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2);
128 * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM
129 * command cmd. The data to be written must have been set up by the caller.
130 * Returns -1 on failure, 0 on success.
132 static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd)
134 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo);
135 if (mc5_cmd_write(adapter, cmd) == 0)
137 CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", addr_lo);
141 static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base,
142 u32 data_array_base, u32 write_cmd,
146 adapter_t *adap = mc5->adapter;
149 * We need the size of the TCAM data and mask arrays in terms of
152 unsigned int size72 = mc5->tcam_size;
153 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX);
155 if (mc5->mode == MC5_MODE_144_BIT) {
156 size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */
160 /* Clear the data array */
161 dbgi_wr_data3(adap, 0, 0, 0);
162 for (i = 0; i < size72; i++)
163 if (mc5_write(adap, data_array_base + (i << addr_shift),
167 /* Initialize the mask array. */
168 for (i = 0; i < server_base; i++) {
169 dbgi_wr_data3(adap, 0x3fffffff, 0xfff80000, 0xff);
170 if (mc5_write(adap, mask_array_base + (i << addr_shift),
174 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
175 if (mc5_write(adap, mask_array_base + (i << addr_shift),
181 mc5->mode == MC5_MODE_144_BIT ? 0xfffffff9 : 0xfffffffd,
183 for (; i < size72; i++)
184 if (mc5_write(adap, mask_array_base + (i << addr_shift),
191 static int init_idt52100(struct mc5 *mc5)
194 adapter_t *adap = mc5->adapter;
196 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
197 V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15));
198 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2);
201 * Use GMRs 14-15 for ELOOKUP, GMRs 12-13 for SYN lookups, and
202 * GMRs 8-9 for ACK- and AOPEN searches.
204 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE);
205 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE);
206 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH);
207 t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN);
208 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000);
209 t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN);
210 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH);
211 t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN);
212 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH);
213 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000);
214 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE);
215 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ);
217 /* Set DBGI command mode for IDT TCAM. */
218 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
221 dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0);
222 if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE))
226 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0);
227 if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) ||
228 mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE))
232 for (i = 0; i < 32; ++i) {
233 if (i >= 12 && i < 15)
234 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
236 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
238 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
240 if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE))
245 dbgi_wr_data3(adap, 1, 0, 0);
246 if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE))
249 return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0,
250 IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0);
255 static int init_idt43102(struct mc5 *mc5)
258 adapter_t *adap = mc5->adapter;
260 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY,
261 adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) :
262 V_RDLAT(0xd) | V_SRCHLAT(0x12));
265 * Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask
266 * for ACK- and AOPEN searches.
268 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE);
269 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE);
270 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD,
271 IDT4_CMD_SEARCH144 | 0x3800);
272 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144);
273 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800);
274 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800);
275 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800);
276 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE);
277 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ);
279 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3);
281 /* Set DBGI command mode for IDT TCAM. */
282 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100);
285 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
286 for (i = 0; i < 7; ++i)
287 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE))
290 for (i = 0; i < 4; ++i)
291 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE))
294 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff);
295 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) ||
296 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) ||
297 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE))
300 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff);
301 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE))
305 dbgi_wr_data3(adap, 0xf0000000, 0, 0);
306 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE))
309 return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0,
310 IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1);
315 /* Put MC5 in DBGI mode. */
316 static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5)
318 t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_PRTYEN | F_MBUSEN,
322 /* Put MC5 in M-Bus mode. */
323 static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
325 t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_DBGIEN,
326 V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
330 * t3_mc5_init - initialize MC5 and the TCAM
331 * @mc5: the MC5 handle
332 * @nservers: desired number the TCP servers (listening ports)
333 * @nfilters: desired number of HW filters (classifiers)
334 * @nroutes: desired number of routes
336 * Initialize MC5 and the TCAM and partition the TCAM for the requested
337 * number of servers, filters, and routes. The number of routes is
338 * typically 0 except for specialized uses of the T3 adapters.
340 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
341 unsigned int nroutes)
344 unsigned int tcam_size = mc5->tcam_size;
345 unsigned int mode72 = mc5->mode == MC5_MODE_72_BIT;
346 adapter_t *adap = mc5->adapter;
351 if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
355 mc5->parity_enabled = 0;
358 t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_TMMODE | F_COMPEN,
359 V_COMPEN(mode72) | V_TMMODE(mode72) | F_TMRST);
360 if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
361 CH_ERR(adap, "TCAM reset timed out\n");
365 t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes);
366 t3_write_reg(adap, A_MC5_DB_FILTER_TABLE,
367 tcam_size - nroutes - nfilters);
368 t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
369 tcam_size - nroutes - nfilters - nservers);
371 /* All the TCAM addresses we access have only the low 32 bits non 0 */
372 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
373 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
375 mc5_dbgi_mode_enable(mc5);
377 switch (mc5->part_type) {
379 err = init_idt52100(mc5);
382 err = init_idt43102(mc5);
385 CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type);
390 mc5_dbgi_mode_disable(mc5);
395 * read_mc5_range - dump a part of the memory managed by MC5
396 * @mc5: the MC5 handle
397 * @start: the start address for the dump
398 * @n: number of 72-bit words to read
399 * @buf: result buffer
401 * Read n 72-bit words from MC5 memory from the given start location.
403 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start,
404 unsigned int n, u32 *buf)
408 adapter_t *adap = mc5->adapter;
410 if (mc5->part_type == IDT75P52100)
411 read_cmd = IDT_CMD_READ;
412 else if (mc5->part_type == IDT75N43102)
413 read_cmd = IDT4_CMD_READ;
417 mc5_dbgi_mode_enable(mc5);
420 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR0, start++);
421 if (mc5_cmd_write(adap, read_cmd)) {
425 dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf);
429 mc5_dbgi_mode_disable(mc5);
433 #define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR)
436 * t3_mc5_intr_handler - MC5 interrupt handler
437 * @mc5: the MC5 handle
439 * The MC5 interrupt handler.
441 void t3_mc5_intr_handler(struct mc5 *mc5)
443 adapter_t *adap = mc5->adapter;
444 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE);
446 if ((cause & F_PARITYERR) && mc5->parity_enabled) {
447 CH_ALERT(adap, "MC5 parity error\n");
448 mc5->stats.parity_err++;
451 if (cause & F_REQQPARERR) {
452 CH_ALERT(adap, "MC5 request queue parity error\n");
453 mc5->stats.reqq_parity_err++;
456 if (cause & F_DISPQPARERR) {
457 CH_ALERT(adap, "MC5 dispatch queue parity error\n");
458 mc5->stats.dispq_parity_err++;
461 if (cause & F_ACTRGNFULL)
462 mc5->stats.active_rgn_full++;
463 if (cause & F_NFASRCHFAIL)
464 mc5->stats.nfa_srch_err++;
465 if (cause & F_UNKNOWNCMD)
466 mc5->stats.unknown_cmd++;
467 if (cause & F_DELACTEMPTY)
468 mc5->stats.del_act_empty++;
469 if (cause & MC5_INT_FATAL)
472 t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause);
476 * t3_mc5_prep - initialize the SW state for MC5
477 * @adapter: the adapter
478 * @mc5: the MC5 handle
479 * @mode: whether the TCAM will be in 72- or 144-bit mode
481 * Initialize the SW state associated with MC5. Among other things
482 * this determines the size of the attached TCAM.
484 void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode)
488 static unsigned int tcam_part_size[] = { /* in K 72-bit entries */
489 64 K, 128 K, 256 K, 32 K
494 u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
496 mc5->adapter = adapter;
497 mc5->parity_enabled = 1;
498 mc5->mode = (unsigned char) mode;
499 mc5->part_type = (unsigned char) G_TMTYPE(cfg);
500 if (cfg & F_TMTYPEHI)
503 mc5->tcam_size = tcam_part_size[G_TMPARTSIZE(cfg)];
504 if (mode == MC5_MODE_144_BIT)