1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 Copyright (c) 2007-2009 Chelsio Inc.
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Neither the name of the Chelsio Corporation nor the names of its
14 contributors may be used to endorse or promote products derived from
15 this software without specific prior written permission.
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
31 ***************************************************************************/
36 CPL_PASS_OPEN_REQ = 0x1,
37 CPL_PASS_ACCEPT_RPL = 0x2,
38 CPL_ACT_OPEN_REQ = 0x3,
40 CPL_SET_TCB_FIELD = 0x5,
43 CPL_CLOSE_CON_REQ = 0x8,
44 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_RX_DATA_ACK = 0xD,
50 CPL_RTE_DELETE_REQ = 0xF,
51 CPL_RTE_WRITE_REQ = 0x10,
52 CPL_RTE_READ_REQ = 0x11,
53 CPL_L2T_WRITE_REQ = 0x12,
54 CPL_L2T_READ_REQ = 0x13,
55 CPL_SMT_WRITE_REQ = 0x14,
56 CPL_SMT_READ_REQ = 0x15,
57 CPL_TX_PKT_LSO = 0x16,
60 CPL_TID_RELEASE = 0x1A,
62 CPL_CLOSE_LISTSRV_RPL = 0x20,
64 CPL_GET_TCB_RPL = 0x22,
65 CPL_L2T_WRITE_RPL = 0x23,
66 CPL_PCMD_READ_RPL = 0x24,
68 CPL_PEER_CLOSE = 0x26,
69 CPL_RTE_DELETE_RPL = 0x27,
70 CPL_RTE_WRITE_RPL = 0x28,
71 CPL_RX_DDP_COMPLETE = 0x29,
72 CPL_RX_PHYS_ADDR = 0x2A,
74 CPL_RX_URG_NOTIFY = 0x2C,
75 CPL_SET_TCB_RPL = 0x2D,
76 CPL_SMT_WRITE_RPL = 0x2E,
77 CPL_TX_DATA_ACK = 0x2F,
79 CPL_ABORT_REQ_RSS = 0x30,
80 CPL_ABORT_RPL_RSS = 0x31,
81 CPL_CLOSE_CON_RPL = 0x32,
83 CPL_L2T_READ_RPL = 0x34,
85 CPL_RDMA_CQE_READ_RSP = 0x36,
86 CPL_RDMA_CQE_ERR = 0x37,
87 CPL_RTE_READ_RPL = 0x38,
90 CPL_ACT_OPEN_RPL = 0x40,
91 CPL_PASS_OPEN_RPL = 0x41,
92 CPL_RX_DATA_DDP = 0x42,
93 CPL_SMT_READ_RPL = 0x43,
95 CPL_ACT_ESTABLISH = 0x50,
96 CPL_PASS_ESTABLISH = 0x51,
98 CPL_PASS_ACCEPT_REQ = 0x70,
100 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */
102 CPL_TX_DMA_ACK = 0xA0,
103 CPL_RDMA_READ_REQ = 0xA1,
104 CPL_RDMA_TERMINATE = 0xA2,
105 CPL_TRACE_PKT = 0xA3,
106 CPL_RDMA_EC_STATUS = 0xA5,
107 CPL_SGE_EC_CR_RETURN = 0xA6,
109 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
114 CPL_ERR_TCAM_PARITY = 1,
115 CPL_ERR_TCAM_FULL = 3,
116 CPL_ERR_CONN_RESET = 20,
117 CPL_ERR_CONN_EXIST = 22,
118 CPL_ERR_ARP_MISS = 23,
119 CPL_ERR_BAD_SYN = 24,
120 CPL_ERR_CONN_TIMEDOUT = 30,
121 CPL_ERR_XMIT_TIMEDOUT = 31,
122 CPL_ERR_PERSIST_TIMEDOUT = 32,
123 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
124 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
125 CPL_ERR_RTX_NEG_ADVICE = 35,
126 CPL_ERR_PERSIST_NEG_ADVICE = 36,
127 CPL_ERR_ABORT_FAILED = 42,
132 CPL_CONN_POLICY_AUTO = 0,
133 CPL_CONN_POLICY_ASK = 1,
134 CPL_CONN_POLICY_FILTER = 2,
135 CPL_CONN_POLICY_DENY = 3
140 ULP_MODE_TCP_DDP = 1,
147 ULP_CRC_HEADER = 1 << 0,
148 ULP_CRC_DATA = 1 << 1
152 CPL_PASS_OPEN_ACCEPT,
153 CPL_PASS_OPEN_REJECT,
154 CPL_PASS_OPEN_ACCEPT_TNL
158 CPL_ABORT_SEND_RST = 0,
160 CPL_ABORT_POST_CLOSE_REQ = 2
163 enum { /* TX_PKT_LSO ethernet types */
170 enum { /* TCP congestion control algorithms */
177 enum { /* RSS hash type */
179 RSS_HASH_2_TUPLE = 1,
180 RSS_HASH_4_TUPLE = 2,
190 #define V_OPCODE(x) ((x) << S_OPCODE)
191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
192 #define G_TID(x) ((x) & 0xFFFFFF)
194 /* tid is assumed to be 24-bits */
195 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
197 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
199 /* extract the TID from a CPL command */
200 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
205 #if defined(__LITTLE_ENDIAN_BITFIELD)
220 #if defined(__LITTLE_ENDIAN_BITFIELD)
231 #define S_HASHTYPE 22
232 #define M_HASHTYPE 0x3
233 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
236 #define M_QNUM 0xFFFF
237 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
240 struct work_request_hdr {
252 #define wrh_hi u.ilp32.wr_hi
253 #define wrh_lo u.ilp32.wr_lo
254 #define wrh_hilo u.lp64.wr_hilo
257 #define S_WR_SGE_CREDITS 0
258 #define M_WR_SGE_CREDITS 0xFF
259 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
260 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
262 #define S_WR_SGLSFLT 8
263 #define M_WR_SGLSFLT 0xFF
264 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
265 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
267 #define S_WR_BCNTLFLT 16
268 #define M_WR_BCNTLFLT 0xF
269 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
270 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
273 * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before
274 * and after the BYPASS WR if the ATOMIC bit is set.
276 #define S_WR_ATOMIC 16
277 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
278 #define F_WR_ATOMIC V_WR_ATOMIC(1U)
281 * Applicable to BYPASS WRs only: the uP will flush buffered non abort
284 #define S_WR_FLUSH 17
285 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
286 #define F_WR_FLUSH V_WR_FLUSH(1U)
289 #define V_WR_CHN(x) ((x) << S_WR_CHN)
290 #define F_WR_CHN V_WR_CHN(1U)
292 #define S_WR_CHN_VLD 19
293 #define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD)
294 #define F_WR_CHN_VLD V_WR_CHN_VLD(1U)
296 #define S_WR_DATATYPE 20
297 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
298 #define F_WR_DATATYPE V_WR_DATATYPE(1U)
300 #define S_WR_COMPL 21
301 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
302 #define F_WR_COMPL V_WR_COMPL(1U)
305 #define V_WR_EOP(x) ((x) << S_WR_EOP)
306 #define F_WR_EOP V_WR_EOP(1U)
309 #define V_WR_SOP(x) ((x) << S_WR_SOP)
310 #define F_WR_SOP V_WR_SOP(1U)
314 #define V_WR_OP(x) ((x) << S_WR_OP)
315 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
319 #define M_WR_LEN 0xFF
320 #define V_WR_LEN(x) ((x) << S_WR_LEN)
321 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
324 #define M_WR_TID 0xFFFFF
325 #define V_WR_TID(x) ((x) << S_WR_TID)
326 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
328 #define S_WR_CR_FLUSH 30
329 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
330 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U)
333 #define V_WR_GEN(x) ((x) << S_WR_GEN)
334 #define F_WR_GEN V_WR_GEN(1U)
335 #define G_WR_GEN(x) ((x) >> S_WR_GEN)
337 # define WR_HDR struct work_request_hdr wr
341 # define RSS_HDR struct rss_header rss_hdr;
344 /* option 0 lower-half fields */
345 #define S_CPL_STATUS 0
346 #define M_CPL_STATUS 0xFF
347 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
348 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
350 #define S_INJECT_TIMER 6
351 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
352 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
354 #define S_NO_OFFLOAD 7
355 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
356 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U)
359 #define M_ULP_MODE 0xF
360 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
361 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
363 #define S_RCV_BUFSIZ 12
364 #define M_RCV_BUFSIZ 0x3FFF
365 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
366 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
370 #define V_TOS(x) ((x) << S_TOS)
371 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
373 /* option 0 upper-half fields */
375 #define V_DELACK(x) ((x) << S_DELACK)
376 #define F_DELACK V_DELACK(1U)
379 #define V_NO_CONG(x) ((x) << S_NO_CONG)
380 #define F_NO_CONG V_NO_CONG(1U)
382 #define S_SRC_MAC_SEL 2
383 #define M_SRC_MAC_SEL 0x3
384 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
385 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
388 #define M_L2T_IDX 0x7FF
389 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
390 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
392 #define S_TX_CHANNEL 15
393 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
394 #define F_TX_CHANNEL V_TX_CHANNEL(1U)
396 #define S_TCAM_BYPASS 16
397 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
398 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U)
401 #define V_NAGLE(x) ((x) << S_NAGLE)
402 #define F_NAGLE V_NAGLE(1U)
404 #define S_WND_SCALE 18
405 #define M_WND_SCALE 0xF
406 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
407 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
409 #define S_KEEP_ALIVE 22
410 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
411 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U)
413 #define S_MAX_RETRANS 23
414 #define M_MAX_RETRANS 0xF
415 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
416 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
418 #define S_MAX_RETRANS_OVERRIDE 27
419 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
420 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U)
423 #define M_MSS_IDX 0xF
424 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
425 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
427 /* option 1 fields */
428 #define S_RSS_ENABLE 0
429 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
430 #define F_RSS_ENABLE V_RSS_ENABLE(1U)
432 #define S_RSS_MASK_LEN 1
433 #define M_RSS_MASK_LEN 0x7
434 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
435 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
438 #define M_CPU_IDX 0x3F
439 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
440 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
442 #define S_OPT1_VLAN 6
443 #define M_OPT1_VLAN 0xFFF
444 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
445 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
447 #define S_MAC_MATCH_VALID 18
448 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
449 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
451 #define S_CONN_POLICY 19
452 #define M_CONN_POLICY 0x3
453 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
454 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
456 #define S_SYN_DEFENSE 21
457 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
458 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
460 #define S_VLAN_PRI 22
461 #define M_VLAN_PRI 0x3
462 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
463 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
465 #define S_VLAN_PRI_VALID 24
466 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
467 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U)
469 #define S_PKT_TYPE 25
470 #define M_PKT_TYPE 0x3
471 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
472 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
474 #define S_MAC_MATCH 27
475 #define M_MAC_MATCH 0x1F
476 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
477 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
479 /* option 2 fields */
480 #define S_CPU_INDEX 0
481 #define M_CPU_INDEX 0x7F
482 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
483 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
485 #define S_CPU_INDEX_VALID 7
486 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
487 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U)
489 #define S_RX_COALESCE 8
490 #define M_RX_COALESCE 0x3
491 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
492 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
494 #define S_RX_COALESCE_VALID 10
495 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
496 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
498 #define S_CONG_CONTROL_FLAVOR 11
499 #define M_CONG_CONTROL_FLAVOR 0x3
500 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
501 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
503 #define S_PACING_FLAVOR 13
504 #define M_PACING_FLAVOR 0x3
505 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
506 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
508 #define S_FLAVORS_VALID 15
509 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
510 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U)
512 #define S_RX_FC_DISABLE 16
513 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
514 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
516 #define S_RX_FC_VALID 17
517 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
518 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
520 struct cpl_pass_open_req {
533 struct cpl_pass_open_rpl {
544 struct cpl_pass_establish {
558 /* cpl_pass_establish.tos_tid fields */
559 #define S_PASS_OPEN_TID 0
560 #define M_PASS_OPEN_TID 0xFFFFFF
561 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
562 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
564 #define S_PASS_OPEN_TOS 24
565 #define M_PASS_OPEN_TOS 0xFF
566 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
567 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
569 /* cpl_pass_establish.l2t_idx fields */
570 #define S_L2T_IDX16 5
571 #define M_L2T_IDX16 0x7FF
572 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
573 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
575 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
576 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
577 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
578 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
579 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
580 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
582 struct cpl_pass_accept_req {
590 struct tcp_options tcp_options;
594 #if defined(__LITTLE_ENDIAN_BITFIELD)
610 struct cpl_pass_accept_rpl {
620 struct cpl_act_open_req {
633 /* cpl_act_open_req.params fields */
634 #define S_AOPEN_VLAN_PRI 9
635 #define M_AOPEN_VLAN_PRI 0x3
636 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
637 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
639 #define S_AOPEN_VLAN_PRI_VALID 11
640 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
641 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U)
643 #define S_AOPEN_PKT_TYPE 12
644 #define M_AOPEN_PKT_TYPE 0x3
645 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
646 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
648 #define S_AOPEN_MAC_MATCH 14
649 #define M_AOPEN_MAC_MATCH 0x1F
650 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
651 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
653 #define S_AOPEN_MAC_MATCH_VALID 19
654 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
655 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U)
657 #define S_AOPEN_IFF_VLAN 20
658 #define M_AOPEN_IFF_VLAN 0xFFF
659 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
660 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
662 struct cpl_act_open_rpl {
674 struct cpl_act_establish {
695 struct cpl_get_tcb_rpl {
711 /* cpl_set_tcb.reply fields */
713 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
714 #define F_NO_REPLY V_NO_REPLY(1U)
716 struct cpl_set_tcb_field {
726 struct cpl_set_tcb_rpl {
737 #if defined(__LITTLE_ENDIAN_BITFIELD)
751 struct cpl_pcmd_reply {
759 struct cpl_close_con_req {
765 struct cpl_close_con_rpl {
774 struct cpl_close_listserv_req {
782 struct cpl_close_listserv_rpl {
789 struct cpl_abort_req_rss {
798 struct cpl_abort_req {
807 struct cpl_abort_rpl_rss {
816 struct cpl_abort_rpl {
825 struct cpl_peer_close {
839 /* tx_data_wr.flags fields */
840 #define S_TX_ACK_PAGES 21
841 #define M_TX_ACK_PAGES 0x7
842 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
843 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
845 /* tx_data_wr.param fields */
847 #define M_TX_PORT 0x7
848 #define V_TX_PORT(x) ((x) << S_TX_PORT)
849 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
853 #define V_TX_MSS(x) ((x) << S_TX_MSS)
854 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
857 #define M_TX_QOS 0xFF
858 #define V_TX_QOS(x) ((x) << S_TX_QOS)
859 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
861 #define S_TX_SNDBUF 16
862 #define M_TX_SNDBUF 0xFFFF
863 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
864 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
874 /* cpl_tx_data.flags fields */
875 #define S_TX_ULP_SUBMODE 6
876 #define M_TX_ULP_SUBMODE 0xF
877 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
878 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
880 #define S_TX_ULP_MODE 10
881 #define M_TX_ULP_MODE 0xF
882 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
883 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
885 #define S_TX_SHOVE 14
886 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
887 #define F_TX_SHOVE V_TX_SHOVE(1U)
890 #define V_TX_MORE(x) ((x) << S_TX_MORE)
891 #define F_TX_MORE V_TX_MORE(1U)
893 /* additional tx_data_wr.flags fields */
894 #define S_TX_CPU_IDX 0
895 #define M_TX_CPU_IDX 0x3F
896 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
897 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
900 #define V_TX_URG(x) ((x) << S_TX_URG)
901 #define F_TX_URG V_TX_URG(1U)
903 #define S_TX_CLOSE 17
904 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
905 #define F_TX_CLOSE V_TX_CLOSE(1U)
908 #define V_TX_INIT(x) ((x) << S_TX_INIT)
909 #define F_TX_INIT V_TX_INIT(1U)
911 #define S_TX_IMM_ACK 19
912 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
913 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
915 #define S_TX_IMM_DMA 20
916 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
917 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
919 struct cpl_tx_data_ack {
934 struct cpl_sge_ec_cr_return {
942 struct cpl_rdma_ec_status {
949 struct mngt_pktsched_wr {
961 struct cpl_iscsi_hdr {
972 /* cpl_iscsi_hdr.pdu_len_ddp fields */
973 #define S_ISCSI_PDU_LEN 0
974 #define M_ISCSI_PDU_LEN 0x7FFF
975 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
976 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
978 #define S_ISCSI_DDP 15
979 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
980 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
989 #if defined(__LITTLE_ENDIAN_BITFIELD)
1005 struct cpl_rx_data_ack {
1007 union opcode_tid ot;
1011 /* cpl_rx_data_ack.ack_seq fields */
1012 #define S_RX_CREDITS 0
1013 #define M_RX_CREDITS 0x7FFFFFF
1014 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1015 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1017 #define S_RX_MODULATE 27
1018 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
1019 #define F_RX_MODULATE V_RX_MODULATE(1U)
1021 #define S_RX_FORCE_ACK 28
1022 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1023 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1025 #define S_RX_DACK_MODE 29
1026 #define M_RX_DACK_MODE 0x3
1027 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1028 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1030 #define S_RX_DACK_CHANGE 31
1031 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1032 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1034 struct cpl_rx_urg_notify {
1036 union opcode_tid ot;
1040 struct cpl_rx_ddp_complete {
1042 union opcode_tid ot;
1046 struct cpl_rx_data_ddp {
1048 union opcode_tid ot;
1057 __be32 ddpvld_status;
1060 /* cpl_rx_data_ddp.ddpvld_status fields */
1061 #define S_DDP_STATUS 0
1062 #define M_DDP_STATUS 0xFF
1063 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1064 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1066 #define S_DDP_VALID 15
1067 #define M_DDP_VALID 0x1FFFF
1068 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1069 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1071 #define S_DDP_PPOD_MISMATCH 15
1072 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1073 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1075 #define S_DDP_PDU 16
1076 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1077 #define F_DDP_PDU V_DDP_PDU(1U)
1079 #define S_DDP_LLIMIT_ERR 17
1080 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1081 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1083 #define S_DDP_PPOD_PARITY_ERR 18
1084 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1085 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1087 #define S_DDP_PADDING_ERR 19
1088 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1089 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1091 #define S_DDP_HDRCRC_ERR 20
1092 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1093 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1095 #define S_DDP_DATACRC_ERR 21
1096 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1097 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1099 #define S_DDP_INVALID_TAG 22
1100 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1101 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1103 #define S_DDP_ULIMIT_ERR 23
1104 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1105 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1107 #define S_DDP_OFFSET_ERR 24
1108 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1109 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1111 #define S_DDP_COLOR_ERR 25
1112 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1113 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1115 #define S_DDP_TID_MISMATCH 26
1116 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1117 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1119 #define S_DDP_INVALID_PPOD 27
1120 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1121 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1123 #define S_DDP_ULP_MODE 28
1124 #define M_DDP_ULP_MODE 0xF
1125 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1126 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1128 /* cpl_rx_data_ddp.ddp_report fields */
1129 #define S_DDP_OFFSET 0
1130 #define M_DDP_OFFSET 0x3FFFFF
1131 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1132 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1134 #define S_DDP_DACK_MODE 22
1135 #define M_DDP_DACK_MODE 0x3
1136 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1137 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1139 #define S_DDP_URG 24
1140 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1141 #define F_DDP_URG V_DDP_URG(1U)
1143 #define S_DDP_PSH 25
1144 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1145 #define F_DDP_PSH V_DDP_PSH(1U)
1147 #define S_DDP_BUF_COMPLETE 26
1148 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1149 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1151 #define S_DDP_BUF_TIMED_OUT 27
1152 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1153 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1155 #define S_DDP_BUF_IDX 28
1156 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1157 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1165 struct cpl_tx_pkt_coalesce {
1171 struct tx_pkt_coalesce_wr {
1173 struct cpl_tx_pkt_coalesce cpl[0];
1176 struct cpl_tx_pkt_lso {
1185 struct cpl_tx_pkt_batch_entry {
1191 struct cpl_tx_pkt_batch {
1193 struct cpl_tx_pkt_batch_entry pkt_entry[7];
1197 /* cpl_tx_pkt*.cntrl fields */
1198 #define S_TXPKT_VLAN 0
1199 #define M_TXPKT_VLAN 0xFFFF
1200 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1201 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1203 #define S_TXPKT_INTF 16
1204 #define M_TXPKT_INTF 0xF
1205 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1206 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1208 #define S_TXPKT_IPCSUM_DIS 20
1209 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1210 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U)
1212 #define S_TXPKT_L4CSUM_DIS 21
1213 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1214 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U)
1216 #define S_TXPKT_VLAN_VLD 22
1217 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1218 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U)
1220 #define S_TXPKT_LOOPBACK 23
1221 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1222 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1224 #define S_TXPKT_OPCODE 24
1225 #define M_TXPKT_OPCODE 0xFF
1226 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1227 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1229 /* cpl_tx_pkt_lso.lso_info fields */
1231 #define M_LSO_MSS 0x3FFF
1232 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1233 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1235 #define S_LSO_ETH_TYPE 14
1236 #define M_LSO_ETH_TYPE 0x3
1237 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1238 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1240 #define S_LSO_TCPHDR_WORDS 16
1241 #define M_LSO_TCPHDR_WORDS 0xF
1242 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1243 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1245 #define S_LSO_IPHDR_WORDS 20
1246 #define M_LSO_IPHDR_WORDS 0xF
1247 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1248 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1250 #define S_LSO_IPV6 24
1251 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1252 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1254 struct cpl_trace_pkt {
1257 #if defined(__LITTLE_ENDIAN_BITFIELD)
1265 #if defined(__LITTLE_ENDIAN_BITFIELD)
1273 #endif /* CHELSIO_FW */
1276 #if defined(__LITTLE_ENDIAN_BITFIELD)
1290 #if defined(__LITTLE_ENDIAN_BITFIELD)
1308 struct cpl_l2t_write_req {
1310 union opcode_tid ot;
1317 /* cpl_l2t_write_req.params fields */
1318 #define S_L2T_W_IDX 0
1319 #define M_L2T_W_IDX 0x7FF
1320 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1321 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1323 #define S_L2T_W_VLAN 11
1324 #define M_L2T_W_VLAN 0xFFF
1325 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1326 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1328 #define S_L2T_W_IFF 23
1329 #define M_L2T_W_IFF 0xF
1330 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1331 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1333 #define S_L2T_W_PRIO 27
1334 #define M_L2T_W_PRIO 0x7
1335 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1336 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1338 struct cpl_l2t_write_rpl {
1340 union opcode_tid ot;
1345 struct cpl_l2t_read_req {
1347 union opcode_tid ot;
1352 struct cpl_l2t_read_rpl {
1354 union opcode_tid ot;
1360 /* cpl_l2t_read_rpl.params fields */
1361 #define S_L2T_R_PRIO 0
1362 #define M_L2T_R_PRIO 0x7
1363 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1364 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1366 #define S_L2T_R_VLAN 8
1367 #define M_L2T_R_VLAN 0xFFF
1368 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1369 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1371 #define S_L2T_R_IFF 20
1372 #define M_L2T_R_IFF 0xF
1373 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1374 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1376 #define S_L2T_STATUS 24
1377 #define M_L2T_STATUS 0xFF
1378 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1379 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1381 struct cpl_smt_write_req {
1383 union opcode_tid ot;
1385 #if defined(__LITTLE_ENDIAN_BITFIELD)
1399 struct cpl_smt_write_rpl {
1401 union opcode_tid ot;
1406 struct cpl_smt_read_req {
1408 union opcode_tid ot;
1410 #if defined(__LITTLE_ENDIAN_BITFIELD)
1420 struct cpl_smt_read_rpl {
1422 union opcode_tid ot;
1424 #if defined(__LITTLE_ENDIAN_BITFIELD)
1438 struct cpl_rte_delete_req {
1440 union opcode_tid ot;
1444 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1445 #define S_RTE_REQ_LUT_IX 8
1446 #define M_RTE_REQ_LUT_IX 0x7FF
1447 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1448 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1450 #define S_RTE_REQ_LUT_BASE 19
1451 #define M_RTE_REQ_LUT_BASE 0x7FF
1452 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1453 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1455 #define S_RTE_READ_REQ_SELECT 31
1456 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1457 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1459 struct cpl_rte_delete_rpl {
1461 union opcode_tid ot;
1466 struct cpl_rte_write_req {
1468 union opcode_tid ot;
1469 #if defined(__LITTLE_ENDIAN_BITFIELD)
1472 __u8 write_l2t_lut:1;
1474 __u8 write_l2t_lut:1;
1486 /* cpl_rte_write_req.lut_params fields */
1487 #define S_RTE_WRITE_REQ_LUT_IX 10
1488 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF
1489 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1490 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1492 #define S_RTE_WRITE_REQ_LUT_BASE 21
1493 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF
1494 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1495 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1497 struct cpl_rte_write_rpl {
1499 union opcode_tid ot;
1504 struct cpl_rte_read_req {
1506 union opcode_tid ot;
1510 struct cpl_rte_read_rpl {
1512 union opcode_tid ot;
1516 #if defined(__LITTLE_ENDIAN_BITFIELD)
1527 struct cpl_tid_release {
1529 union opcode_tid ot;
1533 struct cpl_barrier {
1539 struct cpl_rdma_read_req {
1544 struct cpl_rdma_terminate {
1548 #if defined(__LITTLE_ENDIAN_BITFIELD)
1562 /* cpl_rdma_terminate.tid_len fields */
1563 #define S_FLIT_CNT 0
1564 #define M_FLIT_CNT 0xFF
1565 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1566 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1568 #define S_TERM_TID 8
1569 #define M_TERM_TID 0xFFFFF
1570 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1571 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1573 /* ULP_TX opcodes */
1574 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1576 #define S_ULPTX_CMD 28
1577 #define M_ULPTX_CMD 0xF
1578 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1580 #define S_ULPTX_NFLITS 0
1581 #define M_ULPTX_NFLITS 0xFF
1582 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1586 __be32 cmd_lock_addr;
1590 /* ulp_mem_io.cmd_lock_addr fields */
1591 #define S_ULP_MEMIO_ADDR 0
1592 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
1593 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1595 #define S_ULP_MEMIO_LOCK 27
1596 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1597 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
1599 /* ulp_mem_io.len fields */
1600 #define S_ULP_MEMIO_DATA_LEN 28
1601 #define M_ULP_MEMIO_DATA_LEN 0xF
1602 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1609 /* ulp_txpkt.cmd_dest fields */
1610 #define S_ULP_TXPKT_DEST 24
1611 #define M_ULP_TXPKT_DEST 0xF
1612 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1614 #endif /* T3_CPL_H */