1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 Copyright (c) 2007, Chelsio Inc.
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
10 1. Redistributions of source code must retain the above copyright notice,
11 this list of conditions and the following disclaimer.
13 2. Neither the name of the Chelsio Corporation nor the names of its
14 contributors may be used to endorse or promote products derived from
15 this software without specific prior written permission.
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
29 ***************************************************************************/
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <cxgb_include.h>
37 #define msleep t3_os_sleep
39 /* VSC8211 PHY specific registers. */
41 VSC8211_SIGDET_CTRL = 19,
42 VSC8211_EXT_CTRL = 23,
43 VSC8211_PHY_CTRL = 24,
44 VSC8211_INTR_ENABLE = 25,
45 VSC8211_INTR_STATUS = 26,
46 VSC8211_LED_CTRL = 27,
47 VSC8211_AUX_CTRL_STAT = 28,
48 VSC8211_EXT_PAGE_AXS = 31,
52 VSC_INTR_RX_ERR = 1 << 0,
53 VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */
54 VSC_INTR_CABLE = 1 << 2, /* cable impairment */
55 VSC_INTR_FALSE_CARR = 1 << 3, /* false carrier */
56 VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */
57 VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */
58 VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */
59 VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
60 VSC_INTR_SYMBOL_ERR = 1 << 8, /* symbol error */
61 VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */
62 VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */
63 VSC_INTR_DPLX_CHG = 1 << 12, /* duplex change */
64 VSC_INTR_LINK_CHG = 1 << 13, /* link change */
65 VSC_INTR_SPD_CHG = 1 << 14, /* speed change */
66 VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */
70 VSC_CTRL_CLAUSE37_VIEW = 1 << 4, /* Switch to Clause 37 view */
71 VSC_CTRL_MEDIA_MODE_HI = 0xf000 /* High part of media mode select */
74 #define CFG_CHG_INTR_MASK (VSC_INTR_LINK_CHG | VSC_INTR_NEG_ERR | \
75 VSC_INTR_DPLX_CHG | VSC_INTR_SPD_CHG | \
77 #define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \
80 /* PHY specific auxiliary control & status register fields */
81 #define S_ACSR_ACTIPHY_TMR 0
82 #define M_ACSR_ACTIPHY_TMR 0x3
83 #define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR)
85 #define S_ACSR_SPEED 3
86 #define M_ACSR_SPEED 0x3
87 #define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED)
89 #define S_ACSR_DUPLEX 5
90 #define F_ACSR_DUPLEX (1 << S_ACSR_DUPLEX)
92 #define S_ACSR_ACTIPHY 6
93 #define F_ACSR_ACTIPHY (1 << S_ACSR_ACTIPHY)
96 * Reset the PHY. This PHY completes reset immediately so we never wait.
98 static int vsc8211_reset(struct cphy *cphy, int wait)
100 return t3_phy_reset(cphy, 0, 0);
103 static int vsc8211_intr_enable(struct cphy *cphy)
105 return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, INTR_MASK);
108 static int vsc8211_intr_disable(struct cphy *cphy)
110 return mdio_write(cphy, 0, VSC8211_INTR_ENABLE, 0);
113 static int vsc8211_intr_clear(struct cphy *cphy)
117 /* Clear PHY interrupts by reading the register. */
118 return mdio_read(cphy, 0, VSC8211_INTR_STATUS, &val);
121 static int vsc8211_autoneg_enable(struct cphy *cphy)
123 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
124 BMCR_ANENABLE | BMCR_ANRESTART);
127 static int vsc8211_autoneg_restart(struct cphy *cphy)
129 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE,
133 static int vsc8211_get_link_status(struct cphy *cphy, int *link_state,
134 int *speed, int *duplex, int *fc)
136 unsigned int bmcr, status, lpa, adv;
137 int err, sp = -1, dplx = -1, pause = 0;
139 err = mdio_read(cphy, 0, MII_BMCR, &bmcr);
141 err = mdio_read(cphy, 0, MII_BMSR, &status);
147 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
148 * once more to get the current link state.
150 if (!(status & BMSR_LSTATUS))
151 err = mdio_read(cphy, 0, MII_BMSR, &status);
154 *link_state = status & BMSR_LSTATUS ? PHY_LINK_UP :
157 if (!(bmcr & BMCR_ANENABLE)) {
158 dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
159 if (bmcr & BMCR_SPEED1000)
161 else if (bmcr & BMCR_SPEED100)
165 } else if (status & BMSR_ANEGCOMPLETE) {
166 err = mdio_read(cphy, 0, VSC8211_AUX_CTRL_STAT, &status);
170 dplx = (status & F_ACSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
171 sp = G_ACSR_SPEED(status);
179 if (fc && dplx == DUPLEX_FULL) {
180 err = mdio_read(cphy, 0, MII_LPA, &lpa);
182 err = mdio_read(cphy, 0, MII_ADVERTISE, &adv);
186 if (lpa & adv & ADVERTISE_PAUSE_CAP)
187 pause = PAUSE_RX | PAUSE_TX;
188 else if ((lpa & ADVERTISE_PAUSE_CAP) &&
189 (lpa & ADVERTISE_PAUSE_ASYM) &&
190 (adv & ADVERTISE_PAUSE_ASYM))
192 else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
193 (adv & ADVERTISE_PAUSE_CAP))
206 static int vsc8211_get_link_status_fiber(struct cphy *cphy, int *link_state,
207 int *speed, int *duplex, int *fc)
209 unsigned int bmcr, status, lpa, adv;
210 int err, sp = -1, dplx = -1, pause = 0;
212 err = mdio_read(cphy, 0, MII_BMCR, &bmcr);
214 err = mdio_read(cphy, 0, MII_BMSR, &status);
220 * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
221 * once more to get the current link state.
223 if (!(status & BMSR_LSTATUS))
224 err = mdio_read(cphy, 0, MII_BMSR, &status);
227 *link_state = status & BMSR_LSTATUS ? PHY_LINK_UP :
230 if (!(bmcr & BMCR_ANENABLE)) {
231 dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
232 if (bmcr & BMCR_SPEED1000)
234 else if (bmcr & BMCR_SPEED100)
238 } else if (status & BMSR_ANEGCOMPLETE) {
239 err = mdio_read(cphy, 0, MII_LPA, &lpa);
241 err = mdio_read(cphy, 0, MII_ADVERTISE, &adv);
245 if (adv & lpa & ADVERTISE_1000XFULL) {
248 } else if (adv & lpa & ADVERTISE_1000XHALF) {
253 if (fc && dplx == DUPLEX_FULL) {
254 if (lpa & adv & ADVERTISE_1000XPAUSE)
255 pause = PAUSE_RX | PAUSE_TX;
256 else if ((lpa & ADVERTISE_1000XPAUSE) &&
257 (adv & lpa & ADVERTISE_1000XPSE_ASYM))
259 else if ((lpa & ADVERTISE_1000XPSE_ASYM) &&
260 (adv & ADVERTISE_1000XPAUSE))
274 * Enable/disable auto MDI/MDI-X in forced link speed mode.
276 static int vsc8211_set_automdi(struct cphy *phy, int enable)
280 if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0x52b5)) != 0 ||
281 (err = mdio_write(phy, 0, 18, 0x12)) != 0 ||
282 (err = mdio_write(phy, 0, 17, enable ? 0x2803 : 0x3003)) != 0 ||
283 (err = mdio_write(phy, 0, 16, 0x87fa)) != 0 ||
284 (err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0)
289 static int vsc8211_set_speed_duplex(struct cphy *phy, int speed, int duplex)
293 err = t3_set_phy_speed_duplex(phy, speed, duplex);
295 err = vsc8211_set_automdi(phy, 1);
299 static int vsc8211_power_down(struct cphy *cphy, int enable)
301 return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
302 enable ? BMCR_PDOWN : 0);
305 static int vsc8211_intr_handler(struct cphy *cphy)
308 int err, cphy_cause = 0;
310 err = mdio_read(cphy, 0, VSC8211_INTR_STATUS, &cause);
315 if (cause & CFG_CHG_INTR_MASK)
316 cphy_cause |= cphy_cause_link_change;
317 if (cause & (VSC_INTR_RX_FIFO | VSC_INTR_TX_FIFO))
318 cphy_cause |= cphy_cause_fifo_error;
322 #ifdef C99_NOT_SUPPORTED
323 static struct cphy_ops vsc8211_ops = {
326 vsc8211_intr_disable,
328 vsc8211_intr_handler,
329 vsc8211_autoneg_enable,
330 vsc8211_autoneg_restart,
333 vsc8211_set_speed_duplex,
334 vsc8211_get_link_status,
338 static struct cphy_ops vsc8211_fiber_ops = {
341 vsc8211_intr_disable,
343 vsc8211_intr_handler,
344 vsc8211_autoneg_enable,
345 vsc8211_autoneg_restart,
346 t3_phy_advertise_fiber,
348 t3_set_phy_speed_duplex,
349 vsc8211_get_link_status_fiber,
353 static struct cphy_ops vsc8211_ops = {
354 .reset = vsc8211_reset,
355 .intr_enable = vsc8211_intr_enable,
356 .intr_disable = vsc8211_intr_disable,
357 .intr_clear = vsc8211_intr_clear,
358 .intr_handler = vsc8211_intr_handler,
359 .autoneg_enable = vsc8211_autoneg_enable,
360 .autoneg_restart = vsc8211_autoneg_restart,
361 .advertise = t3_phy_advertise,
362 .set_speed_duplex = vsc8211_set_speed_duplex,
363 .get_link_status = vsc8211_get_link_status,
364 .power_down = vsc8211_power_down,
367 static struct cphy_ops vsc8211_fiber_ops = {
368 .reset = vsc8211_reset,
369 .intr_enable = vsc8211_intr_enable,
370 .intr_disable = vsc8211_intr_disable,
371 .intr_clear = vsc8211_intr_clear,
372 .intr_handler = vsc8211_intr_handler,
373 .autoneg_enable = vsc8211_autoneg_enable,
374 .autoneg_restart = vsc8211_autoneg_restart,
375 .advertise = t3_phy_advertise_fiber,
376 .set_speed_duplex = t3_set_phy_speed_duplex,
377 .get_link_status = vsc8211_get_link_status_fiber,
378 .power_down = vsc8211_power_down,
382 #define VSC8211_PHY_CTRL 24
384 #define S_VSC8211_TXFIFODEPTH 7
385 #define M_VSC8211_TXFIFODEPTH 0x7
386 #define V_VSC8211_TXFIFODEPTH(x) ((x) << S_VSC8211_TXFIFODEPTH)
387 #define G_VSC8211_TXFIFODEPTH(x) (((x) >> S_VSC8211_TXFIFODEPTH) & M_VSC8211_TXFIFODEPTH)
389 #define S_VSC8211_RXFIFODEPTH 4
390 #define M_VSC8211_RXFIFODEPTH 0x7
391 #define V_VSC8211_RXFIFODEPTH(x) ((x) << S_VSC8211_RXFIFODEPTH)
392 #define G_VSC8211_RXFIFODEPTH(x) (((x) >> S_VSC8211_RXFIFODEPTH) & M_VSC8211_RXFIFODEPTH)
394 int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port)
396 /* TX FIFO Depth set bits 9:7 to 100 (IEEE mode) */
397 unsigned int val = 4;
398 unsigned int currentregval;
402 /* Retrieve the port info structure from adater_t */
403 struct port_info *portinfo = adap2pinfo(adap, port);
405 /* What phy is this */
406 struct cphy *phy = &portinfo->phy;
408 /* Read the current value of the PHY control Register */
409 err = mdio_read(phy, 0, VSC8211_PHY_CTRL, ¤tregval);
414 /* IEEE mode supports up to 1518 bytes */
415 /* mtu does not contain the header + FCS (18 bytes) */
418 * If using a packet size > 1500 set TX FIFO Depth bits
419 * 9:7 to 011 (Jumbo packet mode)
423 regval = V_VSC8211_TXFIFODEPTH(val) | V_VSC8211_RXFIFODEPTH(val) |
424 (currentregval & ~V_VSC8211_TXFIFODEPTH(M_VSC8211_TXFIFODEPTH) &
425 ~V_VSC8211_RXFIFODEPTH(M_VSC8211_RXFIFODEPTH));
427 return mdio_write(phy, 0, VSC8211_PHY_CTRL, regval);
430 int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr,
431 const struct mdio_ops *mdio_ops)
433 struct cphy *phy = &pinfo->phy;
437 cphy_init(&pinfo->phy, pinfo->adapter, pinfo, phy_addr, &vsc8211_ops, mdio_ops,
438 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full |
439 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII |
440 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T");
441 msleep(20); /* PHY needs ~10ms to start responding to MDIO */
443 err = mdio_read(phy, 0, VSC8211_EXT_CTRL, &val);
446 if (val & VSC_CTRL_MEDIA_MODE_HI) {
447 /* copper interface, just need to configure the LEDs */
448 return mdio_write(phy, 0, VSC8211_LED_CTRL, 0x100);
451 phy->caps = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
452 SUPPORTED_MII | SUPPORTED_FIBRE | SUPPORTED_IRQ;
453 phy->desc = "1000BASE-X";
454 phy->ops = &vsc8211_fiber_ops;
456 if ((err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 1)) != 0 ||
457 (err = mdio_write(phy, 0, VSC8211_SIGDET_CTRL, 1)) != 0 ||
458 (err = mdio_write(phy, 0, VSC8211_EXT_PAGE_AXS, 0)) != 0 ||
459 (err = mdio_write(phy, 0, VSC8211_EXT_CTRL,
460 val | VSC_CTRL_CLAUSE37_VIEW)) != 0 ||
461 (err = vsc8211_reset(phy, 0)) != 0)
464 udelay(5); /* delay after reset before next SMI */