2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
58 #include "common/t4_msg.h"
59 #include "firmware/t4fw_interface.h"
61 #define KTR_CXGBE KTR_SPARE3
62 MALLOC_DECLARE(M_CXGBE);
63 #define CXGBE_UNIMPLEMENTED(s) \
64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
66 #if defined(__i386__) || defined(__amd64__)
70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
76 #ifndef SYSCTL_ADD_UQUAD
77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
78 #define sysctl_handle_64 sysctl_handle_quad
79 #define CTLTYPE_U64 CTLTYPE_QUAD
82 #if (__FreeBSD_version >= 900030) || \
83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
88 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
89 static __inline uint64_t
90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
93 KASSERT(tag == X86_BUS_SPACE_MEM,
94 ("%s: can only handle mem space", __func__));
96 return (*(volatile uint64_t *)(handle + offset));
100 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
101 bus_size_t offset, uint64_t value)
103 KASSERT(tag == X86_BUS_SPACE_MEM,
104 ("%s: can only handle mem space", __func__));
106 *(volatile uint64_t *)(bsh + offset) = value;
109 static __inline uint64_t
110 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
113 return (uint64_t)bus_space_read_4(tag, handle, offset) +
114 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
118 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
119 bus_size_t offset, uint64_t value)
121 bus_space_write_4(tag, bsh, offset, value);
122 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
127 typedef struct adapter adapter_t;
131 * All ingress queues use this entry size. Note that the firmware event
132 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
137 /* Default queue sizes for all kinds of ingress queues */
141 /* All egress queues use this entry size */
144 /* Default queue sizes for all kinds of egress queues */
148 #if MJUMPAGESIZE != MCLBYTES
149 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
151 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
153 CL_METADATA_SIZE = CACHE_LINE_SIZE,
155 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
157 TX_SGL_SEGS_TSO = 38,
158 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
162 /* adapter intr_type */
163 INTR_INTX = (1 << 0),
169 XGMAC_MTU = (1 << 0),
170 XGMAC_PROMISC = (1 << 1),
171 XGMAC_ALLMULTI = (1 << 2),
172 XGMAC_VLANEX = (1 << 3),
173 XGMAC_UCADDR = (1 << 4),
174 XGMAC_MCADDRS = (1 << 5),
180 /* flags understood by begin_synchronized_op */
181 HOLD_LOCK = (1 << 0),
185 /* flags understood by end_synchronized_op */
186 LOCK_HELD = HOLD_LOCK,
191 FULL_INIT_DONE = (1 << 0),
193 /* INTR_DIRECT = (1 << 2), No longer used. */
194 MASTER_PF = (1 << 3),
195 ADAP_SYSCTL_CTX = (1 << 4),
196 /* TOM_INIT_DONE= (1 << 5), No longer used */
197 BUF_PACKING_OK = (1 << 6),
200 CXGBE_BUSY = (1 << 9),
203 HAS_TRACEQ = (1 << 3),
207 VI_INIT_DONE = (1 << 1),
208 VI_SYSCTL_CTX = (1 << 2),
209 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
210 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
211 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
213 /* adapter debug_flags */
214 DF_DUMP_MBOX = (1 << 0),
217 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
218 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
219 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
220 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
221 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
225 struct port_info *pi;
228 struct ifmedia media;
233 uint16_t *rss, *nm_rss;
234 int smt_idx; /* for convenience */
236 int16_t xact_addr_filt;/* index of exact MAC address filter */
237 uint16_t rss_size; /* size of VI's RSS table slice */
238 uint16_t rss_base; /* start of VI's RSS table slice */
240 eventhandler_tag vlan_c;
245 /* These need to be int as they are used in sysctl */
246 int ntxq; /* # of tx queues */
247 int first_txq; /* index of first tx queue */
248 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
249 int nrxq; /* # of rx queues */
250 int first_rxq; /* index of first rx queue */
251 int nofldtxq; /* # of offload tx queues */
252 int first_ofld_txq; /* index of first offload tx queue */
253 int nofldrxq; /* # of offload rx queues */
254 int first_ofld_rxq; /* index of first offload rx queue */
264 struct timeval last_refreshed;
265 struct fw_vi_stats_vf stats;
268 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
270 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
274 /* tx_sched_class flags */
275 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */
278 struct tx_sched_class {
281 struct t4_sched_class_params params;
286 struct adapter *adapter;
293 struct tx_sched_class *tc; /* traffic classes for this channel */
299 uint8_t lport; /* associated offload logical port */
305 uint8_t rx_chan_map; /* rx MPS channel bitmap */
308 struct link_config link_cfg;
310 struct timeval last_refreshed;
311 struct port_stats stats;
312 u_int tnl_cong_drops;
313 u_int tx_parse_error;
318 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
320 /* Where the cluster came from, how it has been carved up. */
321 struct cluster_layout {
324 uint16_t region1; /* mbufs laid out within this region */
325 /* region2 is the DMA region */
326 uint16_t region3; /* cluster_metadata within this region */
329 struct cluster_metadata {
331 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
336 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
337 struct cluster_layout cll;
345 struct mbuf *m; /* m_nextpkt linked chain of frames */
346 uint8_t desc_used; /* # of hardware descriptors used by the WR */
350 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
352 struct rss_header rss;
357 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
361 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
362 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
363 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
364 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
371 /* netmap related flags */
379 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
381 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
382 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
385 * Ingress Queue: T4 is producer, driver is consumer.
390 struct adapter *adapter;
391 cpl_handler_t set_tcb_rpl;
392 cpl_handler_t l2t_write_rpl;
393 struct iq_desc *desc; /* KVA of descriptor ring */
394 int8_t intr_pktc_idx; /* packet count threshold index */
395 uint8_t gen; /* generation bit */
396 uint8_t intr_params; /* interrupt holdoff parameters */
397 uint8_t intr_next; /* XXX: holdoff for next interrupt */
398 uint16_t qsize; /* size (# of entries) of the queue */
399 uint16_t sidx; /* index of the entry with the status page */
400 uint16_t cidx; /* consumer index */
401 uint16_t cntxt_id; /* SGE context id for the iq */
402 uint16_t abs_id; /* absolute SGE id for the iq */
404 STAILQ_ENTRY(sge_iq) link;
406 bus_dma_tag_t desc_tag;
407 bus_dmamap_t desc_map;
408 bus_addr_t ba; /* bus address of descriptor ring */
417 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
418 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
419 EQ_ENABLED = (1 << 3), /* open for business */
422 /* Listed in order of preference. Update t4_sysctls too if you change these */
423 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
426 * Egress Queue: driver is producer, T4 is consumer.
428 * Note: A free list is an egress queue (driver produces the buffers and T4
429 * consumes them) but it's special enough to have its own struct (see sge_fl).
432 unsigned int flags; /* MUST be first */
433 unsigned int cntxt_id; /* SGE context id for the eq */
434 unsigned int abs_id; /* absolute SGE id for the eq */
437 struct tx_desc *desc; /* KVA of descriptor ring */
439 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
440 u_int udb_qid; /* relative qid within the doorbell page */
441 uint16_t sidx; /* index of the entry with the status page */
442 uint16_t cidx; /* consumer idx (desc idx) */
443 uint16_t pidx; /* producer idx (desc idx) */
444 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
445 uint16_t dbidx; /* pidx of the most recent doorbell */
446 uint16_t iqid; /* iq that gets egr_update for the eq */
447 uint8_t tx_chan; /* tx channel used by the eq */
448 volatile u_int equiq; /* EQUIQ outstanding */
450 bus_dma_tag_t desc_tag;
451 bus_dmamap_t desc_map;
452 bus_addr_t ba; /* bus address of descriptor ring */
456 struct sw_zone_info {
457 uma_zone_t zone; /* zone that this cluster comes from */
458 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
459 int type; /* EXT_xxx type of the cluster */
465 int8_t zidx; /* backpointer to zone; -ve means unused */
466 int8_t next; /* next hwidx for this zone; -1 means no more */
473 MEMWIN0_APERTURE = 2048,
474 MEMWIN0_BASE = 0x1b800,
476 MEMWIN1_APERTURE = 32768,
477 MEMWIN1_BASE = 0x28000,
479 MEMWIN2_APERTURE_T4 = 65536,
480 MEMWIN2_BASE_T4 = 0x30000,
482 MEMWIN2_APERTURE_T5 = 128 * 1024,
483 MEMWIN2_BASE_T5 = 0x60000,
487 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
488 uint32_t mw_base; /* constant after setup_memwin */
489 uint32_t mw_aperture; /* ditto */
490 uint32_t mw_curpos; /* protected by mw_lock */
494 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
495 FL_DOOMED = (1 << 1), /* about to be destroyed */
496 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
497 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
500 #define FL_RUNNING_LOW(fl) \
501 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
502 #define FL_NOT_RUNNING_LOW(fl) \
503 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
507 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
508 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
509 struct cluster_layout cll_def; /* default refill zone, layout */
510 uint16_t lowat; /* # of buffers <= this means fl needs help */
512 uint16_t buf_boundary;
514 /* The 16b idx all deal with hw descriptors */
515 uint16_t dbidx; /* hw pidx after last doorbell */
516 uint16_t sidx; /* index of status page */
517 volatile uint16_t hw_cidx;
519 /* The 32b idx are all buffer idx, not hardware descriptor idx */
520 uint32_t cidx; /* consumer index */
521 uint32_t pidx; /* producer index */
524 u_int rx_offset; /* offset in fl buf (when buffer packing) */
525 volatile uint32_t *udb;
527 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
528 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
529 uint64_t cl_allocated; /* # of clusters allocated */
530 uint64_t cl_recycled; /* # of clusters recycled */
531 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
533 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
538 uint16_t qsize; /* # of hw descriptors (status page included) */
539 uint16_t cntxt_id; /* SGE context id for the freelist */
540 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
541 bus_dma_tag_t desc_tag;
542 bus_dmamap_t desc_map;
544 bus_addr_t ba; /* bus address of descriptor ring */
545 struct cluster_layout cll_alt; /* alternate refill zone, layout */
550 /* txq: SGE egress queue + what's needed for Ethernet NIC */
552 struct sge_eq eq; /* MUST be first */
554 struct ifnet *ifp; /* the interface this txq belongs to */
555 struct mp_ring *r; /* tx software ring */
556 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
558 __be32 cpl_ctrl0; /* for convenience */
559 int tc_idx; /* traffic class */
561 struct task tx_reclaim_task;
562 /* stats for common events first */
564 uint64_t txcsum; /* # of times hardware assisted with checksum */
565 uint64_t tso_wrs; /* # of TSO work requests */
566 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
567 uint64_t imm_wrs; /* # of work requests with immediate data */
568 uint64_t sgl_wrs; /* # of work requests with direct SGL */
569 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
570 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
571 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
572 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
573 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
575 /* stats for not-that-common events */
576 } __aligned(CACHE_LINE_SIZE);
578 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
580 struct sge_iq iq; /* MUST be first */
581 struct sge_fl fl; /* MUST follow iq */
583 struct ifnet *ifp; /* the interface this rxq belongs to */
584 #if defined(INET) || defined(INET6)
585 struct lro_ctrl lro; /* LRO state */
588 /* stats for common events first */
590 uint64_t rxcsum; /* # of times hardware assisted with checksum */
591 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
593 /* stats for not-that-common events */
595 } __aligned(CACHE_LINE_SIZE);
597 static inline struct sge_rxq *
598 iq_to_rxq(struct sge_iq *iq)
601 return (__containerof(iq, struct sge_rxq, iq));
605 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
606 struct sge_ofld_rxq {
607 struct sge_iq iq; /* MUST be first */
608 struct sge_fl fl; /* MUST follow iq */
609 } __aligned(CACHE_LINE_SIZE);
611 static inline struct sge_ofld_rxq *
612 iq_to_ofld_rxq(struct sge_iq *iq)
615 return (__containerof(iq, struct sge_ofld_rxq, iq));
619 STAILQ_ENTRY(wrqe) link;
622 char wr[] __aligned(16);
626 TAILQ_ENTRY(wrq_cookie) link;
632 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
633 * and offload tx queues are of this type.
636 struct sge_eq eq; /* MUST be first */
638 struct adapter *adapter;
639 struct task wrq_tx_task;
641 /* Tx desc reserved but WR not "committed" yet. */
642 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
644 /* List of WRs ready to go out as soon as descriptors are available. */
645 STAILQ_HEAD(, wrqe) wr_list;
649 /* stats for common events first */
651 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
652 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
653 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
655 /* stats for not-that-common events */
658 * Scratch space for work requests that wrap around after reaching the
659 * status page, and some information about the last WR that used it.
663 uint8_t ss[SGE_MAX_WR_LEN];
665 } __aligned(CACHE_LINE_SIZE);
671 struct iq_desc *iq_desc;
673 uint16_t iq_cntxt_id;
679 uint16_t fl_cntxt_id;
686 u_int nid; /* netmap ring # for this queue */
688 /* infrequently used items after this */
690 bus_dma_tag_t iq_desc_tag;
691 bus_dmamap_t iq_desc_map;
695 bus_dma_tag_t fl_desc_tag;
696 bus_dmamap_t fl_desc_map;
698 } __aligned(CACHE_LINE_SIZE);
701 struct tx_desc *desc;
705 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
706 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
707 uint16_t dbidx; /* pidx of the most recent doorbell */
709 volatile uint32_t *udb;
712 __be32 cpl_ctrl0; /* for convenience */
713 u_int nid; /* netmap ring # for this queue */
715 /* infrequently used items after this */
717 bus_dma_tag_t desc_tag;
718 bus_dmamap_t desc_map;
721 } __aligned(CACHE_LINE_SIZE);
724 int nrxq; /* total # of Ethernet rx queues */
725 int ntxq; /* total # of Ethernet tx tx queues */
726 int nofldrxq; /* total # of TOE rx queues */
727 int nofldtxq; /* total # of TOE tx queues */
728 int nnmrxq; /* total # of netmap rx queues */
729 int nnmtxq; /* total # of netmap tx queues */
730 int niq; /* total # of ingress queues */
731 int neq; /* total # of egress queues */
733 struct sge_iq fwq; /* Firmware event queue */
734 struct sge_wrq mgmtq; /* Management queue (control queue) */
735 struct sge_wrq *ctrlq; /* Control queues */
736 struct sge_txq *txq; /* NIC tx queues */
737 struct sge_rxq *rxq; /* NIC rx queues */
738 struct sge_wrq *ofld_txq; /* TOE tx queues */
739 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
740 struct sge_nm_txq *nm_txq; /* netmap tx queues */
741 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
743 uint16_t iq_start; /* first cntxt_id */
744 uint16_t iq_base; /* first abs_id */
745 int eq_start; /* first cntxt_id */
746 int eq_base; /* first abs_id */
747 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
748 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
750 int8_t safe_hwidx1; /* may not have room for metadata */
751 int8_t safe_hwidx2; /* with room for metadata and maybe more */
752 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
753 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
757 const char *nexus_name;
758 const char *ifnet_name;
759 const char *vi_ifnet_name;
760 const char *pf03_drv_name;
761 const char *vf_nexus_name;
762 const char *vf_ifnet_name;
766 SLIST_ENTRY(adapter) link;
769 const struct devnames *names;
771 /* PCIe register resources */
773 struct resource *regs_res;
775 struct resource *msix_res;
776 bus_space_handle_t bh;
780 struct resource *udbs_res;
781 volatile uint8_t *udbs_base;
785 unsigned int vpd_busy;
786 unsigned int vpd_flag;
788 /* Interrupt information */
792 struct resource *res;
794 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
797 struct sge_nm_rxq *nm_rxq;
798 } __aligned(CACHE_LINE_SIZE) *irq;
800 int sge_kdoorbell_reg;
802 bus_dma_tag_t dmat; /* Parent DMA tag */
808 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
809 struct port_info *port[MAX_NPORTS];
810 uint8_t chan_map[MAX_NCHAN];
812 void *tom_softc; /* (struct tom_data *) */
813 struct tom_tunables tt;
814 void *iwarp_softc; /* (struct c4iw_dev *) */
815 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
816 struct l2t_data *l2t; /* L2 table */
817 struct tid_info tids;
820 int offload_map; /* ports with IFCAP_TOE enabled */
821 int active_ulds; /* ULDs activated on this adapter */
825 char ifp_lockname[16];
827 struct ifnet *ifp; /* tracer ifp */
828 struct ifmedia media;
829 int traceq; /* iq used by all tracers, -1 if none */
830 int tracer_valid; /* bitmap of valid tracers */
831 int tracer_enabled; /* bitmap of enabled tracers */
839 struct adapter_params params;
840 const struct chip_params *chip_params;
841 struct t4_virt_res vres;
853 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
858 /* Starving free lists */
859 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
860 TAILQ_HEAD(, sge_fl) sfl;
861 struct callout sfl_callout;
863 struct mtx reg_lock; /* for indirect register access */
865 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
868 const void *last_op_thr;
872 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
873 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
874 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
875 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
877 #define ASSERT_SYNCHRONIZED_OP(sc) \
878 KASSERT(IS_BUSY(sc) && \
879 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
880 ("%s: operation not synchronized.", __func__))
882 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
883 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
884 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
885 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
887 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
888 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
889 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
890 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
891 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
893 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
894 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
895 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
896 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
898 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
899 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
900 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
901 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
902 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
904 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
905 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
906 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
907 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
908 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
910 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
912 if (sc->debug_flags & DF_DUMP_MBOX) { \
914 "%s mbox %u: %016llx %016llx %016llx %016llx " \
915 "%016llx %016llx %016llx %016llx\n", \
916 device_get_nameunit(sc->dev), mbox, \
917 (unsigned long long)t4_read_reg64(sc, data_reg), \
918 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
919 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
920 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
921 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
922 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
923 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
924 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
928 #define for_each_txq(vi, iter, q) \
929 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
930 iter < vi->ntxq; ++iter, ++q)
931 #define for_each_rxq(vi, iter, q) \
932 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
933 iter < vi->nrxq; ++iter, ++q)
934 #define for_each_ofld_txq(vi, iter, q) \
935 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
936 iter < vi->nofldtxq; ++iter, ++q)
937 #define for_each_ofld_rxq(vi, iter, q) \
938 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
939 iter < vi->nofldrxq; ++iter, ++q)
940 #define for_each_nm_txq(vi, iter, q) \
941 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
942 iter < vi->nnmtxq; ++iter, ++q)
943 #define for_each_nm_rxq(vi, iter, q) \
944 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
945 iter < vi->nnmrxq; ++iter, ++q)
946 #define for_each_vi(_pi, _iter, _vi) \
947 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
950 #define IDXINCR(idx, incr, wrap) do { \
951 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
953 #define IDXDIFF(head, tail, wrap) \
954 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
956 /* One for errors, one for firmware events */
957 #define T4_EXTRA_INTR 2
959 /* One for firmware events */
960 #define T4VF_EXTRA_INTR 1
962 static inline uint32_t
963 t4_read_reg(struct adapter *sc, uint32_t reg)
966 return bus_space_read_4(sc->bt, sc->bh, reg);
970 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
973 bus_space_write_4(sc->bt, sc->bh, reg, val);
976 static inline uint64_t
977 t4_read_reg64(struct adapter *sc, uint32_t reg)
980 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
984 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
987 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
991 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
994 *val = pci_read_config(sc->dev, reg, 1);
998 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1001 pci_write_config(sc->dev, reg, val, 1);
1005 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1008 *val = pci_read_config(sc->dev, reg, 2);
1012 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1015 pci_write_config(sc->dev, reg, val, 2);
1019 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1022 *val = pci_read_config(sc->dev, reg, 4);
1026 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1029 pci_write_config(sc->dev, reg, val, 4);
1032 static inline struct port_info *
1033 adap2pinfo(struct adapter *sc, int idx)
1036 return (sc->port[idx]);
1040 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
1043 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN);
1047 is_10G_port(const struct port_info *pi)
1050 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1054 is_25G_port(const struct port_info *pi)
1057 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1061 is_40G_port(const struct port_info *pi)
1064 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1068 is_100G_port(const struct port_info *pi)
1071 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1075 port_top_speed(const struct port_info *pi)
1078 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1080 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1082 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1084 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1086 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1093 tx_resume_threshold(struct sge_eq *eq)
1096 /* not quite the same as qsize / 4, but this will do. */
1097 return (eq->sidx / 4);
1101 t4_use_ldst(struct adapter *sc)
1105 return (sc->flags & FW_OK || !sc->use_bd);
1112 extern int t4_ntxq10g;
1113 extern int t4_nrxq10g;
1114 extern int t4_ntxq1g;
1115 extern int t4_nrxq1g;
1116 extern int t4_intr_types;
1117 extern int t4_tmr_idx_10g;
1118 extern int t4_pktc_idx_10g;
1119 extern int t4_tmr_idx_1g;
1120 extern int t4_pktc_idx_1g;
1121 extern unsigned int t4_qsize_rxq;
1122 extern unsigned int t4_qsize_txq;
1123 extern device_method_t cxgbe_methods[];
1125 int t4_os_find_pci_capability(struct adapter *, int);
1126 int t4_os_pci_save_state(struct adapter *);
1127 int t4_os_pci_restore_state(struct adapter *);
1128 void t4_os_portmod_changed(const struct adapter *, int);
1129 void t4_os_link_changed(struct adapter *, int, int, int);
1130 void t4_iterate(void (*)(struct adapter *, void *), void *);
1131 void t4_init_devnames(struct adapter *);
1132 void t4_add_adapter(struct adapter *);
1133 int t4_detach_common(device_t);
1134 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1135 int t4_map_bars_0_and_4(struct adapter *);
1136 int t4_map_bar_2(struct adapter *);
1137 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1138 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1139 int t4_setup_intr_handlers(struct adapter *);
1140 void t4_sysctls(struct adapter *);
1141 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1142 void doom_vi(struct adapter *, struct vi_info *);
1143 void end_synchronized_op(struct adapter *, int);
1144 int update_mac_settings(struct ifnet *, int);
1145 int adapter_full_init(struct adapter *);
1146 int adapter_full_uninit(struct adapter *);
1147 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1148 int vi_full_init(struct vi_info *);
1149 int vi_full_uninit(struct vi_info *);
1150 void vi_sysctls(struct vi_info *);
1151 void vi_tick(void *);
1155 void cxgbe_nm_attach(struct vi_info *);
1156 void cxgbe_nm_detach(struct vi_info *);
1157 void t4_nm_intr(void *);
1161 void t4_sge_modload(void);
1162 void t4_sge_modunload(void);
1163 uint64_t t4_sge_extfree_refs(void);
1164 void t4_tweak_chip_settings(struct adapter *);
1165 int t4_read_chip_settings(struct adapter *);
1166 int t4_create_dma_tag(struct adapter *);
1167 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1168 struct sysctl_oid_list *);
1169 int t4_destroy_dma_tag(struct adapter *);
1170 int t4_setup_adapter_queues(struct adapter *);
1171 int t4_teardown_adapter_queues(struct adapter *);
1172 int t4_setup_vi_queues(struct vi_info *);
1173 int t4_teardown_vi_queues(struct vi_info *);
1174 void t4_intr_all(void *);
1175 void t4_intr(void *);
1176 void t4_vi_intr(void *);
1177 void t4_intr_err(void *);
1178 void t4_intr_evt(void *);
1179 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1180 void t4_update_fl_bufsize(struct ifnet *);
1181 int parse_pkt(struct adapter *, struct mbuf **);
1182 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1183 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1184 int tnl_cong(struct port_info *, int);
1185 int t4_register_an_handler(an_handler_t);
1186 int t4_register_fw_msg_handler(int, fw_msg_handler_t);
1187 int t4_register_cpl_handler(int, cpl_handler_t);
1191 void t4_tracer_modload(void);
1192 void t4_tracer_modunload(void);
1193 void t4_tracer_port_detach(struct adapter *);
1194 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1195 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1196 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1197 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1199 static inline struct wrqe *
1200 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1202 int len = offsetof(struct wrqe, wr) + wr_len;
1205 wr = malloc(len, M_CXGBE, M_NOWAIT);
1206 if (__predict_false(wr == NULL))
1208 wr->wr_len = wr_len;
1213 static inline void *
1214 wrtod(struct wrqe *wr)
1216 return (&wr->wr[0]);
1220 free_wrqe(struct wrqe *wr)
1226 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1228 struct sge_wrq *wrq = wr->wrq;
1231 t4_wrq_tx_locked(sc, wrq, wr);