2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
57 #include "common/t4_msg.h"
58 #include "firmware/t4fw_interface.h"
60 #define KTR_CXGBE KTR_SPARE3
61 MALLOC_DECLARE(M_CXGBE);
62 #define CXGBE_UNIMPLEMENTED(s) \
63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
65 #if defined(__i386__) || defined(__amd64__)
69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
75 #ifndef SYSCTL_ADD_UQUAD
76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
77 #define sysctl_handle_64 sysctl_handle_quad
78 #define CTLTYPE_U64 CTLTYPE_QUAD
81 #if (__FreeBSD_version >= 900030) || \
82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
88 static __inline uint64_t
89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
92 KASSERT(tag == X86_BUS_SPACE_MEM,
93 ("%s: can only handle mem space", __func__));
95 return (*(volatile uint64_t *)(handle + offset));
99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
100 bus_size_t offset, uint64_t value)
102 KASSERT(tag == X86_BUS_SPACE_MEM,
103 ("%s: can only handle mem space", __func__));
105 *(volatile uint64_t *)(bsh + offset) = value;
108 static __inline uint64_t
109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
112 return (uint64_t)bus_space_read_4(tag, handle, offset) +
113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
118 bus_size_t offset, uint64_t value)
120 bus_space_write_4(tag, bsh, offset, value);
121 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
126 typedef struct adapter adapter_t;
130 * All ingress queues use this entry size. Note that the firmware event
131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
136 /* Default queue sizes for all kinds of ingress queues */
140 /* All egress queues use this entry size */
143 /* Default queue sizes for all kinds of egress queues */
147 #if MJUMPAGESIZE != MCLBYTES
148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
152 CL_METADATA_SIZE = CACHE_LINE_SIZE,
154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
156 TX_SGL_SEGS_TSO = 38,
157 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
161 /* adapter intr_type */
162 INTR_INTX = (1 << 0),
168 XGMAC_MTU = (1 << 0),
169 XGMAC_PROMISC = (1 << 1),
170 XGMAC_ALLMULTI = (1 << 2),
171 XGMAC_VLANEX = (1 << 3),
172 XGMAC_UCADDR = (1 << 4),
173 XGMAC_MCADDRS = (1 << 5),
179 /* flags understood by begin_synchronized_op */
180 HOLD_LOCK = (1 << 0),
184 /* flags understood by end_synchronized_op */
185 LOCK_HELD = HOLD_LOCK,
190 FULL_INIT_DONE = (1 << 0),
192 /* INTR_DIRECT = (1 << 2), No longer used. */
193 MASTER_PF = (1 << 3),
194 ADAP_SYSCTL_CTX = (1 << 4),
195 /* TOM_INIT_DONE= (1 << 5), No longer used */
196 BUF_PACKING_OK = (1 << 6),
198 CXGBE_BUSY = (1 << 9),
202 PORT_INIT_DONE = (1 << 1),
203 PORT_SYSCTL_CTX = (1 << 2),
204 HAS_TRACEQ = (1 << 3),
205 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
206 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
207 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
208 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
210 /* adapter debug_flags */
211 DF_DUMP_MBOX = (1 << 0),
214 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
215 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
216 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
217 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
218 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
222 struct adapter *adapter;
225 struct ifmedia media;
234 int16_t xact_addr_filt;/* index of exact MAC address filter */
235 uint16_t rss_size; /* size of VI's RSS table slice */
236 uint16_t rss_base; /* start of VI's RSS table slice */
237 uint8_t lport; /* associated offload logical port */
243 uint8_t rx_chan_map; /* rx MPS channel bitmap */
245 /* These need to be int as they are used in sysctl */
246 int ntxq; /* # of tx queues */
247 int first_txq; /* index of first tx queue */
248 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
249 int nrxq; /* # of rx queues */
250 int first_rxq; /* index of first rx queue */
252 int nofldtxq; /* # of offload tx queues */
253 int first_ofld_txq; /* index of first offload tx queue */
254 int nofldrxq; /* # of offload rx queues */
255 int first_ofld_rxq; /* index of first offload rx queue */
258 int nnmtxq; /* # of netmap tx queues */
259 int first_nm_txq; /* index of first netmap tx queue */
260 int nnmrxq; /* # of netmap rx queues */
261 int first_nm_rxq; /* index of first netmap rx queue */
263 struct ifnet *nm_ifp;
264 struct ifmedia nm_media;
267 int16_t nm_xact_addr_filt;
268 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
276 struct link_config link_cfg;
278 struct timeval last_refreshed;
279 struct port_stats stats;
280 u_int tnl_cong_drops;
281 u_int tx_parse_error;
283 eventhandler_tag vlan_c;
286 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
288 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
291 /* Where the cluster came from, how it has been carved up. */
292 struct cluster_layout {
295 uint16_t region1; /* mbufs laid out within this region */
296 /* region2 is the DMA region */
297 uint16_t region3; /* cluster_metadata within this region */
300 struct cluster_metadata {
303 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
309 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
310 struct cluster_layout cll;
318 struct mbuf *m; /* m_nextpkt linked chain of frames */
319 uint8_t desc_used; /* # of hardware descriptors used by the WR */
323 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
325 struct rss_header rss;
330 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
334 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
335 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
336 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
337 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
346 * Ingress Queue: T4 is producer, driver is consumer.
351 struct adapter *adapter;
352 struct iq_desc *desc; /* KVA of descriptor ring */
353 int8_t intr_pktc_idx; /* packet count threshold index */
354 uint8_t gen; /* generation bit */
355 uint8_t intr_params; /* interrupt holdoff parameters */
356 uint8_t intr_next; /* XXX: holdoff for next interrupt */
357 uint16_t qsize; /* size (# of entries) of the queue */
358 uint16_t sidx; /* index of the entry with the status page */
359 uint16_t cidx; /* consumer index */
360 uint16_t cntxt_id; /* SGE context id for the iq */
361 uint16_t abs_id; /* absolute SGE id for the iq */
363 STAILQ_ENTRY(sge_iq) link;
365 bus_dma_tag_t desc_tag;
366 bus_dmamap_t desc_map;
367 bus_addr_t ba; /* bus address of descriptor ring */
376 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
377 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
378 EQ_ENABLED = (1 << 3), /* open for business */
381 /* Listed in order of preference. Update t4_sysctls too if you change these */
382 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
385 * Egress Queue: driver is producer, T4 is consumer.
387 * Note: A free list is an egress queue (driver produces the buffers and T4
388 * consumes them) but it's special enough to have its own struct (see sge_fl).
391 unsigned int flags; /* MUST be first */
392 unsigned int cntxt_id; /* SGE context id for the eq */
395 struct tx_desc *desc; /* KVA of descriptor ring */
397 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
398 u_int udb_qid; /* relative qid within the doorbell page */
399 uint16_t sidx; /* index of the entry with the status page */
400 uint16_t cidx; /* consumer idx (desc idx) */
401 uint16_t pidx; /* producer idx (desc idx) */
402 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
403 uint16_t dbidx; /* pidx of the most recent doorbell */
404 uint16_t iqid; /* iq that gets egr_update for the eq */
405 uint8_t tx_chan; /* tx channel used by the eq */
406 volatile u_int equiq; /* EQUIQ outstanding */
408 bus_dma_tag_t desc_tag;
409 bus_dmamap_t desc_map;
410 bus_addr_t ba; /* bus address of descriptor ring */
414 struct sw_zone_info {
415 uma_zone_t zone; /* zone that this cluster comes from */
416 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
417 int type; /* EXT_xxx type of the cluster */
423 int8_t zidx; /* backpointer to zone; -ve means unused */
424 int8_t next; /* next hwidx for this zone; -1 means no more */
429 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
430 FL_DOOMED = (1 << 1), /* about to be destroyed */
431 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
432 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
435 #define FL_RUNNING_LOW(fl) \
436 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
437 #define FL_NOT_RUNNING_LOW(fl) \
438 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
442 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
443 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
444 struct cluster_layout cll_def; /* default refill zone, layout */
445 uint16_t lowat; /* # of buffers <= this means fl needs help */
447 uint16_t buf_boundary;
449 /* The 16b idx all deal with hw descriptors */
450 uint16_t dbidx; /* hw pidx after last doorbell */
451 uint16_t sidx; /* index of status page */
452 volatile uint16_t hw_cidx;
454 /* The 32b idx are all buffer idx, not hardware descriptor idx */
455 uint32_t cidx; /* consumer index */
456 uint32_t pidx; /* producer index */
459 u_int rx_offset; /* offset in fl buf (when buffer packing) */
460 volatile uint32_t *udb;
462 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
463 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
464 uint64_t cl_allocated; /* # of clusters allocated */
465 uint64_t cl_recycled; /* # of clusters recycled */
466 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
468 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
473 uint16_t qsize; /* # of hw descriptors (status page included) */
474 uint16_t cntxt_id; /* SGE context id for the freelist */
475 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
476 bus_dma_tag_t desc_tag;
477 bus_dmamap_t desc_map;
479 bus_addr_t ba; /* bus address of descriptor ring */
480 struct cluster_layout cll_alt; /* alternate refill zone, layout */
485 /* txq: SGE egress queue + what's needed for Ethernet NIC */
487 struct sge_eq eq; /* MUST be first */
489 struct ifnet *ifp; /* the interface this txq belongs to */
490 struct mp_ring *r; /* tx software ring */
491 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
493 __be32 cpl_ctrl0; /* for convenience */
495 struct task tx_reclaim_task;
496 /* stats for common events first */
498 uint64_t txcsum; /* # of times hardware assisted with checksum */
499 uint64_t tso_wrs; /* # of TSO work requests */
500 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
501 uint64_t imm_wrs; /* # of work requests with immediate data */
502 uint64_t sgl_wrs; /* # of work requests with direct SGL */
503 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
504 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
505 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
506 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
507 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
509 /* stats for not-that-common events */
510 } __aligned(CACHE_LINE_SIZE);
512 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
514 struct sge_iq iq; /* MUST be first */
515 struct sge_fl fl; /* MUST follow iq */
517 struct ifnet *ifp; /* the interface this rxq belongs to */
518 #if defined(INET) || defined(INET6)
519 struct lro_ctrl lro; /* LRO state */
522 /* stats for common events first */
524 uint64_t rxcsum; /* # of times hardware assisted with checksum */
525 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
527 /* stats for not-that-common events */
529 } __aligned(CACHE_LINE_SIZE);
531 static inline struct sge_rxq *
532 iq_to_rxq(struct sge_iq *iq)
535 return (__containerof(iq, struct sge_rxq, iq));
540 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
541 struct sge_ofld_rxq {
542 struct sge_iq iq; /* MUST be first */
543 struct sge_fl fl; /* MUST follow iq */
544 } __aligned(CACHE_LINE_SIZE);
546 static inline struct sge_ofld_rxq *
547 iq_to_ofld_rxq(struct sge_iq *iq)
550 return (__containerof(iq, struct sge_ofld_rxq, iq));
555 STAILQ_ENTRY(wrqe) link;
558 char wr[] __aligned(16);
562 TAILQ_ENTRY(wrq_cookie) link;
568 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
569 * and offload tx queues are of this type.
572 struct sge_eq eq; /* MUST be first */
574 struct adapter *adapter;
575 struct task wrq_tx_task;
577 /* Tx desc reserved but WR not "committed" yet. */
578 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
580 /* List of WRs ready to go out as soon as descriptors are available. */
581 STAILQ_HEAD(, wrqe) wr_list;
585 /* stats for common events first */
587 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
588 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
589 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
591 /* stats for not-that-common events */
594 * Scratch space for work requests that wrap around after reaching the
595 * status page, and some infomation about the last WR that used it.
599 uint8_t ss[SGE_MAX_WR_LEN];
601 } __aligned(CACHE_LINE_SIZE);
606 struct port_info *pi;
608 struct iq_desc *iq_desc;
610 uint16_t iq_cntxt_id;
616 uint16_t fl_cntxt_id;
623 u_int nid; /* netmap ring # for this queue */
625 /* infrequently used items after this */
627 bus_dma_tag_t iq_desc_tag;
628 bus_dmamap_t iq_desc_map;
632 bus_dma_tag_t fl_desc_tag;
633 bus_dmamap_t fl_desc_map;
635 } __aligned(CACHE_LINE_SIZE);
638 struct tx_desc *desc;
642 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
643 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
644 uint16_t dbidx; /* pidx of the most recent doorbell */
646 volatile uint32_t *udb;
649 __be32 cpl_ctrl0; /* for convenience */
650 u_int nid; /* netmap ring # for this queue */
652 /* infrequently used items after this */
654 bus_dma_tag_t desc_tag;
655 bus_dmamap_t desc_map;
658 } __aligned(CACHE_LINE_SIZE);
662 int timer_val[SGE_NTIMERS];
663 int counter_val[SGE_NCOUNTERS];
664 int fl_starve_threshold;
665 int fl_starve_threshold2;
669 int nrxq; /* total # of Ethernet rx queues */
670 int ntxq; /* total # of Ethernet tx tx queues */
672 int nofldrxq; /* total # of TOE rx queues */
673 int nofldtxq; /* total # of TOE tx queues */
676 int nnmrxq; /* total # of netmap rx queues */
677 int nnmtxq; /* total # of netmap tx queues */
679 int niq; /* total # of ingress queues */
680 int neq; /* total # of egress queues */
682 struct sge_iq fwq; /* Firmware event queue */
683 struct sge_wrq mgmtq; /* Management queue (control queue) */
684 struct sge_wrq *ctrlq; /* Control queues */
685 struct sge_txq *txq; /* NIC tx queues */
686 struct sge_rxq *rxq; /* NIC rx queues */
688 struct sge_wrq *ofld_txq; /* TOE tx queues */
689 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
692 struct sge_nm_txq *nm_txq; /* netmap tx queues */
693 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
698 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
699 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
703 int8_t safe_hwidx1; /* may not have room for metadata */
704 int8_t safe_hwidx2; /* with room for metadata and maybe more */
705 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
706 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
710 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
712 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
713 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
716 SLIST_ENTRY(adapter) link;
720 /* PCIe register resources */
722 struct resource *regs_res;
724 struct resource *msix_res;
725 bus_space_handle_t bh;
729 struct resource *udbs_res;
730 volatile uint8_t *udbs_base;
735 /* Interrupt information */
739 struct resource *res;
744 bus_dma_tag_t dmat; /* Parent DMA tag */
749 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */
750 struct port_info *port[MAX_NPORTS];
751 uint8_t chan_map[NCHAN];
754 void *tom_softc; /* (struct tom_data *) */
755 struct tom_tunables tt;
756 void *iwarp_softc; /* (struct c4iw_dev *) */
757 void *iscsi_softc; /* (struct cxgbei_data *) */
759 struct l2t_data *l2t; /* L2 table */
760 struct tid_info tids;
765 int offload_map; /* ports with IFCAP_TOE enabled */
766 int active_ulds; /* ULDs activated on this adapter */
771 char ifp_lockname[16];
773 struct ifnet *ifp; /* tracer ifp */
774 struct ifmedia media;
775 int traceq; /* iq used by all tracers, -1 if none */
776 int tracer_valid; /* bitmap of valid tracers */
777 int tracer_enabled; /* bitmap of enabled tracers */
782 struct adapter_params params;
783 struct t4_virt_res vres;
792 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
797 /* Starving free lists */
798 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
799 TAILQ_HEAD(, sge_fl) sfl;
800 struct callout sfl_callout;
802 struct mtx regwin_lock; /* for indirect reads and memory windows */
804 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
805 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
806 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
810 const void *last_op_thr;
817 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
818 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
819 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
820 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
822 #define ASSERT_SYNCHRONIZED_OP(sc) \
823 KASSERT(IS_BUSY(sc) && \
824 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
825 ("%s: operation not synchronized.", __func__))
827 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
828 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
829 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
830 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
832 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
833 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
834 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
835 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
836 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
838 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
839 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
840 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
841 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
843 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
844 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
845 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
846 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
847 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
849 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
850 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
851 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
852 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
853 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
855 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
857 if (sc->debug_flags & DF_DUMP_MBOX) { \
859 "%s mbox %u: %016llx %016llx %016llx %016llx " \
860 "%016llx %016llx %016llx %016llx\n", \
861 device_get_nameunit(sc->dev), mbox, \
862 (unsigned long long)t4_read_reg64(sc, data_reg), \
863 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
864 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
865 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
866 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
867 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
868 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
869 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
873 #define for_each_txq(pi, iter, q) \
874 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
875 iter < pi->ntxq; ++iter, ++q)
876 #define for_each_rxq(pi, iter, q) \
877 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
878 iter < pi->nrxq; ++iter, ++q)
879 #define for_each_ofld_txq(pi, iter, q) \
880 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
881 iter < pi->nofldtxq; ++iter, ++q)
882 #define for_each_ofld_rxq(pi, iter, q) \
883 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
884 iter < pi->nofldrxq; ++iter, ++q)
885 #define for_each_nm_txq(pi, iter, q) \
886 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
887 iter < pi->nnmtxq; ++iter, ++q)
888 #define for_each_nm_rxq(pi, iter, q) \
889 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
890 iter < pi->nnmrxq; ++iter, ++q)
892 #define IDXINCR(idx, incr, wrap) do { \
893 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
895 #define IDXDIFF(head, tail, wrap) \
896 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
898 /* One for errors, one for firmware events */
899 #define T4_EXTRA_INTR 2
901 static inline uint32_t
902 t4_read_reg(struct adapter *sc, uint32_t reg)
905 return bus_space_read_4(sc->bt, sc->bh, reg);
909 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
912 bus_space_write_4(sc->bt, sc->bh, reg, val);
915 static inline uint64_t
916 t4_read_reg64(struct adapter *sc, uint32_t reg)
919 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
923 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
926 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
930 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
933 *val = pci_read_config(sc->dev, reg, 1);
937 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
940 pci_write_config(sc->dev, reg, val, 1);
944 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
947 *val = pci_read_config(sc->dev, reg, 2);
951 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
954 pci_write_config(sc->dev, reg, val, 2);
958 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
961 *val = pci_read_config(sc->dev, reg, 4);
965 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
968 pci_write_config(sc->dev, reg, val, 4);
971 static inline struct port_info *
972 adap2pinfo(struct adapter *sc, int idx)
975 return (sc->port[idx]);
979 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
982 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
986 is_10G_port(const struct port_info *pi)
989 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
993 is_40G_port(const struct port_info *pi)
996 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1000 tx_resume_threshold(struct sge_eq *eq)
1003 /* not quite the same as qsize / 4, but this will do. */
1004 return (eq->sidx / 4);
1008 int t4_os_find_pci_capability(struct adapter *, int);
1009 int t4_os_pci_save_state(struct adapter *);
1010 int t4_os_pci_restore_state(struct adapter *);
1011 void t4_os_portmod_changed(const struct adapter *, int);
1012 void t4_os_link_changed(struct adapter *, int, int, int);
1013 void t4_iterate(void (*)(struct adapter *, void *), void *);
1014 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
1015 int t4_register_an_handler(struct adapter *, an_handler_t);
1016 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
1017 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1018 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
1019 void end_synchronized_op(struct adapter *, int);
1020 int update_mac_settings(struct ifnet *, int);
1021 int adapter_full_init(struct adapter *);
1022 int adapter_full_uninit(struct adapter *);
1023 int port_full_init(struct port_info *);
1024 int port_full_uninit(struct port_info *);
1028 int create_netmap_ifnet(struct port_info *);
1029 int destroy_netmap_ifnet(struct port_info *);
1030 void t4_nm_intr(void *);
1034 void t4_sge_modload(void);
1035 void t4_sge_modunload(void);
1036 uint64_t t4_sge_extfree_refs(void);
1037 void t4_init_sge_cpl_handlers(struct adapter *);
1038 void t4_tweak_chip_settings(struct adapter *);
1039 int t4_read_chip_settings(struct adapter *);
1040 int t4_create_dma_tag(struct adapter *);
1041 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1042 struct sysctl_oid_list *);
1043 int t4_destroy_dma_tag(struct adapter *);
1044 int t4_setup_adapter_queues(struct adapter *);
1045 int t4_teardown_adapter_queues(struct adapter *);
1046 int t4_setup_port_queues(struct port_info *);
1047 int t4_teardown_port_queues(struct port_info *);
1048 void t4_intr_all(void *);
1049 void t4_intr(void *);
1050 void t4_intr_err(void *);
1051 void t4_intr_evt(void *);
1052 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1053 void t4_update_fl_bufsize(struct ifnet *);
1054 int parse_pkt(struct mbuf **);
1055 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1056 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1057 int tnl_cong(struct port_info *, int);
1061 void t4_tracer_modload(void);
1062 void t4_tracer_modunload(void);
1063 void t4_tracer_port_detach(struct adapter *);
1064 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1065 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1066 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1067 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1069 static inline struct wrqe *
1070 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1072 int len = offsetof(struct wrqe, wr) + wr_len;
1075 wr = malloc(len, M_CXGBE, M_NOWAIT);
1076 if (__predict_false(wr == NULL))
1078 wr->wr_len = wr_len;
1083 static inline void *
1084 wrtod(struct wrqe *wr)
1086 return (&wr->wr[0]);
1090 free_wrqe(struct wrqe *wr)
1096 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1098 struct sge_wrq *wrq = wr->wrq;
1101 t4_wrq_tx_locked(sc, wrq, wr);