2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
57 #include "common/t4_msg.h"
58 #include "firmware/t4fw_interface.h"
60 MALLOC_DECLARE(M_CXGBE);
61 #define CXGBE_UNIMPLEMENTED(s) \
62 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
64 #if defined(__i386__) || defined(__amd64__)
68 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
74 #ifndef SYSCTL_ADD_UQUAD
75 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
76 #define sysctl_handle_64 sysctl_handle_quad
77 #define CTLTYPE_U64 CTLTYPE_QUAD
80 #if (__FreeBSD_version >= 900030) || \
81 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
86 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
87 static __inline uint64_t
88 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
91 KASSERT(tag == X86_BUS_SPACE_MEM,
92 ("%s: can only handle mem space", __func__));
94 return (*(volatile uint64_t *)(handle + offset));
98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
99 bus_size_t offset, uint64_t value)
101 KASSERT(tag == X86_BUS_SPACE_MEM,
102 ("%s: can only handle mem space", __func__));
104 *(volatile uint64_t *)(bsh + offset) = value;
107 static __inline uint64_t
108 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
111 return (uint64_t)bus_space_read_4(tag, handle, offset) +
112 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
116 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
117 bus_size_t offset, uint64_t value)
119 bus_space_write_4(tag, bsh, offset, value);
120 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
125 typedef struct adapter adapter_t;
129 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
132 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
134 EQ_ESIZE = 64, /* All egress queues use this entry size */
135 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
137 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
138 #if MJUMPAGESIZE != MCLBYTES
139 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
141 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
143 CL_METADATA_SIZE = CACHE_LINE_SIZE,
149 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
153 /* adapter intr_type */
154 INTR_INTX = (1 << 0),
160 XGMAC_MTU = (1 << 0),
161 XGMAC_PROMISC = (1 << 1),
162 XGMAC_ALLMULTI = (1 << 2),
163 XGMAC_VLANEX = (1 << 3),
164 XGMAC_UCADDR = (1 << 4),
165 XGMAC_MCADDRS = (1 << 5),
171 /* flags understood by begin_synchronized_op */
172 HOLD_LOCK = (1 << 0),
176 /* flags understood by end_synchronized_op */
177 LOCK_HELD = HOLD_LOCK,
182 FULL_INIT_DONE = (1 << 0),
184 /* INTR_DIRECT = (1 << 2), No longer used. */
185 MASTER_PF = (1 << 3),
186 ADAP_SYSCTL_CTX = (1 << 4),
187 TOM_INIT_DONE = (1 << 5),
188 BUF_PACKING_OK = (1 << 6),
190 CXGBE_BUSY = (1 << 9),
194 PORT_INIT_DONE = (1 << 1),
195 PORT_SYSCTL_CTX = (1 << 2),
196 HAS_TRACEQ = (1 << 3),
197 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
198 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
199 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
200 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
203 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
204 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
205 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
206 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
207 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
211 struct adapter *adapter;
214 struct ifmedia media;
223 int16_t xact_addr_filt;/* index of exact MAC address filter */
224 uint16_t rss_size; /* size of VI's RSS table slice */
225 uint8_t lport; /* associated offload logical port */
231 uint8_t rx_chan_map; /* rx MPS channel bitmap */
233 /* These need to be int as they are used in sysctl */
234 int ntxq; /* # of tx queues */
235 int first_txq; /* index of first tx queue */
236 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
237 int nrxq; /* # of rx queues */
238 int first_rxq; /* index of first rx queue */
240 int nofldtxq; /* # of offload tx queues */
241 int first_ofld_txq; /* index of first offload tx queue */
242 int nofldrxq; /* # of offload rx queues */
243 int first_ofld_rxq; /* index of first offload rx queue */
246 int nnmtxq; /* # of netmap tx queues */
247 int first_nm_txq; /* index of first netmap tx queue */
248 int nnmrxq; /* # of netmap rx queues */
249 int first_nm_rxq; /* index of first netmap rx queue */
251 struct ifnet *nm_ifp;
252 struct ifmedia nm_media;
255 int16_t nm_xact_addr_filt;
256 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
264 struct link_config link_cfg;
265 struct port_stats stats;
267 eventhandler_tag vlan_c;
270 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
272 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
275 /* Where the cluster came from, how it has been carved up. */
276 struct cluster_layout {
279 uint16_t region1; /* mbufs laid out within this region */
280 /* region2 is the DMA region */
281 uint16_t region3; /* cluster_metadata within this region */
284 struct cluster_metadata {
287 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
294 struct cluster_layout cll;
306 /* DMA maps used for tx */
309 uint32_t map_total; /* # of DMA maps */
310 uint32_t map_pidx; /* next map to be used */
311 uint32_t map_cidx; /* reclaimed up to this index */
312 uint32_t map_avail; /* # of available maps */
316 uint8_t desc_used; /* # of hardware descriptors used by the WR */
317 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
322 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
323 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
324 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
325 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
334 * Ingress Queue: T4 is producer, driver is consumer.
337 bus_dma_tag_t desc_tag;
338 bus_dmamap_t desc_map;
339 bus_addr_t ba; /* bus address of descriptor ring */
341 uint16_t abs_id; /* absolute SGE id for the iq */
342 int8_t intr_pktc_idx; /* packet count threshold index */
344 __be64 *desc; /* KVA of descriptor ring */
347 struct adapter *adapter;
348 const __be64 *cdesc; /* current descriptor */
349 uint8_t gen; /* generation bit */
350 uint8_t intr_params; /* interrupt holdoff parameters */
351 uint8_t intr_next; /* XXX: holdoff for next interrupt */
352 uint8_t esize; /* size (bytes) of each entry in the queue */
353 uint16_t qsize; /* size (# of entries) of the queue */
354 uint16_t cidx; /* consumer index */
355 uint16_t cntxt_id; /* SGE context id for the iq */
357 STAILQ_ENTRY(sge_iq) link;
368 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
369 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
370 EQ_DOOMED = (1 << 4), /* about to be destroyed */
371 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
372 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
375 /* Listed in order of preference. Update t4_sysctls too if you change these */
376 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
379 * Egress Queue: driver is producer, T4 is consumer.
381 * Note: A free list is an egress queue (driver produces the buffers and T4
382 * consumes them) but it's special enough to have its own struct (see sge_fl).
385 unsigned int flags; /* MUST be first */
386 unsigned int cntxt_id; /* SGE context id for the eq */
387 bus_dma_tag_t desc_tag;
388 bus_dmamap_t desc_map;
392 struct tx_desc *desc; /* KVA of descriptor ring */
393 bus_addr_t ba; /* bus address of descriptor ring */
394 struct sge_qstat *spg; /* status page, for convenience */
396 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
397 u_int udb_qid; /* relative qid within the doorbell page */
398 uint16_t cap; /* max # of desc, for convenience */
399 uint16_t avail; /* available descriptors, for convenience */
400 uint16_t qsize; /* size (# of entries) of the queue */
401 uint16_t cidx; /* consumer idx (desc idx) */
402 uint16_t pidx; /* producer idx (desc idx) */
403 uint16_t pending; /* # of descriptors used since last doorbell */
404 uint16_t iqid; /* iq that gets egr_update for the eq */
405 uint8_t tx_chan; /* tx channel used by the eq */
407 struct callout tx_callout;
411 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
412 uint32_t unstalled; /* recovered from stall */
415 struct sw_zone_info {
416 uma_zone_t zone; /* zone that this cluster comes from */
417 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
418 int type; /* EXT_xxx type of the cluster */
424 int8_t zidx; /* backpointer to zone; -ve means unused */
425 int8_t next; /* next hwidx for this zone; -1 means no more */
430 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
431 FL_DOOMED = (1 << 1), /* about to be destroyed */
432 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
435 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
436 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
439 bus_dma_tag_t desc_tag;
440 bus_dmamap_t desc_map;
441 struct cluster_layout cll_def; /* default refill zone, layout */
442 struct cluster_layout cll_alt; /* alternate refill zone, layout */
447 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
448 bus_addr_t ba; /* bus address of descriptor ring */
449 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
450 uint32_t cap; /* max # of buffers, for convenience */
451 uint16_t qsize; /* size (# of entries) of the queue */
452 uint16_t cntxt_id; /* SGE context id for the freelist */
453 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
454 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */
455 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
456 uint32_t needed; /* # of buffers needed to fill up fl. */
457 uint32_t lowat; /* # of buffers <= this means fl needs help */
458 uint32_t pending; /* # of bufs allocated since last doorbell */
459 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
465 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
466 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
467 uint64_t cl_allocated; /* # of clusters allocated */
468 uint64_t cl_recycled; /* # of clusters recycled */
469 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
472 /* txq: SGE egress queue + what's needed for Ethernet NIC */
474 struct sge_eq eq; /* MUST be first */
476 struct ifnet *ifp; /* the interface this txq belongs to */
477 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
478 struct buf_ring *br; /* tx buffer ring */
479 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
480 struct mbuf *m; /* held up due to temporary resource shortage */
482 struct tx_maps txmaps;
484 /* stats for common events first */
486 uint64_t txcsum; /* # of times hardware assisted with checksum */
487 uint64_t tso_wrs; /* # of TSO work requests */
488 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
489 uint64_t imm_wrs; /* # of work requests with immediate data */
490 uint64_t sgl_wrs; /* # of work requests with direct SGL */
491 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
492 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
493 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
495 /* stats for not-that-common events */
497 uint32_t no_dmamap; /* no DMA map to load the mbuf */
498 uint32_t no_desc; /* out of hardware descriptors */
499 } __aligned(CACHE_LINE_SIZE);
501 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
503 struct sge_iq iq; /* MUST be first */
504 struct sge_fl fl; /* MUST follow iq */
506 struct ifnet *ifp; /* the interface this rxq belongs to */
507 #if defined(INET) || defined(INET6)
508 struct lro_ctrl lro; /* LRO state */
511 /* stats for common events first */
513 uint64_t rxcsum; /* # of times hardware assisted with checksum */
514 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
516 /* stats for not-that-common events */
518 } __aligned(CACHE_LINE_SIZE);
520 static inline struct sge_rxq *
521 iq_to_rxq(struct sge_iq *iq)
524 return (__containerof(iq, struct sge_rxq, iq));
529 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
530 struct sge_ofld_rxq {
531 struct sge_iq iq; /* MUST be first */
532 struct sge_fl fl; /* MUST follow iq */
533 } __aligned(CACHE_LINE_SIZE);
535 static inline struct sge_ofld_rxq *
536 iq_to_ofld_rxq(struct sge_iq *iq)
539 return (__containerof(iq, struct sge_ofld_rxq, iq));
544 STAILQ_ENTRY(wrqe) link;
547 uint64_t wr[] __aligned(16);
551 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
552 * and offload tx queues are of this type.
555 struct sge_eq eq; /* MUST be first */
557 struct adapter *adapter;
559 /* List of WRs held up due to lack of tx descriptors */
560 STAILQ_HEAD(, wrqe) wr_list;
562 /* stats for common events first */
564 uint64_t tx_wrs; /* # of tx work requests */
566 /* stats for not-that-common events */
568 uint32_t no_desc; /* out of hardware descriptors */
569 } __aligned(CACHE_LINE_SIZE);
573 #define CPL_PAD (RX_IQ_ESIZE - sizeof(struct rsp_ctrl) - \
574 sizeof(struct rss_header))
576 struct rss_header rss;
578 uint8_t cpl[CPL_PAD];
579 struct cpl_fw6_msg fw6_msg;
580 struct cpl_rx_pkt rx_pkt;
584 CTASSERT(sizeof(struct nm_iq_desc) == RX_IQ_ESIZE);
587 struct port_info *pi;
589 struct nm_iq_desc *iq_desc;
591 uint16_t iq_cntxt_id;
597 uint16_t fl_cntxt_id;
604 u_int nid; /* netmap ring # for this queue */
606 /* infrequently used items after this */
608 bus_dma_tag_t iq_desc_tag;
609 bus_dmamap_t iq_desc_map;
613 bus_dma_tag_t fl_desc_tag;
614 bus_dmamap_t fl_desc_map;
616 } __aligned(CACHE_LINE_SIZE);
619 struct tx_desc *desc;
623 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
624 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
625 uint16_t dbidx; /* pidx of the most recent doorbell */
627 volatile uint32_t *udb;
630 __be32 cpl_ctrl0; /* for convenience */
631 u_int nid; /* netmap ring # for this queue */
633 /* infrequently used items after this */
635 bus_dma_tag_t desc_tag;
636 bus_dmamap_t desc_map;
639 } __aligned(CACHE_LINE_SIZE);
643 int timer_val[SGE_NTIMERS];
644 int counter_val[SGE_NCOUNTERS];
645 int fl_starve_threshold;
646 int fl_starve_threshold2;
650 int nrxq; /* total # of Ethernet rx queues */
651 int ntxq; /* total # of Ethernet tx tx queues */
653 int nofldrxq; /* total # of TOE rx queues */
654 int nofldtxq; /* total # of TOE tx queues */
657 int nnmrxq; /* total # of netmap rx queues */
658 int nnmtxq; /* total # of netmap tx queues */
660 int niq; /* total # of ingress queues */
661 int neq; /* total # of egress queues */
663 struct sge_iq fwq; /* Firmware event queue */
664 struct sge_wrq mgmtq; /* Management queue (control queue) */
665 struct sge_wrq *ctrlq; /* Control queues */
666 struct sge_txq *txq; /* NIC tx queues */
667 struct sge_rxq *rxq; /* NIC rx queues */
669 struct sge_wrq *ofld_txq; /* TOE tx queues */
670 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
673 struct sge_nm_txq *nm_txq; /* netmap tx queues */
674 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
679 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
680 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
683 int8_t safe_hwidx1; /* may not have room for metadata */
684 int8_t safe_hwidx2; /* with room for metadata and maybe more */
685 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
686 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
690 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
692 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
693 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
696 SLIST_ENTRY(adapter) link;
700 /* PCIe register resources */
702 struct resource *regs_res;
704 struct resource *msix_res;
705 bus_space_handle_t bh;
709 struct resource *udbs_res;
710 volatile uint8_t *udbs_base;
715 /* Interrupt information */
719 struct resource *res;
724 bus_dma_tag_t dmat; /* Parent DMA tag */
729 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
730 struct port_info *port[MAX_NPORTS];
731 uint8_t chan_map[NCHAN];
734 void *tom_softc; /* (struct tom_data *) */
735 struct tom_tunables tt;
736 void *iwarp_softc; /* (struct c4iw_dev *) */
738 struct l2t_data *l2t; /* L2 table */
739 struct tid_info tids;
748 char ifp_lockname[16];
750 struct ifnet *ifp; /* tracer ifp */
751 struct ifmedia media;
752 int traceq; /* iq used by all tracers, -1 if none */
753 int tracer_valid; /* bitmap of valid tracers */
754 int tracer_enabled; /* bitmap of enabled tracers */
759 struct adapter_params params;
760 struct t4_virt_res vres;
769 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
774 /* Starving free lists */
775 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
776 TAILQ_HEAD(, sge_fl) sfl;
777 struct callout sfl_callout;
779 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
780 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
781 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
785 const void *last_op_thr;
791 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
792 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
793 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
794 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
796 /* XXX: not bulletproof, but much better than nothing */
797 #define ASSERT_SYNCHRONIZED_OP(sc) \
798 KASSERT(IS_BUSY(sc) && \
799 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
800 ("%s: operation not synchronized.", __func__))
802 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
803 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
804 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
805 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
807 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
808 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
809 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
810 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
811 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
813 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
814 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
815 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
816 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
818 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
819 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
820 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
821 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
822 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
824 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
825 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
826 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
827 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
828 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
830 #define for_each_txq(pi, iter, q) \
831 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
832 iter < pi->ntxq; ++iter, ++q)
833 #define for_each_rxq(pi, iter, q) \
834 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
835 iter < pi->nrxq; ++iter, ++q)
836 #define for_each_ofld_txq(pi, iter, q) \
837 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
838 iter < pi->nofldtxq; ++iter, ++q)
839 #define for_each_ofld_rxq(pi, iter, q) \
840 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
841 iter < pi->nofldrxq; ++iter, ++q)
842 #define for_each_nm_txq(pi, iter, q) \
843 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
844 iter < pi->nnmtxq; ++iter, ++q)
845 #define for_each_nm_rxq(pi, iter, q) \
846 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
847 iter < pi->nnmrxq; ++iter, ++q)
849 /* One for errors, one for firmware events */
850 #define T4_EXTRA_INTR 2
852 static inline uint32_t
853 t4_read_reg(struct adapter *sc, uint32_t reg)
856 return bus_space_read_4(sc->bt, sc->bh, reg);
860 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
863 bus_space_write_4(sc->bt, sc->bh, reg, val);
866 static inline uint64_t
867 t4_read_reg64(struct adapter *sc, uint32_t reg)
870 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
874 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
877 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
881 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
884 *val = pci_read_config(sc->dev, reg, 1);
888 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
891 pci_write_config(sc->dev, reg, val, 1);
895 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
898 *val = pci_read_config(sc->dev, reg, 2);
902 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
905 pci_write_config(sc->dev, reg, val, 2);
909 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
912 *val = pci_read_config(sc->dev, reg, 4);
916 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
919 pci_write_config(sc->dev, reg, val, 4);
922 static inline struct port_info *
923 adap2pinfo(struct adapter *sc, int idx)
926 return (sc->port[idx]);
930 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
933 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
937 is_10G_port(const struct port_info *pi)
940 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
944 is_40G_port(const struct port_info *pi)
947 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
951 tx_resume_threshold(struct sge_eq *eq)
954 return (eq->qsize / 4);
958 void t4_tx_task(void *, int);
959 void t4_tx_callout(void *);
960 int t4_os_find_pci_capability(struct adapter *, int);
961 int t4_os_pci_save_state(struct adapter *);
962 int t4_os_pci_restore_state(struct adapter *);
963 void t4_os_portmod_changed(const struct adapter *, int);
964 void t4_os_link_changed(struct adapter *, int, int, int);
965 void t4_iterate(void (*)(struct adapter *, void *), void *);
966 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
967 int t4_register_an_handler(struct adapter *, an_handler_t);
968 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
969 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
970 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
971 void end_synchronized_op(struct adapter *, int);
972 int update_mac_settings(struct ifnet *, int);
973 int adapter_full_init(struct adapter *);
974 int adapter_full_uninit(struct adapter *);
975 int port_full_init(struct port_info *);
976 int port_full_uninit(struct port_info *);
980 int create_netmap_ifnet(struct port_info *);
981 int destroy_netmap_ifnet(struct port_info *);
982 void t4_nm_intr(void *);
986 void t4_sge_modload(void);
987 void t4_init_sge_cpl_handlers(struct adapter *);
988 void t4_tweak_chip_settings(struct adapter *);
989 int t4_read_chip_settings(struct adapter *);
990 int t4_create_dma_tag(struct adapter *);
991 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
992 struct sysctl_oid_list *);
993 int t4_destroy_dma_tag(struct adapter *);
994 int t4_setup_adapter_queues(struct adapter *);
995 int t4_teardown_adapter_queues(struct adapter *);
996 int t4_setup_port_queues(struct port_info *);
997 int t4_teardown_port_queues(struct port_info *);
998 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
999 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
1000 void t4_intr_all(void *);
1001 void t4_intr(void *);
1002 void t4_intr_err(void *);
1003 void t4_intr_evt(void *);
1004 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1005 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
1006 void t4_update_fl_bufsize(struct ifnet *);
1007 int can_resume_tx(struct sge_eq *);
1011 void t4_tracer_modload(void);
1012 void t4_tracer_modunload(void);
1013 void t4_tracer_port_detach(struct adapter *);
1014 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1015 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1016 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1017 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1019 static inline struct wrqe *
1020 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1022 int len = offsetof(struct wrqe, wr) + wr_len;
1025 wr = malloc(len, M_CXGBE, M_NOWAIT);
1026 if (__predict_false(wr == NULL))
1028 wr->wr_len = wr_len;
1033 static inline void *
1034 wrtod(struct wrqe *wr)
1036 return (&wr->wr[0]);
1040 free_wrqe(struct wrqe *wr)
1046 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1048 struct sge_wrq *wrq = wr->wrq;
1051 t4_wrq_tx_locked(sc, wrq, wr);