2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
39 #include <sys/types.h>
41 #include <sys/malloc.h>
42 #include <sys/rwlock.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <machine/bus.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
53 #include <net/if_var.h>
54 #include <net/if_media.h>
55 #include <netinet/in.h>
56 #include <netinet/tcp_lro.h>
60 #include "common/t4_msg.h"
61 #include "firmware/t4fw_interface.h"
63 #define KTR_CXGBE KTR_SPARE3
64 MALLOC_DECLARE(M_CXGBE);
65 #define CXGBE_UNIMPLEMENTED(s) \
66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
68 #if defined(__i386__) || defined(__amd64__)
72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
75 #define prefetch(x) __builtin_prefetch(x)
78 #ifndef SYSCTL_ADD_UQUAD
79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
80 #define sysctl_handle_64 sysctl_handle_quad
81 #define CTLTYPE_U64 CTLTYPE_QUAD
84 #if (__FreeBSD_version >= 900030) || \
85 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
90 typedef struct adapter adapter_t;
94 * All ingress queues use this entry size. Note that the firmware event
95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
100 /* Default queue sizes for all kinds of ingress queues */
104 /* All egress queues use this entry size */
107 /* Default queue sizes for all kinds of egress queues */
111 #if MJUMPAGESIZE != MCLBYTES
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
116 CL_METADATA_SIZE = CACHE_LINE_SIZE,
118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
120 TX_SGL_SEGS_TSO = 38,
121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
125 /* adapter intr_type */
126 INTR_INTX = (1 << 0),
132 XGMAC_MTU = (1 << 0),
133 XGMAC_PROMISC = (1 << 1),
134 XGMAC_ALLMULTI = (1 << 2),
135 XGMAC_VLANEX = (1 << 3),
136 XGMAC_UCADDR = (1 << 4),
137 XGMAC_MCADDRS = (1 << 5),
143 /* flags understood by begin_synchronized_op */
144 HOLD_LOCK = (1 << 0),
148 /* flags understood by end_synchronized_op */
149 LOCK_HELD = HOLD_LOCK,
154 FULL_INIT_DONE = (1 << 0),
156 CHK_MBOX_ACCESS = (1 << 2),
157 MASTER_PF = (1 << 3),
158 ADAP_SYSCTL_CTX = (1 << 4),
159 /* TOM_INIT_DONE= (1 << 5), No longer used */
160 BUF_PACKING_OK = (1 << 6),
163 CXGBE_BUSY = (1 << 9),
166 HAS_TRACEQ = (1 << 3),
170 VI_INIT_DONE = (1 << 1),
171 VI_SYSCTL_CTX = (1 << 2),
173 /* adapter debug_flags */
174 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
175 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
176 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
179 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
180 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
181 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
182 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
183 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
187 struct port_info *pi;
194 uint16_t *rss, *nm_rss;
195 int smt_idx; /* for convenience */
197 int16_t xact_addr_filt;/* index of exact MAC address filter */
198 uint16_t rss_size; /* size of VI's RSS table slice */
199 uint16_t rss_base; /* start of VI's RSS table slice */
201 eventhandler_tag vlan_c;
206 /* These need to be int as they are used in sysctl */
207 int ntxq; /* # of tx queues */
208 int first_txq; /* index of first tx queue */
209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
210 int nrxq; /* # of rx queues */
211 int first_rxq; /* index of first rx queue */
212 int nofldtxq; /* # of offload tx queues */
213 int first_ofld_txq; /* index of first offload tx queue */
214 int nofldrxq; /* # of offload rx queues */
215 int first_ofld_rxq; /* index of first offload rx queue */
227 struct timeval last_refreshed;
228 struct fw_vi_stats_vf stats;
231 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
233 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
236 struct tx_ch_rl_params {
237 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
242 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */
243 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */
246 struct tx_cl_rl_params {
249 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
250 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
251 enum fw_sched_params_mode mode; /* aggr or per-flow */
256 /* Tx scheduler parameters for a channel/port */
257 struct tx_sched_params {
258 /* Channel Rate Limiter */
259 struct tx_ch_rl_params ch_rl;
264 /* Class Rate Limiter */
265 struct tx_cl_rl_params cl_rl[];
270 struct adapter *adapter;
277 struct tx_sched_params *sched_params;
283 uint8_t lport; /* associated offload logical port */
289 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
290 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
292 struct link_config link_cfg;
293 struct link_config old_link_cfg;
294 struct ifmedia media;
296 struct timeval last_refreshed;
297 struct port_stats stats;
298 u_int tnl_cong_drops;
299 u_int tx_parse_error;
300 u_long tx_tls_records;
301 u_long tx_tls_octets;
302 u_long rx_tls_records;
303 u_long rx_tls_octets;
308 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
310 /* Where the cluster came from, how it has been carved up. */
311 struct cluster_layout {
314 uint16_t region1; /* mbufs laid out within this region */
315 /* region2 is the DMA region */
316 uint16_t region3; /* cluster_metadata within this region */
319 struct cluster_metadata {
321 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
326 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
327 struct cluster_layout cll;
335 struct mbuf *m; /* m_nextpkt linked chain of frames */
336 uint8_t desc_used; /* # of hardware descriptors used by the WR */
340 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
342 struct rss_header rss;
347 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
351 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
352 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
353 /* 1 << 2 Used to be IQ_INTR */
354 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
355 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
362 /* netmap related flags */
369 CPL_COOKIE_RESERVED = 0,
374 CPL_COOKIE_AVAILABLE1,
375 CPL_COOKIE_AVAILABLE2,
376 CPL_COOKIE_AVAILABLE3,
378 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
383 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
385 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
386 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
389 * Ingress Queue: T4 is producer, driver is consumer.
394 struct adapter *adapter;
395 struct iq_desc *desc; /* KVA of descriptor ring */
396 int8_t intr_pktc_idx; /* packet count threshold index */
397 uint8_t gen; /* generation bit */
398 uint8_t intr_params; /* interrupt holdoff parameters */
399 uint8_t intr_next; /* XXX: holdoff for next interrupt */
400 uint16_t qsize; /* size (# of entries) of the queue */
401 uint16_t sidx; /* index of the entry with the status page */
402 uint16_t cidx; /* consumer index */
403 uint16_t cntxt_id; /* SGE context id for the iq */
404 uint16_t abs_id; /* absolute SGE id for the iq */
406 STAILQ_ENTRY(sge_iq) link;
408 bus_dma_tag_t desc_tag;
409 bus_dmamap_t desc_map;
410 bus_addr_t ba; /* bus address of descriptor ring */
419 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
420 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
421 EQ_ENABLED = (1 << 3), /* open for business */
422 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
425 /* Listed in order of preference. Update t4_sysctls too if you change these */
426 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
429 * Egress Queue: driver is producer, T4 is consumer.
431 * Note: A free list is an egress queue (driver produces the buffers and T4
432 * consumes them) but it's special enough to have its own struct (see sge_fl).
435 unsigned int flags; /* MUST be first */
436 unsigned int cntxt_id; /* SGE context id for the eq */
437 unsigned int abs_id; /* absolute SGE id for the eq */
440 struct tx_desc *desc; /* KVA of descriptor ring */
442 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
443 u_int udb_qid; /* relative qid within the doorbell page */
444 uint16_t sidx; /* index of the entry with the status page */
445 uint16_t cidx; /* consumer idx (desc idx) */
446 uint16_t pidx; /* producer idx (desc idx) */
447 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
448 uint16_t dbidx; /* pidx of the most recent doorbell */
449 uint16_t iqid; /* iq that gets egr_update for the eq */
450 uint8_t tx_chan; /* tx channel used by the eq */
451 volatile u_int equiq; /* EQUIQ outstanding */
453 bus_dma_tag_t desc_tag;
454 bus_dmamap_t desc_map;
455 bus_addr_t ba; /* bus address of descriptor ring */
459 struct sw_zone_info {
460 uma_zone_t zone; /* zone that this cluster comes from */
461 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
462 int type; /* EXT_xxx type of the cluster */
468 int8_t zidx; /* backpointer to zone; -ve means unused */
469 int8_t next; /* next hwidx for this zone; -1 means no more */
476 MEMWIN0_APERTURE = 2048,
477 MEMWIN0_BASE = 0x1b800,
479 MEMWIN1_APERTURE = 32768,
480 MEMWIN1_BASE = 0x28000,
482 MEMWIN2_APERTURE_T4 = 65536,
483 MEMWIN2_BASE_T4 = 0x30000,
485 MEMWIN2_APERTURE_T5 = 128 * 1024,
486 MEMWIN2_BASE_T5 = 0x60000,
490 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
491 uint32_t mw_base; /* constant after setup_memwin */
492 uint32_t mw_aperture; /* ditto */
493 uint32_t mw_curpos; /* protected by mw_lock */
497 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
498 FL_DOOMED = (1 << 1), /* about to be destroyed */
499 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
500 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
503 #define FL_RUNNING_LOW(fl) \
504 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
505 #define FL_NOT_RUNNING_LOW(fl) \
506 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
510 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
511 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
512 struct cluster_layout cll_def; /* default refill zone, layout */
513 uint16_t lowat; /* # of buffers <= this means fl needs help */
515 uint16_t buf_boundary;
517 /* The 16b idx all deal with hw descriptors */
518 uint16_t dbidx; /* hw pidx after last doorbell */
519 uint16_t sidx; /* index of status page */
520 volatile uint16_t hw_cidx;
522 /* The 32b idx are all buffer idx, not hardware descriptor idx */
523 uint32_t cidx; /* consumer index */
524 uint32_t pidx; /* producer index */
527 u_int rx_offset; /* offset in fl buf (when buffer packing) */
528 volatile uint32_t *udb;
530 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
531 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
532 uint64_t cl_allocated; /* # of clusters allocated */
533 uint64_t cl_recycled; /* # of clusters recycled */
534 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
536 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
541 uint16_t qsize; /* # of hw descriptors (status page included) */
542 uint16_t cntxt_id; /* SGE context id for the freelist */
543 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
544 bus_dma_tag_t desc_tag;
545 bus_dmamap_t desc_map;
547 bus_addr_t ba; /* bus address of descriptor ring */
548 struct cluster_layout cll_alt; /* alternate refill zone, layout */
553 /* txq: SGE egress queue + what's needed for Ethernet NIC */
555 struct sge_eq eq; /* MUST be first */
557 struct ifnet *ifp; /* the interface this txq belongs to */
558 struct mp_ring *r; /* tx software ring */
559 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
561 __be32 cpl_ctrl0; /* for convenience */
562 int tc_idx; /* traffic class */
564 struct task tx_reclaim_task;
565 /* stats for common events first */
567 uint64_t txcsum; /* # of times hardware assisted with checksum */
568 uint64_t tso_wrs; /* # of TSO work requests */
569 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
570 uint64_t imm_wrs; /* # of work requests with immediate data */
571 uint64_t sgl_wrs; /* # of work requests with direct SGL */
572 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
573 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
574 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
575 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
576 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
578 /* stats for not-that-common events */
579 } __aligned(CACHE_LINE_SIZE);
581 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
583 struct sge_iq iq; /* MUST be first */
584 struct sge_fl fl; /* MUST follow iq */
586 struct ifnet *ifp; /* the interface this rxq belongs to */
587 #if defined(INET) || defined(INET6)
588 struct lro_ctrl lro; /* LRO state */
591 /* stats for common events first */
593 uint64_t rxcsum; /* # of times hardware assisted with checksum */
594 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
596 /* stats for not-that-common events */
598 } __aligned(CACHE_LINE_SIZE);
600 static inline struct sge_rxq *
601 iq_to_rxq(struct sge_iq *iq)
604 return (__containerof(iq, struct sge_rxq, iq));
608 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
609 struct sge_ofld_rxq {
610 struct sge_iq iq; /* MUST be first */
611 struct sge_fl fl; /* MUST follow iq */
612 } __aligned(CACHE_LINE_SIZE);
614 static inline struct sge_ofld_rxq *
615 iq_to_ofld_rxq(struct sge_iq *iq)
618 return (__containerof(iq, struct sge_ofld_rxq, iq));
622 STAILQ_ENTRY(wrqe) link;
625 char wr[] __aligned(16);
629 TAILQ_ENTRY(wrq_cookie) link;
635 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
636 * and offload tx queues are of this type.
639 struct sge_eq eq; /* MUST be first */
641 struct adapter *adapter;
642 struct task wrq_tx_task;
644 /* Tx desc reserved but WR not "committed" yet. */
645 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
647 /* List of WRs ready to go out as soon as descriptors are available. */
648 STAILQ_HEAD(, wrqe) wr_list;
652 /* stats for common events first */
654 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
655 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
656 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
658 /* stats for not-that-common events */
661 * Scratch space for work requests that wrap around after reaching the
662 * status page, and some information about the last WR that used it.
666 uint8_t ss[SGE_MAX_WR_LEN];
668 } __aligned(CACHE_LINE_SIZE);
670 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
674 struct iq_desc *iq_desc;
676 uint16_t iq_cntxt_id;
682 uint16_t fl_cntxt_id;
689 u_int nid; /* netmap ring # for this queue */
691 /* infrequently used items after this */
693 bus_dma_tag_t iq_desc_tag;
694 bus_dmamap_t iq_desc_map;
698 bus_dma_tag_t fl_desc_tag;
699 bus_dmamap_t fl_desc_map;
701 } __aligned(CACHE_LINE_SIZE);
703 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
705 struct tx_desc *desc;
709 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
710 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
711 uint16_t dbidx; /* pidx of the most recent doorbell */
713 volatile uint32_t *udb;
716 __be32 cpl_ctrl0; /* for convenience */
717 u_int nid; /* netmap ring # for this queue */
719 /* infrequently used items after this */
721 bus_dma_tag_t desc_tag;
722 bus_dmamap_t desc_map;
725 } __aligned(CACHE_LINE_SIZE);
728 int nrxq; /* total # of Ethernet rx queues */
729 int ntxq; /* total # of Ethernet tx queues */
730 int nofldrxq; /* total # of TOE rx queues */
731 int nofldtxq; /* total # of TOE tx queues */
732 int nnmrxq; /* total # of netmap rx queues */
733 int nnmtxq; /* total # of netmap tx queues */
734 int niq; /* total # of ingress queues */
735 int neq; /* total # of egress queues */
737 struct sge_iq fwq; /* Firmware event queue */
738 struct sge_wrq mgmtq; /* Management queue (control queue) */
739 struct sge_wrq *ctrlq; /* Control queues */
740 struct sge_txq *txq; /* NIC tx queues */
741 struct sge_rxq *rxq; /* NIC rx queues */
742 struct sge_wrq *ofld_txq; /* TOE tx queues */
743 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
744 struct sge_nm_txq *nm_txq; /* netmap tx queues */
745 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
747 uint16_t iq_start; /* first cntxt_id */
748 uint16_t iq_base; /* first abs_id */
749 int eq_start; /* first cntxt_id */
750 int eq_base; /* first abs_id */
751 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
752 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
754 int8_t safe_hwidx1; /* may not have room for metadata */
755 int8_t safe_hwidx2; /* with room for metadata and maybe more */
756 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
757 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
761 const char *nexus_name;
762 const char *ifnet_name;
763 const char *vi_ifnet_name;
764 const char *pf03_drv_name;
765 const char *vf_nexus_name;
766 const char *vf_ifnet_name;
770 SLIST_ENTRY(adapter) link;
773 const struct devnames *names;
775 /* PCIe register resources */
777 struct resource *regs_res;
779 struct resource *msix_res;
780 bus_space_handle_t bh;
784 struct resource *udbs_res;
785 volatile uint8_t *udbs_base;
789 unsigned int vpd_busy;
790 unsigned int vpd_flag;
792 /* Interrupt information */
796 struct resource *res;
798 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
801 struct sge_nm_rxq *nm_rxq;
802 } __aligned(CACHE_LINE_SIZE) *irq;
804 int sge_kdoorbell_reg;
806 bus_dma_tag_t dmat; /* Parent DMA tag */
812 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
813 struct port_info *port[MAX_NPORTS];
814 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
816 void *tom_softc; /* (struct tom_data *) */
817 struct tom_tunables tt;
818 struct t4_offload_policy *policy;
819 struct rwlock policy_lock;
821 void *iwarp_softc; /* (struct c4iw_dev *) */
822 struct iw_tunables iwt;
823 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
824 void *ccr_softc; /* (struct ccr_softc *) */
825 struct l2t_data *l2t; /* L2 table */
826 struct tid_info tids;
829 int offload_map; /* ports with IFCAP_TOE enabled */
830 int active_ulds; /* ULDs activated on this adapter */
834 char ifp_lockname[16];
836 struct ifnet *ifp; /* tracer ifp */
837 struct ifmedia media;
838 int traceq; /* iq used by all tracers, -1 if none */
839 int tracer_valid; /* bitmap of valid tracers */
840 int tracer_enabled; /* bitmap of enabled tracers */
848 struct adapter_params params;
849 const struct chip_params *chip_params;
850 struct t4_virt_res vres;
862 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
867 /* Starving free lists */
868 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
869 TAILQ_HEAD(, sge_fl) sfl;
870 struct callout sfl_callout;
872 struct mtx reg_lock; /* for indirect register access */
874 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
880 const void *last_op_thr;
884 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
885 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
886 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
887 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
889 #define ASSERT_SYNCHRONIZED_OP(sc) \
890 KASSERT(IS_BUSY(sc) && \
891 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
892 ("%s: operation not synchronized.", __func__))
894 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
895 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
896 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
897 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
899 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
900 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
901 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
902 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
903 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
905 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
906 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
907 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
908 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
910 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
911 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
912 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
913 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
914 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
916 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
917 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
918 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
919 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
920 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
922 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
924 if (sc->debug_flags & DF_DUMP_MBOX) { \
926 "%s mbox %u: %016llx %016llx %016llx %016llx " \
927 "%016llx %016llx %016llx %016llx\n", \
928 device_get_nameunit(sc->dev), mbox, \
929 (unsigned long long)t4_read_reg64(sc, data_reg), \
930 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
931 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
932 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
933 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
934 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
935 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
936 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
940 #define for_each_txq(vi, iter, q) \
941 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
942 iter < vi->ntxq; ++iter, ++q)
943 #define for_each_rxq(vi, iter, q) \
944 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
945 iter < vi->nrxq; ++iter, ++q)
946 #define for_each_ofld_txq(vi, iter, q) \
947 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
948 iter < vi->nofldtxq; ++iter, ++q)
949 #define for_each_ofld_rxq(vi, iter, q) \
950 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
951 iter < vi->nofldrxq; ++iter, ++q)
952 #define for_each_nm_txq(vi, iter, q) \
953 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
954 iter < vi->nnmtxq; ++iter, ++q)
955 #define for_each_nm_rxq(vi, iter, q) \
956 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
957 iter < vi->nnmrxq; ++iter, ++q)
958 #define for_each_vi(_pi, _iter, _vi) \
959 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
962 #define IDXINCR(idx, incr, wrap) do { \
963 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
965 #define IDXDIFF(head, tail, wrap) \
966 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
968 /* One for errors, one for firmware events */
969 #define T4_EXTRA_INTR 2
971 /* One for firmware events */
972 #define T4VF_EXTRA_INTR 1
975 forwarding_intr_to_fwq(struct adapter *sc)
978 return (sc->intr_count == 1);
981 static inline uint32_t
982 t4_read_reg(struct adapter *sc, uint32_t reg)
985 return bus_space_read_4(sc->bt, sc->bh, reg);
989 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
992 bus_space_write_4(sc->bt, sc->bh, reg, val);
995 static inline uint64_t
996 t4_read_reg64(struct adapter *sc, uint32_t reg)
1000 return bus_space_read_8(sc->bt, sc->bh, reg);
1002 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1003 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1009 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1013 bus_space_write_8(sc->bt, sc->bh, reg, val);
1015 bus_space_write_4(sc->bt, sc->bh, reg, val);
1016 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1021 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1024 *val = pci_read_config(sc->dev, reg, 1);
1028 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1031 pci_write_config(sc->dev, reg, val, 1);
1035 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1038 *val = pci_read_config(sc->dev, reg, 2);
1042 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1045 pci_write_config(sc->dev, reg, val, 2);
1049 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1052 *val = pci_read_config(sc->dev, reg, 4);
1056 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1059 pci_write_config(sc->dev, reg, val, 4);
1062 static inline struct port_info *
1063 adap2pinfo(struct adapter *sc, int idx)
1066 return (sc->port[idx]);
1070 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1073 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1077 is_10G_port(const struct port_info *pi)
1080 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1084 is_25G_port(const struct port_info *pi)
1087 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1091 is_40G_port(const struct port_info *pi)
1094 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1098 is_100G_port(const struct port_info *pi)
1101 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1105 port_top_speed(const struct port_info *pi)
1108 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1110 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1112 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1114 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1116 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1123 tx_resume_threshold(struct sge_eq *eq)
1126 /* not quite the same as qsize / 4, but this will do. */
1127 return (eq->sidx / 4);
1131 t4_use_ldst(struct adapter *sc)
1135 return (sc->flags & FW_OK || !sc->use_bd);
1144 extern int t4_intr_types;
1145 extern int t4_tmr_idx;
1146 extern int t4_pktc_idx;
1147 extern unsigned int t4_qsize_rxq;
1148 extern unsigned int t4_qsize_txq;
1149 extern device_method_t cxgbe_methods[];
1151 int t4_os_find_pci_capability(struct adapter *, int);
1152 int t4_os_pci_save_state(struct adapter *);
1153 int t4_os_pci_restore_state(struct adapter *);
1154 void t4_os_portmod_changed(struct port_info *);
1155 void t4_os_link_changed(struct port_info *);
1156 void t4_iterate(void (*)(struct adapter *, void *), void *);
1157 void t4_init_devnames(struct adapter *);
1158 void t4_add_adapter(struct adapter *);
1159 void t4_aes_getdeckey(void *, const void *, unsigned int);
1160 int t4_detach_common(device_t);
1161 int t4_map_bars_0_and_4(struct adapter *);
1162 int t4_map_bar_2(struct adapter *);
1163 int t4_setup_intr_handlers(struct adapter *);
1164 void t4_sysctls(struct adapter *);
1165 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1166 void doom_vi(struct adapter *, struct vi_info *);
1167 void end_synchronized_op(struct adapter *, int);
1168 int update_mac_settings(struct ifnet *, int);
1169 int adapter_full_init(struct adapter *);
1170 int adapter_full_uninit(struct adapter *);
1171 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1172 int vi_full_init(struct vi_info *);
1173 int vi_full_uninit(struct vi_info *);
1174 void vi_sysctls(struct vi_info *);
1175 void vi_tick(void *);
1176 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1177 int alloc_atid_tab(struct tid_info *, int);
1178 void free_atid_tab(struct tid_info *);
1179 int alloc_atid(struct adapter *, void *);
1180 void *lookup_atid(struct adapter *, int);
1181 void free_atid(struct adapter *, int);
1182 void release_tid(struct adapter *, int, struct sge_wrq *);
1186 void cxgbe_nm_attach(struct vi_info *);
1187 void cxgbe_nm_detach(struct vi_info *);
1188 void t4_nm_intr(void *);
1192 void t4_sge_modload(void);
1193 void t4_sge_modunload(void);
1194 uint64_t t4_sge_extfree_refs(void);
1195 void t4_tweak_chip_settings(struct adapter *);
1196 int t4_read_chip_settings(struct adapter *);
1197 int t4_create_dma_tag(struct adapter *);
1198 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1199 struct sysctl_oid_list *);
1200 int t4_destroy_dma_tag(struct adapter *);
1201 int t4_setup_adapter_queues(struct adapter *);
1202 int t4_teardown_adapter_queues(struct adapter *);
1203 int t4_setup_vi_queues(struct vi_info *);
1204 int t4_teardown_vi_queues(struct vi_info *);
1205 void t4_intr_all(void *);
1206 void t4_intr(void *);
1207 void t4_vi_intr(void *);
1208 void t4_intr_err(void *);
1209 void t4_intr_evt(void *);
1210 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1211 void t4_update_fl_bufsize(struct ifnet *);
1212 int parse_pkt(struct adapter *, struct mbuf **);
1213 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1214 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1215 int tnl_cong(struct port_info *, int);
1216 void t4_register_an_handler(an_handler_t);
1217 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1218 void t4_register_cpl_handler(int, cpl_handler_t);
1219 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1223 void t4_tracer_modload(void);
1224 void t4_tracer_modunload(void);
1225 void t4_tracer_port_detach(struct adapter *);
1226 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1227 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1228 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1229 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1232 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1233 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1234 int t4_init_tx_sched(struct adapter *);
1235 int t4_free_tx_sched(struct adapter *);
1236 void t4_update_tx_sched(struct adapter *);
1237 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1238 void t4_release_cl_rl_kbps(struct adapter *, int, int);
1241 int get_filter_mode(struct adapter *, uint32_t *);
1242 int set_filter_mode(struct adapter *, uint32_t);
1243 int get_filter(struct adapter *, struct t4_filter *);
1244 int set_filter(struct adapter *, struct t4_filter *);
1245 int del_filter(struct adapter *, struct t4_filter *);
1246 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1248 static inline struct wrqe *
1249 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1251 int len = offsetof(struct wrqe, wr) + wr_len;
1254 wr = malloc(len, M_CXGBE, M_NOWAIT);
1255 if (__predict_false(wr == NULL))
1257 wr->wr_len = wr_len;
1262 static inline void *
1263 wrtod(struct wrqe *wr)
1265 return (&wr->wr[0]);
1269 free_wrqe(struct wrqe *wr)
1275 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1277 struct sge_wrq *wrq = wr->wrq;
1280 t4_wrq_tx_locked(sc, wrq, wr);
1285 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1289 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1293 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1294 const uint32_t *val, int len)
1297 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));