2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
58 #include "common/t4_msg.h"
59 #include "firmware/t4fw_interface.h"
61 #define KTR_CXGBE KTR_SPARE3
62 MALLOC_DECLARE(M_CXGBE);
63 #define CXGBE_UNIMPLEMENTED(s) \
64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
66 #if defined(__i386__) || defined(__amd64__)
70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
76 #ifndef SYSCTL_ADD_UQUAD
77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
78 #define sysctl_handle_64 sysctl_handle_quad
79 #define CTLTYPE_U64 CTLTYPE_QUAD
82 #if (__FreeBSD_version >= 900030) || \
83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
88 typedef struct adapter adapter_t;
92 * All ingress queues use this entry size. Note that the firmware event
93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
98 /* Default queue sizes for all kinds of ingress queues */
102 /* All egress queues use this entry size */
105 /* Default queue sizes for all kinds of egress queues */
109 #if MJUMPAGESIZE != MCLBYTES
110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
114 CL_METADATA_SIZE = CACHE_LINE_SIZE,
116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
118 TX_SGL_SEGS_TSO = 38,
119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
123 /* adapter intr_type */
124 INTR_INTX = (1 << 0),
130 XGMAC_MTU = (1 << 0),
131 XGMAC_PROMISC = (1 << 1),
132 XGMAC_ALLMULTI = (1 << 2),
133 XGMAC_VLANEX = (1 << 3),
134 XGMAC_UCADDR = (1 << 4),
135 XGMAC_MCADDRS = (1 << 5),
141 /* flags understood by begin_synchronized_op */
142 HOLD_LOCK = (1 << 0),
146 /* flags understood by end_synchronized_op */
147 LOCK_HELD = HOLD_LOCK,
152 FULL_INIT_DONE = (1 << 0),
154 CHK_MBOX_ACCESS = (1 << 2),
155 MASTER_PF = (1 << 3),
156 ADAP_SYSCTL_CTX = (1 << 4),
157 /* TOM_INIT_DONE= (1 << 5), No longer used */
158 BUF_PACKING_OK = (1 << 6),
161 CXGBE_BUSY = (1 << 9),
164 HAS_TRACEQ = (1 << 3),
168 VI_INIT_DONE = (1 << 1),
169 VI_SYSCTL_CTX = (1 << 2),
170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
174 /* adapter debug_flags */
175 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
176 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
177 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
180 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
181 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
182 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
183 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
184 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
188 struct port_info *pi;
195 uint16_t *rss, *nm_rss;
196 int smt_idx; /* for convenience */
198 int16_t xact_addr_filt;/* index of exact MAC address filter */
199 uint16_t rss_size; /* size of VI's RSS table slice */
200 uint16_t rss_base; /* start of VI's RSS table slice */
202 eventhandler_tag vlan_c;
207 /* These need to be int as they are used in sysctl */
208 int ntxq; /* # of tx queues */
209 int first_txq; /* index of first tx queue */
210 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
211 int nrxq; /* # of rx queues */
212 int first_rxq; /* index of first rx queue */
213 int nofldtxq; /* # of offload tx queues */
214 int first_ofld_txq; /* index of first offload tx queue */
215 int nofldrxq; /* # of offload rx queues */
216 int first_ofld_rxq; /* index of first offload rx queue */
228 struct timeval last_refreshed;
229 struct fw_vi_stats_vf stats;
232 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
234 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
237 struct tx_ch_rl_params {
238 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
243 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */
244 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */
247 struct tx_cl_rl_params {
250 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
251 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
252 enum fw_sched_params_mode mode; /* aggr or per-flow */
257 /* Tx scheduler parameters for a channel/port */
258 struct tx_sched_params {
259 /* Channel Rate Limiter */
260 struct tx_ch_rl_params ch_rl;
265 /* Class Rate Limiter */
266 struct tx_cl_rl_params cl_rl[];
271 struct adapter *adapter;
278 struct tx_sched_params *sched_params;
284 uint8_t lport; /* associated offload logical port */
290 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
291 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
293 struct link_config link_cfg;
294 struct link_config old_link_cfg;
295 struct ifmedia media;
297 struct timeval last_refreshed;
298 struct port_stats stats;
299 u_int tnl_cong_drops;
300 u_int tx_parse_error;
305 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
307 /* Where the cluster came from, how it has been carved up. */
308 struct cluster_layout {
311 uint16_t region1; /* mbufs laid out within this region */
312 /* region2 is the DMA region */
313 uint16_t region3; /* cluster_metadata within this region */
316 struct cluster_metadata {
318 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
323 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
324 struct cluster_layout cll;
332 struct mbuf *m; /* m_nextpkt linked chain of frames */
333 uint8_t desc_used; /* # of hardware descriptors used by the WR */
337 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
339 struct rss_header rss;
344 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
348 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
349 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
350 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
351 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
352 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
359 /* netmap related flags */
367 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
369 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
370 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
373 * Ingress Queue: T4 is producer, driver is consumer.
378 struct adapter *adapter;
379 cpl_handler_t set_tcb_rpl;
380 cpl_handler_t l2t_write_rpl;
381 struct iq_desc *desc; /* KVA of descriptor ring */
382 int8_t intr_pktc_idx; /* packet count threshold index */
383 uint8_t gen; /* generation bit */
384 uint8_t intr_params; /* interrupt holdoff parameters */
385 uint8_t intr_next; /* XXX: holdoff for next interrupt */
386 uint16_t qsize; /* size (# of entries) of the queue */
387 uint16_t sidx; /* index of the entry with the status page */
388 uint16_t cidx; /* consumer index */
389 uint16_t cntxt_id; /* SGE context id for the iq */
390 uint16_t abs_id; /* absolute SGE id for the iq */
392 STAILQ_ENTRY(sge_iq) link;
394 bus_dma_tag_t desc_tag;
395 bus_dmamap_t desc_map;
396 bus_addr_t ba; /* bus address of descriptor ring */
405 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
406 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
407 EQ_ENABLED = (1 << 3), /* open for business */
408 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
411 /* Listed in order of preference. Update t4_sysctls too if you change these */
412 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
415 * Egress Queue: driver is producer, T4 is consumer.
417 * Note: A free list is an egress queue (driver produces the buffers and T4
418 * consumes them) but it's special enough to have its own struct (see sge_fl).
421 unsigned int flags; /* MUST be first */
422 unsigned int cntxt_id; /* SGE context id for the eq */
423 unsigned int abs_id; /* absolute SGE id for the eq */
426 struct tx_desc *desc; /* KVA of descriptor ring */
428 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
429 u_int udb_qid; /* relative qid within the doorbell page */
430 uint16_t sidx; /* index of the entry with the status page */
431 uint16_t cidx; /* consumer idx (desc idx) */
432 uint16_t pidx; /* producer idx (desc idx) */
433 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
434 uint16_t dbidx; /* pidx of the most recent doorbell */
435 uint16_t iqid; /* iq that gets egr_update for the eq */
436 uint8_t tx_chan; /* tx channel used by the eq */
437 volatile u_int equiq; /* EQUIQ outstanding */
439 bus_dma_tag_t desc_tag;
440 bus_dmamap_t desc_map;
441 bus_addr_t ba; /* bus address of descriptor ring */
445 struct sw_zone_info {
446 uma_zone_t zone; /* zone that this cluster comes from */
447 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
448 int type; /* EXT_xxx type of the cluster */
454 int8_t zidx; /* backpointer to zone; -ve means unused */
455 int8_t next; /* next hwidx for this zone; -1 means no more */
462 MEMWIN0_APERTURE = 2048,
463 MEMWIN0_BASE = 0x1b800,
465 MEMWIN1_APERTURE = 32768,
466 MEMWIN1_BASE = 0x28000,
468 MEMWIN2_APERTURE_T4 = 65536,
469 MEMWIN2_BASE_T4 = 0x30000,
471 MEMWIN2_APERTURE_T5 = 128 * 1024,
472 MEMWIN2_BASE_T5 = 0x60000,
476 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
477 uint32_t mw_base; /* constant after setup_memwin */
478 uint32_t mw_aperture; /* ditto */
479 uint32_t mw_curpos; /* protected by mw_lock */
483 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
484 FL_DOOMED = (1 << 1), /* about to be destroyed */
485 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
486 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
489 #define FL_RUNNING_LOW(fl) \
490 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
491 #define FL_NOT_RUNNING_LOW(fl) \
492 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
496 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
497 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
498 struct cluster_layout cll_def; /* default refill zone, layout */
499 uint16_t lowat; /* # of buffers <= this means fl needs help */
501 uint16_t buf_boundary;
503 /* The 16b idx all deal with hw descriptors */
504 uint16_t dbidx; /* hw pidx after last doorbell */
505 uint16_t sidx; /* index of status page */
506 volatile uint16_t hw_cidx;
508 /* The 32b idx are all buffer idx, not hardware descriptor idx */
509 uint32_t cidx; /* consumer index */
510 uint32_t pidx; /* producer index */
513 u_int rx_offset; /* offset in fl buf (when buffer packing) */
514 volatile uint32_t *udb;
516 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
517 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
518 uint64_t cl_allocated; /* # of clusters allocated */
519 uint64_t cl_recycled; /* # of clusters recycled */
520 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
522 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
527 uint16_t qsize; /* # of hw descriptors (status page included) */
528 uint16_t cntxt_id; /* SGE context id for the freelist */
529 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
530 bus_dma_tag_t desc_tag;
531 bus_dmamap_t desc_map;
533 bus_addr_t ba; /* bus address of descriptor ring */
534 struct cluster_layout cll_alt; /* alternate refill zone, layout */
539 /* txq: SGE egress queue + what's needed for Ethernet NIC */
541 struct sge_eq eq; /* MUST be first */
543 struct ifnet *ifp; /* the interface this txq belongs to */
544 struct mp_ring *r; /* tx software ring */
545 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
547 __be32 cpl_ctrl0; /* for convenience */
548 int tc_idx; /* traffic class */
550 struct task tx_reclaim_task;
551 /* stats for common events first */
553 uint64_t txcsum; /* # of times hardware assisted with checksum */
554 uint64_t tso_wrs; /* # of TSO work requests */
555 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
556 uint64_t imm_wrs; /* # of work requests with immediate data */
557 uint64_t sgl_wrs; /* # of work requests with direct SGL */
558 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
559 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
560 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
561 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
562 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
564 /* stats for not-that-common events */
565 } __aligned(CACHE_LINE_SIZE);
567 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
569 struct sge_iq iq; /* MUST be first */
570 struct sge_fl fl; /* MUST follow iq */
572 struct ifnet *ifp; /* the interface this rxq belongs to */
573 #if defined(INET) || defined(INET6)
574 struct lro_ctrl lro; /* LRO state */
577 /* stats for common events first */
579 uint64_t rxcsum; /* # of times hardware assisted with checksum */
580 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
582 /* stats for not-that-common events */
584 } __aligned(CACHE_LINE_SIZE);
586 static inline struct sge_rxq *
587 iq_to_rxq(struct sge_iq *iq)
590 return (__containerof(iq, struct sge_rxq, iq));
594 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
595 struct sge_ofld_rxq {
596 struct sge_iq iq; /* MUST be first */
597 struct sge_fl fl; /* MUST follow iq */
598 } __aligned(CACHE_LINE_SIZE);
600 static inline struct sge_ofld_rxq *
601 iq_to_ofld_rxq(struct sge_iq *iq)
604 return (__containerof(iq, struct sge_ofld_rxq, iq));
608 STAILQ_ENTRY(wrqe) link;
611 char wr[] __aligned(16);
615 TAILQ_ENTRY(wrq_cookie) link;
621 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
622 * and offload tx queues are of this type.
625 struct sge_eq eq; /* MUST be first */
627 struct adapter *adapter;
628 struct task wrq_tx_task;
630 /* Tx desc reserved but WR not "committed" yet. */
631 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
633 /* List of WRs ready to go out as soon as descriptors are available. */
634 STAILQ_HEAD(, wrqe) wr_list;
638 /* stats for common events first */
640 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
641 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
642 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
644 /* stats for not-that-common events */
647 * Scratch space for work requests that wrap around after reaching the
648 * status page, and some information about the last WR that used it.
652 uint8_t ss[SGE_MAX_WR_LEN];
654 } __aligned(CACHE_LINE_SIZE);
656 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
660 struct iq_desc *iq_desc;
662 uint16_t iq_cntxt_id;
668 uint16_t fl_cntxt_id;
675 u_int nid; /* netmap ring # for this queue */
677 /* infrequently used items after this */
679 bus_dma_tag_t iq_desc_tag;
680 bus_dmamap_t iq_desc_map;
684 bus_dma_tag_t fl_desc_tag;
685 bus_dmamap_t fl_desc_map;
687 } __aligned(CACHE_LINE_SIZE);
689 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
691 struct tx_desc *desc;
695 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
696 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
697 uint16_t dbidx; /* pidx of the most recent doorbell */
699 volatile uint32_t *udb;
702 __be32 cpl_ctrl0; /* for convenience */
703 u_int nid; /* netmap ring # for this queue */
705 /* infrequently used items after this */
707 bus_dma_tag_t desc_tag;
708 bus_dmamap_t desc_map;
711 } __aligned(CACHE_LINE_SIZE);
714 int nrxq; /* total # of Ethernet rx queues */
715 int ntxq; /* total # of Ethernet tx queues */
716 int nofldrxq; /* total # of TOE rx queues */
717 int nofldtxq; /* total # of TOE tx queues */
718 int nnmrxq; /* total # of netmap rx queues */
719 int nnmtxq; /* total # of netmap tx queues */
720 int niq; /* total # of ingress queues */
721 int neq; /* total # of egress queues */
723 struct sge_iq fwq; /* Firmware event queue */
724 struct sge_wrq mgmtq; /* Management queue (control queue) */
725 struct sge_wrq *ctrlq; /* Control queues */
726 struct sge_txq *txq; /* NIC tx queues */
727 struct sge_rxq *rxq; /* NIC rx queues */
728 struct sge_wrq *ofld_txq; /* TOE tx queues */
729 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
730 struct sge_nm_txq *nm_txq; /* netmap tx queues */
731 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
733 uint16_t iq_start; /* first cntxt_id */
734 uint16_t iq_base; /* first abs_id */
735 int eq_start; /* first cntxt_id */
736 int eq_base; /* first abs_id */
737 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
738 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
740 int8_t safe_hwidx1; /* may not have room for metadata */
741 int8_t safe_hwidx2; /* with room for metadata and maybe more */
742 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
743 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
747 const char *nexus_name;
748 const char *ifnet_name;
749 const char *vi_ifnet_name;
750 const char *pf03_drv_name;
751 const char *vf_nexus_name;
752 const char *vf_ifnet_name;
756 SLIST_ENTRY(adapter) link;
759 const struct devnames *names;
761 /* PCIe register resources */
763 struct resource *regs_res;
765 struct resource *msix_res;
766 bus_space_handle_t bh;
770 struct resource *udbs_res;
771 volatile uint8_t *udbs_base;
775 unsigned int vpd_busy;
776 unsigned int vpd_flag;
778 /* Interrupt information */
782 struct resource *res;
784 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
787 struct sge_nm_rxq *nm_rxq;
788 } __aligned(CACHE_LINE_SIZE) *irq;
790 int sge_kdoorbell_reg;
792 bus_dma_tag_t dmat; /* Parent DMA tag */
798 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
799 struct port_info *port[MAX_NPORTS];
800 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
802 void *tom_softc; /* (struct tom_data *) */
803 struct tom_tunables tt;
804 void *iwarp_softc; /* (struct c4iw_dev *) */
805 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
806 void *ccr_softc; /* (struct ccr_softc *) */
807 struct l2t_data *l2t; /* L2 table */
808 struct tid_info tids;
811 int offload_map; /* ports with IFCAP_TOE enabled */
812 int active_ulds; /* ULDs activated on this adapter */
816 char ifp_lockname[16];
818 struct ifnet *ifp; /* tracer ifp */
819 struct ifmedia media;
820 int traceq; /* iq used by all tracers, -1 if none */
821 int tracer_valid; /* bitmap of valid tracers */
822 int tracer_enabled; /* bitmap of enabled tracers */
830 struct adapter_params params;
831 const struct chip_params *chip_params;
832 struct t4_virt_res vres;
844 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
849 /* Starving free lists */
850 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
851 TAILQ_HEAD(, sge_fl) sfl;
852 struct callout sfl_callout;
854 struct mtx reg_lock; /* for indirect register access */
856 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
862 const void *last_op_thr;
866 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
867 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
868 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
869 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
871 #define ASSERT_SYNCHRONIZED_OP(sc) \
872 KASSERT(IS_BUSY(sc) && \
873 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
874 ("%s: operation not synchronized.", __func__))
876 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
877 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
878 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
879 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
881 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
882 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
883 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
884 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
885 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
887 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
888 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
889 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
890 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
892 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
893 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
894 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
895 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
896 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
898 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
899 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
900 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
901 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
902 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
904 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
906 if (sc->debug_flags & DF_DUMP_MBOX) { \
908 "%s mbox %u: %016llx %016llx %016llx %016llx " \
909 "%016llx %016llx %016llx %016llx\n", \
910 device_get_nameunit(sc->dev), mbox, \
911 (unsigned long long)t4_read_reg64(sc, data_reg), \
912 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
913 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
914 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
915 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
916 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
917 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
918 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
922 #define for_each_txq(vi, iter, q) \
923 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
924 iter < vi->ntxq; ++iter, ++q)
925 #define for_each_rxq(vi, iter, q) \
926 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
927 iter < vi->nrxq; ++iter, ++q)
928 #define for_each_ofld_txq(vi, iter, q) \
929 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
930 iter < vi->nofldtxq; ++iter, ++q)
931 #define for_each_ofld_rxq(vi, iter, q) \
932 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
933 iter < vi->nofldrxq; ++iter, ++q)
934 #define for_each_nm_txq(vi, iter, q) \
935 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
936 iter < vi->nnmtxq; ++iter, ++q)
937 #define for_each_nm_rxq(vi, iter, q) \
938 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
939 iter < vi->nnmrxq; ++iter, ++q)
940 #define for_each_vi(_pi, _iter, _vi) \
941 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
944 #define IDXINCR(idx, incr, wrap) do { \
945 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
947 #define IDXDIFF(head, tail, wrap) \
948 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
950 /* One for errors, one for firmware events */
951 #define T4_EXTRA_INTR 2
953 /* One for firmware events */
954 #define T4VF_EXTRA_INTR 1
956 static inline uint32_t
957 t4_read_reg(struct adapter *sc, uint32_t reg)
960 return bus_space_read_4(sc->bt, sc->bh, reg);
964 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
967 bus_space_write_4(sc->bt, sc->bh, reg, val);
970 static inline uint64_t
971 t4_read_reg64(struct adapter *sc, uint32_t reg)
975 return bus_space_read_8(sc->bt, sc->bh, reg);
977 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
978 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
984 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
988 bus_space_write_8(sc->bt, sc->bh, reg, val);
990 bus_space_write_4(sc->bt, sc->bh, reg, val);
991 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
996 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
999 *val = pci_read_config(sc->dev, reg, 1);
1003 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1006 pci_write_config(sc->dev, reg, val, 1);
1010 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1013 *val = pci_read_config(sc->dev, reg, 2);
1017 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1020 pci_write_config(sc->dev, reg, val, 2);
1024 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1027 *val = pci_read_config(sc->dev, reg, 4);
1031 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1034 pci_write_config(sc->dev, reg, val, 4);
1037 static inline struct port_info *
1038 adap2pinfo(struct adapter *sc, int idx)
1041 return (sc->port[idx]);
1045 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1048 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1052 is_10G_port(const struct port_info *pi)
1055 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1059 is_25G_port(const struct port_info *pi)
1062 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1066 is_40G_port(const struct port_info *pi)
1069 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1073 is_100G_port(const struct port_info *pi)
1076 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1080 port_top_speed(const struct port_info *pi)
1083 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1085 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1087 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1089 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1091 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1098 tx_resume_threshold(struct sge_eq *eq)
1101 /* not quite the same as qsize / 4, but this will do. */
1102 return (eq->sidx / 4);
1106 t4_use_ldst(struct adapter *sc)
1110 return (sc->flags & FW_OK || !sc->use_bd);
1119 extern int t4_intr_types;
1120 extern int t4_tmr_idx;
1121 extern int t4_pktc_idx;
1122 extern unsigned int t4_qsize_rxq;
1123 extern unsigned int t4_qsize_txq;
1124 extern device_method_t cxgbe_methods[];
1126 int t4_os_find_pci_capability(struct adapter *, int);
1127 int t4_os_pci_save_state(struct adapter *);
1128 int t4_os_pci_restore_state(struct adapter *);
1129 void t4_os_portmod_changed(struct port_info *);
1130 void t4_os_link_changed(struct port_info *);
1131 void t4_iterate(void (*)(struct adapter *, void *), void *);
1132 void t4_init_devnames(struct adapter *);
1133 void t4_add_adapter(struct adapter *);
1134 int t4_detach_common(device_t);
1135 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1136 int t4_map_bars_0_and_4(struct adapter *);
1137 int t4_map_bar_2(struct adapter *);
1138 int t4_setup_intr_handlers(struct adapter *);
1139 void t4_sysctls(struct adapter *);
1140 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1141 void doom_vi(struct adapter *, struct vi_info *);
1142 void end_synchronized_op(struct adapter *, int);
1143 int update_mac_settings(struct ifnet *, int);
1144 int adapter_full_init(struct adapter *);
1145 int adapter_full_uninit(struct adapter *);
1146 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1147 int vi_full_init(struct vi_info *);
1148 int vi_full_uninit(struct vi_info *);
1149 void vi_sysctls(struct vi_info *);
1150 void vi_tick(void *);
1154 void cxgbe_nm_attach(struct vi_info *);
1155 void cxgbe_nm_detach(struct vi_info *);
1156 void t4_nm_intr(void *);
1160 void t4_sge_modload(void);
1161 void t4_sge_modunload(void);
1162 uint64_t t4_sge_extfree_refs(void);
1163 void t4_tweak_chip_settings(struct adapter *);
1164 int t4_read_chip_settings(struct adapter *);
1165 int t4_create_dma_tag(struct adapter *);
1166 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1167 struct sysctl_oid_list *);
1168 int t4_destroy_dma_tag(struct adapter *);
1169 int t4_setup_adapter_queues(struct adapter *);
1170 int t4_teardown_adapter_queues(struct adapter *);
1171 int t4_setup_vi_queues(struct vi_info *);
1172 int t4_teardown_vi_queues(struct vi_info *);
1173 void t4_intr_all(void *);
1174 void t4_intr(void *);
1175 void t4_vi_intr(void *);
1176 void t4_intr_err(void *);
1177 void t4_intr_evt(void *);
1178 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1179 void t4_update_fl_bufsize(struct ifnet *);
1180 int parse_pkt(struct adapter *, struct mbuf **);
1181 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1182 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1183 int tnl_cong(struct port_info *, int);
1184 int t4_register_an_handler(an_handler_t);
1185 int t4_register_fw_msg_handler(int, fw_msg_handler_t);
1186 int t4_register_cpl_handler(int, cpl_handler_t);
1190 void t4_tracer_modload(void);
1191 void t4_tracer_modunload(void);
1192 void t4_tracer_port_detach(struct adapter *);
1193 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1194 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1195 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1196 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1199 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1200 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1201 int t4_init_tx_sched(struct adapter *);
1202 int t4_free_tx_sched(struct adapter *);
1203 void t4_update_tx_sched(struct adapter *);
1204 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1205 void t4_release_cl_rl_kbps(struct adapter *, int, int);
1207 static inline struct wrqe *
1208 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1210 int len = offsetof(struct wrqe, wr) + wr_len;
1213 wr = malloc(len, M_CXGBE, M_NOWAIT);
1214 if (__predict_false(wr == NULL))
1216 wr->wr_len = wr_len;
1221 static inline void *
1222 wrtod(struct wrqe *wr)
1224 return (&wr->wr[0]);
1228 free_wrqe(struct wrqe *wr)
1234 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1236 struct sge_wrq *wrq = wr->wrq;
1239 t4_wrq_tx_locked(sc, wrq, wr);