2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
38 #include <sys/counter.h>
40 #include <sys/types.h>
42 #include <sys/malloc.h>
43 #include <sys/rwlock.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pcireg.h>
51 #include <machine/bus.h>
52 #include <sys/socket.h>
53 #include <sys/sysctl.h>
54 #include <sys/taskqueue.h>
55 #include <net/ethernet.h>
57 #include <net/if_var.h>
58 #include <net/if_media.h>
60 #include <netinet/in.h>
61 #include <netinet/tcp_lro.h>
65 #include "common/t4_msg.h"
66 #include "firmware/t4fw_interface.h"
68 #define KTR_CXGBE KTR_SPARE3
69 MALLOC_DECLARE(M_CXGBE);
70 #define CXGBE_UNIMPLEMENTED(s) \
71 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
74 * Same as LIST_HEAD from queue.h. This is to avoid conflict with LinuxKPI's
75 * LIST_HEAD when building iw_cxgbe.
77 #define CXGBE_LIST_HEAD(name, type) \
79 struct type *lh_first; /* first element */ \
82 #ifndef SYSCTL_ADD_UQUAD
83 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
84 #define sysctl_handle_64 sysctl_handle_quad
85 #define CTLTYPE_U64 CTLTYPE_QUAD
88 SYSCTL_DECL(_hw_cxgbe);
91 typedef struct adapter adapter_t;
95 * All ingress queues use this entry size. Note that the firmware event
96 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
101 /* Default queue sizes for all kinds of ingress queues */
105 /* All egress queues use this entry size */
108 /* Default queue sizes for all kinds of egress queues */
109 CTRL_EQ_QSIZE = 1024,
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
113 CL_METADATA_SIZE = CACHE_LINE_SIZE,
115 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
117 TX_SGL_SEGS_TSO = 38,
119 TX_SGL_SEGS_VM_TSO = 37,
120 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
121 TX_SGL_SEGS_VXLAN_TSO = 37,
122 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
126 /* adapter intr_type */
127 INTR_INTX = (1 << 0),
133 XGMAC_MTU = (1 << 0),
134 XGMAC_PROMISC = (1 << 1),
135 XGMAC_ALLMULTI = (1 << 2),
136 XGMAC_VLANEX = (1 << 3),
137 XGMAC_UCADDR = (1 << 4),
138 XGMAC_MCADDRS = (1 << 5),
144 /* flags understood by begin_synchronized_op */
145 HOLD_LOCK = (1 << 0),
149 /* flags understood by end_synchronized_op */
150 LOCK_HELD = HOLD_LOCK,
154 /* adapter flags. synch_op or adapter_lock. */
155 FULL_INIT_DONE = (1 << 0),
157 CHK_MBOX_ACCESS = (1 << 2),
158 MASTER_PF = (1 << 3),
159 BUF_PACKING_OK = (1 << 6),
161 KERN_TLS_ON = (1 << 8), /* HW is configured for KERN_TLS */
162 CXGBE_BUSY = (1 << 9),
164 /* adapter error_flags. reg_lock for HW_OFF_LIMITS, atomics for the rest. */
165 ADAP_STOPPED = (1 << 0), /* Adapter has been stopped. */
166 ADAP_FATAL_ERR = (1 << 1), /* Encountered a fatal error. */
167 HW_OFF_LIMITS = (1 << 2), /* off limits to all except reset_thread */
168 ADAP_CIM_ERR = (1 << 3), /* Error was related to FW/CIM. */
171 HAS_TRACEQ = (1 << 3),
172 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
176 VI_INIT_DONE = (1 << 1),
177 /* 1 << 2 is unused, was VI_SYSCTL_CTX */
178 TX_USES_VM_WR = (1 << 3),
179 VI_SKIP_STATS = (1 << 4),
181 /* adapter debug_flags */
182 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
183 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
184 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
185 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
186 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
189 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
190 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
191 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
192 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
193 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
197 struct port_info *pi;
198 struct adapter *adapter;
201 struct pfil_head *pfil;
206 uint16_t *rss, *nm_rss;
207 uint16_t viid; /* opaque VI identifier */
211 int16_t xact_addr_filt;/* index of exact MAC address filter */
212 uint16_t rss_size; /* size of VI's RSS table slice */
213 uint16_t rss_base; /* start of VI's RSS table slice */
219 /* These need to be int as they are used in sysctl */
220 int ntxq; /* # of tx queues */
221 int first_txq; /* index of first tx queue */
222 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
223 int nrxq; /* # of rx queues */
224 int first_rxq; /* index of first rx queue */
225 int nofldtxq; /* # of offload tx queues */
226 int first_ofld_txq; /* index of first offload tx queue */
227 int nofldrxq; /* # of offload rx queues */
228 int first_ofld_rxq; /* index of first offload rx queue */
240 struct timeval last_refreshed;
241 struct fw_vi_stats_vf stats;
245 struct sysctl_ctx_list ctx;
246 struct sysctl_oid *rxq_oid;
247 struct sysctl_oid *txq_oid;
248 struct sysctl_oid *nm_rxq_oid;
249 struct sysctl_oid *nm_txq_oid;
250 struct sysctl_oid *ofld_rxq_oid;
251 struct sysctl_oid *ofld_txq_oid;
253 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
258 struct tx_ch_rl_params {
259 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
265 CS_UNINITIALIZED = 0,
266 CS_PARAMS_SET, /* sw parameters have been set. */
267 CS_HW_UPDATE_REQUESTED, /* async HW update requested. */
268 CS_HW_UPDATE_IN_PROGRESS, /* sync hw update in progress. */
269 CS_HW_CONFIGURED /* configured in the hardware. */
274 CF_USER = (1 << 0), /* was configured by driver ioctl. */
277 struct tx_cl_rl_params {
278 enum clrl_state state;
281 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
282 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
283 enum fw_sched_params_mode mode; /* aggr or per-flow */
289 /* Tx scheduler parameters for a channel/port */
290 struct tx_sched_params {
291 /* Channel Rate Limiter */
292 struct tx_ch_rl_params ch_rl;
297 /* Class Rate Limiter (including the default pktsize and burstsize). */
300 struct tx_cl_rl_params cl_rl[];
305 struct adapter *adapter;
311 bool vxlan_tcam_entry;
313 struct tx_sched_params *sched_params;
319 uint8_t lport; /* associated offload logical port */
325 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
326 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
327 uint8_t rx_c_chan; /* rx TP c-channel */
329 struct link_config link_cfg;
330 struct ifmedia media;
332 struct port_stats stats;
333 u_int tnl_cong_drops;
334 u_int tx_parse_error;
338 struct sysctl_ctx_list ctx;
341 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
343 struct cluster_metadata {
351 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
352 int16_t moff; /* offset of metadata from cl */
361 struct mbuf *m; /* m_nextpkt linked chain of frames */
362 uint8_t desc_used; /* # of hardware descriptors used by the WR */
366 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
368 struct rss_header rss;
373 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
377 IQ_OTHER = FW_IQ_IQTYPE_OTHER,
378 IQ_ETH = FW_IQ_IQTYPE_NIC,
379 IQ_OFLD = FW_IQ_IQTYPE_OFLD,
382 IQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
383 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
384 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
385 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
386 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
387 IQ_HW_ALLOCATED = (1 << 5), /* fw/hw resources allocated */
394 /* netmap related flags */
401 CPL_COOKIE_RESERVED = 0,
406 CPL_COOKIE_HASHFILTER,
410 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
415 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
417 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
418 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
421 * Ingress Queue: T4 is producer, driver is consumer.
427 struct adapter *adapter;
428 struct iq_desc *desc; /* KVA of descriptor ring */
429 int8_t intr_pktc_idx; /* packet count threshold index */
430 uint8_t gen; /* generation bit */
431 uint8_t intr_params; /* interrupt holdoff parameters */
432 int8_t cong_drop; /* congestion drop settings for the queue */
433 uint16_t qsize; /* size (# of entries) of the queue */
434 uint16_t sidx; /* index of the entry with the status page */
435 uint16_t cidx; /* consumer index */
436 uint16_t cntxt_id; /* SGE context id for the iq */
437 uint16_t abs_id; /* absolute SGE id for the iq */
438 int16_t intr_idx; /* interrupt used by the queue */
440 STAILQ_ENTRY(sge_iq) link;
442 bus_dma_tag_t desc_tag;
443 bus_dmamap_t desc_map;
444 bus_addr_t ba; /* bus address of descriptor ring */
454 EQ_SW_ALLOCATED = (1 << 0), /* sw resources allocated */
455 EQ_HW_ALLOCATED = (1 << 1), /* hw/fw resources allocated */
456 EQ_ENABLED = (1 << 3), /* open for business */
457 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
460 /* Listed in order of preference. Update t4_sysctls too if you change these */
461 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
464 * Egress Queue: driver is producer, T4 is consumer.
466 * Note: A free list is an egress queue (driver produces the buffers and T4
467 * consumes them) but it's special enough to have its own struct (see sge_fl).
470 unsigned int flags; /* MUST be first */
471 unsigned int cntxt_id; /* SGE context id for the eq */
472 unsigned int abs_id; /* absolute SGE id for the eq */
473 uint8_t type; /* EQ_CTRL/EQ_ETH/EQ_OFLD */
475 uint8_t tx_chan; /* tx channel used by the eq */
478 struct tx_desc *desc; /* KVA of descriptor ring */
479 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
480 u_int udb_qid; /* relative qid within the doorbell page */
481 uint16_t sidx; /* index of the entry with the status page */
482 uint16_t cidx; /* consumer idx (desc idx) */
483 uint16_t pidx; /* producer idx (desc idx) */
484 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
485 uint16_t dbidx; /* pidx of the most recent doorbell */
486 uint16_t iqid; /* cached iq->cntxt_id (see iq below) */
487 volatile u_int equiq; /* EQUIQ outstanding */
488 struct sge_iq *iq; /* iq that receives egr_update for the eq */
490 bus_dma_tag_t desc_tag;
491 bus_dmamap_t desc_map;
492 bus_addr_t ba; /* bus address of descriptor ring */
497 uma_zone_t zone; /* zone that this cluster comes from */
498 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
499 * hwsize[hwidx1] = size1. No spare. */
500 uint16_t size2; /* hwsize[hwidx2] = size2.
501 * spare in cluster = size1 - size2. */
502 int8_t hwidx1; /* SGE bufsize idx for size1 */
503 int8_t hwidx2; /* SGE bufsize idx for size2 */
504 uint8_t type; /* EXT_xxx type of the cluster */
510 MEMWIN0_APERTURE = 2048,
511 MEMWIN0_BASE = 0x1b800,
513 MEMWIN1_APERTURE = 32768,
514 MEMWIN1_BASE = 0x28000,
516 MEMWIN2_APERTURE_T4 = 65536,
517 MEMWIN2_BASE_T4 = 0x30000,
519 MEMWIN2_APERTURE_T5 = 128 * 1024,
520 MEMWIN2_BASE_T5 = 0x60000,
524 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
525 uint32_t mw_base; /* constant after setup_memwin */
526 uint32_t mw_aperture; /* ditto */
527 uint32_t mw_curpos; /* protected by mw_lock */
531 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
532 FL_DOOMED = (1 << 1), /* about to be destroyed */
533 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
534 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
537 #define FL_RUNNING_LOW(fl) \
538 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
539 #define FL_NOT_RUNNING_LOW(fl) \
540 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
544 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
545 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
546 uint16_t zidx; /* refill zone idx */
548 uint16_t lowat; /* # of buffers <= this means fl needs help */
550 uint16_t buf_boundary;
552 /* The 16b idx all deal with hw descriptors */
553 uint16_t dbidx; /* hw pidx after last doorbell */
554 uint16_t sidx; /* index of status page */
555 volatile uint16_t hw_cidx;
557 /* The 32b idx are all buffer idx, not hardware descriptor idx */
558 uint32_t cidx; /* consumer index */
559 uint32_t pidx; /* producer index */
562 u_int rx_offset; /* offset in fl buf (when buffer packing) */
563 volatile uint32_t *udb;
565 uint64_t cl_allocated; /* # of clusters allocated */
566 uint64_t cl_recycled; /* # of clusters recycled */
567 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
569 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
574 uint16_t qsize; /* # of hw descriptors (status page included) */
575 uint16_t cntxt_id; /* SGE context id for the freelist */
576 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
577 bus_dma_tag_t desc_tag;
578 bus_dmamap_t desc_map;
580 bus_addr_t ba; /* bus address of descriptor ring */
586 uint8_t wr_type; /* type 0 or type 1 */
587 uint8_t npkt; /* # of packets in this work request */
588 uint8_t len16; /* # of 16B pieces used by this work request */
590 uint8_t max_npkt; /* maximum number of packets allowed */
591 uint16_t plen; /* total payload (sum of all packets) */
593 /* straight from fw_eth_tx_pkts_vm_wr. */
602 /* txq: SGE egress queue + what's needed for Ethernet NIC */
604 struct sge_eq eq; /* MUST be first */
606 if_t ifp; /* the interface this txq belongs to */
607 struct mp_ring *r; /* tx software ring */
608 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
610 __be32 cpl_ctrl0; /* for convenience */
611 int tc_idx; /* traffic class */
612 uint64_t last_tx; /* cycle count when eth_tx was last called */
615 struct task tx_reclaim_task;
616 /* stats for common events first */
618 uint64_t txcsum; /* # of times hardware assisted with checksum */
619 uint64_t tso_wrs; /* # of TSO work requests */
620 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
621 uint64_t imm_wrs; /* # of work requests with immediate data */
622 uint64_t sgl_wrs; /* # of work requests with direct SGL */
623 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
624 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
625 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
626 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
627 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
628 uint64_t txpkts_flush; /* # of times txp had to be sent by tx_update */
629 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
630 uint64_t vxlan_tso_wrs; /* # of VXLAN TSO work requests */
631 uint64_t vxlan_txcsum;
633 uint64_t kern_tls_records;
634 uint64_t kern_tls_short;
635 uint64_t kern_tls_partial;
636 uint64_t kern_tls_full;
637 uint64_t kern_tls_octets;
638 uint64_t kern_tls_waste;
639 uint64_t kern_tls_options;
640 uint64_t kern_tls_header;
641 uint64_t kern_tls_fin;
642 uint64_t kern_tls_fin_short;
643 uint64_t kern_tls_cbc;
644 uint64_t kern_tls_gcm;
646 /* stats for not-that-common events */
648 /* Optional scratch space for constructing work requests. */
649 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
650 } __aligned(CACHE_LINE_SIZE);
652 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
654 struct sge_iq iq; /* MUST be first */
655 struct sge_fl fl; /* MUST follow iq */
657 if_t ifp; /* the interface this rxq belongs to */
658 struct lro_ctrl lro; /* LRO state */
660 /* stats for common events first */
662 uint64_t rxcsum; /* # of times hardware assisted with checksum */
663 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
664 uint64_t vxlan_rxcsum;
666 /* stats for not-that-common events */
668 } __aligned(CACHE_LINE_SIZE);
670 static inline struct sge_rxq *
671 iq_to_rxq(struct sge_iq *iq)
674 return (__containerof(iq, struct sge_rxq, iq));
677 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
678 struct sge_ofld_rxq {
679 struct sge_iq iq; /* MUST be first */
680 struct sge_fl fl; /* MUST follow iq */
681 counter_u64_t rx_iscsi_ddp_setup_ok;
682 counter_u64_t rx_iscsi_ddp_setup_error;
683 uint64_t rx_iscsi_ddp_pdus;
684 uint64_t rx_iscsi_ddp_octets;
685 uint64_t rx_iscsi_fl_pdus;
686 uint64_t rx_iscsi_fl_octets;
687 uint64_t rx_iscsi_padding_errors;
688 uint64_t rx_iscsi_header_digest_errors;
689 uint64_t rx_iscsi_data_digest_errors;
690 u_long rx_toe_tls_records;
691 u_long rx_toe_tls_octets;
692 } __aligned(CACHE_LINE_SIZE);
694 static inline struct sge_ofld_rxq *
695 iq_to_ofld_rxq(struct sge_iq *iq)
698 return (__containerof(iq, struct sge_ofld_rxq, iq));
702 STAILQ_ENTRY(wrqe) link;
705 char wr[] __aligned(16);
709 TAILQ_ENTRY(wrq_cookie) link;
715 * wrq: SGE egress queue that is given prebuilt work requests. Control queues
719 struct sge_eq eq; /* MUST be first */
721 struct adapter *adapter;
722 struct task wrq_tx_task;
724 /* Tx desc reserved but WR not "committed" yet. */
725 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
727 /* List of WRs ready to go out as soon as descriptors are available. */
728 STAILQ_HEAD(, wrqe) wr_list;
732 /* stats for common events first */
734 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
735 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
736 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
738 /* stats for not-that-common events */
741 * Scratch space for work requests that wrap around after reaching the
742 * status page, and some information about the last WR that used it.
746 uint8_t ss[SGE_MAX_WR_LEN];
748 } __aligned(CACHE_LINE_SIZE);
750 /* ofld_txq: SGE egress queue + miscellaneous items */
751 struct sge_ofld_txq {
753 counter_u64_t tx_iscsi_pdus;
754 counter_u64_t tx_iscsi_octets;
755 counter_u64_t tx_iscsi_iso_wrs;
756 counter_u64_t tx_toe_tls_records;
757 counter_u64_t tx_toe_tls_octets;
758 } __aligned(CACHE_LINE_SIZE);
760 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
762 /* Items used by the driver rx ithread are in this cacheline. */
763 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
764 u_int nid; /* netmap ring # for this queue */
767 struct iq_desc *iq_desc;
769 uint16_t iq_cntxt_id;
775 /* Items used by netmap rxsync are in this cacheline. */
776 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
777 uint16_t fl_cntxt_id;
779 uint32_t fl_sidx2; /* copy of fl_sidx */
782 u_int fl_db_threshold; /* in descriptors */
786 * fl_cidx is used by both the ithread and rxsync, the rest are not used
787 * in the rx fast path.
789 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
791 bus_dma_tag_t iq_desc_tag;
792 bus_dmamap_t iq_desc_map;
796 bus_dma_tag_t fl_desc_tag;
797 bus_dmamap_t fl_desc_map;
801 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
803 struct tx_desc *desc;
807 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
808 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
809 uint16_t dbidx; /* pidx of the most recent doorbell */
811 volatile uint32_t *udb;
814 __be32 cpl_ctrl0; /* for convenience */
815 __be32 op_pkd; /* ditto */
816 u_int nid; /* netmap ring # for this queue */
818 /* infrequently used items after this */
820 bus_dma_tag_t desc_tag;
821 bus_dmamap_t desc_map;
824 } __aligned(CACHE_LINE_SIZE);
827 int nrxq; /* total # of Ethernet rx queues */
828 int ntxq; /* total # of Ethernet tx queues */
829 int nofldrxq; /* total # of TOE rx queues */
830 int nofldtxq; /* total # of TOE tx queues */
831 int nnmrxq; /* total # of netmap rx queues */
832 int nnmtxq; /* total # of netmap tx queues */
833 int niq; /* total # of ingress queues */
834 int neq; /* total # of egress queues */
836 struct sge_iq fwq; /* Firmware event queue */
837 struct sge_wrq *ctrlq; /* Control queues */
838 struct sge_txq *txq; /* NIC tx queues */
839 struct sge_rxq *rxq; /* NIC rx queues */
840 struct sge_ofld_txq *ofld_txq; /* TOE tx queues */
841 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
842 struct sge_nm_txq *nm_txq; /* netmap tx queues */
843 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
845 uint16_t iq_start; /* first cntxt_id */
846 uint16_t iq_base; /* first abs_id */
847 int eq_start; /* first cntxt_id */
848 int eq_base; /* first abs_id */
851 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
852 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
855 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
859 const char *nexus_name;
860 const char *ifnet_name;
861 const char *vi_ifnet_name;
862 const char *pf03_drv_name;
863 const char *vf_nexus_name;
864 const char *vf_ifnet_name;
869 #define CNT_CAL_INFO 3
879 SLIST_ENTRY(adapter) link;
882 const struct devnames *names;
884 /* PCIe register resources */
886 struct resource *regs_res;
888 struct resource *msix_res;
889 bus_space_handle_t bh;
893 struct resource *udbs_res;
894 volatile uint8_t *udbs_base;
898 unsigned int vpd_busy;
899 unsigned int vpd_flag;
901 /* Interrupt information */
905 struct resource *res;
909 struct sge_nm_rxq *nm_rxq;
910 } __aligned(CACHE_LINE_SIZE) *irq;
912 int sge_kdoorbell_reg;
914 bus_dma_tag_t dmat; /* Parent DMA tag */
921 u_int vxlan_refcount;
925 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
926 struct port_info *port[MAX_NPORTS];
927 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
929 CXGBE_LIST_HEAD(, clip_entry) *clip_table;
930 TAILQ_HEAD(, clip_entry) clip_pending; /* these need hw update. */
933 struct timeout_task clip_task;
935 void *tom_softc; /* (struct tom_data *) */
936 struct tom_tunables tt;
937 struct t4_offload_policy *policy;
938 struct rwlock policy_lock;
940 void *iwarp_softc; /* (struct c4iw_dev *) */
941 struct iw_tunables iwt;
942 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
943 struct l2t_data *l2t; /* L2 table */
944 struct smt_data *smt; /* Source MAC Table */
945 struct tid_info tids;
947 struct tls_tunables tlst;
950 int offload_map; /* port_id's with IFCAP_TOE enabled */
951 int bt_map; /* tx_chan's with BASE-T */
952 int active_ulds; /* ULDs activated on this adapter */
955 int error_flags; /* Used by error handler and live reset. */
957 char ifp_lockname[16];
959 if_t ifp; /* tracer ifp */
960 struct ifmedia media;
961 int traceq; /* iq used by all tracers, -1 if none */
962 int tracer_valid; /* bitmap of valid tracers */
963 int tracer_enabled; /* bitmap of enabled tracers */
971 struct adapter_params params;
972 const struct chip_params *chip_params;
973 struct t4_virt_res vres;
985 struct sysctl_ctx_list ctx;
986 struct sysctl_oid *ctrlq_oid;
987 struct sysctl_oid *fwq_oid;
992 /* Starving free lists */
993 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
994 TAILQ_HEAD(, sge_fl) sfl;
995 struct callout sfl_callout;
996 struct callout cal_callout;
997 struct clock_sync cal_info[CNT_CAL_INFO];
1003 * Driver code that can run when the adapter is suspended must use this
1004 * lock or a synchronized_op and check for HW_OFF_LIMITS before
1005 * accessing hardware.
1007 * XXX: could be changed to rwlock. wlock in suspend/resume and for
1008 * indirect register access, rlock everywhere else.
1010 struct mtx reg_lock;
1012 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
1015 struct task tc_task;
1017 struct task fatal_error_task;
1018 struct task reset_task;
1019 const void *reset_thread;
1023 const char *last_op;
1024 const void *last_op_thr;
1030 struct callout ktls_tick;
1033 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
1034 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
1035 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
1036 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
1038 #define ASSERT_SYNCHRONIZED_OP(sc) \
1039 KASSERT(IS_BUSY(sc) && \
1040 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
1041 ("%s: operation not synchronized.", __func__))
1043 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
1044 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
1045 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
1046 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
1048 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
1049 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
1050 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
1051 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
1052 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
1054 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
1055 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
1056 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
1057 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
1059 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
1060 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
1061 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
1062 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
1063 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
1065 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
1066 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
1067 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
1068 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
1069 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
1071 #define for_each_txq(vi, iter, q) \
1072 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
1073 iter < vi->ntxq; ++iter, ++q)
1074 #define for_each_rxq(vi, iter, q) \
1075 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
1076 iter < vi->nrxq; ++iter, ++q)
1077 #define for_each_ofld_txq(vi, iter, q) \
1078 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
1079 iter < vi->nofldtxq; ++iter, ++q)
1080 #define for_each_ofld_rxq(vi, iter, q) \
1081 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
1082 iter < vi->nofldrxq; ++iter, ++q)
1083 #define for_each_nm_txq(vi, iter, q) \
1084 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
1085 iter < vi->nnmtxq; ++iter, ++q)
1086 #define for_each_nm_rxq(vi, iter, q) \
1087 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
1088 iter < vi->nnmrxq; ++iter, ++q)
1089 #define for_each_vi(_pi, _iter, _vi) \
1090 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
1093 #define IDXINCR(idx, incr, wrap) do { \
1094 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
1096 #define IDXDIFF(head, tail, wrap) \
1097 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1099 /* One for errors, one for firmware events */
1100 #define T4_EXTRA_INTR 2
1102 /* One for firmware events */
1103 #define T4VF_EXTRA_INTR 1
1106 forwarding_intr_to_fwq(struct adapter *sc)
1109 return (sc->intr_count == 1);
1112 /* Works reliably inside a sync_op or with reg_lock held. */
1114 hw_off_limits(struct adapter *sc)
1116 int off_limits = atomic_load_int(&sc->error_flags) & HW_OFF_LIMITS;
1118 return (__predict_false(off_limits != 0));
1122 mbuf_nsegs(struct mbuf *m)
1125 KASSERT(m->m_pkthdr.inner_l5hlen > 0,
1126 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1128 return (m->m_pkthdr.inner_l5hlen);
1132 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1135 m->m_pkthdr.inner_l5hlen = nsegs;
1138 /* Internal mbuf flags stored in PH_loc.eight[1]. */
1139 #define MC_NOMAP 0x01
1140 #define MC_RAW_WR 0x02
1144 mbuf_cflags(struct mbuf *m)
1147 return (m->m_pkthdr.PH_loc.eight[4]);
1151 set_mbuf_cflags(struct mbuf *m, uint8_t flags)
1154 m->m_pkthdr.PH_loc.eight[4] = flags;
1158 mbuf_len16(struct mbuf *m)
1163 n = m->m_pkthdr.PH_loc.eight[0];
1164 if (!(mbuf_cflags(m) & MC_TLS))
1165 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1171 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1174 if (!(mbuf_cflags(m) & MC_TLS))
1175 MPASS(len16 > 0 && len16 <= SGE_MAX_WR_LEN / 16);
1176 m->m_pkthdr.PH_loc.eight[0] = len16;
1179 static inline uint32_t
1180 t4_read_reg(struct adapter *sc, uint32_t reg)
1182 if (hw_off_limits(sc))
1183 MPASS(curthread == sc->reset_thread);
1184 return bus_space_read_4(sc->bt, sc->bh, reg);
1188 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1190 if (hw_off_limits(sc))
1191 MPASS(curthread == sc->reset_thread);
1192 bus_space_write_4(sc->bt, sc->bh, reg, val);
1195 static inline uint64_t
1196 t4_read_reg64(struct adapter *sc, uint32_t reg)
1198 if (hw_off_limits(sc))
1199 MPASS(curthread == sc->reset_thread);
1201 return bus_space_read_8(sc->bt, sc->bh, reg);
1203 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1204 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1210 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1212 if (hw_off_limits(sc))
1213 MPASS(curthread == sc->reset_thread);
1215 bus_space_write_8(sc->bt, sc->bh, reg, val);
1217 bus_space_write_4(sc->bt, sc->bh, reg, val);
1218 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1223 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1225 if (hw_off_limits(sc))
1226 MPASS(curthread == sc->reset_thread);
1227 *val = pci_read_config(sc->dev, reg, 1);
1231 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1233 if (hw_off_limits(sc))
1234 MPASS(curthread == sc->reset_thread);
1235 pci_write_config(sc->dev, reg, val, 1);
1239 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1242 if (hw_off_limits(sc))
1243 MPASS(curthread == sc->reset_thread);
1244 *val = pci_read_config(sc->dev, reg, 2);
1248 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1250 if (hw_off_limits(sc))
1251 MPASS(curthread == sc->reset_thread);
1252 pci_write_config(sc->dev, reg, val, 2);
1256 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1258 if (hw_off_limits(sc))
1259 MPASS(curthread == sc->reset_thread);
1260 *val = pci_read_config(sc->dev, reg, 4);
1264 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1266 if (hw_off_limits(sc))
1267 MPASS(curthread == sc->reset_thread);
1268 pci_write_config(sc->dev, reg, val, 4);
1271 static inline struct port_info *
1272 adap2pinfo(struct adapter *sc, int idx)
1275 return (sc->port[idx]);
1279 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1282 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1286 tx_resume_threshold(struct sge_eq *eq)
1289 /* not quite the same as qsize / 4, but this will do. */
1290 return (eq->sidx / 4);
1294 t4_use_ldst(struct adapter *sc)
1298 return (sc->flags & FW_OK || !sc->use_bd);
1305 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1306 const char *msg, const __be64 *const p, const bool err)
1309 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1312 log(err ? LOG_ERR : LOG_DEBUG,
1313 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1314 "%016llx %016llx %016llx %016llx\n",
1315 device_get_nameunit(sc->dev), mbox, msg,
1316 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1317 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1318 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1319 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1321 log(err ? LOG_ERR : LOG_DEBUG,
1322 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1323 "%016llx %016llx %016llx %016llx\n",
1324 device_get_nameunit(sc->dev), mbox, msg,
1325 (long long)t4_read_reg64(sc, reg),
1326 (long long)t4_read_reg64(sc, reg + 8),
1327 (long long)t4_read_reg64(sc, reg + 16),
1328 (long long)t4_read_reg64(sc, reg + 24),
1329 (long long)t4_read_reg64(sc, reg + 32),
1330 (long long)t4_read_reg64(sc, reg + 40),
1331 (long long)t4_read_reg64(sc, reg + 48),
1332 (long long)t4_read_reg64(sc, reg + 56));
1339 extern int t4_intr_types;
1340 extern int t4_tmr_idx;
1341 extern int t4_pktc_idx;
1342 extern unsigned int t4_qsize_rxq;
1343 extern unsigned int t4_qsize_txq;
1344 extern device_method_t cxgbe_methods[];
1346 int t4_os_find_pci_capability(struct adapter *, int);
1347 int t4_os_pci_save_state(struct adapter *);
1348 int t4_os_pci_restore_state(struct adapter *);
1349 void t4_os_portmod_changed(struct port_info *);
1350 void t4_os_link_changed(struct port_info *);
1351 void t4_iterate(void (*)(struct adapter *, void *), void *);
1352 void t4_init_devnames(struct adapter *);
1353 void t4_add_adapter(struct adapter *);
1354 int t4_detach_common(device_t);
1355 int t4_map_bars_0_and_4(struct adapter *);
1356 int t4_map_bar_2(struct adapter *);
1357 int t4_setup_intr_handlers(struct adapter *);
1358 void t4_sysctls(struct adapter *);
1359 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1360 void doom_vi(struct adapter *, struct vi_info *);
1361 void end_synchronized_op(struct adapter *, int);
1362 int update_mac_settings(if_t, int);
1363 int adapter_init(struct adapter *);
1364 int vi_init(struct vi_info *);
1365 void vi_sysctls(struct vi_info *);
1366 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1367 int alloc_atid(struct adapter *, void *);
1368 void *lookup_atid(struct adapter *, int);
1369 void free_atid(struct adapter *, int);
1370 void release_tid(struct adapter *, int, struct sge_wrq *);
1371 int cxgbe_media_change(if_t);
1372 void cxgbe_media_status(if_t, struct ifmediareq *);
1373 void t4_os_cim_err(struct adapter *);
1377 int t6_tls_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1378 struct m_snd_tag **);
1379 void t6_ktls_modload(void);
1380 void t6_ktls_modunload(void);
1381 int t6_ktls_try(if_t, struct socket *, struct ktls_session *);
1382 int t6_ktls_parse_pkt(struct mbuf *);
1383 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int);
1390 struct ktls_session;
1395 void t4_aes_getdeckey(void *, const void *, unsigned int);
1396 void t4_copy_partial_hash(int, union authctx *, void *);
1397 void t4_init_gmac_hash(const char *, int, char *);
1398 void t4_init_hmac_digest(const struct auth_hash *, u_int, const char *, int,
1401 u_int t4_tls_key_info_size(const struct ktls_session *);
1402 int t4_tls_proto_ver(const struct ktls_session *);
1403 int t4_tls_cipher_mode(const struct ktls_session *);
1404 int t4_tls_auth_mode(const struct ktls_session *);
1405 int t4_tls_hmac_ctrl(const struct ktls_session *);
1406 void t4_tls_key_ctx(const struct ktls_session *, int, struct tls_keyctx *);
1407 int t4_alloc_tls_keyid(struct adapter *);
1408 void t4_free_tls_keyid(struct adapter *, int);
1409 void t4_write_tlskey_wr(const struct ktls_session *, int, int, int, int,
1410 struct tls_key_req *);
1416 void cxgbe_nm_attach(struct vi_info *);
1417 void cxgbe_nm_detach(struct vi_info *);
1418 void service_nm_rxq(struct sge_nm_rxq *);
1419 int alloc_nm_rxq(struct vi_info *, struct sge_nm_rxq *, int, int);
1420 int free_nm_rxq(struct vi_info *, struct sge_nm_rxq *);
1421 int alloc_nm_txq(struct vi_info *, struct sge_nm_txq *, int, int);
1422 int free_nm_txq(struct vi_info *, struct sge_nm_txq *);
1426 void t4_sge_modload(void);
1427 void t4_sge_modunload(void);
1428 uint64_t t4_sge_extfree_refs(void);
1429 void t4_tweak_chip_settings(struct adapter *);
1430 int t4_verify_chip_settings(struct adapter *);
1431 void t4_init_rx_buf_info(struct adapter *);
1432 int t4_create_dma_tag(struct adapter *);
1433 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1434 struct sysctl_oid_list *);
1435 int t4_destroy_dma_tag(struct adapter *);
1436 int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
1437 bus_addr_t *, void **);
1438 int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
1440 void free_fl_buffers(struct adapter *, struct sge_fl *);
1441 int t4_setup_adapter_queues(struct adapter *);
1442 int t4_teardown_adapter_queues(struct adapter *);
1443 int t4_setup_vi_queues(struct vi_info *);
1444 int t4_teardown_vi_queues(struct vi_info *);
1445 void t4_intr_all(void *);
1446 void t4_intr(void *);
1448 void t4_nm_intr(void *);
1449 void t4_vi_intr(void *);
1451 void t4_intr_err(void *);
1452 void t4_intr_evt(void *);
1453 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1454 void t4_update_fl_bufsize(if_t);
1455 struct mbuf *alloc_wr_mbuf(int, int);
1456 int parse_pkt(struct mbuf **, bool);
1457 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1458 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1459 int t4_sge_set_conm_context(struct adapter *, int, int, int);
1460 void t4_register_an_handler(an_handler_t);
1461 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1462 void t4_register_cpl_handler(int, cpl_handler_t);
1463 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1465 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1470 void t4_tracer_modload(void);
1471 void t4_tracer_modunload(void);
1472 void t4_tracer_port_detach(struct adapter *);
1473 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1474 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1475 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1476 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1479 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1480 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1481 int t4_init_tx_sched(struct adapter *);
1482 int t4_free_tx_sched(struct adapter *);
1483 void t4_update_tx_sched(struct adapter *);
1484 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1485 void t4_release_cl_rl(struct adapter *, int, int);
1486 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1487 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1489 void t4_init_etid_table(struct adapter *);
1490 void t4_free_etid_table(struct adapter *);
1491 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1492 int cxgbe_rate_tag_alloc(if_t, union if_snd_tag_alloc_params *,
1493 struct m_snd_tag **);
1494 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1495 void cxgbe_ratelimit_query(if_t, struct if_ratelimit_query_results *);
1499 int get_filter_mode(struct adapter *, uint32_t *);
1500 int set_filter_mode(struct adapter *, uint32_t);
1501 int set_filter_mask(struct adapter *, uint32_t);
1502 int get_filter(struct adapter *, struct t4_filter *);
1503 int set_filter(struct adapter *, struct t4_filter *);
1504 int del_filter(struct adapter *, struct t4_filter *);
1505 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1506 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1507 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1508 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1509 void free_hftid_hash(struct tid_info *);
1511 static inline struct wrqe *
1512 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1514 int len = offsetof(struct wrqe, wr) + wr_len;
1517 wr = malloc(len, M_CXGBE, M_NOWAIT);
1518 if (__predict_false(wr == NULL))
1520 wr->wr_len = wr_len;
1525 static inline void *
1526 wrtod(struct wrqe *wr)
1528 return (&wr->wr[0]);
1532 free_wrqe(struct wrqe *wr)
1538 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1540 struct sge_wrq *wrq = wr->wrq;
1543 t4_wrq_tx_locked(sc, wrq, wr);
1548 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1552 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1556 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1557 const uint32_t *val, int len)
1560 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1563 /* Number of len16 -> number of descriptors */
1565 tx_len16_to_desc(int len16)
1568 return (howmany(len16, EQ_ESIZE / 16));