2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
39 #include <sys/types.h>
41 #include <sys/malloc.h>
42 #include <sys/rwlock.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <machine/bus.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
53 #include <net/if_var.h>
54 #include <net/if_media.h>
55 #include <netinet/in.h>
56 #include <netinet/tcp_lro.h>
60 #include "common/t4_msg.h"
61 #include "firmware/t4fw_interface.h"
63 #define KTR_CXGBE KTR_SPARE3
64 MALLOC_DECLARE(M_CXGBE);
65 #define CXGBE_UNIMPLEMENTED(s) \
66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
68 #if defined(__i386__) || defined(__amd64__)
72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
75 #define prefetch(x) __builtin_prefetch(x)
78 #ifndef SYSCTL_ADD_UQUAD
79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
80 #define sysctl_handle_64 sysctl_handle_quad
81 #define CTLTYPE_U64 CTLTYPE_QUAD
84 #if (__FreeBSD_version >= 900030) || \
85 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
90 typedef struct adapter adapter_t;
94 * All ingress queues use this entry size. Note that the firmware event
95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
100 /* Default queue sizes for all kinds of ingress queues */
104 /* All egress queues use this entry size */
107 /* Default queue sizes for all kinds of egress queues */
111 #if MJUMPAGESIZE != MCLBYTES
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
116 CL_METADATA_SIZE = CACHE_LINE_SIZE,
118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
120 TX_SGL_SEGS_TSO = 38,
121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
125 /* adapter intr_type */
126 INTR_INTX = (1 << 0),
132 XGMAC_MTU = (1 << 0),
133 XGMAC_PROMISC = (1 << 1),
134 XGMAC_ALLMULTI = (1 << 2),
135 XGMAC_VLANEX = (1 << 3),
136 XGMAC_UCADDR = (1 << 4),
137 XGMAC_MCADDRS = (1 << 5),
143 /* flags understood by begin_synchronized_op */
144 HOLD_LOCK = (1 << 0),
148 /* flags understood by end_synchronized_op */
149 LOCK_HELD = HOLD_LOCK,
154 FULL_INIT_DONE = (1 << 0),
156 CHK_MBOX_ACCESS = (1 << 2),
157 MASTER_PF = (1 << 3),
158 ADAP_SYSCTL_CTX = (1 << 4),
159 /* TOM_INIT_DONE= (1 << 5), No longer used */
160 BUF_PACKING_OK = (1 << 6),
163 CXGBE_BUSY = (1 << 9),
166 HAS_TRACEQ = (1 << 3),
167 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
171 VI_INIT_DONE = (1 << 1),
172 VI_SYSCTL_CTX = (1 << 2),
174 /* adapter debug_flags */
175 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
176 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
177 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
180 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
181 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
182 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
183 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
184 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
188 struct port_info *pi;
195 uint16_t *rss, *nm_rss;
196 int smt_idx; /* for convenience */
198 int16_t xact_addr_filt;/* index of exact MAC address filter */
199 uint16_t rss_size; /* size of VI's RSS table slice */
200 uint16_t rss_base; /* start of VI's RSS table slice */
202 eventhandler_tag vlan_c;
207 /* These need to be int as they are used in sysctl */
208 int ntxq; /* # of tx queues */
209 int first_txq; /* index of first tx queue */
210 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
211 int nrxq; /* # of rx queues */
212 int first_rxq; /* index of first rx queue */
213 int nofldtxq; /* # of offload tx queues */
214 int first_ofld_txq; /* index of first offload tx queue */
215 int nofldrxq; /* # of offload rx queues */
216 int first_ofld_rxq; /* index of first offload rx queue */
228 struct timeval last_refreshed;
229 struct fw_vi_stats_vf stats;
232 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
234 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
237 struct tx_ch_rl_params {
238 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
243 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */
244 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */
247 struct tx_cl_rl_params {
250 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
251 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
252 enum fw_sched_params_mode mode; /* aggr or per-flow */
257 /* Tx scheduler parameters for a channel/port */
258 struct tx_sched_params {
259 /* Channel Rate Limiter */
260 struct tx_ch_rl_params ch_rl;
265 /* Class Rate Limiter */
266 struct tx_cl_rl_params cl_rl[];
271 struct adapter *adapter;
278 struct tx_sched_params *sched_params;
284 uint8_t lport; /* associated offload logical port */
290 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
291 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
293 struct link_config link_cfg;
294 struct link_config old_link_cfg;
295 struct ifmedia media;
297 struct timeval last_refreshed;
298 struct port_stats stats;
299 u_int tnl_cong_drops;
300 u_int tx_parse_error;
301 u_long tx_tls_records;
302 u_long tx_tls_octets;
303 u_long rx_tls_records;
304 u_long rx_tls_octets;
309 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
311 /* Where the cluster came from, how it has been carved up. */
312 struct cluster_layout {
315 uint16_t region1; /* mbufs laid out within this region */
316 /* region2 is the DMA region */
317 uint16_t region3; /* cluster_metadata within this region */
320 struct cluster_metadata {
322 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
327 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
328 struct cluster_layout cll;
336 struct mbuf *m; /* m_nextpkt linked chain of frames */
337 uint8_t desc_used; /* # of hardware descriptors used by the WR */
341 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
343 struct rss_header rss;
348 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
352 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
353 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
354 /* 1 << 2 Used to be IQ_INTR */
355 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
356 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
363 /* netmap related flags */
370 CPL_COOKIE_RESERVED = 0,
375 CPL_COOKIE_HASHFILTER,
377 CPL_COOKIE_AVAILABLE3,
379 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
384 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
386 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
387 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
390 * Ingress Queue: T4 is producer, driver is consumer.
395 struct adapter *adapter;
396 struct iq_desc *desc; /* KVA of descriptor ring */
397 int8_t intr_pktc_idx; /* packet count threshold index */
398 uint8_t gen; /* generation bit */
399 uint8_t intr_params; /* interrupt holdoff parameters */
400 uint8_t intr_next; /* XXX: holdoff for next interrupt */
401 uint16_t qsize; /* size (# of entries) of the queue */
402 uint16_t sidx; /* index of the entry with the status page */
403 uint16_t cidx; /* consumer index */
404 uint16_t cntxt_id; /* SGE context id for the iq */
405 uint16_t abs_id; /* absolute SGE id for the iq */
407 STAILQ_ENTRY(sge_iq) link;
409 bus_dma_tag_t desc_tag;
410 bus_dmamap_t desc_map;
411 bus_addr_t ba; /* bus address of descriptor ring */
420 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
421 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
422 EQ_ENABLED = (1 << 3), /* open for business */
423 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
426 /* Listed in order of preference. Update t4_sysctls too if you change these */
427 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
430 * Egress Queue: driver is producer, T4 is consumer.
432 * Note: A free list is an egress queue (driver produces the buffers and T4
433 * consumes them) but it's special enough to have its own struct (see sge_fl).
436 unsigned int flags; /* MUST be first */
437 unsigned int cntxt_id; /* SGE context id for the eq */
438 unsigned int abs_id; /* absolute SGE id for the eq */
441 struct tx_desc *desc; /* KVA of descriptor ring */
443 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
444 u_int udb_qid; /* relative qid within the doorbell page */
445 uint16_t sidx; /* index of the entry with the status page */
446 uint16_t cidx; /* consumer idx (desc idx) */
447 uint16_t pidx; /* producer idx (desc idx) */
448 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
449 uint16_t dbidx; /* pidx of the most recent doorbell */
450 uint16_t iqid; /* iq that gets egr_update for the eq */
451 uint8_t tx_chan; /* tx channel used by the eq */
452 volatile u_int equiq; /* EQUIQ outstanding */
454 bus_dma_tag_t desc_tag;
455 bus_dmamap_t desc_map;
456 bus_addr_t ba; /* bus address of descriptor ring */
460 struct sw_zone_info {
461 uma_zone_t zone; /* zone that this cluster comes from */
462 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
463 int type; /* EXT_xxx type of the cluster */
469 int8_t zidx; /* backpointer to zone; -ve means unused */
470 int8_t next; /* next hwidx for this zone; -1 means no more */
477 MEMWIN0_APERTURE = 2048,
478 MEMWIN0_BASE = 0x1b800,
480 MEMWIN1_APERTURE = 32768,
481 MEMWIN1_BASE = 0x28000,
483 MEMWIN2_APERTURE_T4 = 65536,
484 MEMWIN2_BASE_T4 = 0x30000,
486 MEMWIN2_APERTURE_T5 = 128 * 1024,
487 MEMWIN2_BASE_T5 = 0x60000,
491 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
492 uint32_t mw_base; /* constant after setup_memwin */
493 uint32_t mw_aperture; /* ditto */
494 uint32_t mw_curpos; /* protected by mw_lock */
498 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
499 FL_DOOMED = (1 << 1), /* about to be destroyed */
500 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
501 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
504 #define FL_RUNNING_LOW(fl) \
505 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
506 #define FL_NOT_RUNNING_LOW(fl) \
507 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
511 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
512 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
513 struct cluster_layout cll_def; /* default refill zone, layout */
514 uint16_t lowat; /* # of buffers <= this means fl needs help */
516 uint16_t buf_boundary;
518 /* The 16b idx all deal with hw descriptors */
519 uint16_t dbidx; /* hw pidx after last doorbell */
520 uint16_t sidx; /* index of status page */
521 volatile uint16_t hw_cidx;
523 /* The 32b idx are all buffer idx, not hardware descriptor idx */
524 uint32_t cidx; /* consumer index */
525 uint32_t pidx; /* producer index */
528 u_int rx_offset; /* offset in fl buf (when buffer packing) */
529 volatile uint32_t *udb;
531 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
532 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
533 uint64_t cl_allocated; /* # of clusters allocated */
534 uint64_t cl_recycled; /* # of clusters recycled */
535 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
537 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
542 uint16_t qsize; /* # of hw descriptors (status page included) */
543 uint16_t cntxt_id; /* SGE context id for the freelist */
544 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
545 bus_dma_tag_t desc_tag;
546 bus_dmamap_t desc_map;
548 bus_addr_t ba; /* bus address of descriptor ring */
549 struct cluster_layout cll_alt; /* alternate refill zone, layout */
554 /* txq: SGE egress queue + what's needed for Ethernet NIC */
556 struct sge_eq eq; /* MUST be first */
558 struct ifnet *ifp; /* the interface this txq belongs to */
559 struct mp_ring *r; /* tx software ring */
560 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
562 __be32 cpl_ctrl0; /* for convenience */
563 int tc_idx; /* traffic class */
565 struct task tx_reclaim_task;
566 /* stats for common events first */
568 uint64_t txcsum; /* # of times hardware assisted with checksum */
569 uint64_t tso_wrs; /* # of TSO work requests */
570 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
571 uint64_t imm_wrs; /* # of work requests with immediate data */
572 uint64_t sgl_wrs; /* # of work requests with direct SGL */
573 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
574 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
575 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
576 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
577 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
579 /* stats for not-that-common events */
580 } __aligned(CACHE_LINE_SIZE);
582 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
584 struct sge_iq iq; /* MUST be first */
585 struct sge_fl fl; /* MUST follow iq */
587 struct ifnet *ifp; /* the interface this rxq belongs to */
588 #if defined(INET) || defined(INET6)
589 struct lro_ctrl lro; /* LRO state */
592 /* stats for common events first */
594 uint64_t rxcsum; /* # of times hardware assisted with checksum */
595 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
597 /* stats for not-that-common events */
599 } __aligned(CACHE_LINE_SIZE);
601 static inline struct sge_rxq *
602 iq_to_rxq(struct sge_iq *iq)
605 return (__containerof(iq, struct sge_rxq, iq));
609 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
610 struct sge_ofld_rxq {
611 struct sge_iq iq; /* MUST be first */
612 struct sge_fl fl; /* MUST follow iq */
613 } __aligned(CACHE_LINE_SIZE);
615 static inline struct sge_ofld_rxq *
616 iq_to_ofld_rxq(struct sge_iq *iq)
619 return (__containerof(iq, struct sge_ofld_rxq, iq));
623 STAILQ_ENTRY(wrqe) link;
626 char wr[] __aligned(16);
630 TAILQ_ENTRY(wrq_cookie) link;
636 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
637 * and offload tx queues are of this type.
640 struct sge_eq eq; /* MUST be first */
642 struct adapter *adapter;
643 struct task wrq_tx_task;
645 /* Tx desc reserved but WR not "committed" yet. */
646 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
648 /* List of WRs ready to go out as soon as descriptors are available. */
649 STAILQ_HEAD(, wrqe) wr_list;
653 /* stats for common events first */
655 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
656 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
657 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
659 /* stats for not-that-common events */
662 * Scratch space for work requests that wrap around after reaching the
663 * status page, and some information about the last WR that used it.
667 uint8_t ss[SGE_MAX_WR_LEN];
669 } __aligned(CACHE_LINE_SIZE);
671 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
675 struct iq_desc *iq_desc;
677 uint16_t iq_cntxt_id;
683 uint16_t fl_cntxt_id;
690 u_int nid; /* netmap ring # for this queue */
692 /* infrequently used items after this */
694 bus_dma_tag_t iq_desc_tag;
695 bus_dmamap_t iq_desc_map;
699 bus_dma_tag_t fl_desc_tag;
700 bus_dmamap_t fl_desc_map;
702 } __aligned(CACHE_LINE_SIZE);
704 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
706 struct tx_desc *desc;
710 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
711 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
712 uint16_t dbidx; /* pidx of the most recent doorbell */
714 volatile uint32_t *udb;
717 __be32 cpl_ctrl0; /* for convenience */
718 u_int nid; /* netmap ring # for this queue */
720 /* infrequently used items after this */
722 bus_dma_tag_t desc_tag;
723 bus_dmamap_t desc_map;
726 } __aligned(CACHE_LINE_SIZE);
729 int nrxq; /* total # of Ethernet rx queues */
730 int ntxq; /* total # of Ethernet tx queues */
731 int nofldrxq; /* total # of TOE rx queues */
732 int nofldtxq; /* total # of TOE tx queues */
733 int nnmrxq; /* total # of netmap rx queues */
734 int nnmtxq; /* total # of netmap tx queues */
735 int niq; /* total # of ingress queues */
736 int neq; /* total # of egress queues */
738 struct sge_iq fwq; /* Firmware event queue */
739 struct sge_wrq mgmtq; /* Management queue (control queue) */
740 struct sge_wrq *ctrlq; /* Control queues */
741 struct sge_txq *txq; /* NIC tx queues */
742 struct sge_rxq *rxq; /* NIC rx queues */
743 struct sge_wrq *ofld_txq; /* TOE tx queues */
744 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
745 struct sge_nm_txq *nm_txq; /* netmap tx queues */
746 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
748 uint16_t iq_start; /* first cntxt_id */
749 uint16_t iq_base; /* first abs_id */
750 int eq_start; /* first cntxt_id */
751 int eq_base; /* first abs_id */
752 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
753 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
755 int8_t safe_hwidx1; /* may not have room for metadata */
756 int8_t safe_hwidx2; /* with room for metadata and maybe more */
757 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
758 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
762 const char *nexus_name;
763 const char *ifnet_name;
764 const char *vi_ifnet_name;
765 const char *pf03_drv_name;
766 const char *vf_nexus_name;
767 const char *vf_ifnet_name;
771 SLIST_ENTRY(adapter) link;
774 const struct devnames *names;
776 /* PCIe register resources */
778 struct resource *regs_res;
780 struct resource *msix_res;
781 bus_space_handle_t bh;
785 struct resource *udbs_res;
786 volatile uint8_t *udbs_base;
790 unsigned int vpd_busy;
791 unsigned int vpd_flag;
793 /* Interrupt information */
797 struct resource *res;
799 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
802 struct sge_nm_rxq *nm_rxq;
803 } __aligned(CACHE_LINE_SIZE) *irq;
805 int sge_kdoorbell_reg;
807 bus_dma_tag_t dmat; /* Parent DMA tag */
813 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
814 struct port_info *port[MAX_NPORTS];
815 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
817 void *tom_softc; /* (struct tom_data *) */
818 struct tom_tunables tt;
819 struct t4_offload_policy *policy;
820 struct rwlock policy_lock;
822 void *iwarp_softc; /* (struct c4iw_dev *) */
823 struct iw_tunables iwt;
824 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
825 void *ccr_softc; /* (struct ccr_softc *) */
826 struct l2t_data *l2t; /* L2 table */
827 struct smt_data *smt; /* Source MAC Table */
828 struct tid_info tids;
831 int offload_map; /* ports with IFCAP_TOE enabled */
832 int active_ulds; /* ULDs activated on this adapter */
836 char ifp_lockname[16];
838 struct ifnet *ifp; /* tracer ifp */
839 struct ifmedia media;
840 int traceq; /* iq used by all tracers, -1 if none */
841 int tracer_valid; /* bitmap of valid tracers */
842 int tracer_enabled; /* bitmap of enabled tracers */
850 struct adapter_params params;
851 const struct chip_params *chip_params;
852 struct t4_virt_res vres;
864 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
869 /* Starving free lists */
870 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
871 TAILQ_HEAD(, sge_fl) sfl;
872 struct callout sfl_callout;
874 struct mtx reg_lock; /* for indirect register access */
876 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
882 const void *last_op_thr;
886 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
887 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
888 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
889 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
891 #define ASSERT_SYNCHRONIZED_OP(sc) \
892 KASSERT(IS_BUSY(sc) && \
893 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
894 ("%s: operation not synchronized.", __func__))
896 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
897 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
898 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
899 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
901 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
902 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
903 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
904 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
905 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
907 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
908 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
909 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
910 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
912 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
913 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
914 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
915 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
916 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
918 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
919 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
920 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
921 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
922 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
924 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
926 if (sc->debug_flags & DF_DUMP_MBOX) { \
928 "%s mbox %u: %016llx %016llx %016llx %016llx " \
929 "%016llx %016llx %016llx %016llx\n", \
930 device_get_nameunit(sc->dev), mbox, \
931 (unsigned long long)t4_read_reg64(sc, data_reg), \
932 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
933 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
934 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
935 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
936 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
937 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
938 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
942 #define for_each_txq(vi, iter, q) \
943 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
944 iter < vi->ntxq; ++iter, ++q)
945 #define for_each_rxq(vi, iter, q) \
946 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
947 iter < vi->nrxq; ++iter, ++q)
948 #define for_each_ofld_txq(vi, iter, q) \
949 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
950 iter < vi->nofldtxq; ++iter, ++q)
951 #define for_each_ofld_rxq(vi, iter, q) \
952 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
953 iter < vi->nofldrxq; ++iter, ++q)
954 #define for_each_nm_txq(vi, iter, q) \
955 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
956 iter < vi->nnmtxq; ++iter, ++q)
957 #define for_each_nm_rxq(vi, iter, q) \
958 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
959 iter < vi->nnmrxq; ++iter, ++q)
960 #define for_each_vi(_pi, _iter, _vi) \
961 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
964 #define IDXINCR(idx, incr, wrap) do { \
965 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
967 #define IDXDIFF(head, tail, wrap) \
968 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
970 /* One for errors, one for firmware events */
971 #define T4_EXTRA_INTR 2
973 /* One for firmware events */
974 #define T4VF_EXTRA_INTR 1
977 forwarding_intr_to_fwq(struct adapter *sc)
980 return (sc->intr_count == 1);
983 static inline uint32_t
984 t4_read_reg(struct adapter *sc, uint32_t reg)
987 return bus_space_read_4(sc->bt, sc->bh, reg);
991 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
994 bus_space_write_4(sc->bt, sc->bh, reg, val);
997 static inline uint64_t
998 t4_read_reg64(struct adapter *sc, uint32_t reg)
1002 return bus_space_read_8(sc->bt, sc->bh, reg);
1004 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1005 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1011 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1015 bus_space_write_8(sc->bt, sc->bh, reg, val);
1017 bus_space_write_4(sc->bt, sc->bh, reg, val);
1018 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1023 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1026 *val = pci_read_config(sc->dev, reg, 1);
1030 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1033 pci_write_config(sc->dev, reg, val, 1);
1037 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1040 *val = pci_read_config(sc->dev, reg, 2);
1044 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1047 pci_write_config(sc->dev, reg, val, 2);
1051 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1054 *val = pci_read_config(sc->dev, reg, 4);
1058 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1061 pci_write_config(sc->dev, reg, val, 4);
1064 static inline struct port_info *
1065 adap2pinfo(struct adapter *sc, int idx)
1068 return (sc->port[idx]);
1072 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1075 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1079 is_10G_port(const struct port_info *pi)
1082 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1086 is_25G_port(const struct port_info *pi)
1089 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1093 is_40G_port(const struct port_info *pi)
1096 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1100 is_100G_port(const struct port_info *pi)
1103 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1107 port_top_speed(const struct port_info *pi)
1110 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1112 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1114 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1116 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1118 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1125 tx_resume_threshold(struct sge_eq *eq)
1128 /* not quite the same as qsize / 4, but this will do. */
1129 return (eq->sidx / 4);
1133 t4_use_ldst(struct adapter *sc)
1137 return (sc->flags & FW_OK || !sc->use_bd);
1146 extern int t4_intr_types;
1147 extern int t4_tmr_idx;
1148 extern int t4_pktc_idx;
1149 extern unsigned int t4_qsize_rxq;
1150 extern unsigned int t4_qsize_txq;
1151 extern device_method_t cxgbe_methods[];
1153 int t4_os_find_pci_capability(struct adapter *, int);
1154 int t4_os_pci_save_state(struct adapter *);
1155 int t4_os_pci_restore_state(struct adapter *);
1156 void t4_os_portmod_changed(struct port_info *);
1157 void t4_os_link_changed(struct port_info *);
1158 void t4_iterate(void (*)(struct adapter *, void *), void *);
1159 void t4_init_devnames(struct adapter *);
1160 void t4_add_adapter(struct adapter *);
1161 void t4_aes_getdeckey(void *, const void *, unsigned int);
1162 int t4_detach_common(device_t);
1163 int t4_map_bars_0_and_4(struct adapter *);
1164 int t4_map_bar_2(struct adapter *);
1165 int t4_setup_intr_handlers(struct adapter *);
1166 void t4_sysctls(struct adapter *);
1167 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1168 void doom_vi(struct adapter *, struct vi_info *);
1169 void end_synchronized_op(struct adapter *, int);
1170 int update_mac_settings(struct ifnet *, int);
1171 int adapter_full_init(struct adapter *);
1172 int adapter_full_uninit(struct adapter *);
1173 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1174 int vi_full_init(struct vi_info *);
1175 int vi_full_uninit(struct vi_info *);
1176 void vi_sysctls(struct vi_info *);
1177 void vi_tick(void *);
1178 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1179 int alloc_atid_tab(struct tid_info *, int);
1180 void free_atid_tab(struct tid_info *);
1181 int alloc_atid(struct adapter *, void *);
1182 void *lookup_atid(struct adapter *, int);
1183 void free_atid(struct adapter *, int);
1184 void release_tid(struct adapter *, int, struct sge_wrq *);
1188 void cxgbe_nm_attach(struct vi_info *);
1189 void cxgbe_nm_detach(struct vi_info *);
1190 void t4_nm_intr(void *);
1194 void t4_sge_modload(void);
1195 void t4_sge_modunload(void);
1196 uint64_t t4_sge_extfree_refs(void);
1197 void t4_tweak_chip_settings(struct adapter *);
1198 int t4_read_chip_settings(struct adapter *);
1199 int t4_create_dma_tag(struct adapter *);
1200 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1201 struct sysctl_oid_list *);
1202 int t4_destroy_dma_tag(struct adapter *);
1203 int t4_setup_adapter_queues(struct adapter *);
1204 int t4_teardown_adapter_queues(struct adapter *);
1205 int t4_setup_vi_queues(struct vi_info *);
1206 int t4_teardown_vi_queues(struct vi_info *);
1207 void t4_intr_all(void *);
1208 void t4_intr(void *);
1209 void t4_vi_intr(void *);
1210 void t4_intr_err(void *);
1211 void t4_intr_evt(void *);
1212 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1213 void t4_update_fl_bufsize(struct ifnet *);
1214 int parse_pkt(struct adapter *, struct mbuf **);
1215 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1216 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1217 int tnl_cong(struct port_info *, int);
1218 void t4_register_an_handler(an_handler_t);
1219 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1220 void t4_register_cpl_handler(int, cpl_handler_t);
1221 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1223 int ethofld_transmit(struct ifnet *, struct mbuf *);
1224 void send_etid_flush_wr(struct cxgbe_snd_tag *);
1229 void t4_tracer_modload(void);
1230 void t4_tracer_modunload(void);
1231 void t4_tracer_port_detach(struct adapter *);
1232 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1233 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1234 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1235 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1238 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1239 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1240 int t4_init_tx_sched(struct adapter *);
1241 int t4_free_tx_sched(struct adapter *);
1242 void t4_update_tx_sched(struct adapter *);
1243 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1244 void t4_release_cl_rl_kbps(struct adapter *, int, int);
1246 void t4_init_etid_table(struct adapter *);
1247 void t4_free_etid_table(struct adapter *);
1248 struct cxgbe_snd_tag *lookup_etid(struct adapter *, int);
1249 int cxgbe_snd_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1250 struct m_snd_tag **);
1251 int cxgbe_snd_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1252 int cxgbe_snd_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1253 void cxgbe_snd_tag_free(struct m_snd_tag *);
1254 void cxgbe_snd_tag_free_locked(struct cxgbe_snd_tag *);
1258 int get_filter_mode(struct adapter *, uint32_t *);
1259 int set_filter_mode(struct adapter *, uint32_t);
1260 int get_filter(struct adapter *, struct t4_filter *);
1261 int set_filter(struct adapter *, struct t4_filter *);
1262 int del_filter(struct adapter *, struct t4_filter *);
1263 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1264 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1265 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1266 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1268 static inline struct wrqe *
1269 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1271 int len = offsetof(struct wrqe, wr) + wr_len;
1274 wr = malloc(len, M_CXGBE, M_NOWAIT);
1275 if (__predict_false(wr == NULL))
1277 wr->wr_len = wr_len;
1282 static inline void *
1283 wrtod(struct wrqe *wr)
1285 return (&wr->wr[0]);
1289 free_wrqe(struct wrqe *wr)
1295 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1297 struct sge_wrq *wrq = wr->wrq;
1300 t4_wrq_tx_locked(sc, wrq, wr);
1305 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1309 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1313 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1314 const uint32_t *val, int len)
1317 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));