2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
38 #include <sys/counter.h>
40 #include <sys/types.h>
42 #include <sys/malloc.h>
43 #include <sys/rwlock.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <machine/bus.h>
51 #include <sys/socket.h>
52 #include <sys/sysctl.h>
53 #include <net/ethernet.h>
55 #include <net/if_var.h>
56 #include <net/if_media.h>
58 #include <netinet/in.h>
59 #include <netinet/tcp_lro.h>
63 #include "common/t4_msg.h"
64 #include "firmware/t4fw_interface.h"
66 #define KTR_CXGBE KTR_SPARE3
67 MALLOC_DECLARE(M_CXGBE);
68 #define CXGBE_UNIMPLEMENTED(s) \
69 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
71 #if defined(__i386__) || defined(__amd64__)
75 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
78 #define prefetch(x) __builtin_prefetch(x)
81 #ifndef SYSCTL_ADD_UQUAD
82 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
83 #define sysctl_handle_64 sysctl_handle_quad
84 #define CTLTYPE_U64 CTLTYPE_QUAD
87 SYSCTL_DECL(_hw_cxgbe);
90 typedef struct adapter adapter_t;
94 * All ingress queues use this entry size. Note that the firmware event
95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
100 /* Default queue sizes for all kinds of ingress queues */
104 /* All egress queues use this entry size */
107 /* Default queue sizes for all kinds of egress queues */
108 CTRL_EQ_QSIZE = 1024,
111 #if MJUMPAGESIZE != MCLBYTES
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
116 CL_METADATA_SIZE = CACHE_LINE_SIZE,
118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
120 TX_SGL_SEGS_TSO = 38,
121 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
122 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
126 /* adapter intr_type */
127 INTR_INTX = (1 << 0),
133 XGMAC_MTU = (1 << 0),
134 XGMAC_PROMISC = (1 << 1),
135 XGMAC_ALLMULTI = (1 << 2),
136 XGMAC_VLANEX = (1 << 3),
137 XGMAC_UCADDR = (1 << 4),
138 XGMAC_MCADDRS = (1 << 5),
144 /* flags understood by begin_synchronized_op */
145 HOLD_LOCK = (1 << 0),
149 /* flags understood by end_synchronized_op */
150 LOCK_HELD = HOLD_LOCK,
155 FULL_INIT_DONE = (1 << 0),
157 CHK_MBOX_ACCESS = (1 << 2),
158 MASTER_PF = (1 << 3),
159 ADAP_SYSCTL_CTX = (1 << 4),
161 BUF_PACKING_OK = (1 << 6),
163 KERN_TLS_OK = (1 << 8),
165 CXGBE_BUSY = (1 << 9),
168 HAS_TRACEQ = (1 << 3),
169 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
173 VI_INIT_DONE = (1 << 1),
174 VI_SYSCTL_CTX = (1 << 2),
176 /* adapter debug_flags */
177 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
178 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
179 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
180 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
181 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
184 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
185 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
186 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
187 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
188 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
192 struct port_info *pi;
193 struct adapter *adapter;
196 struct pfil_head *pfil;
201 uint16_t *rss, *nm_rss;
202 uint16_t viid; /* opaque VI identifier */
206 int16_t xact_addr_filt;/* index of exact MAC address filter */
207 uint16_t rss_size; /* size of VI's RSS table slice */
208 uint16_t rss_base; /* start of VI's RSS table slice */
214 /* These need to be int as they are used in sysctl */
215 int ntxq; /* # of tx queues */
216 int first_txq; /* index of first tx queue */
217 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
218 int nrxq; /* # of rx queues */
219 int first_rxq; /* index of first rx queue */
220 int nofldtxq; /* # of offload tx queues */
221 int first_ofld_txq; /* index of first offload tx queue */
222 int nofldrxq; /* # of offload rx queues */
223 int first_ofld_rxq; /* index of first offload rx queue */
235 struct timeval last_refreshed;
236 struct fw_vi_stats_vf stats;
239 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
241 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
244 struct tx_ch_rl_params {
245 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
250 CLRL_USER = (1 << 0), /* allocated manually. */
251 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */
252 CLRL_ASYNC = (1 << 2), /* async hw update requested. */
253 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */
256 struct tx_cl_rl_params {
259 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
260 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
261 enum fw_sched_params_mode mode; /* aggr or per-flow */
267 /* Tx scheduler parameters for a channel/port */
268 struct tx_sched_params {
269 /* Channel Rate Limiter */
270 struct tx_ch_rl_params ch_rl;
275 /* Class Rate Limiter (including the default pktsize and burstsize). */
278 struct tx_cl_rl_params cl_rl[];
283 struct adapter *adapter;
290 struct tx_sched_params *sched_params;
296 uint8_t lport; /* associated offload logical port */
302 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
303 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
305 struct link_config link_cfg;
306 struct ifmedia media;
308 struct timeval last_refreshed;
309 struct port_stats stats;
310 u_int tnl_cong_drops;
311 u_int tx_parse_error;
312 u_long tx_toe_tls_records;
313 u_long tx_toe_tls_octets;
314 u_long rx_toe_tls_records;
315 u_long rx_toe_tls_octets;
320 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
322 struct cluster_metadata {
330 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
331 int16_t moff; /* offset of metadata from cl */
340 struct mbuf *m; /* m_nextpkt linked chain of frames */
341 uint8_t desc_used; /* # of hardware descriptors used by the WR */
345 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
347 struct rss_header rss;
352 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
356 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
357 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
358 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
359 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
360 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
367 /* netmap related flags */
374 CPL_COOKIE_RESERVED = 0,
379 CPL_COOKIE_HASHFILTER,
383 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
388 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
390 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
391 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
394 * Ingress Queue: T4 is producer, driver is consumer.
399 struct adapter *adapter;
400 struct iq_desc *desc; /* KVA of descriptor ring */
401 int8_t intr_pktc_idx; /* packet count threshold index */
402 uint8_t gen; /* generation bit */
403 uint8_t intr_params; /* interrupt holdoff parameters */
404 uint8_t intr_next; /* XXX: holdoff for next interrupt */
405 uint16_t qsize; /* size (# of entries) of the queue */
406 uint16_t sidx; /* index of the entry with the status page */
407 uint16_t cidx; /* consumer index */
408 uint16_t cntxt_id; /* SGE context id for the iq */
409 uint16_t abs_id; /* absolute SGE id for the iq */
411 STAILQ_ENTRY(sge_iq) link;
413 bus_dma_tag_t desc_tag;
414 bus_dmamap_t desc_map;
415 bus_addr_t ba; /* bus address of descriptor ring */
424 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
425 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
426 EQ_ENABLED = (1 << 3), /* open for business */
427 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
430 /* Listed in order of preference. Update t4_sysctls too if you change these */
431 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
434 * Egress Queue: driver is producer, T4 is consumer.
436 * Note: A free list is an egress queue (driver produces the buffers and T4
437 * consumes them) but it's special enough to have its own struct (see sge_fl).
440 unsigned int flags; /* MUST be first */
441 unsigned int cntxt_id; /* SGE context id for the eq */
442 unsigned int abs_id; /* absolute SGE id for the eq */
445 struct tx_desc *desc; /* KVA of descriptor ring */
447 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
448 u_int udb_qid; /* relative qid within the doorbell page */
449 uint16_t sidx; /* index of the entry with the status page */
450 uint16_t cidx; /* consumer idx (desc idx) */
451 uint16_t pidx; /* producer idx (desc idx) */
452 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
453 uint16_t dbidx; /* pidx of the most recent doorbell */
454 uint16_t iqid; /* iq that gets egr_update for the eq */
455 uint8_t tx_chan; /* tx channel used by the eq */
456 volatile u_int equiq; /* EQUIQ outstanding */
458 bus_dma_tag_t desc_tag;
459 bus_dmamap_t desc_map;
460 bus_addr_t ba; /* bus address of descriptor ring */
465 uma_zone_t zone; /* zone that this cluster comes from */
466 uint16_t size1; /* same as size of cluster: 2K/4K/9K/16K.
467 * hwsize[hwidx1] = size1. No spare. */
468 uint16_t size2; /* hwsize[hwidx2] = size2.
469 * spare in cluster = size1 - size2. */
470 int8_t hwidx1; /* SGE bufsize idx for size1 */
471 int8_t hwidx2; /* SGE bufsize idx for size2 */
472 uint8_t type; /* EXT_xxx type of the cluster */
478 MEMWIN0_APERTURE = 2048,
479 MEMWIN0_BASE = 0x1b800,
481 MEMWIN1_APERTURE = 32768,
482 MEMWIN1_BASE = 0x28000,
484 MEMWIN2_APERTURE_T4 = 65536,
485 MEMWIN2_BASE_T4 = 0x30000,
487 MEMWIN2_APERTURE_T5 = 128 * 1024,
488 MEMWIN2_BASE_T5 = 0x60000,
492 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
493 uint32_t mw_base; /* constant after setup_memwin */
494 uint32_t mw_aperture; /* ditto */
495 uint32_t mw_curpos; /* protected by mw_lock */
499 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
500 FL_DOOMED = (1 << 1), /* about to be destroyed */
501 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
502 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
505 #define FL_RUNNING_LOW(fl) \
506 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
507 #define FL_NOT_RUNNING_LOW(fl) \
508 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
512 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
513 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
514 uint16_t zidx; /* refill zone idx */
516 uint16_t lowat; /* # of buffers <= this means fl needs help */
518 uint16_t buf_boundary;
520 /* The 16b idx all deal with hw descriptors */
521 uint16_t dbidx; /* hw pidx after last doorbell */
522 uint16_t sidx; /* index of status page */
523 volatile uint16_t hw_cidx;
525 /* The 32b idx are all buffer idx, not hardware descriptor idx */
526 uint32_t cidx; /* consumer index */
527 uint32_t pidx; /* producer index */
530 u_int rx_offset; /* offset in fl buf (when buffer packing) */
531 volatile uint32_t *udb;
533 uint64_t cl_allocated; /* # of clusters allocated */
534 uint64_t cl_recycled; /* # of clusters recycled */
535 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
537 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
542 uint16_t qsize; /* # of hw descriptors (status page included) */
543 uint16_t cntxt_id; /* SGE context id for the freelist */
544 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
545 bus_dma_tag_t desc_tag;
546 bus_dmamap_t desc_map;
548 bus_addr_t ba; /* bus address of descriptor ring */
554 uint8_t wr_type; /* type 0 or type 1 */
555 uint8_t npkt; /* # of packets in this work request */
556 uint8_t len16; /* # of 16B pieces used by this work request */
557 uint8_t score; /* 1-10. coalescing attempted if score > 3 */
558 uint8_t max_npkt; /* maximum number of packets allowed */
559 uint16_t plen; /* total payload (sum of all packets) */
561 /* straight from fw_eth_tx_pkts_vm_wr. */
570 /* txq: SGE egress queue + what's needed for Ethernet NIC */
572 struct sge_eq eq; /* MUST be first */
574 struct ifnet *ifp; /* the interface this txq belongs to */
575 struct mp_ring *r; /* tx software ring */
576 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
578 __be32 cpl_ctrl0; /* for convenience */
579 int tc_idx; /* traffic class */
582 struct task tx_reclaim_task;
583 /* stats for common events first */
585 uint64_t txcsum; /* # of times hardware assisted with checksum */
586 uint64_t tso_wrs; /* # of TSO work requests */
587 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
588 uint64_t imm_wrs; /* # of work requests with immediate data */
589 uint64_t sgl_wrs; /* # of work requests with direct SGL */
590 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
591 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
592 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
593 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
594 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
595 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
597 uint64_t kern_tls_records;
598 uint64_t kern_tls_short;
599 uint64_t kern_tls_partial;
600 uint64_t kern_tls_full;
601 uint64_t kern_tls_octets;
602 uint64_t kern_tls_waste;
603 uint64_t kern_tls_options;
604 uint64_t kern_tls_header;
605 uint64_t kern_tls_fin;
606 uint64_t kern_tls_fin_short;
607 uint64_t kern_tls_cbc;
608 uint64_t kern_tls_gcm;
610 /* stats for not-that-common events */
612 /* Optional scratch space for constructing work requests. */
613 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
614 } __aligned(CACHE_LINE_SIZE);
616 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
618 struct sge_iq iq; /* MUST be first */
619 struct sge_fl fl; /* MUST follow iq */
621 struct ifnet *ifp; /* the interface this rxq belongs to */
622 struct lro_ctrl lro; /* LRO state */
624 /* stats for common events first */
626 uint64_t rxcsum; /* # of times hardware assisted with checksum */
627 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
629 /* stats for not-that-common events */
631 } __aligned(CACHE_LINE_SIZE);
633 static inline struct sge_rxq *
634 iq_to_rxq(struct sge_iq *iq)
637 return (__containerof(iq, struct sge_rxq, iq));
641 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
642 struct sge_ofld_rxq {
643 struct sge_iq iq; /* MUST be first */
644 struct sge_fl fl; /* MUST follow iq */
645 } __aligned(CACHE_LINE_SIZE);
647 static inline struct sge_ofld_rxq *
648 iq_to_ofld_rxq(struct sge_iq *iq)
651 return (__containerof(iq, struct sge_ofld_rxq, iq));
655 STAILQ_ENTRY(wrqe) link;
658 char wr[] __aligned(16);
662 TAILQ_ENTRY(wrq_cookie) link;
668 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
669 * and offload tx queues are of this type.
672 struct sge_eq eq; /* MUST be first */
674 struct adapter *adapter;
675 struct task wrq_tx_task;
677 /* Tx desc reserved but WR not "committed" yet. */
678 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
680 /* List of WRs ready to go out as soon as descriptors are available. */
681 STAILQ_HEAD(, wrqe) wr_list;
685 /* stats for common events first */
687 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
688 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
689 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
691 /* stats for not-that-common events */
694 * Scratch space for work requests that wrap around after reaching the
695 * status page, and some information about the last WR that used it.
699 uint8_t ss[SGE_MAX_WR_LEN];
701 } __aligned(CACHE_LINE_SIZE);
703 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
705 /* Items used by the driver rx ithread are in this cacheline. */
706 volatile int nm_state __aligned(CACHE_LINE_SIZE); /* NM_OFF, NM_ON, or NM_BUSY */
707 u_int nid; /* netmap ring # for this queue */
710 struct iq_desc *iq_desc;
712 uint16_t iq_cntxt_id;
718 /* Items used by netmap rxsync are in this cacheline. */
719 __be64 *fl_desc __aligned(CACHE_LINE_SIZE);
720 uint16_t fl_cntxt_id;
722 uint32_t fl_sidx2; /* copy of fl_sidx */
728 * fl_cidx is used by both the ithread and rxsync, the rest are not used
729 * in the rx fast path.
731 uint32_t fl_cidx __aligned(CACHE_LINE_SIZE);
733 bus_dma_tag_t iq_desc_tag;
734 bus_dmamap_t iq_desc_map;
738 bus_dma_tag_t fl_desc_tag;
739 bus_dmamap_t fl_desc_map;
743 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
745 struct tx_desc *desc;
749 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
750 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
751 uint16_t dbidx; /* pidx of the most recent doorbell */
753 volatile uint32_t *udb;
756 __be32 cpl_ctrl0; /* for convenience */
757 __be32 op_pkd; /* ditto */
758 u_int nid; /* netmap ring # for this queue */
760 /* infrequently used items after this */
762 bus_dma_tag_t desc_tag;
763 bus_dmamap_t desc_map;
766 } __aligned(CACHE_LINE_SIZE);
769 int nrxq; /* total # of Ethernet rx queues */
770 int ntxq; /* total # of Ethernet tx queues */
771 int nofldrxq; /* total # of TOE rx queues */
772 int nofldtxq; /* total # of TOE tx queues */
773 int nnmrxq; /* total # of netmap rx queues */
774 int nnmtxq; /* total # of netmap tx queues */
775 int niq; /* total # of ingress queues */
776 int neq; /* total # of egress queues */
778 struct sge_iq fwq; /* Firmware event queue */
779 struct sge_wrq *ctrlq; /* Control queues */
780 struct sge_txq *txq; /* NIC tx queues */
781 struct sge_rxq *rxq; /* NIC rx queues */
782 struct sge_wrq *ofld_txq; /* TOE tx queues */
783 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
784 struct sge_nm_txq *nm_txq; /* netmap tx queues */
785 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
787 uint16_t iq_start; /* first cntxt_id */
788 uint16_t iq_base; /* first abs_id */
789 int eq_start; /* first cntxt_id */
790 int eq_base; /* first abs_id */
791 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
792 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
795 struct rx_buf_info rx_buf_info[SW_ZONE_SIZES];
799 const char *nexus_name;
800 const char *ifnet_name;
801 const char *vi_ifnet_name;
802 const char *pf03_drv_name;
803 const char *vf_nexus_name;
804 const char *vf_ifnet_name;
810 SLIST_ENTRY(adapter) link;
813 const struct devnames *names;
815 /* PCIe register resources */
817 struct resource *regs_res;
819 struct resource *msix_res;
820 bus_space_handle_t bh;
824 struct resource *udbs_res;
825 volatile uint8_t *udbs_base;
829 unsigned int vpd_busy;
830 unsigned int vpd_flag;
832 /* Interrupt information */
836 struct resource *res;
840 struct sge_nm_rxq *nm_rxq;
841 } __aligned(CACHE_LINE_SIZE) *irq;
843 int sge_kdoorbell_reg;
845 bus_dma_tag_t dmat; /* Parent DMA tag */
851 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
852 struct task async_event_task;
853 struct port_info *port[MAX_NPORTS];
854 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
856 struct mtx clip_table_lock;
857 TAILQ_HEAD(, clip_entry) clip_table;
860 void *tom_softc; /* (struct tom_data *) */
861 struct tom_tunables tt;
862 struct t4_offload_policy *policy;
863 struct rwlock policy_lock;
865 void *iwarp_softc; /* (struct c4iw_dev *) */
866 struct iw_tunables iwt;
867 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
868 void *ccr_softc; /* (struct ccr_softc *) */
869 struct l2t_data *l2t; /* L2 table */
870 struct smt_data *smt; /* Source MAC Table */
871 struct tid_info tids;
873 struct tls_tunables tlst;
876 int offload_map; /* ports with IFCAP_TOE enabled */
877 int active_ulds; /* ULDs activated on this adapter */
881 char ifp_lockname[16];
883 struct ifnet *ifp; /* tracer ifp */
884 struct ifmedia media;
885 int traceq; /* iq used by all tracers, -1 if none */
886 int tracer_valid; /* bitmap of valid tracers */
887 int tracer_enabled; /* bitmap of enabled tracers */
895 struct adapter_params params;
896 const struct chip_params *chip_params;
897 struct t4_virt_res vres;
909 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
914 /* Starving free lists */
915 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
916 TAILQ_HEAD(, sge_fl) sfl;
917 struct callout sfl_callout;
919 struct mtx reg_lock; /* for indirect register access */
921 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
927 const void *last_op_thr;
933 struct callout ktls_tick;
936 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
937 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
938 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
939 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
941 #define ASSERT_SYNCHRONIZED_OP(sc) \
942 KASSERT(IS_BUSY(sc) && \
943 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
944 ("%s: operation not synchronized.", __func__))
946 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
947 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
948 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
949 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
951 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
952 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
953 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
954 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
955 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
957 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
958 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
959 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
960 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
962 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
963 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
964 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
965 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
966 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
968 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
969 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
970 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
971 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
972 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
974 #define for_each_txq(vi, iter, q) \
975 for (q = &vi->adapter->sge.txq[vi->first_txq], iter = 0; \
976 iter < vi->ntxq; ++iter, ++q)
977 #define for_each_rxq(vi, iter, q) \
978 for (q = &vi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
979 iter < vi->nrxq; ++iter, ++q)
980 #define for_each_ofld_txq(vi, iter, q) \
981 for (q = &vi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
982 iter < vi->nofldtxq; ++iter, ++q)
983 #define for_each_ofld_rxq(vi, iter, q) \
984 for (q = &vi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
985 iter < vi->nofldrxq; ++iter, ++q)
986 #define for_each_nm_txq(vi, iter, q) \
987 for (q = &vi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
988 iter < vi->nnmtxq; ++iter, ++q)
989 #define for_each_nm_rxq(vi, iter, q) \
990 for (q = &vi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
991 iter < vi->nnmrxq; ++iter, ++q)
992 #define for_each_vi(_pi, _iter, _vi) \
993 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
996 #define IDXINCR(idx, incr, wrap) do { \
997 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
999 #define IDXDIFF(head, tail, wrap) \
1000 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
1002 /* One for errors, one for firmware events */
1003 #define T4_EXTRA_INTR 2
1005 /* One for firmware events */
1006 #define T4VF_EXTRA_INTR 1
1009 forwarding_intr_to_fwq(struct adapter *sc)
1012 return (sc->intr_count == 1);
1015 static inline uint32_t
1016 t4_read_reg(struct adapter *sc, uint32_t reg)
1019 return bus_space_read_4(sc->bt, sc->bh, reg);
1023 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1026 bus_space_write_4(sc->bt, sc->bh, reg, val);
1029 static inline uint64_t
1030 t4_read_reg64(struct adapter *sc, uint32_t reg)
1034 return bus_space_read_8(sc->bt, sc->bh, reg);
1036 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1037 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1043 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1047 bus_space_write_8(sc->bt, sc->bh, reg, val);
1049 bus_space_write_4(sc->bt, sc->bh, reg, val);
1050 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1055 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1058 *val = pci_read_config(sc->dev, reg, 1);
1062 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1065 pci_write_config(sc->dev, reg, val, 1);
1069 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1072 *val = pci_read_config(sc->dev, reg, 2);
1076 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1079 pci_write_config(sc->dev, reg, val, 2);
1083 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1086 *val = pci_read_config(sc->dev, reg, 4);
1090 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1093 pci_write_config(sc->dev, reg, val, 4);
1096 static inline struct port_info *
1097 adap2pinfo(struct adapter *sc, int idx)
1100 return (sc->port[idx]);
1104 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1107 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1111 tx_resume_threshold(struct sge_eq *eq)
1114 /* not quite the same as qsize / 4, but this will do. */
1115 return (eq->sidx / 4);
1119 t4_use_ldst(struct adapter *sc)
1123 return (sc->flags & FW_OK || !sc->use_bd);
1130 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1131 const char *msg, const __be64 *const p, const bool err)
1134 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1137 log(err ? LOG_ERR : LOG_DEBUG,
1138 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1139 "%016llx %016llx %016llx %016llx\n",
1140 device_get_nameunit(sc->dev), mbox, msg,
1141 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1142 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1143 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1144 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1146 log(err ? LOG_ERR : LOG_DEBUG,
1147 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1148 "%016llx %016llx %016llx %016llx\n",
1149 device_get_nameunit(sc->dev), mbox, msg,
1150 (long long)t4_read_reg64(sc, reg),
1151 (long long)t4_read_reg64(sc, reg + 8),
1152 (long long)t4_read_reg64(sc, reg + 16),
1153 (long long)t4_read_reg64(sc, reg + 24),
1154 (long long)t4_read_reg64(sc, reg + 32),
1155 (long long)t4_read_reg64(sc, reg + 40),
1156 (long long)t4_read_reg64(sc, reg + 48),
1157 (long long)t4_read_reg64(sc, reg + 56));
1164 extern int t4_intr_types;
1165 extern int t4_tmr_idx;
1166 extern int t4_pktc_idx;
1167 extern unsigned int t4_qsize_rxq;
1168 extern unsigned int t4_qsize_txq;
1169 extern device_method_t cxgbe_methods[];
1171 int t4_os_find_pci_capability(struct adapter *, int);
1172 int t4_os_pci_save_state(struct adapter *);
1173 int t4_os_pci_restore_state(struct adapter *);
1174 void t4_os_portmod_changed(struct port_info *);
1175 void t4_os_link_changed(struct port_info *);
1176 void t4_iterate(void (*)(struct adapter *, void *), void *);
1177 void t4_init_devnames(struct adapter *);
1178 void t4_add_adapter(struct adapter *);
1179 int t4_detach_common(device_t);
1180 int t4_map_bars_0_and_4(struct adapter *);
1181 int t4_map_bar_2(struct adapter *);
1182 int t4_setup_intr_handlers(struct adapter *);
1183 void t4_sysctls(struct adapter *);
1184 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1185 void doom_vi(struct adapter *, struct vi_info *);
1186 void end_synchronized_op(struct adapter *, int);
1187 int update_mac_settings(struct ifnet *, int);
1188 int adapter_full_init(struct adapter *);
1189 int adapter_full_uninit(struct adapter *);
1190 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1191 void cxgbe_snd_tag_init(struct cxgbe_snd_tag *, struct ifnet *, int);
1192 int vi_full_init(struct vi_info *);
1193 int vi_full_uninit(struct vi_info *);
1194 void vi_sysctls(struct vi_info *);
1195 void vi_tick(void *);
1196 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1197 int alloc_atid(struct adapter *, void *);
1198 void *lookup_atid(struct adapter *, int);
1199 void free_atid(struct adapter *, int);
1200 void release_tid(struct adapter *, int, struct sge_wrq *);
1201 int cxgbe_media_change(struct ifnet *);
1202 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1203 bool t4_os_dump_cimla(struct adapter *, int, bool);
1204 void t4_os_dump_devlog(struct adapter *);
1208 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1209 struct m_snd_tag **);
1210 void cxgbe_tls_tag_free(struct m_snd_tag *);
1211 void t6_ktls_modload(void);
1212 void t6_ktls_modunload(void);
1213 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *);
1214 int t6_ktls_parse_pkt(struct mbuf *, int *, int *);
1215 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int);
1222 void t4_aes_getdeckey(void *, const void *, unsigned int);
1223 void t4_copy_partial_hash(int, union authctx *, void *);
1224 void t4_init_gmac_hash(const char *, int, char *);
1225 void t4_init_hmac_digest(struct auth_hash *, u_int, const char *, int, char *);
1230 void cxgbe_nm_attach(struct vi_info *);
1231 void cxgbe_nm_detach(struct vi_info *);
1232 void service_nm_rxq(struct sge_nm_rxq *);
1236 void t4_sge_modload(void);
1237 void t4_sge_modunload(void);
1238 uint64_t t4_sge_extfree_refs(void);
1239 void t4_tweak_chip_settings(struct adapter *);
1240 int t4_read_chip_settings(struct adapter *);
1241 int t4_create_dma_tag(struct adapter *);
1242 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1243 struct sysctl_oid_list *);
1244 int t4_destroy_dma_tag(struct adapter *);
1245 int t4_setup_adapter_queues(struct adapter *);
1246 int t4_teardown_adapter_queues(struct adapter *);
1247 int t4_setup_vi_queues(struct vi_info *);
1248 int t4_teardown_vi_queues(struct vi_info *);
1249 void t4_intr_all(void *);
1250 void t4_intr(void *);
1252 void t4_nm_intr(void *);
1253 void t4_vi_intr(void *);
1255 void t4_intr_err(void *);
1256 void t4_intr_evt(void *);
1257 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1258 void t4_update_fl_bufsize(struct ifnet *);
1259 struct mbuf *alloc_wr_mbuf(int, int);
1260 int parse_pkt(struct adapter *, struct mbuf **);
1261 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1262 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1263 int tnl_cong(struct port_info *, int);
1264 void t4_register_an_handler(an_handler_t);
1265 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1266 void t4_register_cpl_handler(int, cpl_handler_t);
1267 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1269 int ethofld_transmit(struct ifnet *, struct mbuf *);
1270 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1275 void t4_tracer_modload(void);
1276 void t4_tracer_modunload(void);
1277 void t4_tracer_port_detach(struct adapter *);
1278 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1279 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1280 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1281 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1284 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1285 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1286 int t4_init_tx_sched(struct adapter *);
1287 int t4_free_tx_sched(struct adapter *);
1288 void t4_update_tx_sched(struct adapter *);
1289 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1290 void t4_release_cl_rl(struct adapter *, int, int);
1291 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1292 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1294 void t4_init_etid_table(struct adapter *);
1295 void t4_free_etid_table(struct adapter *);
1296 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1297 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1298 struct m_snd_tag **);
1299 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1300 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1301 void cxgbe_rate_tag_free(struct m_snd_tag *);
1302 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1303 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *);
1307 int get_filter_mode(struct adapter *, uint32_t *);
1308 int set_filter_mode(struct adapter *, uint32_t);
1309 int get_filter(struct adapter *, struct t4_filter *);
1310 int set_filter(struct adapter *, struct t4_filter *);
1311 int del_filter(struct adapter *, struct t4_filter *);
1312 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1313 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1314 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1315 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1316 void free_hftid_hash(struct tid_info *);
1318 static inline struct wrqe *
1319 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1321 int len = offsetof(struct wrqe, wr) + wr_len;
1324 wr = malloc(len, M_CXGBE, M_NOWAIT);
1325 if (__predict_false(wr == NULL))
1327 wr->wr_len = wr_len;
1332 static inline void *
1333 wrtod(struct wrqe *wr)
1335 return (&wr->wr[0]);
1339 free_wrqe(struct wrqe *wr)
1345 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1347 struct sge_wrq *wrq = wr->wrq;
1350 t4_wrq_tx_locked(sc, wrq, wr);
1355 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1359 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1363 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1364 const uint32_t *val, int len)
1367 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
1370 /* Number of len16 -> number of descriptors */
1372 tx_len16_to_desc(int len16)
1375 return (howmany(len16, EQ_ESIZE / 16));