2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
38 #include <sys/counter.h>
40 #include <sys/types.h>
42 #include <sys/malloc.h>
43 #include <sys/rwlock.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <machine/bus.h>
51 #include <sys/socket.h>
52 #include <sys/sysctl.h>
53 #include <net/ethernet.h>
55 #include <net/if_var.h>
56 #include <net/if_media.h>
57 #include <netinet/in.h>
58 #include <netinet/tcp_lro.h>
62 #include "common/t4_msg.h"
63 #include "firmware/t4fw_interface.h"
65 #define KTR_CXGBE KTR_SPARE3
66 MALLOC_DECLARE(M_CXGBE);
67 #define CXGBE_UNIMPLEMENTED(s) \
68 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
70 #if defined(__i386__) || defined(__amd64__)
74 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
77 #define prefetch(x) __builtin_prefetch(x)
80 #ifndef SYSCTL_ADD_UQUAD
81 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
82 #define sysctl_handle_64 sysctl_handle_quad
83 #define CTLTYPE_U64 CTLTYPE_QUAD
86 SYSCTL_DECL(_hw_cxgbe);
89 typedef struct adapter adapter_t;
93 * All ingress queues use this entry size. Note that the firmware event
94 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
99 /* Default queue sizes for all kinds of ingress queues */
103 /* All egress queues use this entry size */
106 /* Default queue sizes for all kinds of egress queues */
107 CTRL_EQ_QSIZE = 1024,
110 #if MJUMPAGESIZE != MCLBYTES
111 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
113 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
115 CL_METADATA_SIZE = CACHE_LINE_SIZE,
117 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
119 TX_SGL_SEGS_TSO = 38,
120 TX_SGL_SEGS_EO_TSO = 30, /* XXX: lower for IPv6. */
121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
125 /* adapter intr_type */
126 INTR_INTX = (1 << 0),
132 XGMAC_MTU = (1 << 0),
133 XGMAC_PROMISC = (1 << 1),
134 XGMAC_ALLMULTI = (1 << 2),
135 XGMAC_VLANEX = (1 << 3),
136 XGMAC_UCADDR = (1 << 4),
137 XGMAC_MCADDRS = (1 << 5),
143 /* flags understood by begin_synchronized_op */
144 HOLD_LOCK = (1 << 0),
148 /* flags understood by end_synchronized_op */
149 LOCK_HELD = HOLD_LOCK,
154 FULL_INIT_DONE = (1 << 0),
156 CHK_MBOX_ACCESS = (1 << 2),
157 MASTER_PF = (1 << 3),
158 ADAP_SYSCTL_CTX = (1 << 4),
160 BUF_PACKING_OK = (1 << 6),
162 KERN_TLS_OK = (1 << 8),
164 CXGBE_BUSY = (1 << 9),
167 HAS_TRACEQ = (1 << 3),
168 FIXED_IFMEDIA = (1 << 4), /* ifmedia list doesn't change. */
172 VI_INIT_DONE = (1 << 1),
173 VI_SYSCTL_CTX = (1 << 2),
175 /* adapter debug_flags */
176 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
177 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
178 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
179 DF_DISABLE_CFG_RETRY = (1 << 3), /* Disable fallback config */
180 DF_VERBOSE_SLOWINTR = (1 << 4), /* Chatty slow intr handler */
183 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
184 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
185 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
186 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
187 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
191 struct port_info *pi;
198 uint16_t *rss, *nm_rss;
199 uint16_t viid; /* opaque VI identifier */
203 int16_t xact_addr_filt;/* index of exact MAC address filter */
204 uint16_t rss_size; /* size of VI's RSS table slice */
205 uint16_t rss_base; /* start of VI's RSS table slice */
211 /* These need to be int as they are used in sysctl */
212 int ntxq; /* # of tx queues */
213 int first_txq; /* index of first tx queue */
214 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
215 int nrxq; /* # of rx queues */
216 int first_rxq; /* index of first rx queue */
217 int nofldtxq; /* # of offload tx queues */
218 int first_ofld_txq; /* index of first offload tx queue */
219 int nofldrxq; /* # of offload rx queues */
220 int first_ofld_rxq; /* index of first offload rx queue */
232 struct timeval last_refreshed;
233 struct fw_vi_stats_vf stats;
236 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
238 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
241 struct tx_ch_rl_params {
242 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
247 CLRL_USER = (1 << 0), /* allocated manually. */
248 CLRL_SYNC = (1 << 1), /* sync hw update in progress. */
249 CLRL_ASYNC = (1 << 2), /* async hw update requested. */
250 CLRL_ERR = (1 << 3), /* last hw setup ended in error. */
253 struct tx_cl_rl_params {
256 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
257 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
258 enum fw_sched_params_mode mode; /* aggr or per-flow */
264 /* Tx scheduler parameters for a channel/port */
265 struct tx_sched_params {
266 /* Channel Rate Limiter */
267 struct tx_ch_rl_params ch_rl;
272 /* Class Rate Limiter (including the default pktsize and burstsize). */
275 struct tx_cl_rl_params cl_rl[];
280 struct adapter *adapter;
287 struct tx_sched_params *sched_params;
293 uint8_t lport; /* associated offload logical port */
299 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
300 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
302 struct link_config link_cfg;
303 struct ifmedia media;
305 struct timeval last_refreshed;
306 struct port_stats stats;
307 u_int tnl_cong_drops;
308 u_int tx_parse_error;
309 u_long tx_tls_records;
310 u_long tx_tls_octets;
311 u_long rx_tls_records;
312 u_long rx_tls_octets;
317 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
319 /* Where the cluster came from, how it has been carved up. */
320 struct cluster_layout {
323 uint16_t region1; /* mbufs laid out within this region */
324 /* region2 is the DMA region */
325 uint16_t region3; /* cluster_metadata within this region */
328 struct cluster_metadata {
330 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
335 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
336 struct cluster_layout cll;
344 struct mbuf *m; /* m_nextpkt linked chain of frames */
345 uint8_t desc_used; /* # of hardware descriptors used by the WR */
349 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
351 struct rss_header rss;
356 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
360 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
361 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
362 IQ_RX_TIMESTAMP = (1 << 2), /* provide the SGE rx timestamp */
363 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
364 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
371 /* netmap related flags */
378 CPL_COOKIE_RESERVED = 0,
383 CPL_COOKIE_HASHFILTER,
387 NUM_CPL_COOKIES = 8 /* Limited by M_COOKIE. Do not increase. */
392 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
394 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
395 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
398 * Ingress Queue: T4 is producer, driver is consumer.
403 struct adapter *adapter;
404 struct iq_desc *desc; /* KVA of descriptor ring */
405 int8_t intr_pktc_idx; /* packet count threshold index */
406 uint8_t gen; /* generation bit */
407 uint8_t intr_params; /* interrupt holdoff parameters */
408 uint8_t intr_next; /* XXX: holdoff for next interrupt */
409 uint16_t qsize; /* size (# of entries) of the queue */
410 uint16_t sidx; /* index of the entry with the status page */
411 uint16_t cidx; /* consumer index */
412 uint16_t cntxt_id; /* SGE context id for the iq */
413 uint16_t abs_id; /* absolute SGE id for the iq */
415 STAILQ_ENTRY(sge_iq) link;
417 bus_dma_tag_t desc_tag;
418 bus_dmamap_t desc_map;
419 bus_addr_t ba; /* bus address of descriptor ring */
428 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
429 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
430 EQ_ENABLED = (1 << 3), /* open for business */
431 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
434 /* Listed in order of preference. Update t4_sysctls too if you change these */
435 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
438 * Egress Queue: driver is producer, T4 is consumer.
440 * Note: A free list is an egress queue (driver produces the buffers and T4
441 * consumes them) but it's special enough to have its own struct (see sge_fl).
444 unsigned int flags; /* MUST be first */
445 unsigned int cntxt_id; /* SGE context id for the eq */
446 unsigned int abs_id; /* absolute SGE id for the eq */
449 struct tx_desc *desc; /* KVA of descriptor ring */
451 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
452 u_int udb_qid; /* relative qid within the doorbell page */
453 uint16_t sidx; /* index of the entry with the status page */
454 uint16_t cidx; /* consumer idx (desc idx) */
455 uint16_t pidx; /* producer idx (desc idx) */
456 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
457 uint16_t dbidx; /* pidx of the most recent doorbell */
458 uint16_t iqid; /* iq that gets egr_update for the eq */
459 uint8_t tx_chan; /* tx channel used by the eq */
460 volatile u_int equiq; /* EQUIQ outstanding */
462 bus_dma_tag_t desc_tag;
463 bus_dmamap_t desc_map;
464 bus_addr_t ba; /* bus address of descriptor ring */
468 struct sw_zone_info {
469 uma_zone_t zone; /* zone that this cluster comes from */
470 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
471 int type; /* EXT_xxx type of the cluster */
477 int8_t zidx; /* backpointer to zone; -ve means unused */
478 int8_t next; /* next hwidx for this zone; -1 means no more */
485 MEMWIN0_APERTURE = 2048,
486 MEMWIN0_BASE = 0x1b800,
488 MEMWIN1_APERTURE = 32768,
489 MEMWIN1_BASE = 0x28000,
491 MEMWIN2_APERTURE_T4 = 65536,
492 MEMWIN2_BASE_T4 = 0x30000,
494 MEMWIN2_APERTURE_T5 = 128 * 1024,
495 MEMWIN2_BASE_T5 = 0x60000,
499 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
500 uint32_t mw_base; /* constant after setup_memwin */
501 uint32_t mw_aperture; /* ditto */
502 uint32_t mw_curpos; /* protected by mw_lock */
506 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
507 FL_DOOMED = (1 << 1), /* about to be destroyed */
508 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
509 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
512 #define FL_RUNNING_LOW(fl) \
513 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
514 #define FL_NOT_RUNNING_LOW(fl) \
515 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
519 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
520 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
521 struct cluster_layout cll_def; /* default refill zone, layout */
522 uint16_t lowat; /* # of buffers <= this means fl needs help */
524 uint16_t buf_boundary;
526 /* The 16b idx all deal with hw descriptors */
527 uint16_t dbidx; /* hw pidx after last doorbell */
528 uint16_t sidx; /* index of status page */
529 volatile uint16_t hw_cidx;
531 /* The 32b idx are all buffer idx, not hardware descriptor idx */
532 uint32_t cidx; /* consumer index */
533 uint32_t pidx; /* producer index */
536 u_int rx_offset; /* offset in fl buf (when buffer packing) */
537 volatile uint32_t *udb;
539 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
540 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
541 uint64_t cl_allocated; /* # of clusters allocated */
542 uint64_t cl_recycled; /* # of clusters recycled */
543 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
545 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
550 uint16_t qsize; /* # of hw descriptors (status page included) */
551 uint16_t cntxt_id; /* SGE context id for the freelist */
552 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
553 bus_dma_tag_t desc_tag;
554 bus_dmamap_t desc_map;
556 bus_addr_t ba; /* bus address of descriptor ring */
557 struct cluster_layout cll_alt; /* alternate refill zone, layout */
562 /* txq: SGE egress queue + what's needed for Ethernet NIC */
564 struct sge_eq eq; /* MUST be first */
566 struct ifnet *ifp; /* the interface this txq belongs to */
567 struct mp_ring *r; /* tx software ring */
568 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
570 __be32 cpl_ctrl0; /* for convenience */
571 int tc_idx; /* traffic class */
573 struct task tx_reclaim_task;
574 /* stats for common events first */
576 uint64_t txcsum; /* # of times hardware assisted with checksum */
577 uint64_t tso_wrs; /* # of TSO work requests */
578 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
579 uint64_t imm_wrs; /* # of work requests with immediate data */
580 uint64_t sgl_wrs; /* # of work requests with direct SGL */
581 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
582 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
583 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
584 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
585 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
586 uint64_t raw_wrs; /* # of raw work requests (alloc_wr_mbuf) */
587 uint64_t tls_wrs; /* # of TLS work requests */
589 uint64_t kern_tls_records;
590 uint64_t kern_tls_short;
591 uint64_t kern_tls_partial;
592 uint64_t kern_tls_full;
593 uint64_t kern_tls_octets;
594 uint64_t kern_tls_waste;
595 uint64_t kern_tls_options;
596 uint64_t kern_tls_header;
597 uint64_t kern_tls_fin;
598 uint64_t kern_tls_fin_short;
599 uint64_t kern_tls_cbc;
600 uint64_t kern_tls_gcm;
602 /* stats for not-that-common events */
604 /* Optional scratch space for constructing work requests. */
605 uint8_t ss[SGE_MAX_WR_LEN] __aligned(16);
606 } __aligned(CACHE_LINE_SIZE);
608 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
610 struct sge_iq iq; /* MUST be first */
611 struct sge_fl fl; /* MUST follow iq */
613 struct ifnet *ifp; /* the interface this rxq belongs to */
614 #if defined(INET) || defined(INET6)
615 struct lro_ctrl lro; /* LRO state */
618 /* stats for common events first */
620 uint64_t rxcsum; /* # of times hardware assisted with checksum */
621 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
623 /* stats for not-that-common events */
625 } __aligned(CACHE_LINE_SIZE);
627 static inline struct sge_rxq *
628 iq_to_rxq(struct sge_iq *iq)
631 return (__containerof(iq, struct sge_rxq, iq));
635 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
636 struct sge_ofld_rxq {
637 struct sge_iq iq; /* MUST be first */
638 struct sge_fl fl; /* MUST follow iq */
639 } __aligned(CACHE_LINE_SIZE);
641 static inline struct sge_ofld_rxq *
642 iq_to_ofld_rxq(struct sge_iq *iq)
645 return (__containerof(iq, struct sge_ofld_rxq, iq));
649 STAILQ_ENTRY(wrqe) link;
652 char wr[] __aligned(16);
656 TAILQ_ENTRY(wrq_cookie) link;
662 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
663 * and offload tx queues are of this type.
666 struct sge_eq eq; /* MUST be first */
668 struct adapter *adapter;
669 struct task wrq_tx_task;
671 /* Tx desc reserved but WR not "committed" yet. */
672 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
674 /* List of WRs ready to go out as soon as descriptors are available. */
675 STAILQ_HEAD(, wrqe) wr_list;
679 /* stats for common events first */
681 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
682 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
683 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
685 /* stats for not-that-common events */
688 * Scratch space for work requests that wrap around after reaching the
689 * status page, and some information about the last WR that used it.
693 uint8_t ss[SGE_MAX_WR_LEN];
695 } __aligned(CACHE_LINE_SIZE);
697 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
699 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
702 struct iq_desc *iq_desc;
704 uint16_t iq_cntxt_id;
710 uint16_t fl_cntxt_id;
718 u_int nid; /* netmap ring # for this queue */
720 /* infrequently used items after this */
722 bus_dma_tag_t iq_desc_tag;
723 bus_dmamap_t iq_desc_map;
727 bus_dma_tag_t fl_desc_tag;
728 bus_dmamap_t fl_desc_map;
730 } __aligned(CACHE_LINE_SIZE);
732 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
734 struct tx_desc *desc;
738 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
739 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
740 uint16_t dbidx; /* pidx of the most recent doorbell */
742 volatile uint32_t *udb;
745 __be32 cpl_ctrl0; /* for convenience */
746 __be32 op_pkd; /* ditto */
747 u_int nid; /* netmap ring # for this queue */
749 /* infrequently used items after this */
751 bus_dma_tag_t desc_tag;
752 bus_dmamap_t desc_map;
755 } __aligned(CACHE_LINE_SIZE);
758 int nrxq; /* total # of Ethernet rx queues */
759 int ntxq; /* total # of Ethernet tx queues */
760 int nofldrxq; /* total # of TOE rx queues */
761 int nofldtxq; /* total # of TOE tx queues */
762 int nnmrxq; /* total # of netmap rx queues */
763 int nnmtxq; /* total # of netmap tx queues */
764 int niq; /* total # of ingress queues */
765 int neq; /* total # of egress queues */
767 struct sge_iq fwq; /* Firmware event queue */
768 struct sge_wrq *ctrlq; /* Control queues */
769 struct sge_txq *txq; /* NIC tx queues */
770 struct sge_rxq *rxq; /* NIC rx queues */
771 struct sge_wrq *ofld_txq; /* TOE tx queues */
772 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
773 struct sge_nm_txq *nm_txq; /* netmap tx queues */
774 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
776 uint16_t iq_start; /* first cntxt_id */
777 uint16_t iq_base; /* first abs_id */
778 int eq_start; /* first cntxt_id */
779 int eq_base; /* first abs_id */
780 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
781 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
783 int8_t safe_hwidx1; /* may not have room for metadata */
784 int8_t safe_hwidx2; /* with room for metadata and maybe more */
785 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
786 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
790 const char *nexus_name;
791 const char *ifnet_name;
792 const char *vi_ifnet_name;
793 const char *pf03_drv_name;
794 const char *vf_nexus_name;
795 const char *vf_ifnet_name;
801 SLIST_ENTRY(adapter) link;
804 const struct devnames *names;
806 /* PCIe register resources */
808 struct resource *regs_res;
810 struct resource *msix_res;
811 bus_space_handle_t bh;
815 struct resource *udbs_res;
816 volatile uint8_t *udbs_base;
820 unsigned int vpd_busy;
821 unsigned int vpd_flag;
823 /* Interrupt information */
827 struct resource *res;
831 struct sge_nm_rxq *nm_rxq;
832 } __aligned(CACHE_LINE_SIZE) *irq;
834 int sge_kdoorbell_reg;
836 bus_dma_tag_t dmat; /* Parent DMA tag */
842 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
843 struct port_info *port[MAX_NPORTS];
844 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
846 struct mtx clip_table_lock;
847 TAILQ_HEAD(, clip_entry) clip_table;
850 void *tom_softc; /* (struct tom_data *) */
851 struct tom_tunables tt;
852 struct t4_offload_policy *policy;
853 struct rwlock policy_lock;
855 void *iwarp_softc; /* (struct c4iw_dev *) */
856 struct iw_tunables iwt;
857 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
858 void *ccr_softc; /* (struct ccr_softc *) */
859 struct l2t_data *l2t; /* L2 table */
860 struct smt_data *smt; /* Source MAC Table */
861 struct tid_info tids;
863 struct tls_tunables tlst;
866 int offload_map; /* ports with IFCAP_TOE enabled */
867 int active_ulds; /* ULDs activated on this adapter */
871 char ifp_lockname[16];
873 struct ifnet *ifp; /* tracer ifp */
874 struct ifmedia media;
875 int traceq; /* iq used by all tracers, -1 if none */
876 int tracer_valid; /* bitmap of valid tracers */
877 int tracer_enabled; /* bitmap of enabled tracers */
885 struct adapter_params params;
886 const struct chip_params *chip_params;
887 struct t4_virt_res vres;
899 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
904 /* Starving free lists */
905 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
906 TAILQ_HEAD(, sge_fl) sfl;
907 struct callout sfl_callout;
909 struct mtx reg_lock; /* for indirect register access */
911 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
917 const void *last_op_thr;
923 struct callout ktls_tick;
926 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
927 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
928 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
929 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
931 #define ASSERT_SYNCHRONIZED_OP(sc) \
932 KASSERT(IS_BUSY(sc) && \
933 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
934 ("%s: operation not synchronized.", __func__))
936 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
937 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
938 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
939 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
941 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
942 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
943 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
944 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
945 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
947 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
948 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
949 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
950 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
952 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
953 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
954 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
955 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
956 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
958 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
959 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
960 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
961 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
962 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
964 #define for_each_txq(vi, iter, q) \
965 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
966 iter < vi->ntxq; ++iter, ++q)
967 #define for_each_rxq(vi, iter, q) \
968 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
969 iter < vi->nrxq; ++iter, ++q)
970 #define for_each_ofld_txq(vi, iter, q) \
971 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
972 iter < vi->nofldtxq; ++iter, ++q)
973 #define for_each_ofld_rxq(vi, iter, q) \
974 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
975 iter < vi->nofldrxq; ++iter, ++q)
976 #define for_each_nm_txq(vi, iter, q) \
977 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
978 iter < vi->nnmtxq; ++iter, ++q)
979 #define for_each_nm_rxq(vi, iter, q) \
980 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
981 iter < vi->nnmrxq; ++iter, ++q)
982 #define for_each_vi(_pi, _iter, _vi) \
983 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
986 #define IDXINCR(idx, incr, wrap) do { \
987 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
989 #define IDXDIFF(head, tail, wrap) \
990 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
992 /* One for errors, one for firmware events */
993 #define T4_EXTRA_INTR 2
995 /* One for firmware events */
996 #define T4VF_EXTRA_INTR 1
999 forwarding_intr_to_fwq(struct adapter *sc)
1002 return (sc->intr_count == 1);
1005 static inline uint32_t
1006 t4_read_reg(struct adapter *sc, uint32_t reg)
1009 return bus_space_read_4(sc->bt, sc->bh, reg);
1013 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
1016 bus_space_write_4(sc->bt, sc->bh, reg, val);
1019 static inline uint64_t
1020 t4_read_reg64(struct adapter *sc, uint32_t reg)
1024 return bus_space_read_8(sc->bt, sc->bh, reg);
1026 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
1027 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
1033 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
1037 bus_space_write_8(sc->bt, sc->bh, reg, val);
1039 bus_space_write_4(sc->bt, sc->bh, reg, val);
1040 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
1045 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1048 *val = pci_read_config(sc->dev, reg, 1);
1052 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1055 pci_write_config(sc->dev, reg, val, 1);
1059 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1062 *val = pci_read_config(sc->dev, reg, 2);
1066 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1069 pci_write_config(sc->dev, reg, val, 2);
1073 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1076 *val = pci_read_config(sc->dev, reg, 4);
1080 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1083 pci_write_config(sc->dev, reg, val, 4);
1086 static inline struct port_info *
1087 adap2pinfo(struct adapter *sc, int idx)
1090 return (sc->port[idx]);
1094 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1097 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1101 tx_resume_threshold(struct sge_eq *eq)
1104 /* not quite the same as qsize / 4, but this will do. */
1105 return (eq->sidx / 4);
1109 t4_use_ldst(struct adapter *sc)
1113 return (sc->flags & FW_OK || !sc->use_bd);
1120 CH_DUMP_MBOX(struct adapter *sc, int mbox, const int reg,
1121 const char *msg, const __be64 *const p, const bool err)
1124 if (!(sc->debug_flags & DF_DUMP_MBOX) && !err)
1127 log(err ? LOG_ERR : LOG_DEBUG,
1128 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1129 "%016llx %016llx %016llx %016llx\n",
1130 device_get_nameunit(sc->dev), mbox, msg,
1131 (long long)be64_to_cpu(p[0]), (long long)be64_to_cpu(p[1]),
1132 (long long)be64_to_cpu(p[2]), (long long)be64_to_cpu(p[3]),
1133 (long long)be64_to_cpu(p[4]), (long long)be64_to_cpu(p[5]),
1134 (long long)be64_to_cpu(p[6]), (long long)be64_to_cpu(p[7]));
1136 log(err ? LOG_ERR : LOG_DEBUG,
1137 "%s: mbox %u %s %016llx %016llx %016llx %016llx "
1138 "%016llx %016llx %016llx %016llx\n",
1139 device_get_nameunit(sc->dev), mbox, msg,
1140 (long long)t4_read_reg64(sc, reg),
1141 (long long)t4_read_reg64(sc, reg + 8),
1142 (long long)t4_read_reg64(sc, reg + 16),
1143 (long long)t4_read_reg64(sc, reg + 24),
1144 (long long)t4_read_reg64(sc, reg + 32),
1145 (long long)t4_read_reg64(sc, reg + 40),
1146 (long long)t4_read_reg64(sc, reg + 48),
1147 (long long)t4_read_reg64(sc, reg + 56));
1154 extern int t4_intr_types;
1155 extern int t4_tmr_idx;
1156 extern int t4_pktc_idx;
1157 extern unsigned int t4_qsize_rxq;
1158 extern unsigned int t4_qsize_txq;
1159 extern device_method_t cxgbe_methods[];
1161 int t4_os_find_pci_capability(struct adapter *, int);
1162 int t4_os_pci_save_state(struct adapter *);
1163 int t4_os_pci_restore_state(struct adapter *);
1164 void t4_os_portmod_changed(struct port_info *);
1165 void t4_os_link_changed(struct port_info *);
1166 void t4_iterate(void (*)(struct adapter *, void *), void *);
1167 void t4_init_devnames(struct adapter *);
1168 void t4_add_adapter(struct adapter *);
1169 int t4_detach_common(device_t);
1170 int t4_map_bars_0_and_4(struct adapter *);
1171 int t4_map_bar_2(struct adapter *);
1172 int t4_setup_intr_handlers(struct adapter *);
1173 void t4_sysctls(struct adapter *);
1174 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1175 void doom_vi(struct adapter *, struct vi_info *);
1176 void end_synchronized_op(struct adapter *, int);
1177 int update_mac_settings(struct ifnet *, int);
1178 int adapter_full_init(struct adapter *);
1179 int adapter_full_uninit(struct adapter *);
1180 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1181 void cxgbe_snd_tag_init(struct cxgbe_snd_tag *, struct ifnet *, int);
1182 int vi_full_init(struct vi_info *);
1183 int vi_full_uninit(struct vi_info *);
1184 void vi_sysctls(struct vi_info *);
1185 void vi_tick(void *);
1186 int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
1187 int alloc_atid(struct adapter *, void *);
1188 void *lookup_atid(struct adapter *, int);
1189 void free_atid(struct adapter *, int);
1190 void release_tid(struct adapter *, int, struct sge_wrq *);
1191 int cxgbe_media_change(struct ifnet *);
1192 void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
1193 bool t4_os_dump_cimla(struct adapter *, int, bool);
1194 void t4_os_dump_devlog(struct adapter *);
1198 int cxgbe_tls_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1199 struct m_snd_tag **);
1200 void cxgbe_tls_tag_free(struct m_snd_tag *);
1201 void t6_ktls_modload(void);
1202 void t6_ktls_modunload(void);
1203 int t6_ktls_try(struct ifnet *, struct socket *, struct ktls_session *);
1204 int t6_ktls_parse_pkt(struct mbuf *, int *, int *);
1205 int t6_ktls_write_wr(struct sge_txq *, void *, struct mbuf *, u_int, u_int);
1212 void t4_aes_getdeckey(void *, const void *, unsigned int);
1213 void t4_copy_partial_hash(int, union authctx *, void *);
1214 void t4_init_gmac_hash(const char *, int, char *);
1215 void t4_init_hmac_digest(struct auth_hash *, u_int, char *, int, char *);
1220 void cxgbe_nm_attach(struct vi_info *);
1221 void cxgbe_nm_detach(struct vi_info *);
1222 void service_nm_rxq(struct sge_nm_rxq *);
1226 void t4_sge_modload(void);
1227 void t4_sge_modunload(void);
1228 uint64_t t4_sge_extfree_refs(void);
1229 void t4_tweak_chip_settings(struct adapter *);
1230 int t4_read_chip_settings(struct adapter *);
1231 int t4_create_dma_tag(struct adapter *);
1232 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1233 struct sysctl_oid_list *);
1234 int t4_destroy_dma_tag(struct adapter *);
1235 int t4_setup_adapter_queues(struct adapter *);
1236 int t4_teardown_adapter_queues(struct adapter *);
1237 int t4_setup_vi_queues(struct vi_info *);
1238 int t4_teardown_vi_queues(struct vi_info *);
1239 void t4_intr_all(void *);
1240 void t4_intr(void *);
1242 void t4_nm_intr(void *);
1243 void t4_vi_intr(void *);
1245 void t4_intr_err(void *);
1246 void t4_intr_evt(void *);
1247 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1248 void t4_update_fl_bufsize(struct ifnet *);
1249 struct mbuf *alloc_wr_mbuf(int, int);
1250 int parse_pkt(struct adapter *, struct mbuf **);
1251 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1252 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1253 int tnl_cong(struct port_info *, int);
1254 void t4_register_an_handler(an_handler_t);
1255 void t4_register_fw_msg_handler(int, fw_msg_handler_t);
1256 void t4_register_cpl_handler(int, cpl_handler_t);
1257 void t4_register_shared_cpl_handler(int, cpl_handler_t, int);
1259 int ethofld_transmit(struct ifnet *, struct mbuf *);
1260 void send_etid_flush_wr(struct cxgbe_rate_tag *);
1265 void t4_tracer_modload(void);
1266 void t4_tracer_modunload(void);
1267 void t4_tracer_port_detach(struct adapter *);
1268 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1269 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1270 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1271 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1274 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1275 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1276 int t4_init_tx_sched(struct adapter *);
1277 int t4_free_tx_sched(struct adapter *);
1278 void t4_update_tx_sched(struct adapter *);
1279 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1280 void t4_release_cl_rl(struct adapter *, int, int);
1281 int sysctl_tc(SYSCTL_HANDLER_ARGS);
1282 int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
1284 void t4_init_etid_table(struct adapter *);
1285 void t4_free_etid_table(struct adapter *);
1286 struct cxgbe_rate_tag *lookup_etid(struct adapter *, int);
1287 int cxgbe_rate_tag_alloc(struct ifnet *, union if_snd_tag_alloc_params *,
1288 struct m_snd_tag **);
1289 int cxgbe_rate_tag_modify(struct m_snd_tag *, union if_snd_tag_modify_params *);
1290 int cxgbe_rate_tag_query(struct m_snd_tag *, union if_snd_tag_query_params *);
1291 void cxgbe_rate_tag_free(struct m_snd_tag *);
1292 void cxgbe_rate_tag_free_locked(struct cxgbe_rate_tag *);
1293 void cxgbe_ratelimit_query(struct ifnet *, struct if_ratelimit_query_results *);
1297 int get_filter_mode(struct adapter *, uint32_t *);
1298 int set_filter_mode(struct adapter *, uint32_t);
1299 int get_filter(struct adapter *, struct t4_filter *);
1300 int set_filter(struct adapter *, struct t4_filter *);
1301 int del_filter(struct adapter *, struct t4_filter *);
1302 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1303 int t4_hashfilter_ao_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1304 int t4_hashfilter_tcb_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1305 int t4_del_hashfilter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1306 void free_hftid_hash(struct tid_info *);
1308 static inline struct wrqe *
1309 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1311 int len = offsetof(struct wrqe, wr) + wr_len;
1314 wr = malloc(len, M_CXGBE, M_NOWAIT);
1315 if (__predict_false(wr == NULL))
1317 wr->wr_len = wr_len;
1322 static inline void *
1323 wrtod(struct wrqe *wr)
1325 return (&wr->wr[0]);
1329 free_wrqe(struct wrqe *wr)
1335 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1337 struct sge_wrq *wrq = wr->wrq;
1340 t4_wrq_tx_locked(sc, wrq, wr);
1345 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1349 return (rw_via_memwin(sc, idx, addr, val, len, 0));
1353 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
1354 const uint32_t *val, int len)
1357 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));