2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
58 #include "common/t4_msg.h"
59 #include "firmware/t4fw_interface.h"
61 #define KTR_CXGBE KTR_SPARE3
62 MALLOC_DECLARE(M_CXGBE);
63 #define CXGBE_UNIMPLEMENTED(s) \
64 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
66 #if defined(__i386__) || defined(__amd64__)
70 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
76 #ifndef SYSCTL_ADD_UQUAD
77 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
78 #define sysctl_handle_64 sysctl_handle_quad
79 #define CTLTYPE_U64 CTLTYPE_QUAD
82 #if (__FreeBSD_version >= 900030) || \
83 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
88 typedef struct adapter adapter_t;
92 * All ingress queues use this entry size. Note that the firmware event
93 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
98 /* Default queue sizes for all kinds of ingress queues */
102 /* All egress queues use this entry size */
105 /* Default queue sizes for all kinds of egress queues */
109 #if MJUMPAGESIZE != MCLBYTES
110 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
112 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
114 CL_METADATA_SIZE = CACHE_LINE_SIZE,
116 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
118 TX_SGL_SEGS_TSO = 38,
119 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
123 /* adapter intr_type */
124 INTR_INTX = (1 << 0),
130 XGMAC_MTU = (1 << 0),
131 XGMAC_PROMISC = (1 << 1),
132 XGMAC_ALLMULTI = (1 << 2),
133 XGMAC_VLANEX = (1 << 3),
134 XGMAC_UCADDR = (1 << 4),
135 XGMAC_MCADDRS = (1 << 5),
141 /* flags understood by begin_synchronized_op */
142 HOLD_LOCK = (1 << 0),
146 /* flags understood by end_synchronized_op */
147 LOCK_HELD = HOLD_LOCK,
152 FULL_INIT_DONE = (1 << 0),
154 /* INTR_DIRECT = (1 << 2), No longer used. */
155 MASTER_PF = (1 << 3),
156 ADAP_SYSCTL_CTX = (1 << 4),
157 /* TOM_INIT_DONE= (1 << 5), No longer used */
158 BUF_PACKING_OK = (1 << 6),
161 CXGBE_BUSY = (1 << 9),
164 HAS_TRACEQ = (1 << 3),
168 VI_INIT_DONE = (1 << 1),
169 VI_SYSCTL_CTX = (1 << 2),
170 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
171 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
172 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
174 /* adapter debug_flags */
175 DF_DUMP_MBOX = (1 << 0),
178 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
179 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
180 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
181 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
182 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
186 struct port_info *pi;
189 struct ifmedia media;
194 uint16_t *rss, *nm_rss;
195 int smt_idx; /* for convenience */
197 int16_t xact_addr_filt;/* index of exact MAC address filter */
198 uint16_t rss_size; /* size of VI's RSS table slice */
199 uint16_t rss_base; /* start of VI's RSS table slice */
201 eventhandler_tag vlan_c;
206 /* These need to be int as they are used in sysctl */
207 int ntxq; /* # of tx queues */
208 int first_txq; /* index of first tx queue */
209 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
210 int nrxq; /* # of rx queues */
211 int first_rxq; /* index of first rx queue */
212 int nofldtxq; /* # of offload tx queues */
213 int first_ofld_txq; /* index of first offload tx queue */
214 int nofldrxq; /* # of offload rx queues */
215 int first_ofld_rxq; /* index of first offload rx queue */
225 struct timeval last_refreshed;
226 struct fw_vi_stats_vf stats;
229 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
231 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
235 /* tx_sched_class flags */
236 TX_SC_OK = (1 << 0), /* Set up in hardware, active. */
239 struct tx_sched_class {
242 struct t4_sched_class_params params;
247 struct adapter *adapter;
254 struct tx_sched_class *tc; /* traffic classes for this channel */
260 uint8_t lport; /* associated offload logical port */
266 uint8_t rx_chan_map; /* rx MPS channel bitmap */
268 struct link_config link_cfg;
270 struct timeval last_refreshed;
271 struct port_stats stats;
272 u_int tnl_cong_drops;
273 u_int tx_parse_error;
278 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
280 /* Where the cluster came from, how it has been carved up. */
281 struct cluster_layout {
284 uint16_t region1; /* mbufs laid out within this region */
285 /* region2 is the DMA region */
286 uint16_t region3; /* cluster_metadata within this region */
289 struct cluster_metadata {
291 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
296 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
297 struct cluster_layout cll;
305 struct mbuf *m; /* m_nextpkt linked chain of frames */
306 uint8_t desc_used; /* # of hardware descriptors used by the WR */
310 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
312 struct rss_header rss;
317 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
321 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
322 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
323 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
324 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
325 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
332 /* netmap related flags */
340 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
342 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
343 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
346 * Ingress Queue: T4 is producer, driver is consumer.
351 struct adapter *adapter;
352 cpl_handler_t set_tcb_rpl;
353 cpl_handler_t l2t_write_rpl;
354 struct iq_desc *desc; /* KVA of descriptor ring */
355 int8_t intr_pktc_idx; /* packet count threshold index */
356 uint8_t gen; /* generation bit */
357 uint8_t intr_params; /* interrupt holdoff parameters */
358 uint8_t intr_next; /* XXX: holdoff for next interrupt */
359 uint16_t qsize; /* size (# of entries) of the queue */
360 uint16_t sidx; /* index of the entry with the status page */
361 uint16_t cidx; /* consumer index */
362 uint16_t cntxt_id; /* SGE context id for the iq */
363 uint16_t abs_id; /* absolute SGE id for the iq */
365 STAILQ_ENTRY(sge_iq) link;
367 bus_dma_tag_t desc_tag;
368 bus_dmamap_t desc_map;
369 bus_addr_t ba; /* bus address of descriptor ring */
378 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
379 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
380 EQ_ENABLED = (1 << 3), /* open for business */
383 /* Listed in order of preference. Update t4_sysctls too if you change these */
384 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
387 * Egress Queue: driver is producer, T4 is consumer.
389 * Note: A free list is an egress queue (driver produces the buffers and T4
390 * consumes them) but it's special enough to have its own struct (see sge_fl).
393 unsigned int flags; /* MUST be first */
394 unsigned int cntxt_id; /* SGE context id for the eq */
395 unsigned int abs_id; /* absolute SGE id for the eq */
398 struct tx_desc *desc; /* KVA of descriptor ring */
400 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
401 u_int udb_qid; /* relative qid within the doorbell page */
402 uint16_t sidx; /* index of the entry with the status page */
403 uint16_t cidx; /* consumer idx (desc idx) */
404 uint16_t pidx; /* producer idx (desc idx) */
405 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
406 uint16_t dbidx; /* pidx of the most recent doorbell */
407 uint16_t iqid; /* iq that gets egr_update for the eq */
408 uint8_t tx_chan; /* tx channel used by the eq */
409 volatile u_int equiq; /* EQUIQ outstanding */
411 bus_dma_tag_t desc_tag;
412 bus_dmamap_t desc_map;
413 bus_addr_t ba; /* bus address of descriptor ring */
417 struct sw_zone_info {
418 uma_zone_t zone; /* zone that this cluster comes from */
419 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
420 int type; /* EXT_xxx type of the cluster */
426 int8_t zidx; /* backpointer to zone; -ve means unused */
427 int8_t next; /* next hwidx for this zone; -1 means no more */
434 MEMWIN0_APERTURE = 2048,
435 MEMWIN0_BASE = 0x1b800,
437 MEMWIN1_APERTURE = 32768,
438 MEMWIN1_BASE = 0x28000,
440 MEMWIN2_APERTURE_T4 = 65536,
441 MEMWIN2_BASE_T4 = 0x30000,
443 MEMWIN2_APERTURE_T5 = 128 * 1024,
444 MEMWIN2_BASE_T5 = 0x60000,
448 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
449 uint32_t mw_base; /* constant after setup_memwin */
450 uint32_t mw_aperture; /* ditto */
451 uint32_t mw_curpos; /* protected by mw_lock */
455 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
456 FL_DOOMED = (1 << 1), /* about to be destroyed */
457 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
458 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
461 #define FL_RUNNING_LOW(fl) \
462 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
463 #define FL_NOT_RUNNING_LOW(fl) \
464 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
468 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
469 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
470 struct cluster_layout cll_def; /* default refill zone, layout */
471 uint16_t lowat; /* # of buffers <= this means fl needs help */
473 uint16_t buf_boundary;
475 /* The 16b idx all deal with hw descriptors */
476 uint16_t dbidx; /* hw pidx after last doorbell */
477 uint16_t sidx; /* index of status page */
478 volatile uint16_t hw_cidx;
480 /* The 32b idx are all buffer idx, not hardware descriptor idx */
481 uint32_t cidx; /* consumer index */
482 uint32_t pidx; /* producer index */
485 u_int rx_offset; /* offset in fl buf (when buffer packing) */
486 volatile uint32_t *udb;
488 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
489 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
490 uint64_t cl_allocated; /* # of clusters allocated */
491 uint64_t cl_recycled; /* # of clusters recycled */
492 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
494 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
499 uint16_t qsize; /* # of hw descriptors (status page included) */
500 uint16_t cntxt_id; /* SGE context id for the freelist */
501 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
502 bus_dma_tag_t desc_tag;
503 bus_dmamap_t desc_map;
505 bus_addr_t ba; /* bus address of descriptor ring */
506 struct cluster_layout cll_alt; /* alternate refill zone, layout */
511 /* txq: SGE egress queue + what's needed for Ethernet NIC */
513 struct sge_eq eq; /* MUST be first */
515 struct ifnet *ifp; /* the interface this txq belongs to */
516 struct mp_ring *r; /* tx software ring */
517 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
519 __be32 cpl_ctrl0; /* for convenience */
520 int tc_idx; /* traffic class */
522 struct task tx_reclaim_task;
523 /* stats for common events first */
525 uint64_t txcsum; /* # of times hardware assisted with checksum */
526 uint64_t tso_wrs; /* # of TSO work requests */
527 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
528 uint64_t imm_wrs; /* # of work requests with immediate data */
529 uint64_t sgl_wrs; /* # of work requests with direct SGL */
530 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
531 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
532 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
533 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
534 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
536 /* stats for not-that-common events */
537 } __aligned(CACHE_LINE_SIZE);
539 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
541 struct sge_iq iq; /* MUST be first */
542 struct sge_fl fl; /* MUST follow iq */
544 struct ifnet *ifp; /* the interface this rxq belongs to */
545 #if defined(INET) || defined(INET6)
546 struct lro_ctrl lro; /* LRO state */
549 /* stats for common events first */
551 uint64_t rxcsum; /* # of times hardware assisted with checksum */
552 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
554 /* stats for not-that-common events */
556 } __aligned(CACHE_LINE_SIZE);
558 static inline struct sge_rxq *
559 iq_to_rxq(struct sge_iq *iq)
562 return (__containerof(iq, struct sge_rxq, iq));
566 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
567 struct sge_ofld_rxq {
568 struct sge_iq iq; /* MUST be first */
569 struct sge_fl fl; /* MUST follow iq */
570 } __aligned(CACHE_LINE_SIZE);
572 static inline struct sge_ofld_rxq *
573 iq_to_ofld_rxq(struct sge_iq *iq)
576 return (__containerof(iq, struct sge_ofld_rxq, iq));
580 STAILQ_ENTRY(wrqe) link;
583 char wr[] __aligned(16);
587 TAILQ_ENTRY(wrq_cookie) link;
593 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
594 * and offload tx queues are of this type.
597 struct sge_eq eq; /* MUST be first */
599 struct adapter *adapter;
600 struct task wrq_tx_task;
602 /* Tx desc reserved but WR not "committed" yet. */
603 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
605 /* List of WRs ready to go out as soon as descriptors are available. */
606 STAILQ_HEAD(, wrqe) wr_list;
610 /* stats for common events first */
612 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
613 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
614 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
616 /* stats for not-that-common events */
619 * Scratch space for work requests that wrap around after reaching the
620 * status page, and some information about the last WR that used it.
624 uint8_t ss[SGE_MAX_WR_LEN];
626 } __aligned(CACHE_LINE_SIZE);
632 struct iq_desc *iq_desc;
634 uint16_t iq_cntxt_id;
640 uint16_t fl_cntxt_id;
647 u_int nid; /* netmap ring # for this queue */
649 /* infrequently used items after this */
651 bus_dma_tag_t iq_desc_tag;
652 bus_dmamap_t iq_desc_map;
656 bus_dma_tag_t fl_desc_tag;
657 bus_dmamap_t fl_desc_map;
659 } __aligned(CACHE_LINE_SIZE);
662 struct tx_desc *desc;
666 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
667 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
668 uint16_t dbidx; /* pidx of the most recent doorbell */
670 volatile uint32_t *udb;
673 __be32 cpl_ctrl0; /* for convenience */
674 u_int nid; /* netmap ring # for this queue */
676 /* infrequently used items after this */
678 bus_dma_tag_t desc_tag;
679 bus_dmamap_t desc_map;
682 } __aligned(CACHE_LINE_SIZE);
685 int nrxq; /* total # of Ethernet rx queues */
686 int ntxq; /* total # of Ethernet tx tx queues */
687 int nofldrxq; /* total # of TOE rx queues */
688 int nofldtxq; /* total # of TOE tx queues */
689 int nnmrxq; /* total # of netmap rx queues */
690 int nnmtxq; /* total # of netmap tx queues */
691 int niq; /* total # of ingress queues */
692 int neq; /* total # of egress queues */
694 struct sge_iq fwq; /* Firmware event queue */
695 struct sge_wrq mgmtq; /* Management queue (control queue) */
696 struct sge_wrq *ctrlq; /* Control queues */
697 struct sge_txq *txq; /* NIC tx queues */
698 struct sge_rxq *rxq; /* NIC rx queues */
699 struct sge_wrq *ofld_txq; /* TOE tx queues */
700 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
701 struct sge_nm_txq *nm_txq; /* netmap tx queues */
702 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
704 uint16_t iq_start; /* first cntxt_id */
705 uint16_t iq_base; /* first abs_id */
706 int eq_start; /* first cntxt_id */
707 int eq_base; /* first abs_id */
708 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
709 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
711 int8_t safe_hwidx1; /* may not have room for metadata */
712 int8_t safe_hwidx2; /* with room for metadata and maybe more */
713 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
714 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
718 const char *nexus_name;
719 const char *ifnet_name;
720 const char *vi_ifnet_name;
721 const char *pf03_drv_name;
722 const char *vf_nexus_name;
723 const char *vf_ifnet_name;
727 SLIST_ENTRY(adapter) link;
730 const struct devnames *names;
732 /* PCIe register resources */
734 struct resource *regs_res;
736 struct resource *msix_res;
737 bus_space_handle_t bh;
741 struct resource *udbs_res;
742 volatile uint8_t *udbs_base;
746 unsigned int vpd_busy;
747 unsigned int vpd_flag;
749 /* Interrupt information */
753 struct resource *res;
755 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
758 struct sge_nm_rxq *nm_rxq;
759 } __aligned(CACHE_LINE_SIZE) *irq;
761 int sge_kdoorbell_reg;
763 bus_dma_tag_t dmat; /* Parent DMA tag */
769 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
770 struct port_info *port[MAX_NPORTS];
771 uint8_t chan_map[MAX_NCHAN];
773 void *tom_softc; /* (struct tom_data *) */
774 struct tom_tunables tt;
775 void *iwarp_softc; /* (struct c4iw_dev *) */
776 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
777 struct l2t_data *l2t; /* L2 table */
778 struct tid_info tids;
781 int offload_map; /* ports with IFCAP_TOE enabled */
782 int active_ulds; /* ULDs activated on this adapter */
786 char ifp_lockname[16];
788 struct ifnet *ifp; /* tracer ifp */
789 struct ifmedia media;
790 int traceq; /* iq used by all tracers, -1 if none */
791 int tracer_valid; /* bitmap of valid tracers */
792 int tracer_enabled; /* bitmap of enabled tracers */
800 struct adapter_params params;
801 const struct chip_params *chip_params;
802 struct t4_virt_res vres;
814 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
819 /* Starving free lists */
820 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
821 TAILQ_HEAD(, sge_fl) sfl;
822 struct callout sfl_callout;
824 struct mtx reg_lock; /* for indirect register access */
826 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
829 const void *last_op_thr;
833 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
834 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
835 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
836 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
838 #define ASSERT_SYNCHRONIZED_OP(sc) \
839 KASSERT(IS_BUSY(sc) && \
840 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
841 ("%s: operation not synchronized.", __func__))
843 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
844 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
845 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
846 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
848 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
849 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
850 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
851 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
852 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
854 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
855 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
856 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
857 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
859 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
860 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
861 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
862 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
863 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
865 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
866 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
867 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
868 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
869 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
871 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
873 if (sc->debug_flags & DF_DUMP_MBOX) { \
875 "%s mbox %u: %016llx %016llx %016llx %016llx " \
876 "%016llx %016llx %016llx %016llx\n", \
877 device_get_nameunit(sc->dev), mbox, \
878 (unsigned long long)t4_read_reg64(sc, data_reg), \
879 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
880 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
881 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
882 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
883 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
884 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
885 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
889 #define for_each_txq(vi, iter, q) \
890 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
891 iter < vi->ntxq; ++iter, ++q)
892 #define for_each_rxq(vi, iter, q) \
893 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
894 iter < vi->nrxq; ++iter, ++q)
895 #define for_each_ofld_txq(vi, iter, q) \
896 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
897 iter < vi->nofldtxq; ++iter, ++q)
898 #define for_each_ofld_rxq(vi, iter, q) \
899 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
900 iter < vi->nofldrxq; ++iter, ++q)
901 #define for_each_nm_txq(vi, iter, q) \
902 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
903 iter < vi->nnmtxq; ++iter, ++q)
904 #define for_each_nm_rxq(vi, iter, q) \
905 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
906 iter < vi->nnmrxq; ++iter, ++q)
907 #define for_each_vi(_pi, _iter, _vi) \
908 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
911 #define IDXINCR(idx, incr, wrap) do { \
912 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
914 #define IDXDIFF(head, tail, wrap) \
915 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
917 /* One for errors, one for firmware events */
918 #define T4_EXTRA_INTR 2
920 /* One for firmware events */
921 #define T4VF_EXTRA_INTR 1
923 static inline uint32_t
924 t4_read_reg(struct adapter *sc, uint32_t reg)
927 return bus_space_read_4(sc->bt, sc->bh, reg);
931 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
934 bus_space_write_4(sc->bt, sc->bh, reg, val);
937 static inline uint64_t
938 t4_read_reg64(struct adapter *sc, uint32_t reg)
942 return bus_space_read_8(sc->bt, sc->bh, reg);
944 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
945 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
951 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
955 bus_space_write_8(sc->bt, sc->bh, reg, val);
957 bus_space_write_4(sc->bt, sc->bh, reg, val);
958 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
963 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
966 *val = pci_read_config(sc->dev, reg, 1);
970 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
973 pci_write_config(sc->dev, reg, val, 1);
977 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
980 *val = pci_read_config(sc->dev, reg, 2);
984 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
987 pci_write_config(sc->dev, reg, val, 2);
991 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
994 *val = pci_read_config(sc->dev, reg, 4);
998 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1001 pci_write_config(sc->dev, reg, val, 4);
1004 static inline struct port_info *
1005 adap2pinfo(struct adapter *sc, int idx)
1008 return (sc->port[idx]);
1012 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
1015 bcopy(hw_addr, sc->port[idx]->vi[0].hw_addr, ETHER_ADDR_LEN);
1019 is_10G_port(const struct port_info *pi)
1022 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1026 is_25G_port(const struct port_info *pi)
1029 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1033 is_40G_port(const struct port_info *pi)
1036 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1040 is_100G_port(const struct port_info *pi)
1043 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1047 port_top_speed(const struct port_info *pi)
1050 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1052 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1054 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1056 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1058 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1065 tx_resume_threshold(struct sge_eq *eq)
1068 /* not quite the same as qsize / 4, but this will do. */
1069 return (eq->sidx / 4);
1073 t4_use_ldst(struct adapter *sc)
1077 return (sc->flags & FW_OK || !sc->use_bd);
1084 extern int t4_ntxq10g;
1085 extern int t4_nrxq10g;
1086 extern int t4_ntxq1g;
1087 extern int t4_nrxq1g;
1088 extern int t4_intr_types;
1089 extern int t4_tmr_idx_10g;
1090 extern int t4_pktc_idx_10g;
1091 extern int t4_tmr_idx_1g;
1092 extern int t4_pktc_idx_1g;
1093 extern unsigned int t4_qsize_rxq;
1094 extern unsigned int t4_qsize_txq;
1095 extern device_method_t cxgbe_methods[];
1097 int t4_os_find_pci_capability(struct adapter *, int);
1098 int t4_os_pci_save_state(struct adapter *);
1099 int t4_os_pci_restore_state(struct adapter *);
1100 void t4_os_portmod_changed(const struct adapter *, int);
1101 void t4_os_link_changed(struct adapter *, int, int);
1102 void t4_iterate(void (*)(struct adapter *, void *), void *);
1103 void t4_init_devnames(struct adapter *);
1104 void t4_add_adapter(struct adapter *);
1105 int t4_detach_common(device_t);
1106 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1107 int t4_map_bars_0_and_4(struct adapter *);
1108 int t4_map_bar_2(struct adapter *);
1109 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1110 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1111 int t4_setup_intr_handlers(struct adapter *);
1112 void t4_sysctls(struct adapter *);
1113 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1114 void doom_vi(struct adapter *, struct vi_info *);
1115 void end_synchronized_op(struct adapter *, int);
1116 int update_mac_settings(struct ifnet *, int);
1117 int adapter_full_init(struct adapter *);
1118 int adapter_full_uninit(struct adapter *);
1119 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1120 int vi_full_init(struct vi_info *);
1121 int vi_full_uninit(struct vi_info *);
1122 void vi_sysctls(struct vi_info *);
1123 void vi_tick(void *);
1127 void cxgbe_nm_attach(struct vi_info *);
1128 void cxgbe_nm_detach(struct vi_info *);
1129 void t4_nm_intr(void *);
1133 void t4_sge_modload(void);
1134 void t4_sge_modunload(void);
1135 uint64_t t4_sge_extfree_refs(void);
1136 void t4_tweak_chip_settings(struct adapter *);
1137 int t4_read_chip_settings(struct adapter *);
1138 int t4_create_dma_tag(struct adapter *);
1139 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1140 struct sysctl_oid_list *);
1141 int t4_destroy_dma_tag(struct adapter *);
1142 int t4_setup_adapter_queues(struct adapter *);
1143 int t4_teardown_adapter_queues(struct adapter *);
1144 int t4_setup_vi_queues(struct vi_info *);
1145 int t4_teardown_vi_queues(struct vi_info *);
1146 void t4_intr_all(void *);
1147 void t4_intr(void *);
1148 void t4_vi_intr(void *);
1149 void t4_intr_err(void *);
1150 void t4_intr_evt(void *);
1151 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1152 void t4_update_fl_bufsize(struct ifnet *);
1153 int parse_pkt(struct adapter *, struct mbuf **);
1154 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1155 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1156 int tnl_cong(struct port_info *, int);
1157 int t4_register_an_handler(an_handler_t);
1158 int t4_register_fw_msg_handler(int, fw_msg_handler_t);
1159 int t4_register_cpl_handler(int, cpl_handler_t);
1163 void t4_tracer_modload(void);
1164 void t4_tracer_modunload(void);
1165 void t4_tracer_port_detach(struct adapter *);
1166 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1167 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1168 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1169 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1171 static inline struct wrqe *
1172 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1174 int len = offsetof(struct wrqe, wr) + wr_len;
1177 wr = malloc(len, M_CXGBE, M_NOWAIT);
1178 if (__predict_false(wr == NULL))
1180 wr->wr_len = wr_len;
1185 static inline void *
1186 wrtod(struct wrqe *wr)
1188 return (&wr->wr[0]);
1192 free_wrqe(struct wrqe *wr)
1198 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1200 struct sge_wrq *wrq = wr->wrq;
1203 t4_wrq_tx_locked(sc, wrq, wr);