2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
57 #include "firmware/t4fw_interface.h"
59 MALLOC_DECLARE(M_CXGBE);
60 #define CXGBE_UNIMPLEMENTED(s) \
61 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
63 #if defined(__i386__) || defined(__amd64__)
67 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
73 #ifndef SYSCTL_ADD_UQUAD
74 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
75 #define sysctl_handle_64 sysctl_handle_quad
76 #define CTLTYPE_U64 CTLTYPE_QUAD
79 #if (__FreeBSD_version >= 900030) || \
80 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
85 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
86 static __inline uint64_t
87 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
90 KASSERT(tag == X86_BUS_SPACE_MEM,
91 ("%s: can only handle mem space", __func__));
93 return (*(volatile uint64_t *)(handle + offset));
97 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
98 bus_size_t offset, uint64_t value)
100 KASSERT(tag == X86_BUS_SPACE_MEM,
101 ("%s: can only handle mem space", __func__));
103 *(volatile uint64_t *)(bsh + offset) = value;
106 static __inline uint64_t
107 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
110 return (uint64_t)bus_space_read_4(tag, handle, offset) +
111 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
115 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
116 bus_size_t offset, uint64_t value)
118 bus_space_write_4(tag, bsh, offset, value);
119 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
124 typedef struct adapter adapter_t;
128 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
131 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
133 EQ_ESIZE = 64, /* All egress queues use this entry size */
135 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
136 #if MJUMPAGESIZE != MCLBYTES
137 FL_BUF_SIZES_MAX = 5, /* cluster, jumbop, jumbo9k, jumbo16k, extra */
139 FL_BUF_SIZES_MAX = 4, /* cluster, jumbo9k, jumbo16k, extra */
146 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
150 /* adapter intr_type */
151 INTR_INTX = (1 << 0),
157 /* flags understood by begin_synchronized_op */
158 HOLD_LOCK = (1 << 0),
162 /* flags understood by end_synchronized_op */
163 LOCK_HELD = HOLD_LOCK,
168 FULL_INIT_DONE = (1 << 0),
170 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */
171 MASTER_PF = (1 << 3),
172 ADAP_SYSCTL_CTX = (1 << 4),
173 TOM_INIT_DONE = (1 << 5),
174 BUF_PACKING_OK = (1 << 6),
176 CXGBE_BUSY = (1 << 9),
180 PORT_INIT_DONE = (1 << 1),
181 PORT_SYSCTL_CTX = (1 << 2),
182 HAS_TRACEQ = (1 << 3),
185 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
186 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
187 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
188 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
189 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
193 struct adapter *adapter;
196 struct ifmedia media;
205 int16_t xact_addr_filt;/* index of exact MAC address filter */
206 uint16_t rss_size; /* size of VI's RSS table slice */
207 uint8_t lport; /* associated offload logical port */
214 /* These need to be int as they are used in sysctl */
215 int ntxq; /* # of tx queues */
216 int first_txq; /* index of first tx queue */
217 int nrxq; /* # of rx queues */
218 int first_rxq; /* index of first rx queue */
220 int nofldtxq; /* # of offload tx queues */
221 int first_ofld_txq; /* index of first offload tx queue */
222 int nofldrxq; /* # of offload rx queues */
223 int first_ofld_rxq; /* index of first offload rx queue */
231 struct link_config link_cfg;
232 struct port_stats stats;
234 eventhandler_tag vlan_c;
237 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
239 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
245 uint8_t tag_idx; /* the fl->tag entry this map comes from */
260 /* DMA maps used for tx */
263 uint32_t map_total; /* # of DMA maps */
264 uint32_t map_pidx; /* next map to be used */
265 uint32_t map_cidx; /* reclaimed up to this index */
266 uint32_t map_avail; /* # of available maps */
270 uint8_t desc_used; /* # of hardware descriptors used by the WR */
271 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
276 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
277 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
278 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
279 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
288 * Ingress Queue: T4 is producer, driver is consumer.
291 bus_dma_tag_t desc_tag;
292 bus_dmamap_t desc_map;
293 bus_addr_t ba; /* bus address of descriptor ring */
295 uint16_t abs_id; /* absolute SGE id for the iq */
296 int8_t intr_pktc_idx; /* packet count threshold index */
298 __be64 *desc; /* KVA of descriptor ring */
301 struct adapter *adapter;
302 const __be64 *cdesc; /* current descriptor */
303 uint8_t gen; /* generation bit */
304 uint8_t intr_params; /* interrupt holdoff parameters */
305 uint8_t intr_next; /* XXX: holdoff for next interrupt */
306 uint8_t esize; /* size (bytes) of each entry in the queue */
307 uint16_t qsize; /* size (# of entries) of the queue */
308 uint16_t cidx; /* consumer index */
309 uint16_t cntxt_id; /* SGE context id for the iq */
311 STAILQ_ENTRY(sge_iq) link;
322 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
323 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
324 EQ_DOOMED = (1 << 4), /* about to be destroyed */
325 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
326 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
329 /* Listed in order of preference. Update t4_sysctls too if you change these */
330 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
333 * Egress Queue: driver is producer, T4 is consumer.
335 * Note: A free list is an egress queue (driver produces the buffers and T4
336 * consumes them) but it's special enough to have its own struct (see sge_fl).
339 unsigned int flags; /* MUST be first */
340 unsigned int cntxt_id; /* SGE context id for the eq */
341 bus_dma_tag_t desc_tag;
342 bus_dmamap_t desc_map;
346 struct tx_desc *desc; /* KVA of descriptor ring */
347 bus_addr_t ba; /* bus address of descriptor ring */
348 struct sge_qstat *spg; /* status page, for convenience */
350 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
351 u_int udb_qid; /* relative qid within the doorbell page */
352 uint16_t cap; /* max # of desc, for convenience */
353 uint16_t avail; /* available descriptors, for convenience */
354 uint16_t qsize; /* size (# of entries) of the queue */
355 uint16_t cidx; /* consumer idx (desc idx) */
356 uint16_t pidx; /* producer idx (desc idx) */
357 uint16_t pending; /* # of descriptors used since last doorbell */
358 uint16_t iqid; /* iq that gets egr_update for the eq */
359 uint8_t tx_chan; /* tx channel used by the eq */
361 struct callout tx_callout;
365 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
366 uint32_t unstalled; /* recovered from stall */
372 int hwtag:4; /* tag in low 4 bits of the pa. */
375 #define FL_BUF_SIZES(sc) (sc->sge.fl_buf_sizes)
376 #define FL_BUF_SIZE(sc, x) (sc->sge.fl_buf_info[x].size)
377 #define FL_BUF_TYPE(sc, x) (sc->sge.fl_buf_info[x].type)
378 #define FL_BUF_HWTAG(sc, x) (sc->sge.fl_buf_info[x].hwtag)
379 #define FL_BUF_ZONE(sc, x) (sc->sge.fl_buf_info[x].zone)
382 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
383 FL_DOOMED = (1 << 1), /* about to be destroyed */
384 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
387 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
388 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
391 bus_dma_tag_t desc_tag;
392 bus_dmamap_t desc_map;
393 bus_dma_tag_t tag[FL_BUF_SIZES_MAX]; /* only first FL_BUF_SIZES(sc) are
400 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
401 bus_addr_t ba; /* bus address of descriptor ring */
402 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
403 uint32_t cap; /* max # of buffers, for convenience */
404 uint16_t qsize; /* size (# of entries) of the queue */
405 uint16_t cntxt_id; /* SGE context id for the freelist */
406 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
407 uint32_t rx_offset; /* offset in fl buf (when buffer packing) */
408 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
409 uint32_t needed; /* # of buffers needed to fill up fl. */
410 uint32_t lowat; /* # of buffers <= this means fl needs help */
411 uint32_t pending; /* # of bufs allocated since last doorbell */
413 struct mbuf *mstash[8];
414 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
417 /* txq: SGE egress queue + what's needed for Ethernet NIC */
419 struct sge_eq eq; /* MUST be first */
421 struct ifnet *ifp; /* the interface this txq belongs to */
422 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
423 struct buf_ring *br; /* tx buffer ring */
424 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
425 struct mbuf *m; /* held up due to temporary resource shortage */
427 struct tx_maps txmaps;
429 /* stats for common events first */
431 uint64_t txcsum; /* # of times hardware assisted with checksum */
432 uint64_t tso_wrs; /* # of TSO work requests */
433 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
434 uint64_t imm_wrs; /* # of work requests with immediate data */
435 uint64_t sgl_wrs; /* # of work requests with direct SGL */
436 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
437 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
438 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
440 /* stats for not-that-common events */
442 uint32_t no_dmamap; /* no DMA map to load the mbuf */
443 uint32_t no_desc; /* out of hardware descriptors */
444 } __aligned(CACHE_LINE_SIZE);
446 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
448 struct sge_iq iq; /* MUST be first */
449 struct sge_fl fl; /* MUST follow iq */
451 struct ifnet *ifp; /* the interface this rxq belongs to */
452 #if defined(INET) || defined(INET6)
453 struct lro_ctrl lro; /* LRO state */
456 /* stats for common events first */
458 uint64_t rxcsum; /* # of times hardware assisted with checksum */
459 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
461 /* stats for not-that-common events */
463 } __aligned(CACHE_LINE_SIZE);
465 static inline struct sge_rxq *
466 iq_to_rxq(struct sge_iq *iq)
469 return (__containerof(iq, struct sge_rxq, iq));
474 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
475 struct sge_ofld_rxq {
476 struct sge_iq iq; /* MUST be first */
477 struct sge_fl fl; /* MUST follow iq */
478 } __aligned(CACHE_LINE_SIZE);
480 static inline struct sge_ofld_rxq *
481 iq_to_ofld_rxq(struct sge_iq *iq)
484 return (__containerof(iq, struct sge_ofld_rxq, iq));
489 STAILQ_ENTRY(wrqe) link;
492 uint64_t wr[] __aligned(16);
496 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
497 * and offload tx queues are of this type.
500 struct sge_eq eq; /* MUST be first */
502 struct adapter *adapter;
504 /* List of WRs held up due to lack of tx descriptors */
505 STAILQ_HEAD(, wrqe) wr_list;
507 /* stats for common events first */
509 uint64_t tx_wrs; /* # of tx work requests */
511 /* stats for not-that-common events */
513 uint32_t no_desc; /* out of hardware descriptors */
514 } __aligned(CACHE_LINE_SIZE);
517 int timer_val[SGE_NTIMERS];
518 int counter_val[SGE_NCOUNTERS];
519 int fl_starve_threshold;
523 int nrxq; /* total # of Ethernet rx queues */
524 int ntxq; /* total # of Ethernet tx tx queues */
526 int nofldrxq; /* total # of TOE rx queues */
527 int nofldtxq; /* total # of TOE tx queues */
529 int niq; /* total # of ingress queues */
530 int neq; /* total # of egress queues */
532 struct sge_iq fwq; /* Firmware event queue */
533 struct sge_wrq mgmtq; /* Management queue (control queue) */
534 struct sge_wrq *ctrlq; /* Control queues */
535 struct sge_txq *txq; /* NIC tx queues */
536 struct sge_rxq *rxq; /* NIC rx queues */
538 struct sge_wrq *ofld_txq; /* TOE tx queues */
539 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
544 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
545 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
547 u_int fl_buf_sizes __aligned(CACHE_LINE_SIZE);
548 struct fl_buf_info fl_buf_info[FL_BUF_SIZES_MAX];
552 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
554 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
555 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
558 SLIST_ENTRY(adapter) link;
562 /* PCIe register resources */
564 struct resource *regs_res;
566 struct resource *msix_res;
567 bus_space_handle_t bh;
571 struct resource *udbs_res;
572 volatile uint8_t *udbs_base;
577 /* Interrupt information */
581 struct resource *res;
586 bus_dma_tag_t dmat; /* Parent DMA tag */
591 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
592 struct port_info *port[MAX_NPORTS];
593 uint8_t chan_map[NCHAN];
596 void *tom_softc; /* (struct tom_data *) */
597 struct tom_tunables tt;
598 void *iwarp_softc; /* (struct c4iw_dev *) */
600 struct l2t_data *l2t; /* L2 table */
601 struct tid_info tids;
610 char ifp_lockname[16];
612 struct ifnet *ifp; /* tracer ifp */
613 struct ifmedia media;
614 int traceq; /* iq used by all tracers, -1 if none */
615 int tracer_valid; /* bitmap of valid tracers */
616 int tracer_enabled; /* bitmap of enabled tracers */
621 struct adapter_params params;
622 struct t4_virt_res vres;
631 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
636 /* Starving free lists */
637 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
638 TAILQ_HEAD(, sge_fl) sfl;
639 struct callout sfl_callout;
641 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
642 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
643 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
647 const void *last_op_thr;
653 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
654 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
655 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
656 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
658 /* XXX: not bulletproof, but much better than nothing */
659 #define ASSERT_SYNCHRONIZED_OP(sc) \
660 KASSERT(IS_BUSY(sc) && \
661 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
662 ("%s: operation not synchronized.", __func__))
664 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
665 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
666 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
667 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
669 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
670 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
671 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
672 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
673 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
675 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
676 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
677 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
678 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
680 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
681 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
682 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
683 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
684 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
686 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
687 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
688 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
689 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
690 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
692 #define for_each_txq(pi, iter, q) \
693 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
694 iter < pi->ntxq; ++iter, ++q)
695 #define for_each_rxq(pi, iter, q) \
696 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
697 iter < pi->nrxq; ++iter, ++q)
698 #define for_each_ofld_txq(pi, iter, q) \
699 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
700 iter < pi->nofldtxq; ++iter, ++q)
701 #define for_each_ofld_rxq(pi, iter, q) \
702 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
703 iter < pi->nofldrxq; ++iter, ++q)
705 /* One for errors, one for firmware events */
706 #define T4_EXTRA_INTR 2
708 static inline uint32_t
709 t4_read_reg(struct adapter *sc, uint32_t reg)
712 return bus_space_read_4(sc->bt, sc->bh, reg);
716 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
719 bus_space_write_4(sc->bt, sc->bh, reg, val);
722 static inline uint64_t
723 t4_read_reg64(struct adapter *sc, uint32_t reg)
726 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
730 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
733 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
737 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
740 *val = pci_read_config(sc->dev, reg, 1);
744 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
747 pci_write_config(sc->dev, reg, val, 1);
751 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
754 *val = pci_read_config(sc->dev, reg, 2);
758 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
761 pci_write_config(sc->dev, reg, val, 2);
765 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
768 *val = pci_read_config(sc->dev, reg, 4);
772 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
775 pci_write_config(sc->dev, reg, val, 4);
778 static inline struct port_info *
779 adap2pinfo(struct adapter *sc, int idx)
782 return (sc->port[idx]);
786 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
789 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
793 is_10G_port(const struct port_info *pi)
796 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
800 is_40G_port(const struct port_info *pi)
803 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
807 tx_resume_threshold(struct sge_eq *eq)
810 return (eq->qsize / 4);
814 void t4_tx_task(void *, int);
815 void t4_tx_callout(void *);
816 int t4_os_find_pci_capability(struct adapter *, int);
817 int t4_os_pci_save_state(struct adapter *);
818 int t4_os_pci_restore_state(struct adapter *);
819 void t4_os_portmod_changed(const struct adapter *, int);
820 void t4_os_link_changed(struct adapter *, int, int, int);
821 void t4_iterate(void (*)(struct adapter *, void *), void *);
822 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
823 int t4_register_an_handler(struct adapter *, an_handler_t);
824 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
825 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
826 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
827 void end_synchronized_op(struct adapter *, int);
830 void t4_sge_modload(void);
831 void t4_init_sge_cpl_handlers(struct adapter *);
832 void t4_tweak_chip_settings(struct adapter *);
833 int t4_read_chip_settings(struct adapter *);
834 int t4_create_dma_tag(struct adapter *);
835 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
836 struct sysctl_oid_list *);
837 int t4_destroy_dma_tag(struct adapter *);
838 int t4_setup_adapter_queues(struct adapter *);
839 int t4_teardown_adapter_queues(struct adapter *);
840 int t4_setup_port_queues(struct port_info *);
841 int t4_teardown_port_queues(struct port_info *);
842 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
843 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
844 void t4_intr_all(void *);
845 void t4_intr(void *);
846 void t4_intr_err(void *);
847 void t4_intr_evt(void *);
848 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
849 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
850 void t4_update_fl_bufsize(struct ifnet *);
851 int can_resume_tx(struct sge_eq *);
855 void t4_tracer_modload(void);
856 void t4_tracer_modunload(void);
857 void t4_tracer_port_detach(struct adapter *);
858 int t4_get_tracer(struct adapter *, struct t4_tracer *);
859 int t4_set_tracer(struct adapter *, struct t4_tracer *);
860 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
861 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
863 static inline struct wrqe *
864 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
866 int len = offsetof(struct wrqe, wr) + wr_len;
869 wr = malloc(len, M_CXGBE, M_NOWAIT);
870 if (__predict_false(wr == NULL))
878 wrtod(struct wrqe *wr)
884 free_wrqe(struct wrqe *wr)
890 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
892 struct sge_wrq *wrq = wr->wrq;
895 t4_wrq_tx_locked(sc, wrq, wr);