2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
39 #include <sys/malloc.h>
40 #include <sys/rwlock.h>
44 #include <dev/pci/pcivar.h>
45 #include <dev/pci/pcireg.h>
46 #include <machine/bus.h>
47 #include <sys/socket.h>
48 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_var.h>
52 #include <net/if_media.h>
53 #include <netinet/in.h>
54 #include <netinet/tcp_lro.h>
57 #include "common/t4_msg.h"
58 #include "firmware/t4fw_interface.h"
60 #define KTR_CXGBE KTR_SPARE3
61 MALLOC_DECLARE(M_CXGBE);
62 #define CXGBE_UNIMPLEMENTED(s) \
63 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
65 #if defined(__i386__) || defined(__amd64__)
69 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
75 #ifndef SYSCTL_ADD_UQUAD
76 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
77 #define sysctl_handle_64 sysctl_handle_quad
78 #define CTLTYPE_U64 CTLTYPE_QUAD
81 #if (__FreeBSD_version >= 900030) || \
82 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
87 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
88 static __inline uint64_t
89 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
92 KASSERT(tag == X86_BUS_SPACE_MEM,
93 ("%s: can only handle mem space", __func__));
95 return (*(volatile uint64_t *)(handle + offset));
99 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
100 bus_size_t offset, uint64_t value)
102 KASSERT(tag == X86_BUS_SPACE_MEM,
103 ("%s: can only handle mem space", __func__));
105 *(volatile uint64_t *)(bsh + offset) = value;
108 static __inline uint64_t
109 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
112 return (uint64_t)bus_space_read_4(tag, handle, offset) +
113 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
117 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
118 bus_size_t offset, uint64_t value)
120 bus_space_write_4(tag, bsh, offset, value);
121 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
126 typedef struct adapter adapter_t;
130 * All ingress queues use this entry size. Note that the firmware event
131 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
136 /* Default queue sizes for all kinds of ingress queues */
140 /* All egress queues use this entry size */
143 /* Default queue sizes for all kinds of egress queues */
147 #if MJUMPAGESIZE != MCLBYTES
148 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
150 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
152 CL_METADATA_SIZE = CACHE_LINE_SIZE,
154 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
156 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
160 /* adapter intr_type */
161 INTR_INTX = (1 << 0),
167 XGMAC_MTU = (1 << 0),
168 XGMAC_PROMISC = (1 << 1),
169 XGMAC_ALLMULTI = (1 << 2),
170 XGMAC_VLANEX = (1 << 3),
171 XGMAC_UCADDR = (1 << 4),
172 XGMAC_MCADDRS = (1 << 5),
178 /* flags understood by begin_synchronized_op */
179 HOLD_LOCK = (1 << 0),
183 /* flags understood by end_synchronized_op */
184 LOCK_HELD = HOLD_LOCK,
189 FULL_INIT_DONE = (1 << 0),
191 /* INTR_DIRECT = (1 << 2), No longer used. */
192 MASTER_PF = (1 << 3),
193 ADAP_SYSCTL_CTX = (1 << 4),
194 TOM_INIT_DONE = (1 << 5),
195 BUF_PACKING_OK = (1 << 6),
197 CXGBE_BUSY = (1 << 9),
201 PORT_INIT_DONE = (1 << 1),
202 PORT_SYSCTL_CTX = (1 << 2),
203 HAS_TRACEQ = (1 << 3),
204 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
205 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
206 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
207 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
210 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
211 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
212 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
213 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
214 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
218 struct adapter *adapter;
221 struct ifmedia media;
230 int16_t xact_addr_filt;/* index of exact MAC address filter */
231 uint16_t rss_size; /* size of VI's RSS table slice */
232 uint8_t lport; /* associated offload logical port */
238 uint8_t rx_chan_map; /* rx MPS channel bitmap */
240 /* These need to be int as they are used in sysctl */
241 int ntxq; /* # of tx queues */
242 int first_txq; /* index of first tx queue */
243 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
244 int nrxq; /* # of rx queues */
245 int first_rxq; /* index of first rx queue */
247 int nofldtxq; /* # of offload tx queues */
248 int first_ofld_txq; /* index of first offload tx queue */
249 int nofldrxq; /* # of offload rx queues */
250 int first_ofld_rxq; /* index of first offload rx queue */
253 int nnmtxq; /* # of netmap tx queues */
254 int first_nm_txq; /* index of first netmap tx queue */
255 int nnmrxq; /* # of netmap rx queues */
256 int first_nm_rxq; /* index of first netmap rx queue */
258 struct ifnet *nm_ifp;
259 struct ifmedia nm_media;
262 int16_t nm_xact_addr_filt;
263 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
271 struct link_config link_cfg;
273 struct timeval last_refreshed;
274 struct port_stats stats;
275 u_int tnl_cong_drops;
277 eventhandler_tag vlan_c;
280 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
282 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
285 /* Where the cluster came from, how it has been carved up. */
286 struct cluster_layout {
289 uint16_t region1; /* mbufs laid out within this region */
290 /* region2 is the DMA region */
291 uint16_t region3; /* cluster_metadata within this region */
294 struct cluster_metadata {
297 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
303 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
304 struct cluster_layout cll;
316 /* DMA maps used for tx */
319 uint32_t map_total; /* # of DMA maps */
320 uint32_t map_pidx; /* next map to be used */
321 uint32_t map_cidx; /* reclaimed up to this index */
322 uint32_t map_avail; /* # of available maps */
326 uint8_t desc_used; /* # of hardware descriptors used by the WR */
327 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
331 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
333 struct rss_header rss;
338 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
342 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
343 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
344 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
345 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
354 * Ingress Queue: T4 is producer, driver is consumer.
359 struct adapter *adapter;
360 struct iq_desc *desc; /* KVA of descriptor ring */
361 int8_t intr_pktc_idx; /* packet count threshold index */
362 uint8_t gen; /* generation bit */
363 uint8_t intr_params; /* interrupt holdoff parameters */
364 uint8_t intr_next; /* XXX: holdoff for next interrupt */
365 uint16_t qsize; /* size (# of entries) of the queue */
366 uint16_t sidx; /* index of the entry with the status page */
367 uint16_t cidx; /* consumer index */
368 uint16_t cntxt_id; /* SGE context id for the iq */
369 uint16_t abs_id; /* absolute SGE id for the iq */
371 STAILQ_ENTRY(sge_iq) link;
373 bus_dma_tag_t desc_tag;
374 bus_dmamap_t desc_map;
375 bus_addr_t ba; /* bus address of descriptor ring */
386 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
387 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
388 EQ_DOOMED = (1 << 4), /* about to be destroyed */
389 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
390 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
393 /* Listed in order of preference. Update t4_sysctls too if you change these */
394 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
397 * Egress Queue: driver is producer, T4 is consumer.
399 * Note: A free list is an egress queue (driver produces the buffers and T4
400 * consumes them) but it's special enough to have its own struct (see sge_fl).
403 unsigned int flags; /* MUST be first */
404 unsigned int cntxt_id; /* SGE context id for the eq */
405 bus_dma_tag_t desc_tag;
406 bus_dmamap_t desc_map;
410 struct tx_desc *desc; /* KVA of descriptor ring */
411 bus_addr_t ba; /* bus address of descriptor ring */
412 struct sge_qstat *spg; /* status page, for convenience */
414 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
415 u_int udb_qid; /* relative qid within the doorbell page */
416 uint16_t cap; /* max # of desc, for convenience */
417 uint16_t avail; /* available descriptors, for convenience */
418 uint16_t qsize; /* size (# of entries) of the queue */
419 uint16_t cidx; /* consumer idx (desc idx) */
420 uint16_t pidx; /* producer idx (desc idx) */
421 uint16_t pending; /* # of descriptors used since last doorbell */
422 uint16_t iqid; /* iq that gets egr_update for the eq */
423 uint8_t tx_chan; /* tx channel used by the eq */
425 struct callout tx_callout;
429 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
430 uint32_t unstalled; /* recovered from stall */
433 struct sw_zone_info {
434 uma_zone_t zone; /* zone that this cluster comes from */
435 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
436 int type; /* EXT_xxx type of the cluster */
442 int8_t zidx; /* backpointer to zone; -ve means unused */
443 int8_t next; /* next hwidx for this zone; -1 means no more */
448 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
449 FL_DOOMED = (1 << 1), /* about to be destroyed */
450 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
451 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
454 #define FL_RUNNING_LOW(fl) \
455 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
456 #define FL_NOT_RUNNING_LOW(fl) \
457 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
461 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
462 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
463 struct cluster_layout cll_def; /* default refill zone, layout */
464 uint16_t lowat; /* # of buffers <= this means fl needs help */
466 uint16_t buf_boundary;
468 /* The 16b idx all deal with hw descriptors */
469 uint16_t dbidx; /* hw pidx after last doorbell */
470 uint16_t sidx; /* index of status page */
471 volatile uint16_t hw_cidx;
473 /* The 32b idx are all buffer idx, not hardware descriptor idx */
474 uint32_t cidx; /* consumer index */
475 uint32_t pidx; /* producer index */
478 u_int rx_offset; /* offset in fl buf (when buffer packing) */
479 volatile uint32_t *udb;
481 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
482 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
483 uint64_t cl_allocated; /* # of clusters allocated */
484 uint64_t cl_recycled; /* # of clusters recycled */
485 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
487 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
492 uint16_t qsize; /* # of hw descriptors (status page included) */
493 uint16_t cntxt_id; /* SGE context id for the freelist */
494 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
495 bus_dma_tag_t desc_tag;
496 bus_dmamap_t desc_map;
498 bus_addr_t ba; /* bus address of descriptor ring */
499 struct cluster_layout cll_alt; /* alternate refill zone, layout */
502 /* txq: SGE egress queue + what's needed for Ethernet NIC */
504 struct sge_eq eq; /* MUST be first */
506 struct ifnet *ifp; /* the interface this txq belongs to */
507 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
508 struct buf_ring *br; /* tx buffer ring */
509 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
510 struct mbuf *m; /* held up due to temporary resource shortage */
512 struct tx_maps txmaps;
514 /* stats for common events first */
516 uint64_t txcsum; /* # of times hardware assisted with checksum */
517 uint64_t tso_wrs; /* # of TSO work requests */
518 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
519 uint64_t imm_wrs; /* # of work requests with immediate data */
520 uint64_t sgl_wrs; /* # of work requests with direct SGL */
521 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
522 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
523 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
525 /* stats for not-that-common events */
527 uint32_t no_dmamap; /* no DMA map to load the mbuf */
528 uint32_t no_desc; /* out of hardware descriptors */
529 } __aligned(CACHE_LINE_SIZE);
531 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
533 struct sge_iq iq; /* MUST be first */
534 struct sge_fl fl; /* MUST follow iq */
536 struct ifnet *ifp; /* the interface this rxq belongs to */
537 #if defined(INET) || defined(INET6)
538 struct lro_ctrl lro; /* LRO state */
541 /* stats for common events first */
543 uint64_t rxcsum; /* # of times hardware assisted with checksum */
544 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
546 /* stats for not-that-common events */
548 } __aligned(CACHE_LINE_SIZE);
550 static inline struct sge_rxq *
551 iq_to_rxq(struct sge_iq *iq)
554 return (__containerof(iq, struct sge_rxq, iq));
559 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
560 struct sge_ofld_rxq {
561 struct sge_iq iq; /* MUST be first */
562 struct sge_fl fl; /* MUST follow iq */
563 } __aligned(CACHE_LINE_SIZE);
565 static inline struct sge_ofld_rxq *
566 iq_to_ofld_rxq(struct sge_iq *iq)
569 return (__containerof(iq, struct sge_ofld_rxq, iq));
574 STAILQ_ENTRY(wrqe) link;
577 uint64_t wr[] __aligned(16);
581 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
582 * and offload tx queues are of this type.
585 struct sge_eq eq; /* MUST be first */
587 struct adapter *adapter;
589 /* List of WRs held up due to lack of tx descriptors */
590 STAILQ_HEAD(, wrqe) wr_list;
592 /* stats for common events first */
594 uint64_t tx_wrs; /* # of tx work requests */
596 /* stats for not-that-common events */
598 uint32_t no_desc; /* out of hardware descriptors */
599 } __aligned(CACHE_LINE_SIZE);
604 struct port_info *pi;
606 struct iq_desc *iq_desc;
608 uint16_t iq_cntxt_id;
614 uint16_t fl_cntxt_id;
621 u_int nid; /* netmap ring # for this queue */
623 /* infrequently used items after this */
625 bus_dma_tag_t iq_desc_tag;
626 bus_dmamap_t iq_desc_map;
630 bus_dma_tag_t fl_desc_tag;
631 bus_dmamap_t fl_desc_map;
633 } __aligned(CACHE_LINE_SIZE);
636 struct tx_desc *desc;
640 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
641 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
642 uint16_t dbidx; /* pidx of the most recent doorbell */
644 volatile uint32_t *udb;
647 __be32 cpl_ctrl0; /* for convenience */
648 u_int nid; /* netmap ring # for this queue */
650 /* infrequently used items after this */
652 bus_dma_tag_t desc_tag;
653 bus_dmamap_t desc_map;
656 } __aligned(CACHE_LINE_SIZE);
660 int timer_val[SGE_NTIMERS];
661 int counter_val[SGE_NCOUNTERS];
662 int fl_starve_threshold;
663 int fl_starve_threshold2;
667 int nrxq; /* total # of Ethernet rx queues */
668 int ntxq; /* total # of Ethernet tx tx queues */
670 int nofldrxq; /* total # of TOE rx queues */
671 int nofldtxq; /* total # of TOE tx queues */
674 int nnmrxq; /* total # of netmap rx queues */
675 int nnmtxq; /* total # of netmap tx queues */
677 int niq; /* total # of ingress queues */
678 int neq; /* total # of egress queues */
680 struct sge_iq fwq; /* Firmware event queue */
681 struct sge_wrq mgmtq; /* Management queue (control queue) */
682 struct sge_wrq *ctrlq; /* Control queues */
683 struct sge_txq *txq; /* NIC tx queues */
684 struct sge_rxq *rxq; /* NIC rx queues */
686 struct sge_wrq *ofld_txq; /* TOE tx queues */
687 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
690 struct sge_nm_txq *nm_txq; /* netmap tx queues */
691 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
696 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
697 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
701 int8_t safe_hwidx1; /* may not have room for metadata */
702 int8_t safe_hwidx2; /* with room for metadata and maybe more */
703 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
704 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
708 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
710 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
711 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
714 SLIST_ENTRY(adapter) link;
718 /* PCIe register resources */
720 struct resource *regs_res;
722 struct resource *msix_res;
723 bus_space_handle_t bh;
727 struct resource *udbs_res;
728 volatile uint8_t *udbs_base;
733 /* Interrupt information */
737 struct resource *res;
742 bus_dma_tag_t dmat; /* Parent DMA tag */
747 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
748 struct port_info *port[MAX_NPORTS];
749 uint8_t chan_map[NCHAN];
752 void *tom_softc; /* (struct tom_data *) */
753 struct tom_tunables tt;
754 void *iwarp_softc; /* (struct c4iw_dev *) */
757 struct l2t_data *l2t; /* L2 table */
758 struct tid_info tids;
767 char ifp_lockname[16];
769 struct ifnet *ifp; /* tracer ifp */
770 struct ifmedia media;
771 int traceq; /* iq used by all tracers, -1 if none */
772 int tracer_valid; /* bitmap of valid tracers */
773 int tracer_enabled; /* bitmap of enabled tracers */
778 struct adapter_params params;
779 struct t4_virt_res vres;
788 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
793 /* Starving free lists */
794 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
795 TAILQ_HEAD(, sge_fl) sfl;
796 struct callout sfl_callout;
798 struct mtx regwin_lock; /* for indirect reads and memory windows */
800 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
801 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
802 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
806 const void *last_op_thr;
812 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
813 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
814 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
815 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
817 /* XXX: not bulletproof, but much better than nothing */
818 #define ASSERT_SYNCHRONIZED_OP(sc) \
819 KASSERT(IS_BUSY(sc) && \
820 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
821 ("%s: operation not synchronized.", __func__))
823 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
824 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
825 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
826 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
828 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
829 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
830 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
831 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
832 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
834 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
835 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
836 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
837 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
839 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
840 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
841 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
842 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
843 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
845 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
846 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
847 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
848 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
849 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
851 #define for_each_txq(pi, iter, q) \
852 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
853 iter < pi->ntxq; ++iter, ++q)
854 #define for_each_rxq(pi, iter, q) \
855 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
856 iter < pi->nrxq; ++iter, ++q)
857 #define for_each_ofld_txq(pi, iter, q) \
858 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
859 iter < pi->nofldtxq; ++iter, ++q)
860 #define for_each_ofld_rxq(pi, iter, q) \
861 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
862 iter < pi->nofldrxq; ++iter, ++q)
863 #define for_each_nm_txq(pi, iter, q) \
864 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
865 iter < pi->nnmtxq; ++iter, ++q)
866 #define for_each_nm_rxq(pi, iter, q) \
867 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
868 iter < pi->nnmrxq; ++iter, ++q)
870 #define IDXINCR(idx, incr, wrap) do { \
871 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
873 #define IDXDIFF(head, tail, wrap) \
874 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
876 /* One for errors, one for firmware events */
877 #define T4_EXTRA_INTR 2
879 static inline uint32_t
880 t4_read_reg(struct adapter *sc, uint32_t reg)
883 return bus_space_read_4(sc->bt, sc->bh, reg);
887 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
890 bus_space_write_4(sc->bt, sc->bh, reg, val);
893 static inline uint64_t
894 t4_read_reg64(struct adapter *sc, uint32_t reg)
897 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
901 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
904 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
908 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
911 *val = pci_read_config(sc->dev, reg, 1);
915 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
918 pci_write_config(sc->dev, reg, val, 1);
922 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
925 *val = pci_read_config(sc->dev, reg, 2);
929 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
932 pci_write_config(sc->dev, reg, val, 2);
936 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
939 *val = pci_read_config(sc->dev, reg, 4);
943 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
946 pci_write_config(sc->dev, reg, val, 4);
949 static inline struct port_info *
950 adap2pinfo(struct adapter *sc, int idx)
953 return (sc->port[idx]);
957 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
960 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
964 is_10G_port(const struct port_info *pi)
967 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
971 is_40G_port(const struct port_info *pi)
974 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
978 tx_resume_threshold(struct sge_eq *eq)
981 return (eq->qsize / 4);
985 void t4_tx_task(void *, int);
986 void t4_tx_callout(void *);
987 int t4_os_find_pci_capability(struct adapter *, int);
988 int t4_os_pci_save_state(struct adapter *);
989 int t4_os_pci_restore_state(struct adapter *);
990 void t4_os_portmod_changed(const struct adapter *, int);
991 void t4_os_link_changed(struct adapter *, int, int, int);
992 void t4_iterate(void (*)(struct adapter *, void *), void *);
993 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
994 int t4_register_an_handler(struct adapter *, an_handler_t);
995 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
996 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
997 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
998 void end_synchronized_op(struct adapter *, int);
999 int update_mac_settings(struct ifnet *, int);
1000 int adapter_full_init(struct adapter *);
1001 int adapter_full_uninit(struct adapter *);
1002 int port_full_init(struct port_info *);
1003 int port_full_uninit(struct port_info *);
1007 int create_netmap_ifnet(struct port_info *);
1008 int destroy_netmap_ifnet(struct port_info *);
1009 void t4_nm_intr(void *);
1013 void t4_sge_modload(void);
1014 void t4_sge_modunload(void);
1015 uint64_t t4_sge_extfree_refs(void);
1016 void t4_init_sge_cpl_handlers(struct adapter *);
1017 void t4_tweak_chip_settings(struct adapter *);
1018 int t4_read_chip_settings(struct adapter *);
1019 int t4_create_dma_tag(struct adapter *);
1020 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1021 struct sysctl_oid_list *);
1022 int t4_destroy_dma_tag(struct adapter *);
1023 int t4_setup_adapter_queues(struct adapter *);
1024 int t4_teardown_adapter_queues(struct adapter *);
1025 int t4_setup_port_queues(struct port_info *);
1026 int t4_teardown_port_queues(struct port_info *);
1027 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
1028 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
1029 void t4_intr_all(void *);
1030 void t4_intr(void *);
1031 void t4_intr_err(void *);
1032 void t4_intr_evt(void *);
1033 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1034 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
1035 void t4_update_fl_bufsize(struct ifnet *);
1036 int can_resume_tx(struct sge_eq *);
1040 void t4_tracer_modload(void);
1041 void t4_tracer_modunload(void);
1042 void t4_tracer_port_detach(struct adapter *);
1043 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1044 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1045 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1046 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1048 static inline struct wrqe *
1049 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1051 int len = offsetof(struct wrqe, wr) + wr_len;
1054 wr = malloc(len, M_CXGBE, M_NOWAIT);
1055 if (__predict_false(wr == NULL))
1057 wr->wr_len = wr_len;
1062 static inline void *
1063 wrtod(struct wrqe *wr)
1065 return (&wr->wr[0]);
1069 free_wrqe(struct wrqe *wr)
1075 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1077 struct sge_wrq *wrq = wr->wrq;
1080 t4_wrq_tx_locked(sc, wrq, wr);