2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
6 * Written by: Navdeep Parhar <np@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #ifndef __T4_ADAPTER_H__
34 #define __T4_ADAPTER_H__
36 #include <sys/kernel.h>
39 #include <sys/types.h>
41 #include <sys/malloc.h>
42 #include <sys/rwlock.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcireg.h>
48 #include <machine/bus.h>
49 #include <sys/socket.h>
50 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
53 #include <net/if_var.h>
54 #include <net/if_media.h>
55 #include <netinet/in.h>
56 #include <netinet/tcp_lro.h>
60 #include "common/t4_msg.h"
61 #include "firmware/t4fw_interface.h"
63 #define KTR_CXGBE KTR_SPARE3
64 MALLOC_DECLARE(M_CXGBE);
65 #define CXGBE_UNIMPLEMENTED(s) \
66 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
68 #if defined(__i386__) || defined(__amd64__)
72 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
78 #ifndef SYSCTL_ADD_UQUAD
79 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
80 #define sysctl_handle_64 sysctl_handle_quad
81 #define CTLTYPE_U64 CTLTYPE_QUAD
84 #if (__FreeBSD_version >= 900030) || \
85 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
90 typedef struct adapter adapter_t;
94 * All ingress queues use this entry size. Note that the firmware event
95 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
100 /* Default queue sizes for all kinds of ingress queues */
104 /* All egress queues use this entry size */
107 /* Default queue sizes for all kinds of egress queues */
111 #if MJUMPAGESIZE != MCLBYTES
112 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
114 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
116 CL_METADATA_SIZE = CACHE_LINE_SIZE,
118 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
120 TX_SGL_SEGS_TSO = 38,
121 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
125 /* adapter intr_type */
126 INTR_INTX = (1 << 0),
132 XGMAC_MTU = (1 << 0),
133 XGMAC_PROMISC = (1 << 1),
134 XGMAC_ALLMULTI = (1 << 2),
135 XGMAC_VLANEX = (1 << 3),
136 XGMAC_UCADDR = (1 << 4),
137 XGMAC_MCADDRS = (1 << 5),
143 /* flags understood by begin_synchronized_op */
144 HOLD_LOCK = (1 << 0),
148 /* flags understood by end_synchronized_op */
149 LOCK_HELD = HOLD_LOCK,
154 FULL_INIT_DONE = (1 << 0),
156 CHK_MBOX_ACCESS = (1 << 2),
157 MASTER_PF = (1 << 3),
158 ADAP_SYSCTL_CTX = (1 << 4),
159 /* TOM_INIT_DONE= (1 << 5), No longer used */
160 BUF_PACKING_OK = (1 << 6),
163 CXGBE_BUSY = (1 << 9),
166 HAS_TRACEQ = (1 << 3),
170 VI_INIT_DONE = (1 << 1),
171 VI_SYSCTL_CTX = (1 << 2),
172 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
173 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
174 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ),
176 /* adapter debug_flags */
177 DF_DUMP_MBOX = (1 << 0), /* Log all mbox cmd/rpl. */
178 DF_LOAD_FW_ANYTIME = (1 << 1), /* Allow LOAD_FW after init */
179 DF_DISABLE_TCB_CACHE = (1 << 2), /* Disable TCB cache (T6+) */
182 #define IS_DOOMED(vi) ((vi)->flags & DOOMED)
183 #define SET_DOOMED(vi) do {(vi)->flags |= DOOMED;} while (0)
184 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
185 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
186 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
190 struct port_info *pi;
197 uint16_t *rss, *nm_rss;
198 int smt_idx; /* for convenience */
200 int16_t xact_addr_filt;/* index of exact MAC address filter */
201 uint16_t rss_size; /* size of VI's RSS table slice */
202 uint16_t rss_base; /* start of VI's RSS table slice */
204 eventhandler_tag vlan_c;
209 /* These need to be int as they are used in sysctl */
210 int ntxq; /* # of tx queues */
211 int first_txq; /* index of first tx queue */
212 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
213 int nrxq; /* # of rx queues */
214 int first_rxq; /* index of first rx queue */
215 int nofldtxq; /* # of offload tx queues */
216 int first_ofld_txq; /* index of first offload tx queue */
217 int nofldrxq; /* # of offload rx queues */
218 int first_ofld_rxq; /* index of first offload rx queue */
230 struct timeval last_refreshed;
231 struct fw_vi_stats_vf stats;
234 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
236 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
239 struct tx_ch_rl_params {
240 enum fw_sched_params_rate ratemode; /* %port (REL) or kbps (ABS) */
245 TX_CLRL_REFRESH = (1 << 0), /* Need to update hardware state. */
246 TX_CLRL_ERROR = (1 << 1), /* Error, hardware state unknown. */
249 struct tx_cl_rl_params {
252 enum fw_sched_params_rate ratemode; /* %port REL or ABS value */
253 enum fw_sched_params_unit rateunit; /* kbps or pps (when ABS) */
254 enum fw_sched_params_mode mode; /* aggr or per-flow */
259 /* Tx scheduler parameters for a channel/port */
260 struct tx_sched_params {
261 /* Channel Rate Limiter */
262 struct tx_ch_rl_params ch_rl;
267 /* Class Rate Limiter */
268 struct tx_cl_rl_params cl_rl[];
273 struct adapter *adapter;
280 struct tx_sched_params *sched_params;
286 uint8_t lport; /* associated offload logical port */
292 uint8_t mps_bg_map; /* rx MPS buffer group bitmap */
293 uint8_t rx_e_chan_map; /* rx TP e-channel bitmap */
295 struct link_config link_cfg;
296 struct link_config old_link_cfg;
297 struct ifmedia media;
299 struct timeval last_refreshed;
300 struct port_stats stats;
301 u_int tnl_cong_drops;
302 u_int tx_parse_error;
307 #define IS_MAIN_VI(vi) ((vi) == &((vi)->pi->vi[0]))
309 /* Where the cluster came from, how it has been carved up. */
310 struct cluster_layout {
313 uint16_t region1; /* mbufs laid out within this region */
314 /* region2 is the DMA region */
315 uint16_t region3; /* cluster_metadata within this region */
318 struct cluster_metadata {
320 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
325 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
326 struct cluster_layout cll;
334 struct mbuf *m; /* m_nextpkt linked chain of frames */
335 uint8_t desc_used; /* # of hardware descriptors used by the WR */
339 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
341 struct rss_header rss;
346 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
350 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
351 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
352 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
353 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
354 IQ_ADJ_CREDIT = (1 << 4), /* hw is off by 1 credit for this iq */
361 /* netmap related flags */
369 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
371 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
372 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
375 * Ingress Queue: T4 is producer, driver is consumer.
380 struct adapter *adapter;
381 cpl_handler_t set_tcb_rpl;
382 cpl_handler_t l2t_write_rpl;
383 struct iq_desc *desc; /* KVA of descriptor ring */
384 int8_t intr_pktc_idx; /* packet count threshold index */
385 uint8_t gen; /* generation bit */
386 uint8_t intr_params; /* interrupt holdoff parameters */
387 uint8_t intr_next; /* XXX: holdoff for next interrupt */
388 uint16_t qsize; /* size (# of entries) of the queue */
389 uint16_t sidx; /* index of the entry with the status page */
390 uint16_t cidx; /* consumer index */
391 uint16_t cntxt_id; /* SGE context id for the iq */
392 uint16_t abs_id; /* absolute SGE id for the iq */
394 STAILQ_ENTRY(sge_iq) link;
396 bus_dma_tag_t desc_tag;
397 bus_dmamap_t desc_map;
398 bus_addr_t ba; /* bus address of descriptor ring */
407 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
408 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
409 EQ_ENABLED = (1 << 3), /* open for business */
410 EQ_QFLUSH = (1 << 4), /* if_qflush in progress */
413 /* Listed in order of preference. Update t4_sysctls too if you change these */
414 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
417 * Egress Queue: driver is producer, T4 is consumer.
419 * Note: A free list is an egress queue (driver produces the buffers and T4
420 * consumes them) but it's special enough to have its own struct (see sge_fl).
423 unsigned int flags; /* MUST be first */
424 unsigned int cntxt_id; /* SGE context id for the eq */
425 unsigned int abs_id; /* absolute SGE id for the eq */
428 struct tx_desc *desc; /* KVA of descriptor ring */
430 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
431 u_int udb_qid; /* relative qid within the doorbell page */
432 uint16_t sidx; /* index of the entry with the status page */
433 uint16_t cidx; /* consumer idx (desc idx) */
434 uint16_t pidx; /* producer idx (desc idx) */
435 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
436 uint16_t dbidx; /* pidx of the most recent doorbell */
437 uint16_t iqid; /* iq that gets egr_update for the eq */
438 uint8_t tx_chan; /* tx channel used by the eq */
439 volatile u_int equiq; /* EQUIQ outstanding */
441 bus_dma_tag_t desc_tag;
442 bus_dmamap_t desc_map;
443 bus_addr_t ba; /* bus address of descriptor ring */
447 struct sw_zone_info {
448 uma_zone_t zone; /* zone that this cluster comes from */
449 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
450 int type; /* EXT_xxx type of the cluster */
456 int8_t zidx; /* backpointer to zone; -ve means unused */
457 int8_t next; /* next hwidx for this zone; -1 means no more */
464 MEMWIN0_APERTURE = 2048,
465 MEMWIN0_BASE = 0x1b800,
467 MEMWIN1_APERTURE = 32768,
468 MEMWIN1_BASE = 0x28000,
470 MEMWIN2_APERTURE_T4 = 65536,
471 MEMWIN2_BASE_T4 = 0x30000,
473 MEMWIN2_APERTURE_T5 = 128 * 1024,
474 MEMWIN2_BASE_T5 = 0x60000,
478 struct rwlock mw_lock __aligned(CACHE_LINE_SIZE);
479 uint32_t mw_base; /* constant after setup_memwin */
480 uint32_t mw_aperture; /* ditto */
481 uint32_t mw_curpos; /* protected by mw_lock */
485 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
486 FL_DOOMED = (1 << 1), /* about to be destroyed */
487 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
488 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
491 #define FL_RUNNING_LOW(fl) \
492 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
493 #define FL_NOT_RUNNING_LOW(fl) \
494 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
498 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
499 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
500 struct cluster_layout cll_def; /* default refill zone, layout */
501 uint16_t lowat; /* # of buffers <= this means fl needs help */
503 uint16_t buf_boundary;
505 /* The 16b idx all deal with hw descriptors */
506 uint16_t dbidx; /* hw pidx after last doorbell */
507 uint16_t sidx; /* index of status page */
508 volatile uint16_t hw_cidx;
510 /* The 32b idx are all buffer idx, not hardware descriptor idx */
511 uint32_t cidx; /* consumer index */
512 uint32_t pidx; /* producer index */
515 u_int rx_offset; /* offset in fl buf (when buffer packing) */
516 volatile uint32_t *udb;
518 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
519 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
520 uint64_t cl_allocated; /* # of clusters allocated */
521 uint64_t cl_recycled; /* # of clusters recycled */
522 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
524 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
529 uint16_t qsize; /* # of hw descriptors (status page included) */
530 uint16_t cntxt_id; /* SGE context id for the freelist */
531 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
532 bus_dma_tag_t desc_tag;
533 bus_dmamap_t desc_map;
535 bus_addr_t ba; /* bus address of descriptor ring */
536 struct cluster_layout cll_alt; /* alternate refill zone, layout */
541 /* txq: SGE egress queue + what's needed for Ethernet NIC */
543 struct sge_eq eq; /* MUST be first */
545 struct ifnet *ifp; /* the interface this txq belongs to */
546 struct mp_ring *r; /* tx software ring */
547 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
549 __be32 cpl_ctrl0; /* for convenience */
550 int tc_idx; /* traffic class */
552 struct task tx_reclaim_task;
553 /* stats for common events first */
555 uint64_t txcsum; /* # of times hardware assisted with checksum */
556 uint64_t tso_wrs; /* # of TSO work requests */
557 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
558 uint64_t imm_wrs; /* # of work requests with immediate data */
559 uint64_t sgl_wrs; /* # of work requests with direct SGL */
560 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
561 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
562 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
563 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
564 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
566 /* stats for not-that-common events */
567 } __aligned(CACHE_LINE_SIZE);
569 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
571 struct sge_iq iq; /* MUST be first */
572 struct sge_fl fl; /* MUST follow iq */
574 struct ifnet *ifp; /* the interface this rxq belongs to */
575 #if defined(INET) || defined(INET6)
576 struct lro_ctrl lro; /* LRO state */
579 /* stats for common events first */
581 uint64_t rxcsum; /* # of times hardware assisted with checksum */
582 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
584 /* stats for not-that-common events */
586 } __aligned(CACHE_LINE_SIZE);
588 static inline struct sge_rxq *
589 iq_to_rxq(struct sge_iq *iq)
592 return (__containerof(iq, struct sge_rxq, iq));
596 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
597 struct sge_ofld_rxq {
598 struct sge_iq iq; /* MUST be first */
599 struct sge_fl fl; /* MUST follow iq */
600 } __aligned(CACHE_LINE_SIZE);
602 static inline struct sge_ofld_rxq *
603 iq_to_ofld_rxq(struct sge_iq *iq)
606 return (__containerof(iq, struct sge_ofld_rxq, iq));
610 STAILQ_ENTRY(wrqe) link;
613 char wr[] __aligned(16);
617 TAILQ_ENTRY(wrq_cookie) link;
623 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
624 * and offload tx queues are of this type.
627 struct sge_eq eq; /* MUST be first */
629 struct adapter *adapter;
630 struct task wrq_tx_task;
632 /* Tx desc reserved but WR not "committed" yet. */
633 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
635 /* List of WRs ready to go out as soon as descriptors are available. */
636 STAILQ_HEAD(, wrqe) wr_list;
640 /* stats for common events first */
642 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
643 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
644 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
646 /* stats for not-that-common events */
649 * Scratch space for work requests that wrap around after reaching the
650 * status page, and some information about the last WR that used it.
654 uint8_t ss[SGE_MAX_WR_LEN];
656 } __aligned(CACHE_LINE_SIZE);
658 #define INVALID_NM_RXQ_CNTXT_ID ((uint16_t)(-1))
662 struct iq_desc *iq_desc;
664 uint16_t iq_cntxt_id;
670 uint16_t fl_cntxt_id;
677 u_int nid; /* netmap ring # for this queue */
679 /* infrequently used items after this */
681 bus_dma_tag_t iq_desc_tag;
682 bus_dmamap_t iq_desc_map;
686 bus_dma_tag_t fl_desc_tag;
687 bus_dmamap_t fl_desc_map;
689 } __aligned(CACHE_LINE_SIZE);
691 #define INVALID_NM_TXQ_CNTXT_ID ((u_int)(-1))
693 struct tx_desc *desc;
697 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
698 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
699 uint16_t dbidx; /* pidx of the most recent doorbell */
701 volatile uint32_t *udb;
704 __be32 cpl_ctrl0; /* for convenience */
705 u_int nid; /* netmap ring # for this queue */
707 /* infrequently used items after this */
709 bus_dma_tag_t desc_tag;
710 bus_dmamap_t desc_map;
713 } __aligned(CACHE_LINE_SIZE);
716 int nrxq; /* total # of Ethernet rx queues */
717 int ntxq; /* total # of Ethernet tx queues */
718 int nofldrxq; /* total # of TOE rx queues */
719 int nofldtxq; /* total # of TOE tx queues */
720 int nnmrxq; /* total # of netmap rx queues */
721 int nnmtxq; /* total # of netmap tx queues */
722 int niq; /* total # of ingress queues */
723 int neq; /* total # of egress queues */
725 struct sge_iq fwq; /* Firmware event queue */
726 struct sge_wrq mgmtq; /* Management queue (control queue) */
727 struct sge_wrq *ctrlq; /* Control queues */
728 struct sge_txq *txq; /* NIC tx queues */
729 struct sge_rxq *rxq; /* NIC rx queues */
730 struct sge_wrq *ofld_txq; /* TOE tx queues */
731 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
732 struct sge_nm_txq *nm_txq; /* netmap tx queues */
733 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
735 uint16_t iq_start; /* first cntxt_id */
736 uint16_t iq_base; /* first abs_id */
737 int eq_start; /* first cntxt_id */
738 int eq_base; /* first abs_id */
739 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
740 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
742 int8_t safe_hwidx1; /* may not have room for metadata */
743 int8_t safe_hwidx2; /* with room for metadata and maybe more */
744 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
745 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
749 const char *nexus_name;
750 const char *ifnet_name;
751 const char *vi_ifnet_name;
752 const char *pf03_drv_name;
753 const char *vf_nexus_name;
754 const char *vf_ifnet_name;
758 SLIST_ENTRY(adapter) link;
761 const struct devnames *names;
763 /* PCIe register resources */
765 struct resource *regs_res;
767 struct resource *msix_res;
768 bus_space_handle_t bh;
772 struct resource *udbs_res;
773 volatile uint8_t *udbs_base;
777 unsigned int vpd_busy;
778 unsigned int vpd_flag;
780 /* Interrupt information */
784 struct resource *res;
786 volatile int nm_state; /* NM_OFF, NM_ON, or NM_BUSY */
789 struct sge_nm_rxq *nm_rxq;
790 } __aligned(CACHE_LINE_SIZE) *irq;
792 int sge_kdoorbell_reg;
794 bus_dma_tag_t dmat; /* Parent DMA tag */
800 struct taskqueue *tq[MAX_NCHAN]; /* General purpose taskqueues */
801 struct port_info *port[MAX_NPORTS];
802 uint8_t chan_map[MAX_NCHAN]; /* channel -> port */
804 void *tom_softc; /* (struct tom_data *) */
805 struct tom_tunables tt;
806 struct iw_tunables iwt;
807 void *iwarp_softc; /* (struct c4iw_dev *) */
808 void *iscsi_ulp_softc; /* (struct cxgbei_data *) */
809 void *ccr_softc; /* (struct ccr_softc *) */
810 struct l2t_data *l2t; /* L2 table */
811 struct tid_info tids;
814 int offload_map; /* ports with IFCAP_TOE enabled */
815 int active_ulds; /* ULDs activated on this adapter */
819 char ifp_lockname[16];
821 struct ifnet *ifp; /* tracer ifp */
822 struct ifmedia media;
823 int traceq; /* iq used by all tracers, -1 if none */
824 int tracer_valid; /* bitmap of valid tracers */
825 int tracer_enabled; /* bitmap of enabled tracers */
833 struct adapter_params params;
834 const struct chip_params *chip_params;
835 struct t4_virt_res vres;
847 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
852 /* Starving free lists */
853 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
854 TAILQ_HEAD(, sge_fl) sfl;
855 struct callout sfl_callout;
857 struct mtx reg_lock; /* for indirect register access */
859 struct memwin memwin[NUM_MEMWIN]; /* memory windows */
865 const void *last_op_thr;
869 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
870 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
871 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
872 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
874 #define ASSERT_SYNCHRONIZED_OP(sc) \
875 KASSERT(IS_BUSY(sc) && \
876 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
877 ("%s: operation not synchronized.", __func__))
879 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
880 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
881 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
882 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
884 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
885 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
886 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
887 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
888 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
890 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
891 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
892 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
893 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
895 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
896 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
897 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
898 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
899 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
901 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
902 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
903 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
904 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
905 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
907 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
909 if (sc->debug_flags & DF_DUMP_MBOX) { \
911 "%s mbox %u: %016llx %016llx %016llx %016llx " \
912 "%016llx %016llx %016llx %016llx\n", \
913 device_get_nameunit(sc->dev), mbox, \
914 (unsigned long long)t4_read_reg64(sc, data_reg), \
915 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
916 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
917 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
918 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
919 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
920 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
921 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
925 #define for_each_txq(vi, iter, q) \
926 for (q = &vi->pi->adapter->sge.txq[vi->first_txq], iter = 0; \
927 iter < vi->ntxq; ++iter, ++q)
928 #define for_each_rxq(vi, iter, q) \
929 for (q = &vi->pi->adapter->sge.rxq[vi->first_rxq], iter = 0; \
930 iter < vi->nrxq; ++iter, ++q)
931 #define for_each_ofld_txq(vi, iter, q) \
932 for (q = &vi->pi->adapter->sge.ofld_txq[vi->first_ofld_txq], iter = 0; \
933 iter < vi->nofldtxq; ++iter, ++q)
934 #define for_each_ofld_rxq(vi, iter, q) \
935 for (q = &vi->pi->adapter->sge.ofld_rxq[vi->first_ofld_rxq], iter = 0; \
936 iter < vi->nofldrxq; ++iter, ++q)
937 #define for_each_nm_txq(vi, iter, q) \
938 for (q = &vi->pi->adapter->sge.nm_txq[vi->first_nm_txq], iter = 0; \
939 iter < vi->nnmtxq; ++iter, ++q)
940 #define for_each_nm_rxq(vi, iter, q) \
941 for (q = &vi->pi->adapter->sge.nm_rxq[vi->first_nm_rxq], iter = 0; \
942 iter < vi->nnmrxq; ++iter, ++q)
943 #define for_each_vi(_pi, _iter, _vi) \
944 for ((_vi) = (_pi)->vi, (_iter) = 0; (_iter) < (_pi)->nvi; \
947 #define IDXINCR(idx, incr, wrap) do { \
948 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
950 #define IDXDIFF(head, tail, wrap) \
951 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
953 /* One for errors, one for firmware events */
954 #define T4_EXTRA_INTR 2
956 /* One for firmware events */
957 #define T4VF_EXTRA_INTR 1
959 static inline uint32_t
960 t4_read_reg(struct adapter *sc, uint32_t reg)
963 return bus_space_read_4(sc->bt, sc->bh, reg);
967 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
970 bus_space_write_4(sc->bt, sc->bh, reg, val);
973 static inline uint64_t
974 t4_read_reg64(struct adapter *sc, uint32_t reg)
978 return bus_space_read_8(sc->bt, sc->bh, reg);
980 return (uint64_t)bus_space_read_4(sc->bt, sc->bh, reg) +
981 ((uint64_t)bus_space_read_4(sc->bt, sc->bh, reg + 4) << 32);
987 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
991 bus_space_write_8(sc->bt, sc->bh, reg, val);
993 bus_space_write_4(sc->bt, sc->bh, reg, val);
994 bus_space_write_4(sc->bt, sc->bh, reg + 4, val>> 32);
999 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
1002 *val = pci_read_config(sc->dev, reg, 1);
1006 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
1009 pci_write_config(sc->dev, reg, val, 1);
1013 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
1016 *val = pci_read_config(sc->dev, reg, 2);
1020 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
1023 pci_write_config(sc->dev, reg, val, 2);
1027 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
1030 *val = pci_read_config(sc->dev, reg, 4);
1034 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
1037 pci_write_config(sc->dev, reg, val, 4);
1040 static inline struct port_info *
1041 adap2pinfo(struct adapter *sc, int idx)
1044 return (sc->port[idx]);
1048 t4_os_set_hw_addr(struct port_info *pi, uint8_t hw_addr[])
1051 bcopy(hw_addr, pi->vi[0].hw_addr, ETHER_ADDR_LEN);
1055 is_10G_port(const struct port_info *pi)
1058 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
1062 is_25G_port(const struct port_info *pi)
1065 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G) != 0);
1069 is_40G_port(const struct port_info *pi)
1072 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
1076 is_100G_port(const struct port_info *pi)
1079 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G) != 0);
1083 port_top_speed(const struct port_info *pi)
1086 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100G)
1088 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G)
1090 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_25G)
1092 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G)
1094 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G)
1101 tx_resume_threshold(struct sge_eq *eq)
1104 /* not quite the same as qsize / 4, but this will do. */
1105 return (eq->sidx / 4);
1109 t4_use_ldst(struct adapter *sc)
1113 return (sc->flags & FW_OK || !sc->use_bd);
1122 extern int t4_intr_types;
1123 extern int t4_tmr_idx;
1124 extern int t4_pktc_idx;
1125 extern unsigned int t4_qsize_rxq;
1126 extern unsigned int t4_qsize_txq;
1127 extern device_method_t cxgbe_methods[];
1129 int t4_os_find_pci_capability(struct adapter *, int);
1130 int t4_os_pci_save_state(struct adapter *);
1131 int t4_os_pci_restore_state(struct adapter *);
1132 void t4_os_portmod_changed(struct port_info *);
1133 void t4_os_link_changed(struct port_info *);
1134 void t4_iterate(void (*)(struct adapter *, void *), void *);
1135 void t4_init_devnames(struct adapter *);
1136 void t4_add_adapter(struct adapter *);
1137 int t4_detach_common(device_t);
1138 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1139 int t4_map_bars_0_and_4(struct adapter *);
1140 int t4_map_bar_2(struct adapter *);
1141 int t4_setup_intr_handlers(struct adapter *);
1142 void t4_sysctls(struct adapter *);
1143 int begin_synchronized_op(struct adapter *, struct vi_info *, int, char *);
1144 void doom_vi(struct adapter *, struct vi_info *);
1145 void end_synchronized_op(struct adapter *, int);
1146 int update_mac_settings(struct ifnet *, int);
1147 int adapter_full_init(struct adapter *);
1148 int adapter_full_uninit(struct adapter *);
1149 uint64_t cxgbe_get_counter(struct ifnet *, ift_counter);
1150 int vi_full_init(struct vi_info *);
1151 int vi_full_uninit(struct vi_info *);
1152 void vi_sysctls(struct vi_info *);
1153 void vi_tick(void *);
1157 void cxgbe_nm_attach(struct vi_info *);
1158 void cxgbe_nm_detach(struct vi_info *);
1159 void t4_nm_intr(void *);
1163 void t4_sge_modload(void);
1164 void t4_sge_modunload(void);
1165 uint64_t t4_sge_extfree_refs(void);
1166 void t4_tweak_chip_settings(struct adapter *);
1167 int t4_read_chip_settings(struct adapter *);
1168 int t4_create_dma_tag(struct adapter *);
1169 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1170 struct sysctl_oid_list *);
1171 int t4_destroy_dma_tag(struct adapter *);
1172 int t4_setup_adapter_queues(struct adapter *);
1173 int t4_teardown_adapter_queues(struct adapter *);
1174 int t4_setup_vi_queues(struct vi_info *);
1175 int t4_teardown_vi_queues(struct vi_info *);
1176 void t4_intr_all(void *);
1177 void t4_intr(void *);
1178 void t4_vi_intr(void *);
1179 void t4_intr_err(void *);
1180 void t4_intr_evt(void *);
1181 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1182 void t4_update_fl_bufsize(struct ifnet *);
1183 int parse_pkt(struct adapter *, struct mbuf **);
1184 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1185 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1186 int tnl_cong(struct port_info *, int);
1187 int t4_register_an_handler(an_handler_t);
1188 int t4_register_fw_msg_handler(int, fw_msg_handler_t);
1189 int t4_register_cpl_handler(int, cpl_handler_t);
1193 void t4_tracer_modload(void);
1194 void t4_tracer_modunload(void);
1195 void t4_tracer_port_detach(struct adapter *);
1196 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1197 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1198 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1199 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1202 int t4_set_sched_class(struct adapter *, struct t4_sched_params *);
1203 int t4_set_sched_queue(struct adapter *, struct t4_sched_queue *);
1204 int t4_init_tx_sched(struct adapter *);
1205 int t4_free_tx_sched(struct adapter *);
1206 void t4_update_tx_sched(struct adapter *);
1207 int t4_reserve_cl_rl_kbps(struct adapter *, int, u_int, int *);
1208 void t4_release_cl_rl_kbps(struct adapter *, int, int);
1210 static inline struct wrqe *
1211 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1213 int len = offsetof(struct wrqe, wr) + wr_len;
1216 wr = malloc(len, M_CXGBE, M_NOWAIT);
1217 if (__predict_false(wr == NULL))
1219 wr->wr_len = wr_len;
1224 static inline void *
1225 wrtod(struct wrqe *wr)
1227 return (&wr->wr[0]);
1231 free_wrqe(struct wrqe *wr)
1237 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1239 struct sge_wrq *wrq = wr->wrq;
1242 t4_wrq_tx_locked(sc, wrq, wr);