2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2011 Chelsio Communications, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 #ifndef __CHELSIO_COMMON_H
33 #define __CHELSIO_COMMON_H
37 #define GLBL_INTR_MASK (F_CIM | F_MPS | F_PL | F_PCIE | F_MC0 | F_EDC0 | \
38 F_EDC1 | F_LE | F_TP | F_MA | F_PM_TX | F_PM_RX | F_ULP_RX | \
39 F_CPL_SWITCH | F_SGE | F_ULP_TX)
42 MAX_NPORTS = 4, /* max # of ports */
43 SERNUM_LEN = 24, /* Serial # length */
44 EC_LEN = 16, /* E/C length */
45 ID_LEN = 16, /* ID length */
46 PN_LEN = 16, /* Part Number length */
47 MD_LEN = 16, /* MFG diags version length */
48 MACADDR_LEN = 12, /* MAC Address length */
52 T4_REGMAP_SIZE = (160 * 1024),
53 T5_REGMAP_SIZE = (332 * 1024),
56 enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
58 enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
60 enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
65 PAUSE_AUTONEG = 1 << 2
70 FEC_BASER_RS = 1 << 1,
71 FEC_RESERVED = 1 << 2,
74 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
77 u64 tx_octets; /* total # of octets in good frames */
78 u64 tx_frames; /* all good frames */
79 u64 tx_bcast_frames; /* all broadcast frames */
80 u64 tx_mcast_frames; /* all multicast frames */
81 u64 tx_ucast_frames; /* all unicast frames */
82 u64 tx_error_frames; /* all error frames */
84 u64 tx_frames_64; /* # of Tx frames in a particular range */
86 u64 tx_frames_128_255;
87 u64 tx_frames_256_511;
88 u64 tx_frames_512_1023;
89 u64 tx_frames_1024_1518;
90 u64 tx_frames_1519_max;
92 u64 tx_drop; /* # of dropped Tx frames */
93 u64 tx_pause; /* # of transmitted pause frames */
94 u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
95 u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
96 u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
97 u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
98 u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
99 u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
100 u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
101 u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
103 u64 rx_octets; /* total # of octets in good frames */
104 u64 rx_frames; /* all good frames */
105 u64 rx_bcast_frames; /* all broadcast frames */
106 u64 rx_mcast_frames; /* all multicast frames */
107 u64 rx_ucast_frames; /* all unicast frames */
108 u64 rx_too_long; /* # of frames exceeding MTU */
109 u64 rx_jabber; /* # of jabber frames */
110 u64 rx_fcs_err; /* # of received frames with bad FCS */
111 u64 rx_len_err; /* # of received frames with length error */
112 u64 rx_symbol_err; /* symbol errors */
113 u64 rx_runt; /* # of short frames */
115 u64 rx_frames_64; /* # of Rx frames in a particular range */
116 u64 rx_frames_65_127;
117 u64 rx_frames_128_255;
118 u64 rx_frames_256_511;
119 u64 rx_frames_512_1023;
120 u64 rx_frames_1024_1518;
121 u64 rx_frames_1519_max;
123 u64 rx_pause; /* # of received pause frames */
124 u64 rx_ppp0; /* # of received PPP prio 0 frames */
125 u64 rx_ppp1; /* # of received PPP prio 1 frames */
126 u64 rx_ppp2; /* # of received PPP prio 2 frames */
127 u64 rx_ppp3; /* # of received PPP prio 3 frames */
128 u64 rx_ppp4; /* # of received PPP prio 4 frames */
129 u64 rx_ppp5; /* # of received PPP prio 5 frames */
130 u64 rx_ppp6; /* # of received PPP prio 6 frames */
131 u64 rx_ppp7; /* # of received PPP prio 7 frames */
133 u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
134 u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
135 u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
136 u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
137 u64 rx_trunc0; /* buffer-group 0 truncated packets */
138 u64 rx_trunc1; /* buffer-group 1 truncated packets */
139 u64 rx_trunc2; /* buffer-group 2 truncated packets */
140 u64 rx_trunc3; /* buffer-group 3 truncated packets */
143 struct lb_port_stats {
156 u64 frames_1024_1518;
171 struct tp_tcp_stats {
175 u64 tcp_retrans_segs;
178 struct tp_usm_stats {
184 struct tp_fcoe_stats {
190 struct tp_err_stats {
191 u32 mac_in_errs[MAX_NCHAN];
192 u32 hdr_in_errs[MAX_NCHAN];
193 u32 tcp_in_errs[MAX_NCHAN];
194 u32 tnl_cong_drops[MAX_NCHAN];
195 u32 ofld_chan_drops[MAX_NCHAN];
196 u32 tnl_tx_drops[MAX_NCHAN];
197 u32 ofld_vlan_drops[MAX_NCHAN];
198 u32 tcp6_in_errs[MAX_NCHAN];
203 struct tp_proxy_stats {
204 u32 proxy[MAX_NCHAN];
207 struct tp_cpl_stats {
212 struct tp_rdma_stats {
218 int timer_val[SGE_NTIMERS]; /* final, scaled values */
219 int counter_val[SGE_NCOUNTERS];
220 int fl_starve_threshold;
221 int fl_starve_threshold2;
230 u32 sge_fl_buffer_size[SGE_FLBUF_SIZES];
234 unsigned int tre; /* log2 of core clocks per TP tick */
235 unsigned int dack_re; /* DACK timer resolution */
236 unsigned int la_mask; /* what events are recorded by TP LA */
237 unsigned short tx_modq[MAX_NCHAN]; /* channel to modulation queue map */
239 uint32_t vlan_pri_map;
240 uint32_t ingress_config;
248 int8_t protocol_shift;
249 int8_t ethertype_shift;
250 int8_t macmatch_shift;
251 int8_t matchtype_shift;
258 u8 sn[SERNUM_LEN + 1];
261 u8 na[MACADDR_LEN + 1];
266 unsigned int vpd_cap_addr;
268 unsigned short speed;
269 unsigned short width;
273 * Firmware device log.
275 struct devlog_params {
276 u32 memtype; /* which memory (FW_MEMTYPE_* ) */
277 u32 start; /* start of log in firmware memory */
278 u32 size; /* size of log */
279 u32 addr; /* start address in flat addr space */
282 /* Stores chip specific parameters */
286 u8 cng_ch_bits_log; /* congestion channel map bits width */
295 /* VF-only parameters. */
298 * Global Receive Side Scaling (RSS) parameters in host-native format.
301 unsigned int mode; /* RSS mode */
304 u_int synmapen:1; /* SYN Map Enable */
305 u_int syn4tupenipv6:1; /* enable hashing 4-tuple IPv6 SYNs */
306 u_int syn2tupenipv6:1; /* enable hashing 2-tuple IPv6 SYNs */
307 u_int syn4tupenipv4:1; /* enable hashing 4-tuple IPv4 SYNs */
308 u_int syn2tupenipv4:1; /* enable hashing 2-tuple IPv4 SYNs */
309 u_int ofdmapen:1; /* Offload Map Enable */
310 u_int tnlmapen:1; /* Tunnel Map Enable */
311 u_int tnlalllookup:1; /* Tunnel All Lookup */
312 u_int hashtoeplitz:1; /* use Toeplitz hash */
318 * Maximum resources provisioned for a PCI VF.
320 struct vf_resources {
321 unsigned int nvi; /* N virtual interfaces */
322 unsigned int neq; /* N egress Qs */
323 unsigned int nethctrl; /* N egress ETH or CTRL Qs */
324 unsigned int niqflint; /* N ingress Qs/w free list(s) & intr */
325 unsigned int niq; /* N ingress Qs */
326 unsigned int tc; /* PCI-E traffic class */
327 unsigned int pmask; /* port access rights mask */
328 unsigned int nexactf; /* N exact MPS filters */
329 unsigned int r_caps; /* read capabilities */
330 unsigned int wx_caps; /* write/execute capabilities */
333 struct adapter_params {
334 struct sge_params sge;
335 struct tp_params tp; /* PF-only */
336 struct vpd_params vpd;
337 struct pci_params pci;
338 struct devlog_params devlog; /* PF-only */
339 struct rss_params rss; /* VF-only */
340 struct vf_resources vfres; /* VF-only */
341 unsigned int core_vdd;
343 unsigned int sf_size; /* serial flash size in bytes */
344 unsigned int sf_nsec; /* # of flash sectors */
346 unsigned int fw_vers; /* firmware version */
347 unsigned int bs_vers; /* bootstrap version */
348 unsigned int tp_vers; /* TP microcode version */
349 unsigned int er_vers; /* expansion ROM version */
350 unsigned int scfg_vers; /* Serial Configuration version */
351 unsigned int vpd_vers; /* VPD version */
353 unsigned short mtus[NMTUS];
354 unsigned short a_wnd[NCCTRL_WIN];
355 unsigned short b_wnd[NCCTRL_WIN];
362 unsigned int cim_la_size;
364 uint8_t nports; /* # of ethernet ports */
366 unsigned int chipid:4; /* chip ID. T4 = 4, T5 = 5, ... */
367 unsigned int rev:4; /* chip revision */
368 unsigned int fpga:1; /* this is an FPGA */
369 unsigned int offload:1; /* hw is TOE capable, fw has divvied up card
370 resources for TOE operation. */
371 unsigned int bypass:1; /* this is a bypass card */
372 unsigned int ethoffload:1;
374 unsigned int ofldq_wr_cred;
375 unsigned int eo_wr_cred;
377 unsigned int max_ordird_qp;
378 unsigned int max_ird_adapter;
380 uint32_t mps_bg_map; /* rx buffer group map for all ports (upto 4) */
382 bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
383 bool fr_nsmr_tpte_wr_support; /* FW support for FR_NSMR_TPTE_WR */
386 #define CHELSIO_T4 0x4
387 #define CHELSIO_T5 0x5
388 #define CHELSIO_T6 0x6
391 * State needed to monitor the forward progress of SGE Ingress DMA activities
392 * and possible hangs.
394 struct sge_idma_monitor_state {
395 unsigned int idma_1s_thresh; /* 1s threshold in Core Clock ticks */
396 unsigned int idma_stalled[2]; /* synthesized stalled timers in HZ */
397 unsigned int idma_state[2]; /* IDMA Hang detect state */
398 unsigned int idma_qid[2]; /* IDMA Hung Ingress Queue ID */
399 unsigned int idma_warn[2]; /* time to warning in HZ */
402 struct trace_params {
403 u32 data[TRACE_LEN / 4];
404 u32 mask[TRACE_LEN / 4];
405 unsigned short snap_len;
406 unsigned short min_len;
407 unsigned char skip_ofst;
408 unsigned char skip_len;
409 unsigned char invert;
414 /* OS-specific code owns all the requested_* fields */
415 unsigned char requested_aneg; /* link aneg user has requested */
416 unsigned char requested_fc; /* flow control user has requested */
417 unsigned char requested_fec; /* FEC user has requested */
418 unsigned int requested_speed; /* speed user has requested */
420 unsigned short supported; /* link capabilities */
421 unsigned short advertising; /* advertised capabilities */
422 unsigned short lp_advertising; /* peer advertised capabilities */
423 unsigned int speed; /* actual link speed */
424 unsigned char fc; /* actual link flow control */
425 unsigned char fec; /* actual FEC */
426 unsigned char link_ok; /* link up? */
427 unsigned char link_down_rc; /* link down reason */
432 #ifndef PCI_VENDOR_ID_CHELSIO
433 # define PCI_VENDOR_ID_CHELSIO 0x1425
436 #define for_each_port(adapter, iter) \
437 for (iter = 0; iter < (adapter)->params.nports; ++iter)
439 static inline int is_ftid(const struct adapter *sc, u_int tid)
442 return (tid >= sc->params.ftid_min && tid <= sc->params.ftid_max);
445 static inline int is_etid(const struct adapter *sc, u_int tid)
448 return (tid >= sc->params.etid_min);
451 static inline int is_offload(const struct adapter *adap)
453 return adap->params.offload;
456 static inline int is_ethoffload(const struct adapter *adap)
458 return adap->params.ethoffload;
461 static inline int chip_id(struct adapter *adap)
463 return adap->params.chipid;
466 static inline int chip_rev(struct adapter *adap)
468 return adap->params.rev;
471 static inline int is_t4(struct adapter *adap)
473 return adap->params.chipid == CHELSIO_T4;
476 static inline int is_t5(struct adapter *adap)
478 return adap->params.chipid == CHELSIO_T5;
481 static inline int is_t6(struct adapter *adap)
483 return adap->params.chipid == CHELSIO_T6;
486 static inline int is_fpga(struct adapter *adap)
488 return adap->params.fpga;
491 static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
493 return adap->params.vpd.cclk / 1000;
496 static inline unsigned int us_to_core_ticks(const struct adapter *adap,
499 return (us * adap->params.vpd.cclk) / 1000;
502 static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
505 /* add Core Clock / 2 to round ticks to nearest uS */
506 return ((ticks * 1000 + adapter->params.vpd.cclk/2) /
507 adapter->params.vpd.cclk);
510 static inline unsigned int dack_ticks_to_usec(const struct adapter *adap,
513 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
516 static inline u_int us_to_tcp_ticks(const struct adapter *adap, u_long us)
519 return (us * adap->params.vpd.cclk / 1000 >> adap->params.tp.tre);
522 void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask, u32 val);
524 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
525 int size, void *rpl, bool sleep_ok, int timeout);
526 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
527 void *rpl, bool sleep_ok);
529 static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
530 const void *cmd, int size, void *rpl,
533 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
537 static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
540 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
543 static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
546 return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
549 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
550 unsigned int data_reg, u32 *vals, unsigned int nregs,
551 unsigned int start_idx);
552 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
553 unsigned int data_reg, const u32 *vals,
554 unsigned int nregs, unsigned int start_idx);
556 u32 t4_hw_pci_read_cfg4(adapter_t *adapter, int reg);
560 void t4_intr_enable(struct adapter *adapter);
561 void t4_intr_disable(struct adapter *adapter);
562 void t4_intr_clear(struct adapter *adapter);
563 int t4_slow_intr_handler(struct adapter *adapter);
565 int t4_hash_mac_addr(const u8 *addr);
566 int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
567 struct link_config *lc);
568 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port);
569 int t4_seeprom_read(struct adapter *adapter, u32 addr, u32 *data);
570 int t4_seeprom_write(struct adapter *adapter, u32 addr, u32 data);
571 int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz);
572 int t4_seeprom_wp(struct adapter *adapter, int enable);
573 int t4_read_flash(struct adapter *adapter, unsigned int addr, unsigned int nwords,
574 u32 *data, int byte_oriented);
575 int t4_write_flash(struct adapter *adapter, unsigned int addr,
576 unsigned int n, const u8 *data, int byte_oriented);
577 int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
578 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
579 int t5_fw_init_extern_mem(struct adapter *adap);
580 int t4_load_bootcfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
581 int t4_load_boot(struct adapter *adap, u8 *boot_data,
582 unsigned int boot_addr, unsigned int size);
583 int t4_flash_erase_sectors(struct adapter *adapter, int start, int end);
584 int t4_flash_cfg_addr(struct adapter *adapter);
585 int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
586 int t4_get_fw_version(struct adapter *adapter, u32 *vers);
587 int t4_get_bs_version(struct adapter *adapter, u32 *vers);
588 int t4_get_tp_version(struct adapter *adapter, u32 *vers);
589 int t4_get_exprom_version(struct adapter *adapter, u32 *vers);
590 int t4_get_scfg_version(struct adapter *adapter, u32 *vers);
591 int t4_get_vpd_version(struct adapter *adapter, u32 *vers);
592 int t4_get_version_info(struct adapter *adapter);
593 int t4_init_hw(struct adapter *adapter, u32 fw_params);
594 const struct chip_params *t4_get_chip_params(int chipid);
595 int t4_prep_adapter(struct adapter *adapter, u32 *buf);
596 int t4_shutdown_adapter(struct adapter *adapter);
597 int t4_init_devlog_params(struct adapter *adapter, int fw_attach);
598 int t4_init_sge_params(struct adapter *adapter);
599 int t4_init_tp_params(struct adapter *adap, bool sleep_ok);
600 int t4_filter_field_shift(const struct adapter *adap, int filter_sel);
601 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf, int port_id);
602 void t4_fatal_err(struct adapter *adapter);
603 void t4_db_full(struct adapter *adapter);
604 void t4_db_dropped(struct adapter *adapter);
605 int t4_set_trace_filter(struct adapter *adapter, const struct trace_params *tp,
606 int filter_index, int enable);
607 void t4_get_trace_filter(struct adapter *adapter, struct trace_params *tp,
608 int filter_index, int *enabled);
609 int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
610 int start, int n, const u16 *rspq, unsigned int nrspq);
611 int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
613 int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
614 unsigned int flags, unsigned int defq, unsigned int skeyidx,
616 int t4_read_rss(struct adapter *adapter, u16 *entries);
617 void t4_read_rss_key(struct adapter *adapter, u32 *key, bool sleep_ok);
618 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx,
620 void t4_read_rss_pf_config(struct adapter *adapter, unsigned int index,
621 u32 *valp, bool sleep_ok);
622 void t4_write_rss_pf_config(struct adapter *adapter, unsigned int index,
623 u32 val, bool sleep_ok);
624 void t4_read_rss_vf_config(struct adapter *adapter, unsigned int index,
625 u32 *vfl, u32 *vfh, bool sleep_ok);
626 void t4_write_rss_vf_config(struct adapter *adapter, unsigned int index,
627 u32 vfl, u32 vfh, bool sleep_ok);
628 u32 t4_read_rss_pf_map(struct adapter *adapter, bool sleep_ok);
629 void t4_write_rss_pf_map(struct adapter *adapter, u32 pfmap, bool sleep_ok);
630 u32 t4_read_rss_pf_mask(struct adapter *adapter, bool sleep_ok);
631 void t4_write_rss_pf_mask(struct adapter *adapter, u32 pfmask, bool sleep_ok);
632 int t4_mps_set_active_ports(struct adapter *adap, unsigned int port_mask);
633 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
634 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]);
635 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres);
636 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
637 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n);
638 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n,
640 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n,
641 const unsigned int *valp);
642 int t4_cim_ctl_read(struct adapter *adap, unsigned int addr, unsigned int n,
644 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr);
645 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
646 unsigned int *pif_req_wrptr, unsigned int *pif_rsp_wrptr);
647 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp);
648 int t4_get_flash_params(struct adapter *adapter);
650 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg, int drv_fw_attach);
651 int t4_mc_read(struct adapter *adap, int idx, u32 addr,
652 __be32 *data, u64 *parity);
653 int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *parity);
654 int t4_mem_read(struct adapter *adap, int mtype, u32 addr, u32 size,
656 void t4_idma_monitor_init(struct adapter *adapter,
657 struct sge_idma_monitor_state *idma);
658 void t4_idma_monitor(struct adapter *adapter,
659 struct sge_idma_monitor_state *idma,
662 unsigned int t4_get_regs_len(struct adapter *adapter);
663 void t4_get_regs(struct adapter *adap, u8 *buf, size_t buf_size);
665 const char *t4_get_port_type_description(enum fw_port_type port_type);
666 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
667 void t4_get_port_stats_offset(struct adapter *adap, int idx,
668 struct port_stats *stats,
669 struct port_stats *offset);
670 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p);
671 void t4_clr_port_stats(struct adapter *adap, int idx);
673 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
674 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]);
675 void t4_read_pace_tbl(struct adapter *adap, unsigned int pace_vals[NTX_SCHED]);
676 void t4_get_tx_sched(struct adapter *adap, unsigned int sched, unsigned int *kbps,
677 unsigned int *ipg, bool sleep_ok);
678 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
679 unsigned int mask, unsigned int val);
680 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr);
681 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st,
683 void t4_tp_get_proxy_stats(struct adapter *adap, struct tp_proxy_stats *st,
685 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st,
687 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st,
689 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st,
691 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
692 struct tp_tcp_stats *v6, bool sleep_ok);
693 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx,
694 struct tp_fcoe_stats *st, bool sleep_ok);
695 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
696 const unsigned short *alpha, const unsigned short *beta);
698 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf);
700 int t4_set_sched_bps(struct adapter *adap, int sched, unsigned int kbps);
701 int t4_set_sched_ipg(struct adapter *adap, int sched, unsigned int ipg);
702 int t4_set_pace_tbl(struct adapter *adap, const unsigned int *pace_vals,
703 unsigned int start, unsigned int n);
704 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate);
705 int t4_set_filter_mode(struct adapter *adap, unsigned int mode_map,
707 void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid);
709 void t4_wol_magic_enable(struct adapter *adap, unsigned int port, const u8 *addr);
710 int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
711 u64 mask0, u64 mask1, unsigned int crc, bool enable);
713 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
714 enum dev_master master, enum dev_state *state);
715 int t4_fw_bye(struct adapter *adap, unsigned int mbox);
716 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
717 int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force);
718 int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
719 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
720 const u8 *fw_data, unsigned int size, int force);
721 int t4_fw_forceinstall(struct adapter *adap, const u8 *fw_data,
723 int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
724 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
725 unsigned int vf, unsigned int nparams, const u32 *params,
727 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf,
728 unsigned int vf, unsigned int nparams, const u32 *params,
730 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
731 unsigned int pf, unsigned int vf,
732 unsigned int nparams, const u32 *params,
733 const u32 *val, int timeout);
734 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
735 unsigned int vf, unsigned int nparams, const u32 *params,
737 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
738 unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
739 unsigned int rxqi, unsigned int rxq, unsigned int tc,
740 unsigned int vi, unsigned int cmask, unsigned int pmask,
741 unsigned int exactf, unsigned int rcaps, unsigned int wxcaps);
742 int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
743 unsigned int port, unsigned int pf, unsigned int vf,
744 unsigned int nmac, u8 *mac, u16 *rss_size,
745 unsigned int portfunc, unsigned int idstype);
746 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
747 unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
749 int t4_free_vi(struct adapter *adap, unsigned int mbox,
750 unsigned int pf, unsigned int vf,
752 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
753 int mtu, int promisc, int all_multi, int bcast, int vlanex,
755 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, unsigned int viid,
756 bool free, unsigned int naddr, const u8 **addr, u16 *idx,
757 u64 *hash, bool sleep_ok);
758 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
759 int idx, const u8 *addr, bool persist, bool add_smt);
760 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
761 bool ucast, u64 vec, bool sleep_ok);
762 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
763 unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
764 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
765 bool rx_en, bool tx_en);
766 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
767 unsigned int nblinks);
768 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
769 unsigned int mmd, unsigned int reg, unsigned int *valp);
770 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
771 unsigned int mmd, unsigned int reg, unsigned int val);
772 int t4_i2c_rd(struct adapter *adap, unsigned int mbox,
773 int port, unsigned int devid,
774 unsigned int offset, unsigned int len,
776 int t4_i2c_wr(struct adapter *adap, unsigned int mbox,
777 int port, unsigned int devid,
778 unsigned int offset, unsigned int len,
780 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf,
781 unsigned int vf, unsigned int iqtype, unsigned int iqid,
782 unsigned int fl0id, unsigned int fl1id);
783 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
784 unsigned int vf, unsigned int iqtype, unsigned int iqid,
785 unsigned int fl0id, unsigned int fl1id);
786 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
787 unsigned int vf, unsigned int eqid);
788 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
789 unsigned int vf, unsigned int eqid);
790 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
791 unsigned int vf, unsigned int eqid);
792 int t4_sge_ctxt_rd(struct adapter *adap, unsigned int mbox, unsigned int cid,
793 enum ctxt_type ctype, u32 *data);
794 int t4_sge_ctxt_rd_bd(struct adapter *adap, unsigned int cid, enum ctxt_type ctype,
796 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox);
797 const char *t4_link_down_rc_str(unsigned char link_down_rc);
798 int t4_update_port_info(struct port_info *pi);
799 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
800 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, u32 addr, u32 val);
801 int t4_sched_config(struct adapter *adapter, int type, int minmaxen,
803 int t4_sched_params(struct adapter *adapter, int type, int level, int mode,
804 int rateunit, int ratemode, int channel, int cl,
805 int minrate, int maxrate, int weight, int pktsize,
807 int t4_sched_params_ch_rl(struct adapter *adapter, int channel, int ratemode,
808 unsigned int maxrate, int sleep_ok);
809 int t4_sched_params_cl_wrr(struct adapter *adapter, int channel, int cl,
810 int weight, int sleep_ok);
811 int t4_sched_params_cl_rl_kbps(struct adapter *adapter, int channel, int cl,
812 int mode, unsigned int maxrate, int pktsize,
814 int t4_config_watchdog(struct adapter *adapter, unsigned int mbox,
815 unsigned int pf, unsigned int vf,
816 unsigned int timeout, unsigned int action);
817 int t4_get_devlog_level(struct adapter *adapter, unsigned int *level);
818 int t4_set_devlog_level(struct adapter *adapter, unsigned int level);
819 void t4_sge_decode_idma_state(struct adapter *adapter, int state);
821 void t4_tp_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
822 u32 start_index, bool sleep_ok);
823 void t4_tp_pio_write(struct adapter *adap, const u32 *buff, u32 nregs,
824 u32 start_index, bool sleep_ok);
825 void t4_tp_tm_pio_read(struct adapter *adap, u32 *buff, u32 nregs,
826 u32 start_index, bool sleep_ok);
827 void t4_tp_mib_read(struct adapter *adap, u32 *buff, u32 nregs,
828 u32 start_index, bool sleep_ok);
830 static inline int t4vf_query_params(struct adapter *adapter,
831 unsigned int nparams, const u32 *params,
834 return t4_query_params(adapter, 0, 0, 0, nparams, params, vals);
837 static inline int t4vf_set_params(struct adapter *adapter,
838 unsigned int nparams, const u32 *params,
841 return t4_set_params(adapter, 0, 0, 0, nparams, params, vals);
844 static inline int t4vf_wr_mbox(struct adapter *adap, const void *cmd,
847 return t4_wr_mbox(adap, adap->mbox, cmd, size, rpl);
850 int t4vf_wait_dev_ready(struct adapter *adapter);
851 int t4vf_fw_reset(struct adapter *adapter);
852 int t4vf_get_sge_params(struct adapter *adapter);
853 int t4vf_get_rss_glb_config(struct adapter *adapter);
854 int t4vf_get_vfres(struct adapter *adapter);
855 int t4vf_prep_adapter(struct adapter *adapter);
856 int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
857 enum t4_bar2_qtype qtype, int user, u64 *pbar2_qoffset,
858 unsigned int *pbar2_qid);
860 #endif /* __CHELSIO_COMMON_H */